; --------------------------------------------------------------------------------
; @Title: LPC54xxx On-Chip Peripherals
; @Props: Released
; @Author: KWI, RSA, KRZ
; @Changelog: 2021-04-06 KWI
;             2022-01-21 RSA
;             2024-04-25 KRZ
; @Manufacturer: NXP - NXP Semiconductors
; @Doc: Generated (TRACE32, build: 168851.), based on:
;       LPC54S005.xml (Ver. 1.0), LPC54S016.xml (Ver. 1.0), LPC54S018.xml (Ver. 1.0),
;       LPC54005.xml (Ver. 1.0), LPC54016.xml (Ver. 1.0), LPC54018.xml (Ver. 1.0),
;       LPC54101.xml (Ver. 1.0), LPC54102_cm4.xml (Ver. 1.0), LPC54113.xml (Ver. 1.0),
;       LPC54114_cm4.xml (Ver. 1.0), LPC54605.xml (Ver. 1.0), LPC54606.xml (Ver. 1.0),
;       LPC54607.xml (Ver. 1.0), LPC54608.xml (Ver. 1.0), LPC54616.xml (Ver. 1.0),
;       LPC54618.xml (Ver. 1.0), LPC54628.xml (Ver. 1.0)
; @Core: Cortex-M4F, Cortex-M0+
; @Chip: LPC54S005*, LPC54S016*, LPC54S018*, LPC54005*, LPC54016*, LPC54018*,
;        LPC54101*, LPC54102*, LPC54113*, LPC54114*, LPC54605*, LPC54606*,
;        LPC54607*, LPC54608*, LPC54616*, LPC54618*, LPC54628*
; @Copyright: (C) 1989-2024 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; Copyright 2016-2022 NXP
; All rights reserved.
;
; SPDX-License-Identifier: BSD-3-Clause
; --------------------------------------------------------------------------------
; $Id: perlpc54xxx.per 17822 2024-04-26 09:23:43Z kwisniewski $

AUTOINDENT.ON CENTER TREE
ENUMDELIMITER ","
base ad:0x0
sif (CORENAME()=="CORTEXM0+")
tree.close "Core Registers (Cortex-M0+)"
AUTOINDENT.PUSH
AUTOINDENT.OFF
tree "System Control"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 0x8
if (CORENAME()=="CORTEXM1")
group.long 0x10++0x0b
line.long 0x00 "STCSR,SysTick Control and Status Register"
bitfld.long 0x00 16. " COUNTFLAG    ,Returns 1 if timer counted to 0" "0,1"
bitfld.long 0x00 2.  "                CLKSOURCE     ,Always reads as one" "No effect,Processor clock"
textline "                 "
bitfld.long 0x00 1.  " TICKINT      ,Counting down to 0 " "No SysTick,SysTick"
bitfld.long 0x00 0.  "       ENABLE        ,Counter enable" "Disabled,Enabled"
line.long 0x04 "STRVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD       ,Value to load into the STCVR when the counter reaches 0"
line.long 0x08 "STCVR,SysTick Current Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT      ,Reads return the current value of the SysTick counter"
else
group.long 0x10++0x0b
line.long 0x00 "STCSR,SysTick Control and Status Register"
bitfld.long 0x00 16. " COUNTFLAG    ,Returns 1 if timer counted to 0" "0,1"
bitfld.long 0x00 2.  "                CLKSOURCE     ,Always reads as one" "External clock,Processor clock"
textline "                 "
bitfld.long 0x00 1.  " TICKINT      ,Counting down to 0 " "No SysTick,SysTick"
bitfld.long 0x00 0.  "       ENABLE        ,Counter enable" "Disabled,Enabled"
line.long 0x04 "STRVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD       ,Value to load into the STCVR when the counter reaches 0"
line.long 0x08 "STCVR,SysTick Current Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT      ,Reads return the current value of the SysTick counter"
endif
if (CORENAME()=="CORTEXM1")
rgroup.long 0x1c++0x03
line.long 0x00 "STCR,SysTick Calibration Value Register"
bitfld.long 0x00 31. " NOREF        ,Reads as one" "0,1"
bitfld.long 0x00 30. "                SKEW          ,Reads as zero" "0,1"
textline "                 "
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS        ,Indicates calibration value is not known"
else
rgroup.long 0x1c++0x03
line.long 0x00 "STCR,SysTick Calibration Value Register"
bitfld.long 0x00 31. " NOREF        ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented"
bitfld.long 0x00 30. "  SKEW          ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
textline "                 "
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS        ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
endif
rgroup.long 0xd00++0x03
line.long 0x00 "CPUID,CPU ID Base Register"
hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER  ,Implementer code"
hexmask.long.byte 0x00 20.--23. 1. "               VARIANT       ,Implementation defined variant number"
textline "                 "
hexmask.long.byte 0x00 4.--15. 1.  " PARTNO       ,Number of processor within family"
hexmask.long.byte 0x00 0.--3. 1. "               REVISION      ,Implementation defined revision number"
group.long 0xd04++0x03
line.long 0x00 "ICSR,Interrupt Control State Register"
bitfld.long 0x00 31. " NMIPENDSET   ,Setting this bit will activate an NMI" "No effect,Set pending"
bitfld.long 0x00 28. "      PENDSVSET     ,Set a pending PendSV interrupt" "No effect,Set pending"
textline "                 "
bitfld.long 0x00 27. " PENDSVCLR    ,Clear a pending PendSV interrupt" "No effect,Clear pending"
bitfld.long 0x00 26. "    PENDSTSET     ,Set a pending SysTick" "No effect,Set pending"
textline "                 "
bitfld.long 0x00 25. " PENDSVCLR    ,Clear a pending SysTick" "No effect,Clear pending"
bitfld.long 0x00 23. "    ISRPREEMPT    ,Pending exception service" "No service,Service"
textline "                 "
bitfld.long 0x00 22. " ISRPENDING   ,External interrupt pending flag" "No interrupt,Interrupt"
hexmask.long.byte 0x00 12.--17. 1. "     VECTPENDING   ,Active exception number field"
textline "                 "
hexmask.long.byte 0x00 0.--5. 1.  " VECTACTIVET  ,Active exception number field"
if (CORENAME()=="CORTEXM0+")
group.long 0xd08++0x03
line.long 0x00 "VTOR,Vector Table Offset Register"
hexmask.long 0x00 7.--31. 0x80 " TBLOFF       ,Vector table address"
else
textline "                 "
endif
group.long 0xd0c++0x03
line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
hexmask.long.word 0x00 16.--31. 1. " VECTKEY      ,Vector Key"
bitfld.long 0x00 15. "             ENDIANNESS    ,Data endianness bit" "Little-endian,Big-endian"
textline "                 "
bitfld.long 0x00 2. " SYSRESETREQ  ,System reset setup request" "No effect,Reset"
bitfld.long 0x00 1. "        VECTCLRACTIVE ,Clears all active state information" "No clear,Clear"
group.long 0xd10++0x03
line.long 0x00 "SCR,System Control Register"
bitfld.long 0x00 4. " SEVONPEND    ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
bitfld.long 0x00 2. "       SLEEPDEEP     ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
textline "                 "
bitfld.long 0x00 1. " SLEEPONEXIT  ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
rgroup.long 0xd14++0x03
line.long 0x00 "CCR,Configuration and Control Register"
bitfld.long 0x00 9. " STKALIGN     ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned"
bitfld.long 0x00 3. "         UNALIGN_TRP   ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped"
group.long 0xd1c++0x0b
line.long 0x00 "SHPR2,System Handler Priority Register 2"
bitfld.long 0x00 30.--31. " PRI_11       ,Priority of system handler 11-SVCall" "00,01,10,11"
line.long 0x04 "SHPR3,System Handler Priority Register 3"
bitfld.long 0x04 30.--31. " PRI_15       ,Priority of system handler 15-SysTick" "00,01,10,11"
bitfld.long 0x04 22.--23. "               PRI_14        ,Priority of system handler 14- PendSV" "00,01,10,11"
line.long 0x08 "SHCSR,System Handler Control and State Register"
bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending"
if (CORENAME()=="CORTEXM0+")
hgroup.long 0x08++0x03
hide.long 0x00 "ACTLR,Auxiliary Control Register"
else
textline "                 "
endif
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Memory Protection Unit (MPU)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 15.
rgroup.long 0xD90++0x03
line.long 0x00 "MPU_TYPE,MPU Type Register"
bitfld.long 0x00 8.--15. 1. " DREGION    ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,?..."
group.long 0xD94++0x03
line.long 0x00 "MPU_CTRL,MPU Control Register"
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
bitfld.long 0x00 1. "         HFNMIENA  ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
bitfld.long 0x00 0. "          ENABLE   ,Enables the MPU" "Disabled,Enabled"
group.long 0xD98++0x03
line.long 0x00 "MPU_RNR,MPU Region Number Register"
hexmask.long.byte 0x00 0.--7. 1. " REGION     ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
tree.close "MPU regions"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
group.long 0xD9C++0x03 "Region 0"
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
hexmask.long 0x00 8.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
group.long 0xD9C++0x03 "Region 1"
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
hexmask.long 0x00 8.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
group.long 0xD9C++0x03 "Region 2"
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
hexmask.long 0x00 8.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
group.long 0xD9C++0x03 "Region 3"
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
hexmask.long 0x00 8.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
group.long 0xD9C++0x03 "Region 4"
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
hexmask.long 0x00 8.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
group.long 0xD9C++0x03 "Region 5"
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
hexmask.long 0x00 8.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
group.long 0xD9C++0x03 "Region 6"
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
hexmask.long 0x00 8.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
group.long 0xD9C++0x03 "Region 7"
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
hexmask.long 0x00 8.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
textline "                        "
textline "                        "
endif
tree.end
width 0x0b
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Nested Vectored Interrupt Controller (NVIC)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 12.
tree "Interrupt Enable Registers"
group.long 0x100++0x03
line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "     SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "     SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                     "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "     SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "     SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                     "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "     SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "     SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                     "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "     SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "     SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                     "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "     SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "     SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                     "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "     SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "     SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                     "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "     SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "     SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                     "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "     SET/CLRENA9  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "     SET/CLRENA8  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                     "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "     SET/CLRENA6  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "     SET/CLRENA5  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                     "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "     SET/CLRENA3  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "     SET/CLRENA2  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                     "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "     SET/CLRENA0  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
tree.end
tree "Interrupt Pending Registers"
group.long 0x200++0x03
line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                     "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                     "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                     "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                     "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                     "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                     "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                     "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEN9  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEN8  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                     "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEN6  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEN5  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                     "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEN3  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEN2  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                     "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEN0  ,Interrupt Set/Clear Pending" "Not pending,Pending"
tree.end
width 6.
tree "Interrupt Priority Registers"
group.long 0x400++0x1F
line.long 0x00 "INT0,Interrupt Priority Register"
bitfld.long 0x00 30.--31. " IP_3  ,Priority of interrupt 3" "0,1,2,3"
bitfld.long 0x00 22.--23. "  IP_2  ,Priority of interrupt 2" "0,1,2,3"
bitfld.long 0x00 14.--15. "  IP_1  ,Priority of interrupt 1" "0,1,2,3"
bitfld.long 0x00 6.--7.   "  IP_0  ,Priority of interrupt 0" "0,1,2,3"
line.long 0x04 "INT1,Interrupt Priority Register"
bitfld.long 0x04 30.--31. " IP_7  ,Priority of interrupt 7" "0,1,2,3"
bitfld.long 0x04 22.--23. "  IP_6  ,Priority of interrupt 6" "0,1,2,3"
bitfld.long 0x04 14.--15. "  IP_5  ,Priority of interrupt 5" "0,1,2,3"
bitfld.long 0x04 6.--7.   "  IP_4  ,Priority of interrupt 4" "0,1,2,3"
line.long 0x08 "INT2,Interrupt Priority Register"
bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3"
bitfld.long 0x08 22.--23. "  IP_10 ,Priority of interrupt 10" "0,1,2,3"
bitfld.long 0x08 14.--15. "  IP_9  ,Priority of interrupt 9" "0,1,2,3"
bitfld.long 0x08 6.--7.   "  IP_8  ,Priority of interrupt 8" "0,1,2,3"
line.long 0x0C "INT3,Interrupt Priority Register"
bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3"
bitfld.long 0x0C 22.--23. "  IP_14 ,Priority of interrupt 14" "0,1,2,3"
bitfld.long 0x0C 14.--15. "  IP_13 ,Priority of interrupt 13" "0,1,2,3"
bitfld.long 0x0C 6.--7.   "  IP_12 ,Priority of interrupt 12" "0,1,2,3"
line.long 0x10 "INT4,Interrupt Priority Register"
bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3"
bitfld.long 0x10 22.--23. "  IP_18 ,Priority of interrupt 18" "0,1,2,3"
bitfld.long 0x10 14.--15. "  IP_17 ,Priority of interrupt 17" "0,1,2,3"
bitfld.long 0x10 6.--7.   "  IP_16 ,Priority of interrupt 16" "0,1,2,3"
line.long 0x14 "INT5,Interrupt Priority Register"
bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3"
bitfld.long 0x14 22.--23. "  IP_22 ,Priority of interrupt 22" "0,1,2,3"
bitfld.long 0x14 14.--15. "  IP_21 ,Priority of interrupt 21" "0,1,2,3"
bitfld.long 0x14 6.--7.   "  IP_20 ,Priority of interrupt 20" "0,1,2,3"
line.long 0x18 "INT6,Interrupt Priority Register"
bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3"
bitfld.long 0x18 22.--23. "  IP_26 ,Priority of interrupt 26" "0,1,2,3"
bitfld.long 0x18 14.--15. "  IP_25 ,Priority of interrupt 25" "0,1,2,3"
bitfld.long 0x18 6.--7.   "  IP_24 ,Priority of interrupt 24" "0,1,2,3"
line.long 0x1C "INT7,Interrupt Priority Register"
bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3"
bitfld.long 0x1C 22.--23. "  IP_30 ,Priority of interrupt 30" "0,1,2,3"
bitfld.long 0x1C 14.--15. "  IP_29 ,Priority of interrupt 29" "0,1,2,3"
bitfld.long 0x1C 6.--7.   "  IP_28 ,Priority of interrupt 28" "0,1,2,3"
tree.end
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Debug"
tree "Core Debug"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 0xA
group.long 0xD30++0x03
line.long 0x00 "DFSR,Data Fault Status Register"
eventfld.long 0x00 4. " EXTERNAL          ,External debug request flag" "No occurred,Occurred"
eventfld.long 0x00 3. "    VCATCH             ,Vector catch flag" "No occurred,Occurred"
textline "                   "
eventfld.long 0x00 2. " DWTRAP            ,Data Watchpoint flag" "No match,Match"
textline "                   "
eventfld.long 0x00 1. " BKPT              ,BKPT flag" "No match,Match"
eventfld.long 0x00 0. "       HALTED             ,Halt request flag" "No request,Request"
if (CORENAME()=="CORTEXM1")
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 30. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 29. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 28. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 27. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 26. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. "       S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
textline "                   "
bitfld.long 0x00 23. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 22. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 21. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 20. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 19. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 18. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 17. " S_HALT/DBGKEY     ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. "     S_REGRDY/DBGKEY    ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline "                   "
textline "                   "
textfld "                                 "
bitfld.long 0x00 0. " C_DEBUGEN          ,Debug Enable" "Disabled,Enabled"
else
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 30. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 29. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 28. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 27. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 26. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. "       S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline "                   "
bitfld.long 0x00 23. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 22. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 21. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 20. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 19. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 18. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 17. " S_HALT/DBGKEY     ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. "     S_REGRDY/DBGKEY    ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline "                   "
bitfld.long 0x00 3. " C_MASKINTS        ,Interrupts Mask" "Not masked,Masked"
bitfld.long 0x00 2. "     C_STEP             ,Steps the core in halted debug" "Not halted,Halted"
textline "                   "
bitfld.long 0x00 1. " C_HALT            ,Core Halted" "Not halted,Halted"
bitfld.long 0x00 0. "     C_DEBUGEN          ,Debug Enable" "Disabled,Enabled"
endif
else
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 30. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 29. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 28. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 27. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 26. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. "       S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
textline "                   "
bitfld.long 0x00 23. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 22. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 21. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 20. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY   ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
bitfld.long 0x00 18. "  S_SLEEP/DBGKEY     ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
textline "                   "
bitfld.long 0x00 17. " S_HALT/DBGKEY     ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. "     S_REGRDY/DBGKEY    ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline "                   "
textline "                   "
textfld "                                 "
bitfld.long 0x00 0. " C_DEBUGEN          ,Debug Enable" "Disabled,Enabled"
else
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 30. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 29. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 28. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 27. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 26. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. "       S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline "                   "
bitfld.long 0x00 23. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 22. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 21. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 20. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY   ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
bitfld.long 0x00 18. "  S_SLEEP/DBGKEY     ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
textline "                   "
bitfld.long 0x00 17. " S_HALT/DBGKEY     ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. "     S_REGRDY/DBGKEY    ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline "                   "
bitfld.long 0x00 3. " C_MASKINTS        ,Interrupts Mask" "Not masked,Masked"
bitfld.long 0x00 2. "     C_STEP             ,Steps the core in halted debug" "Not halted,Halted"
textline "                   "
bitfld.long 0x00 1. " C_HALT            ,Core Halted" "Not halted,Halted"
bitfld.long 0x00 0. "     C_DEBUGEN          ,Debug Enable" "Disabled,Enabled"
endif
endif
wgroup.long 0xDF4++0x03
line.long 0x00 "DCRSR,Debug Core Selector Register"
bitfld.long 0x00 16. " REGWnR            ,Register Read/Write" "Read,Write"
bitfld.long 0x00 0.--4. "          REGSEL             ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..."
group.long 0xDF8++0x07
line.long 0x00 "DCRDR,Debug Core Register Data Register"
hexmask.long 0x00 0.--31. 1. " DATA              ,Data for reading and writing registers to and from the processor"
line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x04 24. " DWTENA            ,Global enable or disable for the DW unit" "Disabled,Enabled"
bitfld.long 0x04 10. "       VC_HARDERR         ,Debug trap on a Hard Fault" "No error,Error"
textline "                   "
bitfld.long 0x04 0.  " VC_CORERESET      ,Reset Vector Catch" "No reset,Reset"
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Breakpoint Unit (BPU)"
sif COMPonent.AVAILABLE("BPU")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1))
width 8.
group.long 0x00++0x03
line.long 0x00 "BP_CTRL,Breakpoint Control Register"
bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1.     "              KEY  ,Key field" "No write,Write"
bitfld.long 0x00 0.     "  ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled"
group.long 0x8++0x03
line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0"
bitfld.long 0x00 30.--31. " BP_MATCH  ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. "  COMP ,Comparison address"
bitfld.long 0x00 0.     "  ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled"
group.long 0xC++0x03
line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1"
bitfld.long 0x00 30.--31. " BP_MATCH  ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. "  COMP ,Comparison address"
bitfld.long 0x00 0.     "  ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled"
group.long 0x10++0x03
line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2"
bitfld.long 0x00 30.--31. " BP_MATCH  ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. "  COMP ,Comparison address"
bitfld.long 0x00 0.     "  ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled"
group.long 0x14++0x03
line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3"
bitfld.long 0x00 30.--31. " BP_MATCH  ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. "  COMP ,Comparison address"
bitfld.long 0x00 0.     "  ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled"
else
newline
textline "BPU component base address not specified"
newline
endif
tree.end
tree "Data Watchpoint and Trace Unit (DWT)"
sif COMPonent.AVAILABLE("DWT")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
width 14.
rgroup.long 0x00++0x03
line.long 0x00 "DW_CTRL,DW Control Register "
bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x1c++0x03
line.long 0x00 "DW_PCSR,DW Program Counter Sample Register"
hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF"
group.long 0x20++0x0b
line.long 0x00 "DW_COMP0,DW Comparator Register 0"
hexmask.long 0x00 0.--31. 1. " COMP1     ,Compare against PC or the data address"
line.long 0x04 "DW_MASK0,DW Mask Register 0"
hexmask.long.byte 0x04 0.--4. 1. " MASK      ,Mask on data address when matching against COMP"
line.long 0x08 "DW_FUNCTION0,DW Function Register 0"
bitfld.long 0x08 24. " MATCHED   ,Comparator match" "No match,Match"
bitfld.long 0x08 0.--3. "  FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
group.long 0x30++0x0b
line.long 0x00 "DW_COMP1,DW Comparator Register 1"
hexmask.long 0x00 0.--31. 1. " COMP      ,Compare against PC or the data address"
line.long 0x04 "DW_MASK1,DW Mask Register 1 "
hexmask.long.byte 0x04 0.--4. 1. " MASK      ,Mask on data address when matching against COMP"
line.long 0x08 "DW_FUNCTION1,DW Function Register 1"
bitfld.long 0x08 24. " MATCHED   ,Comparator match" "No match,Match"
bitfld.long 0x08 0.--3. "  FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
else
newline
textline "DWT component base address not specified"
newline
endif
tree.end
tree.end
AUTOINDENT.POP
tree.end
endif
sif (CORENAME()=="CORTEXM4F")
tree.close "Core Registers (Cortex-M4F)"
AUTOINDENT.PUSH
AUTOINDENT.OFF
tree "System Control"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 12.
group.long 0x08++0x03
line.long 0x00 "ACTLR,Auxiliary Control Register"
bitfld.long 0x00 9. " DISFPCA        ,Disables lazy stacking of floating point context" "No,Yes"
bitfld.long 0x00 8. "                   DISOOFP        ,Disables floating point instructions completing" "No,Yes"
bitfld.long 0x00 2. "              DISFOLD         ,Disables folding of IT instructions" "No,Yes"
textline "                     "
bitfld.long 0x00 1. " DISDEFWBUF     ,Disables write buffer use during default memory map accesses" "No,Yes"
bitfld.long 0x00 0. "                   DISMCYCINT     ,Disables interruption of multi-cycle instructions" "No,Yes"
group.long 0x10++0x0B
line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
rbitfld.long 0x00 16. " COUNTFLAG      ,Counter Flag" "Not counted,Counted"
bitfld.long 0x00 2. "           CLKSOURCE      ,SysTick clock source" "External,Core"
bitfld.long 0x00 1. "         TICKINT         ,SysTick Handler" "No SysTick,SysTick"
textline "                     "
bitfld.long 0x00 0. " ENABLE         ,Counter Enable" "Disabled,Enabled"
line.long 0x04 "SYST_RVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD         ,The value to load into the SYST_CVR when the counter reaches 0"
line.long 0x08 "SYST_CVR,SysTick Current Value Register"
rgroup.long 0x1C++0x03
line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register"
bitfld.long 0x00 31. " NOREF          ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
bitfld.long 0x00 30. "       SKEW           ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
hexmask.long.tbyte 0x00 0.--23. 1. "          TENMS           ,Holds a reload value to be used for 10ms (100Hz) timing"
rgroup.long 0xD00++0x03
line.long 0x00 "CPUID,CPU ID Base Register"
hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER    ,Implementer Code"
bitfld.long 0x00 20.--23. "                    VARIANT        ,Indicates processor revision" "Revision 0,?..."
bitfld.long 0x00 16.--19. "       ARCHITECTURE    ,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                     "
hexmask.long.word 0x00 4.--15. 1. " PARTNO         ,Indicates part number"
bitfld.long 0x00 0.--3. "                  REVISION       ,Indicates patch release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xD04++0x23
line.long 0x00 "ICSR,Interrupt Control State Register"
bitfld.long 0x00 31. " NMIPENDSET     ,Set Pending NMI Bit" "Inactive,Active"
bitfld.long 0x00 28. "              PENDSVSET      ,Set Pending pendSV Bit" "Not pending,Pending"
bitfld.long 0x00 27. "      PENDSVCLR       ,Removes the pending status of the PendSV exception" "No effect,Removed"
textline "                     "
bitfld.long 0x00 26. " PENDSTSET      ,Set Pending SysTick Bit" "Not pending,Pending"
bitfld.long 0x00 25. "           PENDSTCLR      ,Clear Pending SysTick Bit" "No effect,Removed"
bitfld.long 0x00 23. "        ISRPREEMPT      ,Use Only at Debug Time" "Not active,Active"
textline "                     "
bitfld.long 0x00 22. " ISRPENDING     ,Indicates whether an external interrupt" "Not pending,Pending"
hexmask.long.word 0x00 12.--20. 1. "           VECTPENDING    ,Pending ISR Number Field"
bitfld.long 0x00 11. "             RETTOBASE       ,Interrupt Exception" "Active,Not active"
textline "                     "
hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE     ,The exception number of the current executing exception"
line.long 0x04 "VTOR,Vector Table Offset Register"
hexmask.long 0x04 7.--31. 0x80 " TBLOFF         ,Vector table address"
line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
hexmask.long.word 0x08 16.--31. 1. " VECTKEY        ,Register Key"
rbitfld.long 0x08 15. "                  ENDIANESS      ,Data endianness Bit" "Little,Big"
bitfld.long 0x08 8.--10. "           PRIGROUP        ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
textline "                     "
bitfld.long 0x08 2. " SYSRESETREQ    ,System Reset Request" "Not requested,Requested"
bitfld.long 0x08 1. "         VECTCLRACTIVE  ,Clear Active Vector Bit" "No effect,Clear"
bitfld.long 0x08 0. "        VECTRESET       ,System Reset" "No effect,Reset"
line.long 0x0C "SCR,System Control Register"
bitfld.long 0x0C 4. " SEVONPEND      ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
bitfld.long 0x0C 2. "            SLEEPDEEP      ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
bitfld.long 0x0C 1. "   SLEEPONEXIT     ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
line.long 0x10 "CCR,Configuration Control Register"
bitfld.long 0x10 18. " BP             ,Branch prediction enable bit" "Disabled,Enabled"
bitfld.long 0x10 17. "              IC             ,Instruction cache enable bit" "Disabled,Enabled"
bitfld.long 0x10 16. "         DC              ,Cache enable bit" "Disabled,Enabled"
textline "                     "
bitfld.long 0x10 9. " STKALIGN       ,8-byte Stack Frame Alignment" "4-byte/no adjustment,8-byte/adjustment"
bitfld.long 0x10 8. "  BFHFNMIGN      ,Enable NMI and Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled"
bitfld.long 0x10 4. "         DIV_0_TRP       ,Trap Divide by Zero" "Disabled,Enabled"
textline "                     "
bitfld.long 0x10 3. " UNALIGN_TRP    ,Trap for Unaligned Access" "Disabled,Enabled"
bitfld.long 0x10 1. "              USERSETMPEND   ,Controls whether unprivileged software can access the STIR" "Denied,Allowed"
bitfld.long 0x10 0. "          NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level"
line.long 0x14 "SHPR1,SSystem Handler Priority Register 1"
hexmask.long.byte 0x14 24.--31. 1. " PRI_7          ,Priority of System Handler 7"
hexmask.long.byte 0x14 16.--23. 1. "                    PRI_6          ,Priority of system handler 6(UsageFault)"
hexmask.long.byte 0x14 8.--15. 1. "               PRI_5           ,Priority of system handler 5(BusFault)"
textline "                     "
hexmask.long.byte 0x14 0.--7. 1. " PRI_4          ,Priority of system handler 4(MemManage)"
line.long 0x18 "SHPR2,System Handler Priority Register 2"
hexmask.long.byte 0x18 24.--31. 1. " PRI_11         ,Priority of system handler 11(SVCall)"
hexmask.long.byte 0x18 16.--23. 1. "                    PRI_10         ,Priority of System Handler 10"
hexmask.long.byte 0x18 8.--15. 1. "               PRI_9           ,Priority of System Handler 9"
textline "                     "
hexmask.long.byte 0x18 0.--7. 1. " PRI_8          ,Priority of System Handler 8"
line.long 0x1C "SHPR3,System Handler Priority Register 3"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_15         ,Priority of System Handler 15(SysTick)"
hexmask.long.byte 0x1C 16.--23. 1. "                    PRI_14         ,Priority of System Handler 14(PendSV)"
hexmask.long.byte 0x1C 8.--15. 1. "               PRI_13          ,Priority of System Handler 13"
textline "                     "
hexmask.long.byte 0x1C 0.--7. 1. " PRI_12         ,Priority of System Handler 12(DebugMonitor)"
line.long 0x20 "SHCSR,System Handler Control and State Register"
bitfld.long 0x20 18. " USGFAULTENA    ,Enable UsageFault" "Disabled,Enabled"
bitfld.long 0x20 17. "              BUSFAULTENA    ,Enable BusFault" "Disabled,Enabled"
bitfld.long 0x20 16. "         MEMFAULTENA     ,Enable MemManage fault" "Disabled,Enabled"
textline "                     "
bitfld.long 0x20 15. " SVCALLPENDED   ,SVCall is pending" "Not pending,Pending"
bitfld.long 0x20 14. "           BUSFAULTPENDED ,BusFault is pending" "Not pending,Pending"
bitfld.long 0x20 13. "      MEMFAULTPENDED  ,MemManage is pending" "Not pending,Pending"
textline "                     "
bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault is pending" "Not pending,Pending"
bitfld.long 0x20 11. "           SYSTICKACT     ,SysTick is Active" "Not active,Active"
bitfld.long 0x20 10. "       PENDSVACT       ,PendSV is Active" "Not active,Active"
textline "                     "
bitfld.long 0x20 8. " MONITORACT     ,Monitor is Active" "Not active,Active"
bitfld.long 0x20 7. "            SVCALLACT      ,SVCall is Active" "Not active,Active"
bitfld.long 0x20 3. "       USGFAULTACT     ,UsageFault is Active" "Not active,Active"
textline "                     "
bitfld.long 0x20 1. " BUSFAULTACT    ,BusFault is Active" "Not active,Active"
bitfld.long 0x20 0. "            MEMFAULTACT    ,MemManage is Active" "Not active,Active"
group.byte 0xD28++0x1
line.byte 0x00 "MMFSR,MemManage Status Register"
bitfld.byte 0x00 7. "       MMARVALID      ,Address Valid Flag" "Not valid,Valid"
bitfld.byte 0x00 5. "             MLSPERR        ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred"
bitfld.byte 0x00 4. "     MSTKERR         ,tacking Access Violations" "Not occurred,Occurred"
textline "                     "
bitfld.byte 0x00 3. " MUNSTKERR      ,Unstack Access Violations" "Not occurred,Occurred"
bitfld.byte 0x00 1. "          DACCVIOL       ,Data Access Violation" "Not occurred,Occurred"
bitfld.byte 0x00 0. "     IACCVIOL        ,Instruction Access Violation" "Not occurred,Occurred"
line.byte 0x01 "BFSR,Bus Fault Status Register"
bitfld.byte 0x01 7. "       BFARVALID      ,Address Valid Flag" "Not valid,Valid"
bitfld.byte 0x01 5. "             LSPERR         ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred"
bitfld.byte 0x01 4. "     STKERR          ,Derived bus fault(exception entry)" "Not occurred,Occurred"
textline "                     "
bitfld.byte 0x01 3. " UNSTKERR       ,Derived bus fault(exception return)" "Not occurred,Occurred"
bitfld.byte 0x01 2. "          IMPRECISERR    ,Imprecise data access error" "Not occurred,Occurred"
bitfld.byte 0x01 1. "     PRECISERR       ,Precise data access error" "Not occurred,Occurred"
textline "                     "
bitfld.byte 0x01 0. " IBUSERR        ,Bus fault on an instruction prefetch" "Not occurred,Occurred"
group.word 0xD2A++0x1
line.word 0x00 "USAFAULT,Usage Fault Status Register"
bitfld.word 0x00 9. "     DIVBYZERO      ,Divide by zero error" "No error,Error"
bitfld.word 0x00 8. "              UNALIGNED      ,Unaligned access error" "No error,Error"
bitfld.word 0x00 3. "         NOCP            ,A coprocessor access error" "No error,Error"
textline "                     "
bitfld.word 0x00 2. " INVPC          ,An integrity check error" "No error,Error"
bitfld.word 0x00 1. "              INVSTATE       ,Invalid Combination of EPSR and Instruction" "No error,Error"
bitfld.word 0x00 0. "         UNDEFINSTR      ,Undefined instruction error" "No error,Error"
group.long 0xD2C++0x07
line.long 0x00 "HFSR,Hard Fault Status Register"
bitfld.long 0x00 31. " DEBUGEVT       ,Indicates when a Debug event has occurred" "Not occurred,Occurred"
bitfld.long 0x00 30. "          FORCED         ,Indicates that a fault with configurable priority" "Not occurred,Occurred"
bitfld.long 0x00 1. "     VECTTBL         ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred"
line.long 0x04 "DFSR,Debug Fault Status Register"
bitfld.long 0x04 4. " EXTERNAL       ,Indicates a debug event generated because of the assertion of EDBGRQ" "Not asserted,Asserted"
bitfld.long 0x04 3. "          VCATCH         ,Vector Catch Flag" "Not occurred,Occurred"
bitfld.long 0x04 2. "     DWTTRAP         ,Indicates a debug event generated by the DWT" "Not occurred,Occurred"
textline "                     "
bitfld.long 0x04 1. " BKPT           ,BKPT Flag" "Not executed,Executed"
bitfld.long 0x04 0. "          HALTED         ,Indicates a debug event generated by either" "Not requested,Requested"
group.long 0xD34++0x0B
line.long 0x00 "MMFAR,MemManage Fault Address Register"
line.long 0x04 "BFAR,BusFault Address Register"
line.long 0x08 "AFSR,Auxiliary Fault Status Register"
group.long 0xD88++0x03
line.long 0x00 "CPACR,Coprocessor Access Control Register"
bitfld.long 0x00 22.--23. " CP11           ,Access privileges for coprocessor 11" "Access denied,Privileged only,Reserved,Full access"
bitfld.long 0x00 20.--21. "       CP10           ,Access privileges for coprocessor 10" "Access denied,Privileged only,Reserved,Full access"
bitfld.long 0x00 14.--15. "  CP7             ,Access privileges for coprocessor 7" "Access denied,Privileged only,Reserved,Full access"
textline "                     "
bitfld.long 0x00 12.--13. " CP6            ,Access privileges for coprocessor 6" "Access denied,Privileged only,Reserved,Full access"
bitfld.long 0x00 10.--11. "       CP5            ,Access privileges for coprocessor 5" "Access denied,Privileged only,Reserved,Full access"
bitfld.long 0x00 8.--9. "  CP4             ,Access privileges for coprocessor 4" "Access denied,Privileged only,Reserved,Full access"
textline "                     "
bitfld.long 0x00 6.--7. " CP3            ,Access privileges for coprocessor 3" "Access denied,Privileged only,Reserved,Full access"
bitfld.long 0x00 4.--5. "       CP2            ,Access privileges for coprocessor 2" "Access denied,Privileged only,Reserved,Full access"
bitfld.long 0x00 2.--3. "  CP1             ,Access privileges for coprocessor 1" "Access denied,Privileged only,Reserved,Full access"
textline "                     "
bitfld.long 0x00 0.--1. " CP0            ,Access privileges for coprocessor 0" "Access denied,Privileged only,Reserved,Full access"
wgroup.long 0xF00++0x03
line.long 0x00 "STIR,Software Trigger Interrupt Register"
hexmask.long.word 0x00 0.--8. 1. " INTID          ,Indicates the interrupt to be triggered"
width 10.
tree "Feature Registers"
rgroup.long 0xD40++0x0B
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
bitfld.long 0x00 4.--7. " STATE1    ,Thumb instruction set support" ",,,Supported,?..."
bitfld.long 0x00 0.--3. "              STATE0         ,ARM instruction set support" "Not supported,?..."
line.long 0x04 "ID_PFR1,Processor Feature Register 1"
bitfld.long 0x04 8.--11. " MPROF     ,M profile programmers' model" ",,2-stack,?..."
line.long 0x08 "ID_DFR0,Debug Feature Register 0"
bitfld.long 0x08 20.--23. " DBGMOD    ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..."
hgroup.long 0xD4C++0x03
hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
rgroup.long 0xD50++0x03
line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
bitfld.long 0x00 20.--23. " AUXREG    ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..."
bitfld.long 0x00 16.--19. "          TCMSUP         ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
bitfld.long 0x00 12.--15. "        SHRLEV    ,Indicates the number of shareability levels implemented" "Level 1,?..."
textline "                   "
bitfld.long 0x00 8.--11. " OUTMSHR   ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored"
bitfld.long 0x00 4.--7. "          PMSASUP        ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..."
hgroup.long 0xD54++0x03
hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
rgroup.long 0xD58++0x03
line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
bitfld.long 0x00 24.--27. " WFISTALL  ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
rgroup.long 0xD60++0x13
line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
bitfld.long 0x00 24.--27. " DIVIDE    ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
bitfld.long 0x00 20.--23. "          DEBUG          ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
bitfld.long 0x00 16.--19. "        COPROC    ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..."
textline "                   "
bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
bitfld.long 0x00 8.--11. "          BITFIELD       ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
bitfld.long 0x00 4.--7. "    BITCOUNT  ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1"
bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
bitfld.long 0x04 20.--23. "          IMMEDIATE      ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
bitfld.long 0x04 16.--19. "  IFTHEN    ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
textline "                   "
bitfld.long 0x04 12.--15. " EXTEND    ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..."
line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2"
bitfld.long 0x08 24.--27. " REVERSAL  ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
bitfld.long 0x08 20.--23. "   MULTU          ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
bitfld.long 0x08 16.--19. "    MULTS     ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..."
textline "                   "
bitfld.long 0x08 12.--15. " MULT      ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..."
bitfld.long 0x08 8.--11. "          MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
bitfld.long 0x08 4.--7. "  MEMHINT   ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
textline "                   "
bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..."
line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3"
bitfld.long 0x0C 24.--27. " TRUENOP   ,Indicates the support for a true  NOP instruction" "Not supported,Supported,?..."
bitfld.long 0x0C 20.--23. "          THUMBCOPY      ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
bitfld.long 0x0C 16.--19. "        TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
textline "                   "
bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..."
bitfld.long 0x0C 8.--11. "          SVC            ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
bitfld.long 0x0C 4.--7. "        SIMD      ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..."
textline "                   "
bitfld.long 0x0C 0.--3. " SATURATE  ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..."
line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4"
bitfld.long 0x10 24.--27. " PSR_M     ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..."
bitfld.long 0x10 20.--23. "          SYNCHPRIMFRAC  ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..."
bitfld.long 0x10 16.--19. "        BARRIER   ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..."
textline "                   "
bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
bitfld.long 0x10 4.--7. "          WITHSHIFTS     ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..."
bitfld.long 0x10 0.--3. "        UNPRIV    ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..."
tree.end
width 6.
tree "CoreSight Identification Registers"
rgroup.long 0xFE0++0x0F
line.long 0x00 "PID0,Peripheral ID0"
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
line.long 0x04 "PID1,Peripheral ID1"
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
hexmask.long.byte 0x04 0.--3. 1. "  Part_Num[11:8] ,Part Number bits[11:8]"
line.long 0x08 "PID2,Peripheral ID2"
hexmask.long.byte 0x08 4.--7. 1. " Revision      ,Revision"
bitfld.long 0x08 3. "  JEDEC          ,JEDEC assigned ID fields" "0,JEDEC"
hexmask.long.byte 0x08 0.--2. 1. "  JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
line.long 0x0C "PID3,Peripheral ID3"
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd        ,Minor revision field"
hexmask.long.byte 0x0C 0.--3. 1. "  CMB            ,Customer-modified block"
rgroup.long 0xFD0++0x03
line.long 0x00 "PID4,Peripheral Identification Register 4"
hexmask.long.byte 0x00 4.--7. 1. " Count         ,4KB count"
hexmask.long.byte 0x00 0.--3. 1. "  JEP106_CC      ,JEP106 continuation code"
rgroup.long 0xFF0++0x0F
line.long 0x00 "CID0,Component ID0 (Preamble)"
line.long 0x04 "CID1,Component ID1"
hexmask.long.byte 0x04 4.--7. 1. " CC            ,Component Class"
hexmask.long.byte 0x04 0.--3. 1. "  Preamble       ,Preamble"
line.long 0x08 "CID2,Component ID2"
line.long 0x0C "CID3,Component ID3"
tree.end
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Memory Protection Unit"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 15.
rgroup.long 0xD90++0x03
line.long 0x00 "MPU_TYPE,MPU Type Register"
bitfld.long 0x00 16.--23. " IREGION    ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
bitfld.long 0x00 8.--15. "               DREGION   ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
bitfld.long 0x00 0. "                    SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported"
group.long 0xD94++0x03
line.long 0x00 "MPU_CTRL,MPU Control Register"
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
bitfld.long 0x00 1. "         HFNMIENA  ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
bitfld.long 0x00 0. "          ENABLE   ,Enables the MPU" "Disabled,Enabled"
group.long 0xD98++0x03
line.long 0x00 "MPU_RNR,MPU Region Number Register"
hexmask.long.byte 0x00 0.--7. 1. " REGION     ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
tree.close "MPU regions"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
group.long 0xD9C++0x03 "Region 0"
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
group.long 0xD9C++0x03 "Region 1"
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
group.long 0xD9C++0x03 "Region 2"
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
group.long 0xD9C++0x03 "Region 3"
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
group.long 0xD9C++0x03 "Region 4"
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
group.long 0xD9C++0x03 "Region 5"
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
group.long 0xD9C++0x03 "Region 6"
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
group.long 0xD9C++0x03 "Region 7"
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
group.long 0xD9C++0x03 "Region 8"
saveout 0xD98 %l 0x8
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x8
line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
saveout 0xD98 %l 0x8
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x8
hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
group.long 0xD9C++0x03 "Region 9"
saveout 0xD98 %l 0x9
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x9
line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
saveout 0xD98 %l 0x9
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x9
hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
group.long 0xD9C++0x03 "Region 10"
saveout 0xD98 %l 0xA
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xA
line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
saveout 0xD98 %l 0xA
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xA
hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
group.long 0xD9C++0x03 "Region 11"
saveout 0xD98 %l 0xB
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xB
line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
saveout 0xD98 %l 0xB
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xB
hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
group.long 0xD9C++0x03 "Region 12"
saveout 0xD98 %l 0xC
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xC
line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
saveout 0xD98 %l 0xC
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xC
hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
group.long 0xD9C++0x03 "Region 13"
saveout 0xD98 %l 0xD
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xD
line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
saveout 0xD98 %l 0xD
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xD
hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
group.long 0xD9C++0x03 "Region 14"
saveout 0xD98 %l 0xE
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xE
line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
saveout 0xD98 %l 0xE
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xE
hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
group.long 0xD9C++0x03 "Region 15"
saveout 0xD98 %l 0xF
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xF
line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
saveout 0xD98 %l 0xF
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xF
hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
textline "                        "
textline "                        "
endif
tree.end
width 0x0b
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Nested Vectored Interrupt Controller"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 6.
rgroup.long 0x04++0x03
line.long 0x00 "ICTR,Interrupt Controller Type Register"
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..."
tree "Interrupt Enable Registers"
width 23.
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
group.long 0x100++0x03
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
group.long 0x100++0x7
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
group.long 0x100++0x0B
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
group.long 0x100++0x0F
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  ENA99  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  ENA98  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  ENA96  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
group.long 0x100++0x13
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  ENA99  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  ENA98  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  ENA96  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
group.long 0x100++0x17
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  ENA99  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  ENA98  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  ENA96  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
group.long 0x100++0x1B
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  ENA99  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  ENA98  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  ENA96  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 30. 0x18 30. 0x98 30. "  ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 29. 0x18 29. 0x98 29. "  ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 28. 0x18 28. 0x98 28. "  ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 27. 0x18 27. 0x98 27. "  ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 26. 0x18 26. 0x98 26. "  ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 24. 0x18 24. 0x98 24. "  ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 23. 0x18 23. 0x98 23. "  ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 22. 0x18 22. 0x98 22. "  ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 21. 0x18 21. 0x98 21. "  ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 20. 0x18 20. 0x98 20. "  ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 18. 0x18 18. 0x98 18. "  ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 17. 0x18 17. 0x98 17. "  ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 16. 0x18 16. 0x98 16. "  ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 15. 0x18 15. 0x98 15. "  ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 14. 0x18 14. 0x98 14. "  ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 12. 0x18 12. 0x98 12. "  ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 11. 0x18 11. 0x98 11. "  ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 10. 0x18 10. 0x98 10. "  ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 9. 0x18 9. 0x98 9. "  ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 8. 0x18 8. 0x98 8. "  ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 6. 0x18 6. 0x98 6. "  ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 5. 0x18 5. 0x98 5. "  ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 4. 0x18 4. 0x98 4. "  ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 3. 0x18 3. 0x98 3. "  ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 2. 0x18 2. 0x98 2. "  ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 0. 0x18 0. 0x98 0. "  ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
group.long 0x100++0x1F
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  ENA99  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  ENA98  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  ENA96  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 30. 0x18 30. 0x98 30. "  ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 29. 0x18 29. 0x98 29. "  ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 28. 0x18 28. 0x98 28. "  ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 27. 0x18 27. 0x98 27. "  ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 26. 0x18 26. 0x98 26. "  ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 24. 0x18 24. 0x98 24. "  ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 23. 0x18 23. 0x98 23. "  ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 22. 0x18 22. 0x98 22. "  ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 21. 0x18 21. 0x98 21. "  ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 20. 0x18 20. 0x98 20. "  ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 18. 0x18 18. 0x98 18. "  ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 17. 0x18 17. 0x98 17. "  ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 16. 0x18 16. 0x98 16. "  ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 15. 0x18 15. 0x98 15. "  ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 14. 0x18 14. 0x98 14. "  ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 12. 0x18 12. 0x98 12. "  ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 11. 0x18 11. 0x98 11. "  ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 10. 0x18 10. 0x98 10. "  ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 9. 0x18 9. 0x98 9. "  ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 8. 0x18 8. 0x98 8. "  ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 6. 0x18 6. 0x98 6. "  ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 5. 0x18 5. 0x98 5. "  ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 4. 0x18 4. 0x98 4. "  ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 3. 0x18 3. 0x98 3. "  ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 2. 0x18 2. 0x98 2. "  ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 0. 0x18 0. 0x98 0. "  ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. "  ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. "  ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. "  ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. "  ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. "  ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. "  ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. "  ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. "  ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. "  ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. "  ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. "  ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. "  ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. "  ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x100++0x1F
hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
endif
tree.end
tree "Interrupt Pending Registers"
width 23.
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
group.long 0x200++0x03
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
group.long 0x200++0x07
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
group.long 0x200++0x0B
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
group.long 0x200++0x0F
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  PEN99  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  PEN98  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  PEN96  ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
group.long 0x200++0x13
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  PEN99  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  PEN98  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  PEN96  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
group.long 0x200++0x17
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  PEN99  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  PEN98  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  PEN96  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
group.long 0x200++0x1B
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  PEN99  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  PEN98  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  PEN96  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 30. 0x18 30. 0x98 30. "  PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 29. 0x18 29. 0x98 29. "  PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 28. 0x18 28. 0x98 28. "  PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 27. 0x18 27. 0x98 27. "  PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 26. 0x18 26. 0x98 26. "  PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 24. 0x18 24. 0x98 24. "  PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 23. 0x18 23. 0x98 23. "  PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 22. 0x18 22. 0x98 22. "  PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 21. 0x18 21. 0x98 21. "  PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 20. 0x18 20. 0x98 20. "  PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 18. 0x18 18. 0x98 18. "  PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 17. 0x18 17. 0x98 17. "  PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 16. 0x18 16. 0x98 16. "  PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 15. 0x18 15. 0x98 15. "  PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 14. 0x18 14. 0x98 14. "  PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 12. 0x18 12. 0x98 12. "  PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 11. 0x18 11. 0x98 11. "  PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 10. 0x18 10. 0x98 10. "  PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 9. 0x18 9. 0x98 9. "  PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 8. 0x18 8. 0x98 8. "  PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 6. 0x18 6. 0x98 6. "  PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 5. 0x18 5. 0x98 5. "  PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 4. 0x18 4. 0x98 4. "  PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 3. 0x18 3. 0x98 3. "  PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 2. 0x18 2. 0x98 2. "  PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 0. 0x18 0. 0x98 0. "  PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
group.long 0x200++0x1F
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  PEN99  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  PEN98  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  PEN96  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 30. 0x18 30. 0x98 30. "  PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 29. 0x18 29. 0x98 29. "  PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 28. 0x18 28. 0x98 28. "  PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 27. 0x18 27. 0x98 27. "  PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 26. 0x18 26. 0x98 26. "  PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 24. 0x18 24. 0x98 24. "  PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 23. 0x18 23. 0x98 23. "  PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 22. 0x18 22. 0x98 22. "  PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 21. 0x18 21. 0x98 21. "  PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 20. 0x18 20. 0x98 20. "  PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 18. 0x18 18. 0x98 18. "  PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 17. 0x18 17. 0x98 17. "  PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 16. 0x18 16. 0x98 16. "  PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 15. 0x18 15. 0x98 15. "  PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 14. 0x18 14. 0x98 14. "  PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 12. 0x18 12. 0x98 12. "  PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 11. 0x18 11. 0x98 11. "  PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 10. 0x18 10. 0x98 10. "  PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 9. 0x18 9. 0x98 9. "  PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 8. 0x18 8. 0x98 8. "  PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 6. 0x18 6. 0x98 6. "  PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 5. 0x18 5. 0x98 5. "  PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 4. 0x18 4. 0x98 4. "  PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 3. 0x18 3. 0x98 3. "  PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 2. 0x18 2. 0x98 2. "  PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 0. 0x18 0. 0x98 0. "  PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. "  PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. "  PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. "  PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. "  PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. "  PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. "  PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. "  PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. "  PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. "  PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. "  PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. "  PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. "  PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. "  PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x200++0x1F
hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
endif
tree.end
tree "Interrupt Active Bit Registers"
width 9.
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
rgroup.long 0x300++0x03
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
rgroup.long 0x300++0x07
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
rgroup.long 0x300++0x0B
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
rgroup.long 0x300++0x0F
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
line.long 0x0c "ACTIVE4,Active Bit Register 4"
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 30. "  ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 29. "  ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 28. "  ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 27. "  ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 26. "  ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 24. "  ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 23. "  ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 22. "  ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 21. "  ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 20. "  ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 18. "  ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 17. "  ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 16. "  ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 15. "  ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 14. "  ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 12. "  ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 11. "  ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 10. "  ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 9. "  ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 8. "  ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 6. "  ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 5. "  ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 4. "  ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 3. "  ACTIVE99  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 2. "  ACTIVE98  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 1. " ACTIVE97  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 0. "  ACTIVE96  ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
rgroup.long 0x300++0x13
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
line.long 0x0c "ACTIVE4,Active Bit Register 4"
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 30. "  ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 29. "  ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 28. "  ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 27. "  ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 26. "  ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 24. "  ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 23. "  ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 22. "  ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 21. "  ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 20. "  ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 18. "  ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 17. "  ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 16. "  ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 15. "  ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 14. "  ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 12. "  ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 11. "  ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 10. "  ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 9. "  ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 8. "  ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 6. "  ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 5. "  ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 4. "  ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 3. "  ACTIVE99  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 2. "  ACTIVE98  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 1. " ACTIVE97  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 0. "  ACTIVE96  ,Interrupt Active Flag" "Not active,Active"
line.long 0x10 "ACTIVE5,Active Bit Register 5"
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 30. "  ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 29. "  ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 28. "  ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 27. "  ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 26. "  ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 24. "  ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 23. "  ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 22. "  ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 21. "  ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 20. "  ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 18. "  ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 17. "  ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 16. "  ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 15. "  ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 14. "  ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 12. "  ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 11. "  ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 10. "  ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 9. "  ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 8. "  ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 6. "  ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 5. "  ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 4. "  ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 3. "  ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 2. "  ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 0. "  ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
rgroup.long 0x300++0x17
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
line.long 0x0c "ACTIVE4,Active Bit Register 4"
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 30. "  ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 29. "  ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 28. "  ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 27. "  ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 26. "  ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 24. "  ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 23. "  ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 22. "  ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 21. "  ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 20. "  ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 18. "  ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 17. "  ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 16. "  ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 15. "  ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 14. "  ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 12. "  ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 11. "  ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 10. "  ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 9. "  ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 8. "  ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 6. "  ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 5. "  ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 4. "  ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 3. "  ACTIVE99  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 2. "  ACTIVE98  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 1. " ACTIVE97  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 0. "  ACTIVE96  ,Interrupt Active Flag" "Not active,Active"
line.long 0x10 "ACTIVE5,Active Bit Register 5"
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 30. "  ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 29. "  ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 28. "  ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 27. "  ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 26. "  ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 24. "  ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 23. "  ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 22. "  ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 21. "  ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 20. "  ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 18. "  ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 17. "  ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 16. "  ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 15. "  ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 14. "  ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 12. "  ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 11. "  ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 10. "  ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 9. "  ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 8. "  ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 6. "  ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 5. "  ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 4. "  ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 3. "  ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 2. "  ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 0. "  ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
line.long 0x14 "ACTIVE6,Active Bit Register 6"
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 30. "  ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 29. "  ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 28. "  ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 27. "  ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 26. "  ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 24. "  ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 23. "  ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 22. "  ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 21. "  ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 20. "  ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 18. "  ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 17. "  ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 16. "  ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 15. "  ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 14. "  ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 12. "  ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 11. "  ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 10. "  ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 9. "  ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 8. "  ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 6. "  ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 5. "  ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 4. "  ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 3. "  ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 2. "  ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 0. "  ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
rgroup.long 0x300++0x1B
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
line.long 0x0c "ACTIVE4,Active Bit Register 4"
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 30. "  ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 29. "  ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 28. "  ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 27. "  ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 26. "  ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 24. "  ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 23. "  ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 22. "  ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 21. "  ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 20. "  ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 18. "  ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 17. "  ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 16. "  ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 15. "  ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 14. "  ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 12. "  ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 11. "  ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 10. "  ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 9. "  ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 8. "  ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 6. "  ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 5. "  ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 4. "  ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 3. "  ACTIVE99  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 2. "  ACTIVE98  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 1. " ACTIVE97  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 0. "  ACTIVE96  ,Interrupt Active Flag" "Not active,Active"
line.long 0x10 "ACTIVE5,Active Bit Register 5"
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 30. "  ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 29. "  ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 28. "  ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 27. "  ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 26. "  ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 24. "  ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 23. "  ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 22. "  ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 21. "  ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 20. "  ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 18. "  ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 17. "  ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 16. "  ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 15. "  ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 14. "  ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 12. "  ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 11. "  ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 10. "  ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 9. "  ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 8. "  ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 6. "  ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 5. "  ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 4. "  ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 3. "  ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 2. "  ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 0. "  ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
line.long 0x14 "ACTIVE6,Active Bit Register 6"
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 30. "  ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 29. "  ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 28. "  ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 27. "  ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 26. "  ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 24. "  ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 23. "  ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 22. "  ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 21. "  ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 20. "  ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 18. "  ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 17. "  ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 16. "  ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 15. "  ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 14. "  ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 12. "  ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 11. "  ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 10. "  ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 9. "  ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 8. "  ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 6. "  ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 5. "  ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 4. "  ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 3. "  ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 2. "  ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 0. "  ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
line.long 0x18 "ACTIVE7,Active Bit Register 7"
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 30. "  ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 29. "  ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 28. "  ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 27. "  ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 26. "  ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 24. "  ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 23. "  ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 22. "  ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 21. "  ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 20. "  ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 18. "  ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 17. "  ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 16. "  ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 15. "  ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 14. "  ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 12. "  ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 11. "  ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 10. "  ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 9. "  ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 8. "  ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 6. "  ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 5. "  ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 4. "  ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 3. "  ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 2. "  ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 0. "  ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
rgroup.long 0x300++0x1F
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
line.long 0x0c "ACTIVE4,Active Bit Register 4"
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 30. "  ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 29. "  ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 28. "  ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 27. "  ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 26. "  ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 24. "  ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 23. "  ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 22. "  ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 21. "  ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 20. "  ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 18. "  ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 17. "  ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 16. "  ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 15. "  ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 14. "  ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 12. "  ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 11. "  ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 10. "  ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 9. "  ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 8. "  ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 6. "  ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 5. "  ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 4. "  ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 3. "  ACTIVE99  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 2. "  ACTIVE98  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 1. " ACTIVE97  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 0. "  ACTIVE96  ,Interrupt Active Flag" "Not active,Active"
line.long 0x10 "ACTIVE5,Active Bit Register 5"
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 30. "  ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 29. "  ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 28. "  ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 27. "  ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 26. "  ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 24. "  ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 23. "  ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 22. "  ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 21. "  ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 20. "  ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 18. "  ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 17. "  ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 16. "  ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 15. "  ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 14. "  ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 12. "  ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 11. "  ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 10. "  ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 9. "  ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 8. "  ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 6. "  ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 5. "  ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 4. "  ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 3. "  ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 2. "  ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 0. "  ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
line.long 0x14 "ACTIVE6,Active Bit Register 6"
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 30. "  ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 29. "  ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 28. "  ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 27. "  ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 26. "  ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 24. "  ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 23. "  ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 22. "  ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 21. "  ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 20. "  ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 18. "  ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 17. "  ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 16. "  ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 15. "  ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 14. "  ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 12. "  ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 11. "  ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 10. "  ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 9. "  ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 8. "  ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 6. "  ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 5. "  ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 4. "  ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 3. "  ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 2. "  ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 0. "  ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
line.long 0x18 "ACTIVE7,Active Bit Register 7"
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 30. "  ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 29. "  ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 28. "  ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 27. "  ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 26. "  ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 24. "  ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 23. "  ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 22. "  ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 21. "  ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 20. "  ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 18. "  ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 17. "  ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 16. "  ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 15. "  ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 14. "  ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 12. "  ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 11. "  ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 10. "  ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 9. "  ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 8. "  ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 6. "  ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 5. "  ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 4. "  ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 3. "  ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 2. "  ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 0. "  ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
line.long 0x1c "ACTIVE8,Active Bit Register 8"
bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 14. "  ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 13. "  ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 12. "  ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 11. "  ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 10. "  ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 8. "  ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 7. "  ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 6. "  ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 5. "  ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 4. "  ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 2. "  ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 1. "  ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 0. "  ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x300++0x1F
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
hide.long 0x04 "ACTIVE2,Active Bit Register 2"
hide.long 0x08 "ACTIVE3,Active Bit Register 3"
hide.long 0x0c "ACTIVE4,Active Bit Register 4"
hide.long 0x10 "ACTIVE5,Active Bit Register 5"
hide.long 0x14 "ACTIVE6,Active Bit Register 6"
hide.long 0x18 "ACTIVE7,Active Bit Register 7"
hide.long 0x1c "ACTIVE8,Active Bit Register 8"
endif
tree.end
tree "Interrupt Priority Registers"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
group.long 0x400++0x1F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
group.long 0x400++0x3F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
group.long 0x400++0x5F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67  ,Interrupt 67  Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66  ,Interrupt 66  Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65  ,Interrupt 65  Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64  ,Interrupt 64  Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71  ,Interrupt 71  Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70  ,Interrupt 70  Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69  ,Interrupt 69  Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68  ,Interrupt 68  Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75  ,Interrupt 75  Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74  ,Interrupt 74  Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73  ,Interrupt 73  Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72  ,Interrupt 72  Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79  ,Interrupt 79  Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78  ,Interrupt 78  Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77  ,Interrupt 77  Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76  ,Interrupt 76  Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83  ,Interrupt 83  Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82  ,Interrupt 82  Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81  ,Interrupt 81  Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80  ,Interrupt 80  Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87  ,Interrupt 87  Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86  ,Interrupt 86  Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85  ,Interrupt 85  Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84  ,Interrupt 84  Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91  ,Interrupt 91  Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90  ,Interrupt 90  Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89  ,Interrupt 89  Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88  ,Interrupt 88  Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95  ,Interrupt 95  Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94  ,Interrupt 94  Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93  ,Interrupt 93  Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92  ,Interrupt 92  Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
group.long 0x400++0x7F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67  ,Interrupt 67  Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66  ,Interrupt 66  Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65  ,Interrupt 65  Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64  ,Interrupt 64  Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71  ,Interrupt 71  Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70  ,Interrupt 70  Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69  ,Interrupt 69  Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68  ,Interrupt 68  Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75  ,Interrupt 75  Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74  ,Interrupt 74  Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73  ,Interrupt 73  Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72  ,Interrupt 72  Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79  ,Interrupt 79  Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78  ,Interrupt 78  Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77  ,Interrupt 77  Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76  ,Interrupt 76  Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83  ,Interrupt 83  Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82  ,Interrupt 82  Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81  ,Interrupt 81  Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80  ,Interrupt 80  Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87  ,Interrupt 87  Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86  ,Interrupt 86  Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85  ,Interrupt 85  Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84  ,Interrupt 84  Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91  ,Interrupt 91  Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90  ,Interrupt 90  Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89  ,Interrupt 89  Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88  ,Interrupt 88  Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95  ,Interrupt 95  Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94  ,Interrupt 94  Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93  ,Interrupt 93  Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92  ,Interrupt 92  Priority"
line.long 0x60 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x60 24.--31. 1. " PRI_99  ,Interrupt 99  Priority"
hexmask.long.byte 0x60 16.--23. 1. "  PRI_98  ,Interrupt 98  Priority"
hexmask.long.byte 0x60 8.--15. 1. "  PRI_97  ,Interrupt 97  Priority"
hexmask.long.byte 0x60 0.--7. 1. "  PRI_96  ,Interrupt 96  Priority"
line.long 0x64 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x64 16.--23. 1. "  PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x64 8.--15. 1. "  PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x64 0.--7. 1. "  PRI_100 ,Interrupt 100 Priority"
line.long 0x68 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x68 16.--23. 1. "  PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x68 8.--15. 1. "  PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x68 0.--7. 1. "  PRI_104 ,Interrupt 104 Priority"
line.long 0x6C "IPR27,Interrupt Priority Register"
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0x6C 16.--23. 1. "  PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0x6C 8.--15. 1. "  PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0x6C 0.--7. 1. "  PRI_108 ,Interrupt 108 Priority"
line.long 0x70 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x70 16.--23. 1. "  PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x70 8.--15. 1. "  PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x70 0.--7. 1. "  PRI_112 ,Interrupt 112 Priority"
line.long 0x74 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x74 16.--23. 1. "  PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x74 8.--15. 1. "  PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x74 0.--7. 1. "  PRI_116 ,Interrupt 116 Priority"
line.long 0x78 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x78 16.--23. 1. "  PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x78 8.--15. 1. "  PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x78 0.--7. 1. "  PRI_120 ,Interrupt 120 Priority"
line.long 0x7C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x7C 16.--23. 1. "  PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x7C 8.--15. 1. "  PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x7C 0.--7. 1. "  PRI_124 ,Interrupt 124 Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
group.long 0x400++0x9F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67  ,Interrupt 67  Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66  ,Interrupt 66  Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65  ,Interrupt 65  Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64  ,Interrupt 64  Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71  ,Interrupt 71  Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70  ,Interrupt 70  Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69  ,Interrupt 69  Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68  ,Interrupt 68  Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75  ,Interrupt 75  Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74  ,Interrupt 74  Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73  ,Interrupt 73  Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72  ,Interrupt 72  Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79  ,Interrupt 79  Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78  ,Interrupt 78  Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77  ,Interrupt 77  Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76  ,Interrupt 76  Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83  ,Interrupt 83  Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82  ,Interrupt 82  Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81  ,Interrupt 81  Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80  ,Interrupt 80  Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87  ,Interrupt 87  Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86  ,Interrupt 86  Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85  ,Interrupt 85  Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84  ,Interrupt 84  Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91  ,Interrupt 91  Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90  ,Interrupt 90  Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89  ,Interrupt 89  Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88  ,Interrupt 88  Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95  ,Interrupt 95  Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94  ,Interrupt 94  Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93  ,Interrupt 93  Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92  ,Interrupt 92  Priority"
line.long 0x60 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x60 24.--31. 1. " PRI_99  ,Interrupt 99  Priority"
hexmask.long.byte 0x60 16.--23. 1. "  PRI_98  ,Interrupt 98  Priority"
hexmask.long.byte 0x60 8.--15. 1. "  PRI_97  ,Interrupt 97  Priority"
hexmask.long.byte 0x60 0.--7. 1. "  PRI_96  ,Interrupt 96  Priority"
line.long 0x64 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x64 16.--23. 1. "  PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x64 8.--15. 1. "  PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x64 0.--7. 1. "  PRI_100 ,Interrupt 100 Priority"
line.long 0x68 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x68 16.--23. 1. "  PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x68 8.--15. 1. "  PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x68 0.--7. 1. "  PRI_104 ,Interrupt 104 Priority"
line.long 0x6C "IPR27,Interrupt Priority Register"
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0x6C 16.--23. 1. "  PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0x6C 8.--15. 1. "  PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0x6C 0.--7. 1. "  PRI_108 ,Interrupt 108 Priority"
line.long 0x70 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x70 16.--23. 1. "  PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x70 8.--15. 1. "  PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x70 0.--7. 1. "  PRI_112 ,Interrupt 112 Priority"
line.long 0x74 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x74 16.--23. 1. "  PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x74 8.--15. 1. "  PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x74 0.--7. 1. "  PRI_116 ,Interrupt 116 Priority"
line.long 0x78 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x78 16.--23. 1. "  PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x78 8.--15. 1. "  PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x78 0.--7. 1. "  PRI_120 ,Interrupt 120 Priority"
line.long 0x7C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x7C 16.--23. 1. "  PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x7C 8.--15. 1. "  PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x7C 0.--7. 1. "  PRI_124 ,Interrupt 124 Priority"
line.long 0x80 "IPR32,Interrupt Priority Register"
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
hexmask.long.byte 0x80 16.--23. 1. "  PRI_130 ,Interrupt 130 Priority"
hexmask.long.byte 0x80 8.--15. 1. "  PRI_129 ,Interrupt 129 Priority"
hexmask.long.byte 0x80 0.--7. 1. "  PRI_128 ,Interrupt 128 Priority"
line.long 0x84 "IPR33,Interrupt Priority Register"
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
hexmask.long.byte 0x84 16.--23. 1. "  PRI_134 ,Interrupt 134 Priority"
hexmask.long.byte 0x84 8.--15. 1. "  PRI_133 ,Interrupt 133 Priority"
hexmask.long.byte 0x84 0.--7. 1. "  PRI_132 ,Interrupt 132 Priority"
line.long 0x88 "IPR34,Interrupt Priority Register"
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
hexmask.long.byte 0x88 16.--23. 1. "  PRI_138 ,Interrupt 138 Priority"
hexmask.long.byte 0x88 8.--15. 1. "  PRI_137 ,Interrupt 137 Priority"
hexmask.long.byte 0x88 0.--7. 1. "  PRI_136 ,Interrupt 136 Priority"
line.long 0x8C "IPR35,Interrupt Priority Register"
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
hexmask.long.byte 0x8C 16.--23. 1. "  PRI_142 ,Interrupt 142 Priority"
hexmask.long.byte 0x8C 8.--15. 1. "  PRI_141 ,Interrupt 141 Priority"
hexmask.long.byte 0x8C 0.--7. 1. "  PRI_140 ,Interrupt 140 Priority"
line.long 0x90 "IPR36,Interrupt Priority Register"
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
hexmask.long.byte 0x90 16.--23. 1. "  PRI_146 ,Interrupt 146 Priority"
hexmask.long.byte 0x90 8.--15. 1. "  PRI_145 ,Interrupt 145 Priority"
hexmask.long.byte 0x90 0.--7. 1. "  PRI_144 ,Interrupt 144 Priority"
line.long 0x94 "IPR37,Interrupt Priority Register"
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
hexmask.long.byte 0x94 16.--23. 1. "  PRI_150 ,Interrupt 150 Priority"
hexmask.long.byte 0x94 8.--15. 1. "  PRI_149 ,Interrupt 149 Priority"
hexmask.long.byte 0x94 0.--7. 1. "  PRI_148 ,Interrupt 148 Priority"
line.long 0x98 "IPR38,Interrupt Priority Register"
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
hexmask.long.byte 0x98 16.--23. 1. "  PRI_154 ,Interrupt 154 Priority"
hexmask.long.byte 0x98 8.--15. 1. "  PRI_153 ,Interrupt 153 Priority"
hexmask.long.byte 0x98 0.--7. 1. "  PRI_152 ,Interrupt 152 Priority"
line.long 0x9C "IPR39,Interrupt Priority Register"
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
hexmask.long.byte 0x9C 16.--23. 1. "  PRI_158 ,Interrupt 158 Priority"
hexmask.long.byte 0x9C 8.--15. 1. "  PRI_157 ,Interrupt 157 Priority"
hexmask.long.byte 0x9C 0.--7. 1. "  PRI_156 ,Interrupt 156 Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
group.long 0x400++0xBF
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67  ,Interrupt 67  Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66  ,Interrupt 66  Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65  ,Interrupt 65  Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64  ,Interrupt 64  Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71  ,Interrupt 71  Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70  ,Interrupt 70  Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69  ,Interrupt 69  Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68  ,Interrupt 68  Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75  ,Interrupt 75  Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74  ,Interrupt 74  Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73  ,Interrupt 73  Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72  ,Interrupt 72  Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79  ,Interrupt 79  Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78  ,Interrupt 78  Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77  ,Interrupt 77  Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76  ,Interrupt 76  Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83  ,Interrupt 83  Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82  ,Interrupt 82  Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81  ,Interrupt 81  Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80  ,Interrupt 80  Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87  ,Interrupt 87  Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86  ,Interrupt 86  Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85  ,Interrupt 85  Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84  ,Interrupt 84  Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91  ,Interrupt 91  Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90  ,Interrupt 90  Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89  ,Interrupt 89  Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88  ,Interrupt 88  Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95  ,Interrupt 95  Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94  ,Interrupt 94  Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93  ,Interrupt 93  Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92  ,Interrupt 92  Priority"
line.long 0x60 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x60 24.--31. 1. " PRI_99  ,Interrupt 99  Priority"
hexmask.long.byte 0x60 16.--23. 1. "  PRI_98  ,Interrupt 98  Priority"
hexmask.long.byte 0x60 8.--15. 1. "  PRI_97  ,Interrupt 97  Priority"
hexmask.long.byte 0x60 0.--7. 1. "  PRI_96  ,Interrupt 96  Priority"
line.long 0x64 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x64 16.--23. 1. "  PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x64 8.--15. 1. "  PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x64 0.--7. 1. "  PRI_100 ,Interrupt 100 Priority"
line.long 0x68 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x68 16.--23. 1. "  PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x68 8.--15. 1. "  PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x68 0.--7. 1. "  PRI_104 ,Interrupt 104 Priority"
line.long 0x6C "IPR27,Interrupt Priority Register"
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0x6C 16.--23. 1. "  PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0x6C 8.--15. 1. "  PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0x6C 0.--7. 1. "  PRI_108 ,Interrupt 108 Priority"
line.long 0x70 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x70 16.--23. 1. "  PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x70 8.--15. 1. "  PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x70 0.--7. 1. "  PRI_112 ,Interrupt 112 Priority"
line.long 0x74 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x74 16.--23. 1. "  PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x74 8.--15. 1. "  PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x74 0.--7. 1. "  PRI_116 ,Interrupt 116 Priority"
line.long 0x78 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x78 16.--23. 1. "  PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x78 8.--15. 1. "  PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x78 0.--7. 1. "  PRI_120 ,Interrupt 120 Priority"
line.long 0x7C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x7C 16.--23. 1. "  PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x7C 8.--15. 1. "  PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x7C 0.--7. 1. "  PRI_124 ,Interrupt 124 Priority"
line.long 0x80 "IPR32,Interrupt Priority Register"
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
hexmask.long.byte 0x80 16.--23. 1. "  PRI_130 ,Interrupt 130 Priority"
hexmask.long.byte 0x80 8.--15. 1. "  PRI_129 ,Interrupt 129 Priority"
hexmask.long.byte 0x80 0.--7. 1. "  PRI_128 ,Interrupt 128 Priority"
line.long 0x84 "IPR33,Interrupt Priority Register"
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
hexmask.long.byte 0x84 16.--23. 1. "  PRI_134 ,Interrupt 134 Priority"
hexmask.long.byte 0x84 8.--15. 1. "  PRI_133 ,Interrupt 133 Priority"
hexmask.long.byte 0x84 0.--7. 1. "  PRI_132 ,Interrupt 132 Priority"
line.long 0x88 "IPR34,Interrupt Priority Register"
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
hexmask.long.byte 0x88 16.--23. 1. "  PRI_138 ,Interrupt 138 Priority"
hexmask.long.byte 0x88 8.--15. 1. "  PRI_137 ,Interrupt 137 Priority"
hexmask.long.byte 0x88 0.--7. 1. "  PRI_136 ,Interrupt 136 Priority"
line.long 0x8C "IPR35,Interrupt Priority Register"
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
hexmask.long.byte 0x8C 16.--23. 1. "  PRI_142 ,Interrupt 142 Priority"
hexmask.long.byte 0x8C 8.--15. 1. "  PRI_141 ,Interrupt 141 Priority"
hexmask.long.byte 0x8C 0.--7. 1. "  PRI_140 ,Interrupt 140 Priority"
line.long 0x90 "IPR36,Interrupt Priority Register"
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
hexmask.long.byte 0x90 16.--23. 1. "  PRI_146 ,Interrupt 146 Priority"
hexmask.long.byte 0x90 8.--15. 1. "  PRI_145 ,Interrupt 145 Priority"
hexmask.long.byte 0x90 0.--7. 1. "  PRI_144 ,Interrupt 144 Priority"
line.long 0x94 "IPR37,Interrupt Priority Register"
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
hexmask.long.byte 0x94 16.--23. 1. "  PRI_150 ,Interrupt 150 Priority"
hexmask.long.byte 0x94 8.--15. 1. "  PRI_149 ,Interrupt 149 Priority"
hexmask.long.byte 0x94 0.--7. 1. "  PRI_148 ,Interrupt 148 Priority"
line.long 0x98 "IPR38,Interrupt Priority Register"
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
hexmask.long.byte 0x98 16.--23. 1. "  PRI_154 ,Interrupt 154 Priority"
hexmask.long.byte 0x98 8.--15. 1. "  PRI_153 ,Interrupt 153 Priority"
hexmask.long.byte 0x98 0.--7. 1. "  PRI_152 ,Interrupt 152 Priority"
line.long 0x9C "IPR39,Interrupt Priority Register"
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
hexmask.long.byte 0x9C 16.--23. 1. "  PRI_158 ,Interrupt 158 Priority"
hexmask.long.byte 0x9C 8.--15. 1. "  PRI_157 ,Interrupt 157 Priority"
hexmask.long.byte 0x9C 0.--7. 1. "  PRI_156 ,Interrupt 156 Priority"
line.long 0xA0 "IPR40,Interrupt Priority Register"
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
hexmask.long.byte 0xA0 16.--23. 1. "  PRI_162 ,Interrupt 162 Priority"
hexmask.long.byte 0xA0 8.--15. 1. "  PRI_161 ,Interrupt 161 Priority"
hexmask.long.byte 0xA0 0.--7. 1. "  PRI_160 ,Interrupt 160 Priority"
line.long 0xA4 "IPR41,Interrupt Priority Register"
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
hexmask.long.byte 0xA4 16.--23. 1. "  PRI_166 ,Interrupt 166 Priority"
hexmask.long.byte 0xA4 8.--15. 1. "  PRI_165 ,Interrupt 165 Priority"
hexmask.long.byte 0xA4 0.--7. 1. "  PRI_164 ,Interrupt 164 Priority"
line.long 0xA8 "IPR42,Interrupt Priority Register"
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
hexmask.long.byte 0xA8 16.--23. 1. "  PRI_170 ,Interrupt 170 Priority"
hexmask.long.byte 0xA8 8.--15. 1. "  PRI_169 ,Interrupt 169 Priority"
hexmask.long.byte 0xA8 0.--7. 1. "  PRI_168 ,Interrupt 168 Priority"
line.long 0xAC "IPR43,Interrupt Priority Register"
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
hexmask.long.byte 0xAC 16.--23. 1. "  PRI_174 ,Interrupt 174 Priority"
hexmask.long.byte 0xAC 8.--15. 1. "  PRI_173 ,Interrupt 173 Priority"
hexmask.long.byte 0xAC 0.--7. 1. "  PRI_172 ,Interrupt 172 Priority"
line.long 0xB0 "IPR44,Interrupt Priority Register"
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
hexmask.long.byte 0xB0 16.--23. 1. "  PRI_178 ,Interrupt 178 Priority"
hexmask.long.byte 0xB0 8.--15. 1. "  PRI_177 ,Interrupt 177 Priority"
hexmask.long.byte 0xB0 0.--7. 1. "  PRI_176 ,Interrupt 176 Priority"
line.long 0xB4 "IPR45,Interrupt Priority Register"
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
hexmask.long.byte 0xB4 16.--23. 1. "  PRI_182 ,Interrupt 182 Priority"
hexmask.long.byte 0xB4 8.--15. 1. "  PRI_181 ,Interrupt 181 Priority"
hexmask.long.byte 0xB4 0.--7. 1. "  PRI_180 ,Interrupt 180 Priority"
line.long 0xB8 "IPR46,Interrupt Priority Register"
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
hexmask.long.byte 0xB8 16.--23. 1. "  PRI_186 ,Interrupt 186 Priority"
hexmask.long.byte 0xB8 8.--15. 1. "  PRI_185 ,Interrupt 185 Priority"
hexmask.long.byte 0xB8 0.--7. 1. "  PRI_184 ,Interrupt 184 Priority"
line.long 0xBC "IPR47,Interrupt Priority Register"
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
hexmask.long.byte 0xBC 16.--23. 1. "  PRI_190 ,Interrupt 190 Priority"
hexmask.long.byte 0xBC 8.--15. 1. "  PRI_189 ,Interrupt 189 Priority"
hexmask.long.byte 0xBC 0.--7. 1. "  PRI_188 ,Interrupt 188 Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
group.long 0x400++0xDF
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67  ,Interrupt 67  Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66  ,Interrupt 66  Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65  ,Interrupt 65  Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64  ,Interrupt 64  Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71  ,Interrupt 71  Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70  ,Interrupt 70  Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69  ,Interrupt 69  Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68  ,Interrupt 68  Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75  ,Interrupt 75  Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74  ,Interrupt 74  Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73  ,Interrupt 73  Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72  ,Interrupt 72  Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79  ,Interrupt 79  Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78  ,Interrupt 78  Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77  ,Interrupt 77  Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76  ,Interrupt 76  Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83  ,Interrupt 83  Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82  ,Interrupt 82  Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81  ,Interrupt 81  Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80  ,Interrupt 80  Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87  ,Interrupt 87  Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86  ,Interrupt 86  Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85  ,Interrupt 85  Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84  ,Interrupt 84  Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91  ,Interrupt 91  Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90  ,Interrupt 90  Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89  ,Interrupt 89  Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88  ,Interrupt 88  Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95  ,Interrupt 95  Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94  ,Interrupt 94  Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93  ,Interrupt 93  Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92  ,Interrupt 92  Priority"
line.long 0x60 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x60 24.--31. 1. " PRI_99  ,Interrupt 99  Priority"
hexmask.long.byte 0x60 16.--23. 1. "  PRI_98  ,Interrupt 98  Priority"
hexmask.long.byte 0x60 8.--15. 1. "  PRI_97  ,Interrupt 97  Priority"
hexmask.long.byte 0x60 0.--7. 1. "  PRI_96  ,Interrupt 96  Priority"
line.long 0x64 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x64 16.--23. 1. "  PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x64 8.--15. 1. "  PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x64 0.--7. 1. "  PRI_100 ,Interrupt 100 Priority"
line.long 0x68 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x68 16.--23. 1. "  PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x68 8.--15. 1. "  PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x68 0.--7. 1. "  PRI_104 ,Interrupt 104 Priority"
line.long 0x6C "IPR27,Interrupt Priority Register"
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0x6C 16.--23. 1. "  PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0x6C 8.--15. 1. "  PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0x6C 0.--7. 1. "  PRI_108 ,Interrupt 108 Priority"
line.long 0x70 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x70 16.--23. 1. "  PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x70 8.--15. 1. "  PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x70 0.--7. 1. "  PRI_112 ,Interrupt 112 Priority"
line.long 0x74 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x74 16.--23. 1. "  PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x74 8.--15. 1. "  PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x74 0.--7. 1. "  PRI_116 ,Interrupt 116 Priority"
line.long 0x78 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x78 16.--23. 1. "  PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x78 8.--15. 1. "  PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x78 0.--7. 1. "  PRI_120 ,Interrupt 120 Priority"
line.long 0x7C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x7C 16.--23. 1. "  PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x7C 8.--15. 1. "  PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x7C 0.--7. 1. "  PRI_124 ,Interrupt 124 Priority"
line.long 0x80 "IPR32,Interrupt Priority Register"
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
hexmask.long.byte 0x80 16.--23. 1. "  PRI_130 ,Interrupt 130 Priority"
hexmask.long.byte 0x80 8.--15. 1. "  PRI_129 ,Interrupt 129 Priority"
hexmask.long.byte 0x80 0.--7. 1. "  PRI_128 ,Interrupt 128 Priority"
line.long 0x84 "IPR33,Interrupt Priority Register"
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
hexmask.long.byte 0x84 16.--23. 1. "  PRI_134 ,Interrupt 134 Priority"
hexmask.long.byte 0x84 8.--15. 1. "  PRI_133 ,Interrupt 133 Priority"
hexmask.long.byte 0x84 0.--7. 1. "  PRI_132 ,Interrupt 132 Priority"
line.long 0x88 "IPR34,Interrupt Priority Register"
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
hexmask.long.byte 0x88 16.--23. 1. "  PRI_138 ,Interrupt 138 Priority"
hexmask.long.byte 0x88 8.--15. 1. "  PRI_137 ,Interrupt 137 Priority"
hexmask.long.byte 0x88 0.--7. 1. "  PRI_136 ,Interrupt 136 Priority"
line.long 0x8C "IPR35,Interrupt Priority Register"
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
hexmask.long.byte 0x8C 16.--23. 1. "  PRI_142 ,Interrupt 142 Priority"
hexmask.long.byte 0x8C 8.--15. 1. "  PRI_141 ,Interrupt 141 Priority"
hexmask.long.byte 0x8C 0.--7. 1. "  PRI_140 ,Interrupt 140 Priority"
line.long 0x90 "IPR36,Interrupt Priority Register"
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
hexmask.long.byte 0x90 16.--23. 1. "  PRI_146 ,Interrupt 146 Priority"
hexmask.long.byte 0x90 8.--15. 1. "  PRI_145 ,Interrupt 145 Priority"
hexmask.long.byte 0x90 0.--7. 1. "  PRI_144 ,Interrupt 144 Priority"
line.long 0x94 "IPR37,Interrupt Priority Register"
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
hexmask.long.byte 0x94 16.--23. 1. "  PRI_150 ,Interrupt 150 Priority"
hexmask.long.byte 0x94 8.--15. 1. "  PRI_149 ,Interrupt 149 Priority"
hexmask.long.byte 0x94 0.--7. 1. "  PRI_148 ,Interrupt 148 Priority"
line.long 0x98 "IPR38,Interrupt Priority Register"
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
hexmask.long.byte 0x98 16.--23. 1. "  PRI_154 ,Interrupt 154 Priority"
hexmask.long.byte 0x98 8.--15. 1. "  PRI_153 ,Interrupt 153 Priority"
hexmask.long.byte 0x98 0.--7. 1. "  PRI_152 ,Interrupt 152 Priority"
line.long 0x9C "IPR39,Interrupt Priority Register"
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
hexmask.long.byte 0x9C 16.--23. 1. "  PRI_158 ,Interrupt 158 Priority"
hexmask.long.byte 0x9C 8.--15. 1. "  PRI_157 ,Interrupt 157 Priority"
hexmask.long.byte 0x9C 0.--7. 1. "  PRI_156 ,Interrupt 156 Priority"
line.long 0xA0 "IPR40,Interrupt Priority Register"
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
hexmask.long.byte 0xA0 16.--23. 1. "  PRI_162 ,Interrupt 162 Priority"
hexmask.long.byte 0xA0 8.--15. 1. "  PRI_161 ,Interrupt 161 Priority"
hexmask.long.byte 0xA0 0.--7. 1. "  PRI_160 ,Interrupt 160 Priority"
line.long 0xA4 "IPR41,Interrupt Priority Register"
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
hexmask.long.byte 0xA4 16.--23. 1. "  PRI_166 ,Interrupt 166 Priority"
hexmask.long.byte 0xA4 8.--15. 1. "  PRI_165 ,Interrupt 165 Priority"
hexmask.long.byte 0xA4 0.--7. 1. "  PRI_164 ,Interrupt 164 Priority"
line.long 0xA8 "IPR42,Interrupt Priority Register"
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
hexmask.long.byte 0xA8 16.--23. 1. "  PRI_170 ,Interrupt 170 Priority"
hexmask.long.byte 0xA8 8.--15. 1. "  PRI_169 ,Interrupt 169 Priority"
hexmask.long.byte 0xA8 0.--7. 1. "  PRI_168 ,Interrupt 168 Priority"
line.long 0xAC "IPR43,Interrupt Priority Register"
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
hexmask.long.byte 0xAC 16.--23. 1. "  PRI_174 ,Interrupt 174 Priority"
hexmask.long.byte 0xAC 8.--15. 1. "  PRI_173 ,Interrupt 173 Priority"
hexmask.long.byte 0xAC 0.--7. 1. "  PRI_172 ,Interrupt 172 Priority"
line.long 0xB0 "IPR44,Interrupt Priority Register"
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
hexmask.long.byte 0xB0 16.--23. 1. "  PRI_178 ,Interrupt 178 Priority"
hexmask.long.byte 0xB0 8.--15. 1. "  PRI_177 ,Interrupt 177 Priority"
hexmask.long.byte 0xB0 0.--7. 1. "  PRI_176 ,Interrupt 176 Priority"
line.long 0xB4 "IPR45,Interrupt Priority Register"
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
hexmask.long.byte 0xB4 16.--23. 1. "  PRI_182 ,Interrupt 182 Priority"
hexmask.long.byte 0xB4 8.--15. 1. "  PRI_181 ,Interrupt 181 Priority"
hexmask.long.byte 0xB4 0.--7. 1. "  PRI_180 ,Interrupt 180 Priority"
line.long 0xB8 "IPR46,Interrupt Priority Register"
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
hexmask.long.byte 0xB8 16.--23. 1. "  PRI_186 ,Interrupt 186 Priority"
hexmask.long.byte 0xB8 8.--15. 1. "  PRI_185 ,Interrupt 185 Priority"
hexmask.long.byte 0xB8 0.--7. 1. "  PRI_184 ,Interrupt 184 Priority"
line.long 0xBC "IPR47,Interrupt Priority Register"
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
hexmask.long.byte 0xBC 16.--23. 1. "  PRI_190 ,Interrupt 190 Priority"
hexmask.long.byte 0xBC 8.--15. 1. "  PRI_189 ,Interrupt 189 Priority"
hexmask.long.byte 0xBC 0.--7. 1. "  PRI_188 ,Interrupt 188 Priority"
line.long 0xC0 "IPR48,Interrupt Priority Register"
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
hexmask.long.byte 0xC0 16.--23. 1. "  PRI_194 ,Interrupt 194 Priority"
hexmask.long.byte 0xC0 8.--15. 1. "  PRI_193 ,Interrupt 193 Priority"
hexmask.long.byte 0xC0 0.--7. 1. "  PRI_192 ,Interrupt 192 Priority"
line.long 0xC4 "IPR49,Interrupt Priority Register"
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
hexmask.long.byte 0xC4 16.--23. 1. "  PRI_198 ,Interrupt 198 Priority"
hexmask.long.byte 0xC4 8.--15. 1. "  PRI_197 ,Interrupt 197 Priority"
hexmask.long.byte 0xC4 0.--7. 1. "  PRI_196 ,Interrupt 196 Priority"
line.long 0xC8 "IPR50,Interrupt Priority Register"
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
hexmask.long.byte 0xC8 16.--23. 1. "  PRI_202 ,Interrupt 202 Priority"
hexmask.long.byte 0xC8 8.--15. 1. "  PRI_201 ,Interrupt 201 Priority"
hexmask.long.byte 0xC8 0.--7. 1. "  PRI_200 ,Interrupt 200 Priority"
line.long 0xCC "IPR51,Interrupt Priority Register"
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
hexmask.long.byte 0xCC 16.--23. 1. "  PRI_206 ,Interrupt 206 Priority"
hexmask.long.byte 0xCC 8.--15. 1. "  PRI_205 ,Interrupt 205 Priority"
hexmask.long.byte 0xCC 0.--7. 1. "  PRI_204 ,Interrupt 204 Priority"
line.long 0xD0 "IPR52,Interrupt Priority Register"
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
hexmask.long.byte 0xD0 16.--23. 1. "  PRI_210 ,Interrupt 210 Priority"
hexmask.long.byte 0xD0 8.--15. 1. "  PRI_209 ,Interrupt 209 Priority"
hexmask.long.byte 0xD0 0.--7. 1. "  PRI_208 ,Interrupt 208 Priority"
line.long 0xD4 "IPR53,Interrupt Priority Register"
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
hexmask.long.byte 0xD4 16.--23. 1. "  PRI_214 ,Interrupt 214 Priority"
hexmask.long.byte 0xD4 8.--15. 1. "  PRI_213 ,Interrupt 213 Priority"
hexmask.long.byte 0xD4 0.--7. 1. "  PRI_212 ,Interrupt 212 Priority"
line.long 0xD8 "IPR54,Interrupt Priority Register"
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
hexmask.long.byte 0xD8 16.--23. 1. "  PRI_218 ,Interrupt 218 Priority"
hexmask.long.byte 0xD8 8.--15. 1. "  PRI_217 ,Interrupt 217 Priority"
hexmask.long.byte 0xD8 0.--7. 1. "  PRI_216 ,Interrupt 216 Priority"
line.long 0xDC "IPR55,Interrupt Priority Register"
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
hexmask.long.byte 0xDC 16.--23. 1. "  PRI_222 ,Interrupt 222 Priority"
hexmask.long.byte 0xDC 8.--15. 1. "  PRI_221 ,Interrupt 221 Priority"
hexmask.long.byte 0xDC 0.--7. 1. "  PRI_220 ,Interrupt 220 Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
group.long 0x400++0xEF
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2 ,Interrupt 2 Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1 ,Interrupt 1 Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0 ,Interrupt 0 Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6 ,Interrupt 6 Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5 ,Interrupt 5 Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4 ,Interrupt 4 Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10 ,Interrupt 10 Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9 ,Interrupt 9 Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8 ,Interrupt 8 Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14 ,Interrupt 14 Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13 ,Interrupt 13 Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12 ,Interrupt 12 Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18 ,Interrupt 18 Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17 ,Interrupt 17 Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16 ,Interrupt 16 Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22 ,Interrupt 22 Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21 ,Interrupt 21 Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20 ,Interrupt 20 Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26 ,Interrupt 26 Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25 ,Interrupt 25 Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24 ,Interrupt 24 Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30 ,Interrupt 30 Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29 ,Interrupt 29 Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28 ,Interrupt 28 Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34 ,Interrupt 34 Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33 ,Interrupt 33 Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32 ,Interrupt 32 Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38 ,Interrupt 38 Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37 ,Interrupt 37 Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36 ,Interrupt 36 Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42 ,Interrupt 42 Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41 ,Interrupt 41 Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40 ,Interrupt 40 Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46 ,Interrupt 46 Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45 ,Interrupt 45 Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44 ,Interrupt 44 Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50 ,Interrupt 50 Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49 ,Interrupt 49 Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48 ,Interrupt 48 Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54 ,Interrupt 54 Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53 ,Interrupt 53 Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52 ,Interrupt 52 Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58 ,Interrupt 58 Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57 ,Interrupt 57 Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56 ,Interrupt 56 Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62 ,Interrupt 62 Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61 ,Interrupt 61 Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60 ,Interrupt 60 Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66 ,Interrupt 66 Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65 ,Interrupt 65 Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64 ,Interrupt 64 Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70 ,Interrupt 70 Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69 ,Interrupt 69 Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68 ,Interrupt 68 Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74 ,Interrupt 74 Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73 ,Interrupt 73 Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72 ,Interrupt 72 Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78 ,Interrupt 78 Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77 ,Interrupt 77 Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76 ,Interrupt 76 Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82 ,Interrupt 82 Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81 ,Interrupt 81 Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80 ,Interrupt 80 Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86 ,Interrupt 86 Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85 ,Interrupt 85 Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84 ,Interrupt 84 Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90 ,Interrupt 90 Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89 ,Interrupt 89 Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88 ,Interrupt 88 Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94 ,Interrupt 94 Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93 ,Interrupt 93 Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92 ,Interrupt 92 Priority"
line.long 0x60 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
hexmask.long.byte 0x60 16.--23. 1. "  PRI_98 ,Interrupt 98 Priority"
hexmask.long.byte 0x60 8.--15. 1. "  PRI_97 ,Interrupt 97 Priority"
hexmask.long.byte 0x60 0.--7. 1. "  PRI_96 ,Interrupt 96 Priority"
line.long 0x64 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x64 16.--23. 1. "  PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x64 8.--15. 1. "  PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x64 0.--7. 1. "  PRI_100 ,Interrupt 100 Priority"
line.long 0x68 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x68 16.--23. 1. "  PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x68 8.--15. 1. "  PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x68 0.--7. 1. "  PRI_104 ,Interrupt 104 Priority"
line.long 0x6C "IPR27,Interrupt Priority Register"
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0x6C 16.--23. 1. "  PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0x6C 8.--15. 1. "  PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0x6C 0.--7. 1. "  PRI_108 ,Interrupt 108 Priority"
line.long 0x70 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x70 16.--23. 1. "  PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x70 8.--15. 1. "  PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x70 0.--7. 1. "  PRI_112 ,Interrupt 112 Priority"
line.long 0x74 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x74 16.--23. 1. "  PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x74 8.--15. 1. "  PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x74 0.--7. 1. "  PRI_116 ,Interrupt 116 Priority"
line.long 0x78 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x78 16.--23. 1. "  PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x78 8.--15. 1. "  PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x78 0.--7. 1. "  PRI_120 ,Interrupt 120 Priority"
line.long 0x7C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x7C 16.--23. 1. "  PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x7C 8.--15. 1. "  PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x7C 0.--7. 1. "  PRI_124 ,Interrupt 124 Priority"
line.long 0x80 "IPR32,Interrupt Priority Register"
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
hexmask.long.byte 0x80 16.--23. 1. "  PRI_130 ,Interrupt 130 Priority"
hexmask.long.byte 0x80 8.--15. 1. "  PRI_129 ,Interrupt 129 Priority"
hexmask.long.byte 0x80 0.--7. 1. "  PRI_128 ,Interrupt 128 Priority"
line.long 0x84 "IPR33,Interrupt Priority Register"
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
hexmask.long.byte 0x84 16.--23. 1. "  PRI_134 ,Interrupt 134 Priority"
hexmask.long.byte 0x84 8.--15. 1. "  PRI_133 ,Interrupt 133 Priority"
hexmask.long.byte 0x84 0.--7. 1. "  PRI_132 ,Interrupt 132 Priority"
line.long 0x88 "IPR34,Interrupt Priority Register"
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
hexmask.long.byte 0x88 16.--23. 1. "  PRI_138 ,Interrupt 138 Priority"
hexmask.long.byte 0x88 8.--15. 1. "  PRI_137 ,Interrupt 137 Priority"
hexmask.long.byte 0x88 0.--7. 1. "  PRI_136 ,Interrupt 136 Priority"
line.long 0x8C "IPR35,Interrupt Priority Register"
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
hexmask.long.byte 0x8C 16.--23. 1. "  PRI_142 ,Interrupt 142 Priority"
hexmask.long.byte 0x8C 8.--15. 1. "  PRI_141 ,Interrupt 141 Priority"
hexmask.long.byte 0x8C 0.--7. 1. "  PRI_140 ,Interrupt 140 Priority"
line.long 0x90 "IPR36,Interrupt Priority Register"
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
hexmask.long.byte 0x90 16.--23. 1. "  PRI_146 ,Interrupt 146 Priority"
hexmask.long.byte 0x90 8.--15. 1. "  PRI_145 ,Interrupt 145 Priority"
hexmask.long.byte 0x90 0.--7. 1. "  PRI_144 ,Interrupt 144 Priority"
line.long 0x94 "IPR37,Interrupt Priority Register"
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
hexmask.long.byte 0x94 16.--23. 1. "  PRI_150 ,Interrupt 150 Priority"
hexmask.long.byte 0x94 8.--15. 1. "  PRI_149 ,Interrupt 149 Priority"
hexmask.long.byte 0x94 0.--7. 1. "  PRI_148 ,Interrupt 148 Priority"
line.long 0x98 "IPR38,Interrupt Priority Register"
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
hexmask.long.byte 0x98 16.--23. 1. "  PRI_154 ,Interrupt 154 Priority"
hexmask.long.byte 0x98 8.--15. 1. "  PRI_153 ,Interrupt 153 Priority"
hexmask.long.byte 0x98 0.--7. 1. "  PRI_152 ,Interrupt 152 Priority"
line.long 0x9C "IPR39,Interrupt Priority Register"
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
hexmask.long.byte 0x9C 16.--23. 1. "  PRI_158 ,Interrupt 158 Priority"
hexmask.long.byte 0x9C 8.--15. 1. "  PRI_157 ,Interrupt 157 Priority"
hexmask.long.byte 0x9C 0.--7. 1. "  PRI_156 ,Interrupt 156 Priority"
line.long 0xA0 "IPR40,Interrupt Priority Register"
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
hexmask.long.byte 0xA0 16.--23. 1. "  PRI_162 ,Interrupt 162 Priority"
hexmask.long.byte 0xA0 8.--15. 1. "  PRI_161 ,Interrupt 161 Priority"
hexmask.long.byte 0xA0 0.--7. 1. "  PRI_160 ,Interrupt 160 Priority"
line.long 0xA4 "IPR41,Interrupt Priority Register"
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
hexmask.long.byte 0xA4 16.--23. 1. "  PRI_166 ,Interrupt 166 Priority"
hexmask.long.byte 0xA4 8.--15. 1. "  PRI_165 ,Interrupt 165 Priority"
hexmask.long.byte 0xA4 0.--7. 1. "  PRI_164 ,Interrupt 164 Priority"
line.long 0xA8 "IPR42,Interrupt Priority Register"
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
hexmask.long.byte 0xA8 16.--23. 1. "  PRI_170 ,Interrupt 170 Priority"
hexmask.long.byte 0xA8 8.--15. 1. "  PRI_169 ,Interrupt 169 Priority"
hexmask.long.byte 0xA8 0.--7. 1. "  PRI_168 ,Interrupt 168 Priority"
line.long 0xAC "IPR43,Interrupt Priority Register"
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
hexmask.long.byte 0xAC 16.--23. 1. "  PRI_174 ,Interrupt 174 Priority"
hexmask.long.byte 0xAC 8.--15. 1. "  PRI_173 ,Interrupt 173 Priority"
hexmask.long.byte 0xAC 0.--7. 1. "  PRI_172 ,Interrupt 172 Priority"
line.long 0xB0 "IPR44,Interrupt Priority Register"
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
hexmask.long.byte 0xB0 16.--23. 1. "  PRI_178 ,Interrupt 178 Priority"
hexmask.long.byte 0xB0 8.--15. 1. "  PRI_177 ,Interrupt 177 Priority"
hexmask.long.byte 0xB0 0.--7. 1. "  PRI_176 ,Interrupt 176 Priority"
line.long 0xB4 "IPR45,Interrupt Priority Register"
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
hexmask.long.byte 0xB4 16.--23. 1. "  PRI_182 ,Interrupt 182 Priority"
hexmask.long.byte 0xB4 8.--15. 1. "  PRI_181 ,Interrupt 181 Priority"
hexmask.long.byte 0xB4 0.--7. 1. "  PRI_180 ,Interrupt 180 Priority"
line.long 0xB8 "IPR46,Interrupt Priority Register"
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
hexmask.long.byte 0xB8 16.--23. 1. "  PRI_186 ,Interrupt 186 Priority"
hexmask.long.byte 0xB8 8.--15. 1. "  PRI_185 ,Interrupt 185 Priority"
hexmask.long.byte 0xB8 0.--7. 1. "  PRI_184 ,Interrupt 184 Priority"
line.long 0xBC "IPR47,Interrupt Priority Register"
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
hexmask.long.byte 0xBC 16.--23. 1. "  PRI_190 ,Interrupt 190 Priority"
hexmask.long.byte 0xBC 8.--15. 1. "  PRI_189 ,Interrupt 189 Priority"
hexmask.long.byte 0xBC 0.--7. 1. "  PRI_188 ,Interrupt 188 Priority"
line.long 0xC0 "IPR48,Interrupt Priority Register"
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
hexmask.long.byte 0xC0 16.--23. 1. "  PRI_194 ,Interrupt 194 Priority"
hexmask.long.byte 0xC0 8.--15. 1. "  PRI_193 ,Interrupt 193 Priority"
hexmask.long.byte 0xC0 0.--7. 1. "  PRI_192 ,Interrupt 192 Priority"
line.long 0xC4 "IPR49,Interrupt Priority Register"
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
hexmask.long.byte 0xC4 16.--23. 1. "  PRI_198 ,Interrupt 198 Priority"
hexmask.long.byte 0xC4 8.--15. 1. "  PRI_197 ,Interrupt 197 Priority"
hexmask.long.byte 0xC4 0.--7. 1. "  PRI_196 ,Interrupt 196 Priority"
line.long 0xC8 "IPR50,Interrupt Priority Register"
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
hexmask.long.byte 0xC8 16.--23. 1. "  PRI_202 ,Interrupt 202 Priority"
hexmask.long.byte 0xC8 8.--15. 1. "  PRI_201 ,Interrupt 201 Priority"
hexmask.long.byte 0xC8 0.--7. 1. "  PRI_200 ,Interrupt 200 Priority"
line.long 0xCC "IPR51,Interrupt Priority Register"
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
hexmask.long.byte 0xCC 16.--23. 1. "  PRI_206 ,Interrupt 206 Priority"
hexmask.long.byte 0xCC 8.--15. 1. "  PRI_205 ,Interrupt 205 Priority"
hexmask.long.byte 0xCC 0.--7. 1. "  PRI_204 ,Interrupt 204 Priority"
line.long 0xD0 "IPR52,Interrupt Priority Register"
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
hexmask.long.byte 0xD0 16.--23. 1. "  PRI_210 ,Interrupt 210 Priority"
hexmask.long.byte 0xD0 8.--15. 1. "  PRI_209 ,Interrupt 209 Priority"
hexmask.long.byte 0xD0 0.--7. 1. "  PRI_208 ,Interrupt 208 Priority"
line.long 0xD4 "IPR53,Interrupt Priority Register"
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
hexmask.long.byte 0xD4 16.--23. 1. "  PRI_214 ,Interrupt 214 Priority"
hexmask.long.byte 0xD4 8.--15. 1. "  PRI_213 ,Interrupt 213 Priority"
hexmask.long.byte 0xD4 0.--7. 1. "  PRI_212 ,Interrupt 212 Priority"
line.long 0xD8 "IPR54,Interrupt Priority Register"
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
hexmask.long.byte 0xD8 16.--23. 1. "  PRI_218 ,Interrupt 218 Priority"
hexmask.long.byte 0xD8 8.--15. 1. "  PRI_217 ,Interrupt 217 Priority"
hexmask.long.byte 0xD8 0.--7. 1. "  PRI_216 ,Interrupt 216 Priority"
line.long 0xDC "IPR55,Interrupt Priority Register"
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
hexmask.long.byte 0xDC 16.--23. 1. "  PRI_222 ,Interrupt 222 Priority"
hexmask.long.byte 0xDC 8.--15. 1. "  PRI_221 ,Interrupt 221 Priority"
hexmask.long.byte 0xDC 0.--7. 1. "  PRI_220 ,Interrupt 220 Priority"
line.long 0xE0 "IPR56,Interrupt Priority Register"
hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
hexmask.long.byte 0xE0 16.--23. 1. "  PRI_226 ,Interrupt 226 Priority"
hexmask.long.byte 0xE0 8.--15. 1. "  PRI_225 ,Interrupt 225 Priority"
hexmask.long.byte 0xE0 0.--7. 1. "  PRI_224 ,Interrupt 224 Priority"
line.long 0xE4 "IPR57,Interrupt Priority Register"
hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
hexmask.long.byte 0xE4 16.--23. 1. "  PRI_230 ,Interrupt 230 Priority"
hexmask.long.byte 0xE4 8.--15. 1. "  PRI_229 ,Interrupt 229 Priority"
hexmask.long.byte 0xE4 0.--7. 1. "  PRI_228 ,Interrupt 228 Priority"
line.long 0xE8 "IPR58,Interrupt Priority Register"
hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
hexmask.long.byte 0xE8 16.--23. 1. "  PRI_234 ,Interrupt 234 Priority"
hexmask.long.byte 0xE8 8.--15. 1. "  PRI_233 ,Interrupt 233 Priority"
hexmask.long.byte 0xE8 0.--7. 1. "  PRI_232 ,Interrupt 232 Priority"
line.long 0xEC "IPR59,Interrupt Priority Register"
hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
hexmask.long.byte 0xEC 16.--23. 1. "  PRI_238 ,Interrupt 238 Priority"
hexmask.long.byte 0xEC 8.--15. 1. "  PRI_237 ,Interrupt 237 Priority"
hexmask.long.byte 0xEC 0.--7. 1. "  PRI_236 ,Interrupt 236 Priority"
else
hgroup.long 0x400++0xEF
hide.long 0x0 "IPR0,Interrupt Priority Register"
hide.long 0x4 "IPR1,Interrupt Priority Register"
hide.long 0x8 "IPR2,Interrupt Priority Register"
hide.long 0xC "IPR3,Interrupt Priority Register"
hide.long 0x10 "IPR4,Interrupt Priority Register"
hide.long 0x14 "IPR5,Interrupt Priority Register"
hide.long 0x18 "IPR6,Interrupt Priority Register"
hide.long 0x1C "IPR7,Interrupt Priority Register"
hide.long 0x20 "IPR8,Interrupt Priority Register"
hide.long 0x24 "IPR9,Interrupt Priority Register"
hide.long 0x28 "IPR10,Interrupt Priority Register"
hide.long 0x2C "IPR11,Interrupt Priority Register"
hide.long 0x30 "IPR12,Interrupt Priority Register"
hide.long 0x34 "IPR13,Interrupt Priority Register"
hide.long 0x38 "IPR14,Interrupt Priority Register"
hide.long 0x3C "IPR15,Interrupt Priority Register"
hide.long 0x40 "IPR16,Interrupt Priority Register"
hide.long 0x44 "IPR17,Interrupt Priority Register"
hide.long 0x48 "IPR18,Interrupt Priority Register"
hide.long 0x4C "IPR19,Interrupt Priority Register"
hide.long 0x50 "IPR20,Interrupt Priority Register"
hide.long 0x54 "IPR21,Interrupt Priority Register"
hide.long 0x58 "IPR22,Interrupt Priority Register"
hide.long 0x5C "IPR23,Interrupt Priority Register"
hide.long 0x60 "IPR24,Interrupt Priority Register"
hide.long 0x64 "IPR25,Interrupt Priority Register"
hide.long 0x68 "IPR26,Interrupt Priority Register"
hide.long 0x6C "IPR27,Interrupt Priority Register"
hide.long 0x70 "IPR28,Interrupt Priority Register"
hide.long 0x74 "IPR29,Interrupt Priority Register"
hide.long 0x78 "IPR30,Interrupt Priority Register"
hide.long 0x7C "IPR31,Interrupt Priority Register"
hide.long 0x80 "IPR32,Interrupt Priority Register"
hide.long 0x84 "IPR33,Interrupt Priority Register"
hide.long 0x88 "IPR34,Interrupt Priority Register"
hide.long 0x8C "IPR35,Interrupt Priority Register"
hide.long 0x90 "IPR36,Interrupt Priority Register"
hide.long 0x94 "IPR37,Interrupt Priority Register"
hide.long 0x98 "IPR38,Interrupt Priority Register"
hide.long 0x9C "IPR39,Interrupt Priority Register"
hide.long 0xA0 "IPR40,Interrupt Priority Register"
hide.long 0xA4 "IPR41,Interrupt Priority Register"
hide.long 0xA8 "IPR42,Interrupt Priority Register"
hide.long 0xAC "IPR43,Interrupt Priority Register"
hide.long 0xB0 "IPR44,Interrupt Priority Register"
hide.long 0xB4 "IPR45,Interrupt Priority Register"
hide.long 0xB8 "IPR46,Interrupt Priority Register"
hide.long 0xBC "IPR47,Interrupt Priority Register"
hide.long 0xC0 "IPR48,Interrupt Priority Register"
hide.long 0xC4 "IPR49,Interrupt Priority Register"
hide.long 0xC8 "IPR50,Interrupt Priority Register"
hide.long 0xCC "IPR51,Interrupt Priority Register"
hide.long 0xD0 "IPR52,Interrupt Priority Register"
hide.long 0xD4 "IPR53,Interrupt Priority Register"
hide.long 0xD8 "IPR54,Interrupt Priority Register"
hide.long 0xDC "IPR55,Interrupt Priority Register"
hide.long 0xE0 "IPR56,Interrupt Priority Register"
hide.long 0xE4 "IPR57,Interrupt Priority Register"
hide.long 0xE8 "IPR58,Interrupt Priority Register"
hide.long 0xEC "IPR59,Interrupt Priority Register"
endif
tree.end
width 0x0b
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
sif CORENAME()=="CORTEXM4F"
tree "Floating-point Unit (FPU)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 8.
group.long 0xF34++0x0B
line.long 0x00 "FPCCR,Floating-Point Context Control Register"
bitfld.long 0x00 31. " ASPEN        ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled"
bitfld.long 0x00 30. "                      LSPEN    ,Enables lazy context save of FP state" "Disabled,Enabled"
bitfld.long 0x00 8. "       MONRDY  ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able"
textline "                 "
bitfld.long 0x00 6. " BFRDY        ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able"
bitfld.long 0x00 5. "                      MMRDY    ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able"
bitfld.long 0x00 4. "       HFRDY   ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able"
textline "                 "
bitfld.long 0x00 3. " THREAD       ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread"
bitfld.long 0x00 1. "                       USER     ,Indicates the privilege level of the software executing" "Privileged,Unprivileged"
bitfld.long 0x00 0. "   LSPACT  ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active"
line.long 0x04 "FPCAR,Floating-Point Context Address Register"
hexmask.long 0x04 3.--31. 0x8 " ADDRESS      ,The location of the unpopulated floating-point register space allocated on an exception stack frame"
line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register"
bitfld.long 0x08 26. " AHP          ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative"
bitfld.long 0x08 25. "                 DN       ,Default value for FPSCR.DN" "NaN operands,Any operation"
bitfld.long 0x08 24. "  FZ      ,Default value for FPSCR.FZ" "No Flush mode,Flush mode"
textline "                 "
bitfld.long 0x08 22.--23. " RMODE        ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero"
rgroup.long 0xF40++0x07
line.long 0x00 "MVFR0,Media and FP Feature Register 0"
bitfld.long 0x00 28.--31. " FPRNDMOD     ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..."
bitfld.long 0x00 24.--27. "                 SRTERR   ,Indicates the hardware support for FP short vectors" "Not supported,?..."
bitfld.long 0x00 20.--23. "  SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..."
textline "                 "
bitfld.long 0x00 16.--19. " DIV          ,Indicates the hardware support for FP divide operations" ",Supported,?..."
bitfld.long 0x00 12.--15. "                     FPEXTRP  ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..."
bitfld.long 0x00 8.--11. "  DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..."
textline "                 "
bitfld.long 0x00 4.--7. " SNGLPREC     ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..."
bitfld.long 0x00 0.--3. "                     A_SIMD   ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..."
line.long 0x04 "MVFR1,Media and FP Feature Register 1"
bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..."
bitfld.long 0x04 24.--27. "                     FP_HPFP  ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..."
textline "                 "
bitfld.long 0x04 4.--7. " D_NAN        ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..."
bitfld.long 0x04 0.--3. "               FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..."
width 0xB
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
endif
tree "Debug"
tree "Core Debug"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 7.
group.long 0xD30++0x03
line.long 0x00 "DFSR,Debug Fault Status Register"
eventfld.long 0x00 4. " EXTERNAL     ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
eventfld.long 0x00 3. "  VCATCH     ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
eventfld.long 0x00 2. "  DWTTRAP    ,Indicates a debug event generated by the DWT" "Not generated,Generated"
newline
eventfld.long 0x00 1. " BKPT         ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
eventfld.long 0x00 0. "  HALTED     ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
newline
hgroup.long 0xDF0++0x03
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
in
newline
wgroup.long 0xDF4++0x03
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
bitfld.long 0x00 16. " REGWNR       ,Register Read/Write" "Read,Write"
hexmask.long.byte 0x00 0.--6. 1. "          REGSEL     ,Specifies the ARM core register or special-purpose register or Floating-point extension register"
group.long 0xDF8++0x03
line.long 0x00 "DCRDR,Debug Core Register Data Register"
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
group.long 0xDFC++0x03
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x00 24. " TRCENA       ,Global enable for all DWT and ITM features" "Disabled,Enabled"
bitfld.long 0x00 19. "       MON_REQ    ,DebugMonitor semaphore bit" "0,1"
bitfld.long 0x00 18. "              MON_STEP   ,Setting this bit to 1 makes the step request pending" "No step,Step"
newline
bitfld.long 0x00 17. " MON_PEND     ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
bitfld.long 0x00 16. "    MON_EN     ,Enable the DebugMonitor exception" "Disabled,Enabled"
bitfld.long 0x00 10. "       VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
newline
bitfld.long 0x00 9. " VC_INTERR    ,Enable halting debug trap" "Disabled,Enabled"
bitfld.long 0x00 8. "       VC_BUSERR  ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
bitfld.long 0x00 7. "       VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
newline
bitfld.long 0x00 6. " VC_CHKERR    ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
bitfld.long 0x00 5. "       VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
bitfld.long 0x00 4. "       VC_MMERR   ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
newline
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
else
group.long 0xDFC++0x03
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x00 24. " TRCENA       ,Global enable for all DWT and ITM features" "Disabled,Enabled"
bitfld.long 0x00 19. "       MON_REQ    ,DebugMonitor semaphore bit" "0,1"
newline
bitfld.long 0x00 17. " MON_PEND     ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
bitfld.long 0x00 16. "    MON_EN     ,Enable the DebugMonitor exception" "Disabled,Enabled"
bitfld.long 0x00 10. "       VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
newline
bitfld.long 0x00 9. " VC_INTERR    ,Enable halting debug trap" "Disabled,Enabled"
bitfld.long 0x00 8. "       VC_BUSERR  ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
bitfld.long 0x00 7. "       VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
newline
bitfld.long 0x00 6. " VC_CHKERR    ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
bitfld.long 0x00 5. "       VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
bitfld.long 0x00 4. "       VC_MMERR   ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
newline
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
endif
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Flash Patch and Breakpoint Unit (FPB)"
sif COMPonent.AVAILABLE("FPB")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
width 10.
group.long 0x00++0x07
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
bitfld.long 0x00 28.--31. " REV     ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..."
rbitfld.long 0x00 4.--7. 12.--14. "     NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
bitfld.long 0x00 1. "  KEY   ,Key Field" "Low,High"
bitfld.long 0x00 0. "      ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
textline ""
line.long 0x04 "FP_REMAP,Flash Patch Remap Register"
bitfld.long 0x04 29. " RMPSPT  ,Indicates whether the FPB unit supports flash patch remap" "Not supported,SRAM region"
hexmask.long.tbyte 0x04 5.--28. 0x20 "               REMAP ,Remap Base Address Field"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0x8++0x03
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP  ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
group.long 0x8++0x03
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0x8++0x03
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE    ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0xC++0x03
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP  ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
group.long 0xC++0x03
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0xC++0x03
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE    ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0x10++0x03
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP  ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
group.long 0x10++0x03
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0x10++0x03
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE    ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0x14++0x03
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP  ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
group.long 0x14++0x03
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0x14++0x03
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE    ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0x18++0x03
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP  ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00)
group.long 0x18++0x03
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0x18++0x03
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE    ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0x1C++0x03
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP  ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00)
group.long 0x1C++0x03
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0x1C++0x03
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE    ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0x20++0x03
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP  ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00)
group.long 0x20++0x03
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0x20++0x03
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE    ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0x24++0x03
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP  ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00)
group.long 0x24++0x03
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0x24++0x03
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE    ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
width 6.
tree "CoreSight Identification Registers"
rgroup.long 0xFE0++0x0F
line.long 0x00 "PID0,Peripheral ID0"
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
line.long 0x04 "PID1,Peripheral ID1"
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
hexmask.long.byte 0x04 0.--3. 1. "  Part_Num[11:8] ,Part Number bits[11:8]"
line.long 0x08 "PID2,Peripheral ID2"
hexmask.long.byte 0x08 4.--7. 1. " Revision      ,Revision"
bitfld.long 0x08 3. "  JEDEC          ,JEDEC assigned ID fields" "0,JEDEC"
hexmask.long.byte 0x08 0.--2. 1. "  JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
line.long 0x0c "PID3,Peripheral ID3"
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd        ,Minor revision field"
hexmask.long.byte 0x0C 0.--3. 1. "  CMB            ,Customer-modified block"
rgroup.long 0xFD0++0x03
line.long 0x00 "PID4,Peripheral Identification Register 4"
hexmask.long.byte 0x00 4.--7. 1. " Count         ,4KB count"
hexmask.long.byte 0x00 0.--3. 1. "  JEP106_CC      ,JEP106 continuation code"
rgroup.long 0xFF0++0x0F
line.long 0x00 "CID0,Component ID0 (Preamble)"
line.long 0x04 "CID1,Component ID1"
hexmask.long.byte 0x04 4.--7. 1. " CC            ,Component Class"
hexmask.long.byte 0x04 0.--3. 1. "  Preamble       ,Preamble"
line.long 0x08 "CID2,Component ID2"
line.long 0x0c "CID3,Component ID3"
tree.end
width 0xB
else
newline
textline "FPB component base address not specified"
newline
endif
tree.end
tree "Data Watchpoint and Trace Unit (DWT)"
sif COMPonent.AVAILABLE("DWT")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
width 15.
group.long 0x00++0x1B
line.long 0x00 "DWT_CTRL,Control Register"
rbitfld.long 0x00 28.--31. " NUMCOMP     ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 27. "             NOTRCPKT   ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
rbitfld.long 0x00 26. "  NOEXTTRIG   ,Shows whether the implementation includes external match signals" "Supported,Not supported"
textline "                        "
rbitfld.long 0x00 25. " NOCYCCNT    ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
rbitfld.long 0x00 24. "  NOPRFCNT   ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
bitfld.long 0x00 22. "  CYCEVTENA   ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 21. " FOLDEVTENA  ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 20. "       LSUEVTENA  ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 19. "       SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 18. " EXCEVTENA   ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 17. "       CPIEVTENA  ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 16. "       EXCTRCENA   ,Enables generation of exception trace" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
bitfld.long 0x00 10.--11. "       SYNCTAP    ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
bitfld.long 0x00 9. "     CYCTAP      ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
textline "                        "
bitfld.long 0x00 5.--8. " POSTINIT    ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1.--4. "             POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "             CYCCNTENA   ,Enables CYCCNT" "Disabled,Enabled"
line.long 0x04 "DWT_CYCCNT,Cycle Count Register"
line.long 0x08 "DWT_CPICNT,CPI Count Register"
hexmask.long.byte 0x08 0.--7. 1. " CPICNT      ,The base CPI counter"
line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register"
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT      ,The exception overhead counter"
line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register"
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT    ,Sleep Counter"
line.long 0x14 "DWT_LSUCNT,LSU Count Register"
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT      ,Load-store counter"
line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count Register"
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT     ,Folded-instruction counter"
rgroup.long 0x1C++0x03
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
textline "                        "
group.long 0x20++0x07
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
line.long 0x04 "DWT_MASK0,DWT Mask Registers 0"
bitfld.long 0x04 0.--4. " MASK        ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20)
group.long 0x28++0x03
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 7. " CYCMATCH    ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
bitfld.long 0x00 5. "    EMITRANGE  ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "       FUNCTION   ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00)
group.long 0x28++0x03
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 7. " CYCMATCH    ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
bitfld.long 0x00 5. "    EMITRANGE  ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "       FUNCTION   ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80)
group.long 0x28++0x03
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 7. " CYCMATCH    ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
bitfld.long 0x00 5. "    EMITRANGE  ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "       FUNCTION   ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
else
group.long 0x28++0x03
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 7. " CYCMATCH    ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
bitfld.long 0x00 5. "    EMITRANGE  ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "       FUNCTION   ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
endif
group.long (0x30)++0x07
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
line.long 0x04 "DWT_MASK1,DWT Mask Registers 1"
bitfld.long 0x04 0.--4. " MASK        ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20)
group.long (0x30+0x08)++0x03
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00)
group.long (0x30+0x08)++0x03
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
else
group.long (0x30+0x08)++0x03
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
endif
group.long (0x40)++0x07
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
line.long 0x04 "DWT_MASK2,DWT Mask Registers 2"
bitfld.long 0x04 0.--4. " MASK        ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20)
group.long (0x40+0x08)++0x03
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00)
group.long (0x40+0x08)++0x03
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
else
group.long (0x40+0x08)++0x03
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
endif
group.long (0x50)++0x07
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
line.long 0x04 "DWT_MASK3,DWT Mask Registers 3"
bitfld.long 0x04 0.--4. " MASK        ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20)
group.long (0x50+0x08)++0x03
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00)
group.long (0x50+0x08)++0x03
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
else
group.long (0x50+0x08)++0x03
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
endif
width 6.
tree "CoreSight Identification Registers"
rgroup.long 0xFE0++0x0F
line.long 0x00 "PID0,Peripheral ID0"
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
line.long 0x04 "PID1,Peripheral ID1"
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
hexmask.long.byte 0x04 0.--3. 1. "  Part_Num[11:8] ,Part Number bits[11:8]"
line.long 0x08 "PID2,Peripheral ID2"
hexmask.long.byte 0x08 4.--7. 1. " Revision      ,Revision"
bitfld.long 0x08 3. "  JEDEC          ,JEDEC assigned ID fields" "0,JEDEC"
hexmask.long.byte 0x08 0.--2. 1. "  JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
line.long 0x0c "PID3,Peripheral ID3"
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd        ,Minor revision field"
hexmask.long.byte 0x0C 0.--3. 1. "  CMB            ,Customer-modified block"
rgroup.long 0xFD0++0x03
line.long 0x00 "PID4,Peripheral Identification Register 4"
hexmask.long.byte 0x00 4.--7. 1. " Count         ,4KB count"
hexmask.long.byte 0x00 0.--3. 1. "  JEP106_CC      ,JEP106 continuation code"
rgroup.long 0xFF0++0x0F
line.long 0x00 "CID0,Component ID0 (Preamble)"
line.long 0x04 "CID1,Component ID1"
hexmask.long.byte 0x04 4.--7. 1. " CC            ,Component Class"
hexmask.long.byte 0x04 0.--3. 1. "  Preamble       ,Preamble"
line.long 0x08 "CID2,Component ID2"
line.long 0x0c "CID3,Component ID3"
tree.end
width 0x0B
else
newline
textline "DWT component base address not specified"
newline
endif
tree.end
tree.end
AUTOINDENT.POP
tree.end
endif
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54113*")||cpuis("LPC54114*")||cpuis("LPC54605*")||cpuis("LPC54606*")||cpuis("LPC54607*")||cpuis("LPC54608*")||cpuis("LPC54616*")||cpuis("LPC54618*")||cpuis("LPC54628*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
base ad:0x400A0000
elif (cpuis("LPC54101*")||cpuis("LPC54102*"))
base ad:0x1C034000
endif
tree "ADC (12-bit ADC Controller)"
group.long 0x0++0x3
line.long 0x0 "CTRL,ADC Control register. Contains the clock divide value. resolution selection. sampling time selection. and mode controls."
bitfld.long 0x0 12.--14. "TSAMP,Sample Time. The default sampling period (TSAMP = '000') at the start of each conversion is 2.5 ADC clock periods. Depending on a variety of factors  including operating conditions and the output impedance of the analog source  longer sampling.." "0,1,2,3,4,5,6,7"
bitfld.long 0x0 11. "BYPASSCAL,Bypass Calibration. This bit may be set to avoid the need to calibrate if offset error is not a concern in the application." "0: Calibrate. The stored calibration value will be..,1: Bypass calibration. Calibration is not utilized."
newline
bitfld.long 0x0 9.--10. "RESOL,The number of bits of ADC resolution. Accuracy can be reduced to achieve higher conversion rates. A single conversion (including one conversion in a burst or sequence) requires the selected number of bits of resolution plus 3 ADC clocks. This field.." "0: 6-bit resolution. An ADC conversion requires 9..,1: 8-bit resolution. An ADC conversion requires 11..,2: 10-bit resolution. An ADC conversion requires 13..,3: 12-bit resolution. An ADC conversion requires 15.."
bitfld.long 0x0 8. "ASYNMODE,Select clock mode." "0: Synchronous mode. The ADC clock is derived from..,1: Asynchronous mode. The ADC clock is based on the.."
newline
hexmask.long.byte 0x0 0.--7. 1. "CLKDIV,In synchronous mode only  the system clock is divided by this value plus one to produce the clock for the ADC converter  which should be less than or equal to 72 MHz. Typically  software should program the smallest value in this field that yields.."
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
group.long 0x4++0x3
line.long 0x0 "INSEL,Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0."
bitfld.long 0x0 0.--1. "SEL,Selects the input source for channel 0. All other values are reserved." "0: ADC0_IN0 function.,?,?,3: Internal temperature sensor."
endif
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x8)++0x3
line.long 0x0 "SEQ_CTRL$1,ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n."
bitfld.long 0x0 31. "SEQ_ENA,Sequence Enable. In order to avoid spuriously triggering the sequence  care should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state (as defined by the TRIGPOL bit). If this condition is not met  the.." "0: Disabled. Sequence n is disabled. Sequence n..,1: Enabled. Sequence n is enabled."
bitfld.long 0x0 30. "MODE,Indicates whether the primary method for retrieving conversion results for this sequence will be accomplished via reading the global data register (SEQA_GDAT) at the end of each conversion  or the individual channel result registers at the end of.." "0: End of conversion. The sequence A interrupt/DMA..,1: End of sequence. The sequence A interrupt/DMA.."
newline
bitfld.long 0x0 29. "LOWPRIO,Set priority for sequence A." "0: Low priority. Any B trigger which occurs while..,1: High priority. Setting this bit to a 1 will.."
bitfld.long 0x0 28. "SINGLESTEP,When this bit is set  a hardware trigger or a write to the START bit will launch a single conversion on the next channel in the sequence instead of the default response of launching an entire sequence of conversions. Once all of the channels.." "0,1"
newline
bitfld.long 0x0 27. "BURST,Writing a 1 to this bit will cause this conversion sequence to be continuously cycled through. Other sequence A triggers will be ignored while this bit is set. Repeated conversions can be halted by clearing this bit. The sequence currently in.." "0,1"
bitfld.long 0x0 26. "START,Writing a 1 to this field will launch one pass through this conversion sequence. The behavior will be identical to a sequence triggered by a hardware trigger. Do not write 1 to this bit if the BURST bit is set. This bit is only set to a 1.." "0,1"
newline
bitfld.long 0x0 19. "SYNCBYPASS,Setting this bit allows the hardware trigger input to bypass synchronization flip-flop stages and therefore shorten the time between the trigger input signal and the start of a conversion. There are slightly different criteria for whether or.." "0: Enable trigger synchronization. The hardware..,1: Bypass trigger synchronization. The hardware.."
bitfld.long 0x0 18. "TRIGPOL,Select the polarity of the selected input trigger for this conversion sequence. In order to avoid generating a spurious trigger  it is recommended writing to this field only when SEQA_ENA (bit 31) is low. It is safe to change this field and set.." "0: Negative edge. A negative edge launches the..,1: Positive edge. A positive edge launches the.."
newline
hexmask.long.byte 0x0 12.--17. 1. "TRIGGER,Selects which of the available hardware trigger sources will cause this conversion sequence to be initiated. Program the trigger input number in this field. See Table 476. In order to avoid generating a spurious trigger  it is recommended writing.."
hexmask.long.word 0x0 0.--11. 1. "CHANNELS,Selects which one or more of the ADC channels will be sampled and converted when this sequence is launched. A 1 in any bit of this field will cause the corresponding channel to be included in the conversion sequence  where bit 0 corresponds to.."
repeat.end
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x10)++0x3
line.long 0x0 "SEQ_GDAT$1,ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n."
bitfld.long 0x0 31. "DATAVALID,This bit is set to '1' at the end of each conversion when a new result is loaded into the RESULT field. It is cleared whenever this register is read. This bit will cause a conversion-complete interrupt for the corresponding sequence if the MODE.." "0,1"
bitfld.long 0x0 30. "OVERRUN,This bit is set if a new conversion result is loaded into the RESULT field before a previous result has been read - i.e. while the DATAVALID bit is set. This bit is cleared  along with the DATAVALID bit  whenever this register is read. This bit.." "0,1"
newline
hexmask.long.byte 0x0 26.--29. 1. "CHN,These bits contain the channel from which the RESULT bits were converted (e.g. 0000 identifies channel 0  0001 channel 1  etc.)."
bitfld.long 0x0 18.--19. "THCMPCROSS,Indicates whether the result of the last conversion performed represented a crossing of the threshold level established by the designated LOW threshold comparison register (THRn_LOW) and  if so  in what direction the crossing occurred." "0,1,2,3"
newline
bitfld.long 0x0 16.--17. "THCMPRANGE,Indicates whether the result of the last conversion performed was above  below or within the range established by the designated threshold comparison registers (THRn_LOW and THRn_HIGH)." "0,1,2,3"
hexmask.long.word 0x0 4.--15. 1. "RESULT,This field contains the 12-bit ADC conversion result from the most recent conversion performed under conversion sequence associated with this register. The result is a binary fraction representing the voltage on the currently-selected input.."
repeat.end
repeat 12. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x20)++0x3
line.long 0x0 "DAT[$1],ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0."
bitfld.long 0x0 31. "DATAVALID,This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to.." "0,1"
bitfld.long 0x0 30. "OVERRUN,This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared  along with the DONE bit  whenever.." "0,1"
newline
hexmask.long.byte 0x0 26.--29. 1. "CHANNEL,This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register  0b0001 for the DAT1 register  etc)"
bitfld.long 0x0 18.--19. "THCMPCROSS,Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold.." "0: No threshold Crossing detected: The most recent..,1: Reserved,2: Downward Threshold Crossing Detected,3: Upward Threshold Crossing Detected"
newline
bitfld.long 0x0 16.--17. "THCMPRANGE,Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the.." "0: In Range: The last completed conversion was..,1: Below Range: The last completed conversion on..,2: Above Range: The last completed conversion was..,3: Reserved"
hexmask.long.word 0x0 4.--15. 1. "RESULT,This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin  as it falls within the range of VREFP to VREFN. Zero in the field.."
repeat.end
sif (cpuis("LPC54113*"))
group.long 0x4++0x3
line.long 0x0 "INSEL,Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0."
bitfld.long 0x0 0.--1. "SEL,Selects the input source for channel 0. All other values are reserved." "0: ADC0_IN0 function.,?,?,3: Internal temperature sensor."
endif
sif (cpuis("LPC54114*"))
group.long 0x4++0x3
line.long 0x0 "INSEL,Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0."
bitfld.long 0x0 0.--1. "SEL,Selects the input source for channel 0. All other values are reserved." "0: ADC0_IN0 function.,?,?,3: Internal temperature sensor."
endif
sif (cpuis("LPC54605*"))
group.long 0x4++0x3
line.long 0x0 "INSEL,Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0."
bitfld.long 0x0 0.--1. "SEL,Selects the input source for channel 0. All other values are reserved." "0: ADC0_IN0 function.,?,?,3: Internal temperature sensor."
endif
sif (cpuis("LPC54606*"))
group.long 0x4++0x3
line.long 0x0 "INSEL,Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0."
bitfld.long 0x0 0.--1. "SEL,Selects the input source for channel 0. All other values are reserved." "0: ADC0_IN0 function.,?,?,3: Internal temperature sensor."
endif
sif (cpuis("LPC54607*"))
group.long 0x4++0x3
line.long 0x0 "INSEL,Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0."
bitfld.long 0x0 0.--1. "SEL,Selects the input source for channel 0. All other values are reserved." "0: ADC0_IN0 function.,?,?,3: Internal temperature sensor."
endif
sif (cpuis("LPC54608*"))
group.long 0x4++0x3
line.long 0x0 "INSEL,Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0."
bitfld.long 0x0 0.--1. "SEL,Selects the input source for channel 0. All other values are reserved." "0: ADC0_IN0 function.,?,?,3: Internal temperature sensor."
endif
sif (cpuis("LPC54616*"))
group.long 0x4++0x3
line.long 0x0 "INSEL,Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0."
bitfld.long 0x0 0.--1. "SEL,Selects the input source for channel 0. All other values are reserved." "0: ADC0_IN0 function.,?,?,3: Internal temperature sensor."
endif
sif (cpuis("LPC54618*"))
group.long 0x4++0x3
line.long 0x0 "INSEL,Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0."
bitfld.long 0x0 0.--1. "SEL,Selects the input source for channel 0. All other values are reserved." "0: ADC0_IN0 function.,?,?,3: Internal temperature sensor."
endif
sif (cpuis("LPC54628*"))
group.long 0x4++0x3
line.long 0x0 "INSEL,Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0."
bitfld.long 0x0 0.--1. "SEL,Selects the input source for channel 0. All other values are reserved." "0: ADC0_IN0 function.,?,?,3: Internal temperature sensor."
endif
group.long 0x50++0x23
line.long 0x0 "THR0_LOW,ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0."
hexmask.long.word 0x0 4.--15. 1. "THRLOW,Low threshold value against which ADC results will be compared"
line.long 0x4 "THR1_LOW,ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1."
hexmask.long.word 0x4 4.--15. 1. "THRLOW,Low threshold value against which ADC results will be compared"
line.long 0x8 "THR0_HIGH,ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0."
hexmask.long.word 0x8 4.--15. 1. "THRHIGH,High threshold value against which ADC results will be compared"
line.long 0xC "THR1_HIGH,ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1."
hexmask.long.word 0xC 4.--15. 1. "THRHIGH,High threshold value against which ADC results will be compared"
line.long 0x10 "CHAN_THRSEL,ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel"
bitfld.long 0x10 11. "CH11_THRSEL,Threshold select for channel 11. See description for channel 0." "0,1"
bitfld.long 0x10 10. "CH10_THRSEL,Threshold select for channel 10. See description for channel 0." "0,1"
newline
bitfld.long 0x10 9. "CH9_THRSEL,Threshold select for channel 9. See description for channel 0." "0,1"
bitfld.long 0x10 8. "CH8_THRSEL,Threshold select for channel 8. See description for channel 0." "0,1"
newline
bitfld.long 0x10 7. "CH7_THRSEL,Threshold select for channel 7. See description for channel 0." "0,1"
bitfld.long 0x10 6. "CH6_THRSEL,Threshold select for channel 6. See description for channel 0." "0,1"
newline
bitfld.long 0x10 5. "CH5_THRSEL,Threshold select for channel 5. See description for channel 0." "0,1"
bitfld.long 0x10 4. "CH4_THRSEL,Threshold select for channel 4. See description for channel 0." "0,1"
newline
bitfld.long 0x10 3. "CH3_THRSEL,Threshold select for channel 3. See description for channel 0." "0,1"
bitfld.long 0x10 2. "CH2_THRSEL,Threshold select for channel 2. See description for channel 0." "0,1"
newline
bitfld.long 0x10 1. "CH1_THRSEL,Threshold select for channel 1. See description for channel 0." "0,1"
bitfld.long 0x10 0. "CH0_THRSEL,Threshold select for channel 0." "0: Threshold 0. Results for this channel will be..,1: Threshold 1. Results for this channel will be.."
line.long 0x14 "INTEN,ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A. sequence-B. threshold compare and data overrun interrupts to be generated."
bitfld.long 0x14 25.--26. "ADCMPINTEN11,Channel 21 threshold comparison interrupt enable. See description for channel 0." "0,1,2,3"
bitfld.long 0x14 23.--24. "ADCMPINTEN10,Channel 10 threshold comparison interrupt enable. See description for channel 0." "0,1,2,3"
newline
bitfld.long 0x14 21.--22. "ADCMPINTEN9,Channel 9 threshold comparison interrupt enable. See description for channel 0." "0,1,2,3"
bitfld.long 0x14 19.--20. "ADCMPINTEN8,Channel 8 threshold comparison interrupt enable. See description for channel 0." "0,1,2,3"
newline
bitfld.long 0x14 17.--18. "ADCMPINTEN7,Channel 7 threshold comparison interrupt enable. See description for channel 0." "0,1,2,3"
bitfld.long 0x14 15.--16. "ADCMPINTEN6,Channel 6 threshold comparison interrupt enable. See description for channel 0." "0,1,2,3"
newline
bitfld.long 0x14 13.--14. "ADCMPINTEN5,Channel 5 threshold comparison interrupt enable. See description for channel 0." "0,1,2,3"
bitfld.long 0x14 11.--12. "ADCMPINTEN4,Channel 4 threshold comparison interrupt enable. See description for channel 0." "0,1,2,3"
newline
bitfld.long 0x14 9.--10. "ADCMPINTEN3,Channel 3 threshold comparison interrupt enable. See description for channel 0." "0,1,2,3"
bitfld.long 0x14 7.--8. "ADCMPINTEN2,Channel 2 threshold comparison interrupt enable. See description for channel 0." "0,1,2,3"
newline
bitfld.long 0x14 5.--6. "ADCMPINTEN1,Channel 1 threshold comparison interrupt enable. See description for channel 0." "0,1,2,3"
bitfld.long 0x14 3.--4. "ADCMPINTEN0,Threshold comparison interrupt enable for channel 0." "0: Disabled.,1: Outside threshold.,2: Crossing threshold.,?"
newline
bitfld.long 0x14 2. "OVR_INTEN,Overrun interrupt enable." "0: Disabled. The overrun interrupt is disabled.,1: Enabled. The overrun interrupt is enabled."
bitfld.long 0x14 1. "SEQB_INTEN,Sequence B interrupt enable." "0: Disabled. The sequence B interrupt/DMA trigger..,1: Enabled. The sequence B interrupt/DMA trigger is.."
newline
bitfld.long 0x14 0. "SEQA_INTEN,Sequence A interrupt enable." "0: Disabled. The sequence A interrupt/DMA trigger..,1: Enabled. The sequence A interrupt/DMA trigger is.."
line.long 0x18 "FLAGS,ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers)."
rbitfld.long 0x18 31. "OVR_INT,Overrun Interrupt flag. Any overrun bit in any of the individual channel data registers will cause this interrupt. In addition  if the MODE bit in either of the SEQn_CTRL registers is 0 then the OVERRUN bit in the corresponding SEQn_GDAT register.." "0,1"
rbitfld.long 0x18 30. "THCMP_INT,Threshold Comparison Interrupt. This bit will be set if any of the THCMP flags in the lower bits of this register are set to 1 (due to an enabled out-of-range or threshold-crossing event on any channel). Each type of threshold comparison.." "0,1"
newline
rbitfld.long 0x18 29. "SEQB_INT,Sequence A interrupt/DMA trigger. If the MODE bit in the SEQB_CTRL register is 0  this flag will mirror the DATAVALID bit in the sequence A global data register (SEQB_GDAT)  which is set at the end of every ADC conversion performed as part of.." "0,1"
rbitfld.long 0x18 28. "SEQA_INT,Sequence A interrupt/DMA trigger. If the MODE bit in the SEQA_CTRL register is 0  this flag will mirror the DATAVALID bit in the sequence A global data register (SEQA_GDAT)  which is set at the end of every ADC conversion performed as part of.." "0,1"
newline
rbitfld.long 0x18 25. "SEQB_OVR,Mirrors the global OVERRUN status flag in the SEQB_GDAT register" "0,1"
rbitfld.long 0x18 24. "SEQA_OVR,Mirrors the global OVERRUN status flag in the SEQA_GDAT register" "0,1"
newline
rbitfld.long 0x18 23. "OVERRUN11,Mirrors the OVERRRUN status flag from the result register for ADC channel 11" "0,1"
rbitfld.long 0x18 22. "OVERRUN10,Mirrors the OVERRRUN status flag from the result register for ADC channel 10" "0,1"
newline
rbitfld.long 0x18 21. "OVERRUN9,Mirrors the OVERRRUN status flag from the result register for ADC channel 9" "0,1"
rbitfld.long 0x18 20. "OVERRUN8,Mirrors the OVERRRUN status flag from the result register for ADC channel 8" "0,1"
newline
rbitfld.long 0x18 19. "OVERRUN7,Mirrors the OVERRRUN status flag from the result register for ADC channel 7" "0,1"
rbitfld.long 0x18 18. "OVERRUN6,Mirrors the OVERRRUN status flag from the result register for ADC channel 6" "0,1"
newline
rbitfld.long 0x18 17. "OVERRUN5,Mirrors the OVERRRUN status flag from the result register for ADC channel 5" "0,1"
rbitfld.long 0x18 16. "OVERRUN4,Mirrors the OVERRRUN status flag from the result register for ADC channel 4" "0,1"
newline
rbitfld.long 0x18 15. "OVERRUN3,Mirrors the OVERRRUN status flag from the result register for ADC channel 3" "0,1"
rbitfld.long 0x18 14. "OVERRUN2,Mirrors the OVERRRUN status flag from the result register for ADC channel 2" "0,1"
newline
rbitfld.long 0x18 13. "OVERRUN1,Mirrors the OVERRRUN status flag from the result register for ADC channel 1" "0,1"
rbitfld.long 0x18 12. "OVERRUN0,Mirrors the OVERRRUN status flag from the result register for ADC channel 0" "0,1"
newline
bitfld.long 0x18 11. "THCMP11,Threshold comparison event on Channel 11. See description for channel 0." "0,1"
bitfld.long 0x18 10. "THCMP10,Threshold comparison event on Channel 10. See description for channel 0." "0,1"
newline
bitfld.long 0x18 9. "THCMP9,Threshold comparison event on Channel 9. See description for channel 0." "0,1"
bitfld.long 0x18 8. "THCMP8,Threshold comparison event on Channel 8. See description for channel 0." "0,1"
newline
bitfld.long 0x18 7. "THCMP7,Threshold comparison event on Channel 7. See description for channel 0." "0,1"
bitfld.long 0x18 6. "THCMP6,Threshold comparison event on Channel 6. See description for channel 0." "0,1"
newline
bitfld.long 0x18 5. "THCMP5,Threshold comparison event on Channel 5. See description for channel 0." "0,1"
bitfld.long 0x18 4. "THCMP4,Threshold comparison event on Channel 4. See description for channel 0." "0,1"
newline
bitfld.long 0x18 3. "THCMP3,Threshold comparison event on Channel 3. See description for channel 0." "0,1"
bitfld.long 0x18 2. "THCMP2,Threshold comparison event on Channel 2. See description for channel 0." "0,1"
newline
bitfld.long 0x18 1. "THCMP1,Threshold comparison event on Channel 1. See description for channel 0." "0,1"
bitfld.long 0x18 0. "THCMP0,Threshold comparison event on Channel 0. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1." "0,1"
line.long 0x1C "STARTUP,ADC Startup register."
bitfld.long 0x1C 1. "ADC_INIT,ADC Initialization. After enabling the ADC (setting the ADC_ENA bit)  the API routine will EITHER set this bit or the CALIB bit in the CALIB register  depending on whether or not calibration is required. Setting this bit will launch the 'dummy'.." "0,1"
bitfld.long 0x1C 0. "ADC_ENA,ADC Enable bit. This bit can only be set to a 1 by software. It is cleared automatically whenever the ADC is powered down. This bit must not be set until at least 10 microseconds after the ADC is powered up (typically by altering a system-level.." "0,1"
line.long 0x20 "CALIB,ADC Calibration register."
hexmask.long.byte 0x20 2.--8. 1. "CALVALUE,Calibration Value. This read-only field displays the calibration value established during last calibration cycle. This value is not typically of any use to the user."
bitfld.long 0x20 1. "CALREQD,Calibration required. This read-only bit indicates if calibration is required when enabling the ADC. CALREQD will be '1' if no calibration has been run since the chip was powered-up and if the BYPASSCAL bit in the CTRL register is low. Software.." "0,1"
newline
bitfld.long 0x20 0. "CALIB,Calibration request. Setting this bit will launch an ADC calibration cycle. This bit can only be set to a '1' by software. It is cleared automatically when the calibration cycle completes." "0,1"
tree.end
sif (cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
tree "AES (AES-256 Encryption/Decryption Engine)"
base ad:0x400A1000
group.long 0x0++0x3
line.long 0x0 "CFG,AES Configuration register"
bitfld.long 0x0 24.--25. "OUTTEXT_SEL,Output text source select." "0,1,2,3"
bitfld.long 0x0 20.--21. "HOLD_SEL,Holding register source select." "0,1,2,3"
bitfld.long 0x0 16.--17. "INBLK_SEL,Input block select." "0,1,2,3"
bitfld.long 0x0 8.--9. "KEY_CFG,Key Configuration." "0,1,2,3"
bitfld.long 0x0 7. "OUTTEXT_WSWAP,Word swap output text." "0,1"
bitfld.long 0x0 6. "OUTTEXT_BSWAP,Byte swap output text." "0,1"
bitfld.long 0x0 5. "INTEXT_WSWAP,Word swap input text." "0,1"
newline
bitfld.long 0x0 4. "INTEXT_BSWAP,Byte swap input text." "0,1"
bitfld.long 0x0 2. "GF128_SEL,GF128 hash selection." "0,1"
bitfld.long 0x0 0.--1. "PROC_EN,Process type enable." "0,1,2,3"
group.word 0x0++0x1
line.word 0x0 "CFG0_15,AES Configuration register 0:15"
bitfld.word 0x0 8.--9. "KEY_CFG,Key Configuration." "0,1,2,3"
bitfld.word 0x0 7. "OUTTEXT_WSWAP,Word swap output text." "0,1"
bitfld.word 0x0 6. "OUTTEXT_BSWAP,Byte swap output text." "0,1"
bitfld.word 0x0 5. "INTEXT_WSWAP,Word swap input text." "0,1"
bitfld.word 0x0 4. "INTEXT_BSWAP,Byte swap input text." "0,1"
bitfld.word 0x0 2. "GF128_SEL,GF128 hash selection." "0,1"
bitfld.word 0x0 0.--1. "PROC_EN,Process type enable." "0,1,2,3"
group.byte 0x0++0x1
line.byte 0x0 "CFG0_7,AES Configuration register 0:7"
bitfld.byte 0x0 7. "OUTTEXT_WSWAP,Word swap output text." "0,1"
bitfld.byte 0x0 6. "OUTTEXT_BSWAP,Byte swap output text." "0,1"
bitfld.byte 0x0 5. "INTEXT_WSWAP,Word swap input text." "0,1"
bitfld.byte 0x0 4. "INTEXT_BSWAP,Byte swap input text." "0,1"
bitfld.byte 0x0 2. "GF128_SEL,GF128 hash selection." "0,1"
bitfld.byte 0x0 0.--1. "PROC_EN,Process type enable." "0,1,2,3"
line.byte 0x1 "CFG8_15,AES Configuration register 8:15"
bitfld.byte 0x1 0.--1. "KEY_CFG,Key Configuration." "0,1,2,3"
group.word 0x2++0x1
line.word 0x0 "CFG16_31,AES Configuration register 16:31"
bitfld.word 0x0 8.--9. "OUTTEXT_SEL,Output text source select." "0,1,2,3"
bitfld.word 0x0 4.--5. "HOLD_SEL,Holding register source select." "0,1,2,3"
bitfld.word 0x0 0.--1. "INBLK_SEL,Input block select." "0,1,2,3"
group.long 0x4++0xB
line.long 0x0 "CMD,AES Command register"
bitfld.long 0x0 9. "WIPE,When set this bit performs abort  clears KEY and GF128_Y registers and disables cipher." "0,1"
bitfld.long 0x0 8. "ABORT,Aborts Encrypt/Decrypt and GF128 Hash operation." "0,1"
bitfld.long 0x0 4. "SWITCH_MODE,When this bit is set the mode switches from forward mode (encryption) to reverse mode (decryption) or reverse mode to forward mode." "0,1"
bitfld.long 0x0 1. "COPY_TO_Y,Copy output text to GF128Y." "0,1"
line.long 0x4 "STAT,AES Status register"
bitfld.long 0x4 5. "KEY_VALID,Key valid." "0,1"
bitfld.long 0x4 4. "REVERSE,Reverse mode." "0,1"
bitfld.long 0x4 2. "OUT_READY,Output text ready." "0,1"
bitfld.long 0x4 1. "IN_READY,Input text ready." "0,1"
bitfld.long 0x4 0. "IDLE,AES engine Idle." "0,1"
line.long 0x8 "CTR_INCR,Counter Increment"
hexmask.long 0x8 0.--31. 1. "CTR_INCR,Increment value for HOLDING register when in counter modes."
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x20)++0x3
line.long 0x0 "KEY[$1],Bits of the AES key"
hexmask.long 0x0 0.--31. 1. "KEY,Contains the bits of the AES key."
repeat.end
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x40)++0x3
line.long 0x0 "INTEXT[$1],Input text bits"
hexmask.long 0x0 0.--31. 1. "INTEXT,Contains bits of the AES key."
repeat.end
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x50)++0x3
line.long 0x0 "HOLDING[$1],Holding register bits"
hexmask.long 0x0 0.--31. 1. "HOLDING,Contains the first word (bits 31:0) of the 128 bit Holding value."
repeat.end
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x60)++0x3
line.long 0x0 "OUTTEXT[$1],Output text bits"
hexmask.long 0x0 0.--31. 1. "OUTTEXT,Contains the bits of the 128 bit Output text data."
repeat.end
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x70)++0x3
line.long 0x0 "GF128_Y[$1],Y bits input of GF128 hash"
hexmask.long 0x0 0.--31. 1. "GF128_Y,Contains the bits of the Y input of GF128 hash."
repeat.end
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x80)++0x3
line.long 0x0 "GF128_Z[$1],Result bits of GF128 hash"
hexmask.long 0x0 0.--31. 1. "GF128_Z,Contains bits of the result of GF128 hash."
repeat.end
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x90)++0x3
line.long 0x0 "GCM_TAG[$1],GCM Tag bits"
hexmask.long 0x0 0.--31. 1. "GCM_TAG,Contains bits of the 128 bit GCM tag."
repeat.end
tree.end
endif
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54113*")||cpuis("LPC54114*")||cpuis("LPC54605*")||cpuis("LPC54606*")||cpuis("LPC54607*")||cpuis("LPC54608*")||cpuis("LPC54616*")||cpuis("LPC54618*")||cpuis("LPC54628*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
base ad:0x40040000
elif (cpuis("LPC54101*")||cpuis("LPC54102*"))
base ad:0x40080000
endif
tree "ASYNC_SYSCON (Asynchronous System Configuration)"
group.long 0x0++0x3
line.long 0x0 "ASYNCPRESETCTRL,Async peripheral reset control"
sif (cpuis("LPC54101*"))
bitfld.long 0x0 15. "FRG0,FRG reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 14. "CT32B1,CT32B 1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 13. "CT32B0,CT32B 0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x0 15. "FRG0,FRG reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 14. "CT32B1,CT32B 1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 13. "CT32B0,CT32B 0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
endif
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x0 14. "CTIMER4,Standard counter/timer CTIMER4 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 13. "CTIMER3,Standard counter/timer CTIMER3 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x0 14. "CTIMER4,Standard counter/timer CTIMER4 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x0 13. "CTIMER3,Standard counter/timer CTIMER3 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x0 14. "CTIMER4,Standard counter/timer CTIMER4 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 13. "CTIMER3,Standard counter/timer CTIMER3 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x0 14. "CTIMER4,Standard counter/timer CTIMER4 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 13. "CTIMER3,Standard counter/timer CTIMER3 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x0 14. "CTIMER4,Standard counter/timer CTIMER4 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x0 13. "CTIMER3,Standard counter/timer CTIMER3 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x0 14. "CTIMER4,Standard counter/timer CTIMER4 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 13. "CTIMER3,Standard counter/timer CTIMER3 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x0 14. "CTIMER4,Standard counter/timer CTIMER4 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 13. "CTIMER3,Standard counter/timer CTIMER3 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x0 14. "CTIMER4,Standard counter/timer CTIMER4 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x0 13. "CTIMER3,Standard counter/timer CTIMER3 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x0 14. "CTIMER4,Standard counter/timer CTIMER4 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 13. "CTIMER3,Standard counter/timer CTIMER3 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x0 14. "CTIMER4,Standard counter/timer CTIMER4 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 13. "CTIMER3,Standard counter/timer CTIMER3 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x0 10. "SPI1,SPI1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x0 9. "SPI0,SPI0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x0 10. "SPI1,SPI1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 9. "SPI0,SPI0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
endif
sif (cpuis("LPC54101*"))
newline
bitfld.long 0x0 7. "I2C2,I2C2 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 6. "I2C1,I2C1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 5. "I2C0,I2C0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x0 4. "USART3,USART3 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 3. "USART2,USART2 reset control.0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 2. "USART1,USART1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x0 1. "USART0,USART0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x0 7. "I2C2,I2C2 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 6. "I2C1,I2C1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x0 5. "I2C0,I2C0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 4. "USART3,USART3 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 3. "USART2,USART2 reset control.0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x0 2. "USART1,USART1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 1. "USART0,USART0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
endif
wgroup.long 0x4++0x7
line.long 0x0 "ASYNCPRESETCTRLSET,Set bits in ASYNCPRESETCTRL"
hexmask.long 0x0 0.--31. 1. "ARST_SET,Writing ones to this register sets the corresponding bit or bits in the ASYNCPRESETCTRL register  if they are implemented. Bits that do not correspond to defined bits in ASYNCPRESETCTRL are reserved and only zeroes should be written to them."
line.long 0x4 "ASYNCPRESETCTRLCLR,Clear bits in ASYNCPRESETCTRL"
hexmask.long 0x4 0.--31. 1. "ARST_CLR,Writing ones to this register clears the corresponding bit or bits in the ASYNCPRESETCTRL register  if they are implemented. Bits that do not correspond to defined bits in ASYNCPRESETCTRL are reserved and only zeroes should be written to them."
group.long 0x10++0x3
line.long 0x0 "ASYNCAPBCLKCTRL,Async peripheral clock control"
sif (cpuis("LPC54101*"))
bitfld.long 0x0 15. "FRG0,Controls the clock for the Fractional Rate Generator used with the USARTs. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 14. "CT32B1,Controls the clock for CT32B1. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 13. "CT32B0,Controls the clock for CT32B0. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x0 15. "FRG0,Controls the clock for the Fractional Rate Generator used with the USARTs. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 14. "CT32B1,Controls the clock for CT32B1. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 13. "CT32B0,Controls the clock for CT32B0. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
endif
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x0 14. "CTIMER4,Controls the clock for CTIMER4. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 13. "CTIMER3,Controls the clock for CTIMER3. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x0 14. "CTIMER4,Controls the clock for CTIMER4. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 13. "CTIMER3,Controls the clock for CTIMER3. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x0 14. "CTIMER4,Controls the clock for CTIMER4. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 13. "CTIMER3,Controls the clock for CTIMER3. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x0 14. "CTIMER4,Controls the clock for CTIMER4. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 13. "CTIMER3,Controls the clock for CTIMER3. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x0 14. "CTIMER4,Controls the clock for CTIMER4. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 13. "CTIMER3,Controls the clock for CTIMER3. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x0 14. "CTIMER4,Controls the clock for CTIMER4. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 13. "CTIMER3,Controls the clock for CTIMER3. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x0 14. "CTIMER4,Controls the clock for CTIMER4. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 13. "CTIMER3,Controls the clock for CTIMER3. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x0 14. "CTIMER4,Controls the clock for CTIMER4. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 13. "CTIMER3,Controls the clock for CTIMER3. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x0 14. "CTIMER4,Controls the clock for CTIMER4. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 13. "CTIMER3,Controls the clock for CTIMER3. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x0 14. "CTIMER4,Controls the clock for CTIMER4. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 13. "CTIMER3,Controls the clock for CTIMER3. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x0 10. "SPI1,Controls the clock for SPI1. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 9. "SPI0,Controls the clock for SPI0. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x0 10. "SPI1,Controls the clock for SPI1. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 9. "SPI0,Controls the clock for SPI0. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
endif
sif (cpuis("LPC54101*"))
newline
bitfld.long 0x0 7. "I2C2,Controls the clock for I2C2. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 6. "I2C1,Controls the clock for I2C1. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 5. "I2C0,Controls the clock for I2C0. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 4. "USART3,Controls the clock for USART3. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 3. "USART2,Controls the clock for USART2. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 2. "USART1,Controls the clock for USART1. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 1. "USART0,Controls the clock for USART0. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x0 7. "I2C2,Controls the clock for I2C2. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 6. "I2C1,Controls the clock for I2C1. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 5. "I2C0,Controls the clock for I2C0. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 4. "USART3,Controls the clock for USART3. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 3. "USART2,Controls the clock for USART2. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 2. "USART1,Controls the clock for USART1. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 1. "USART0,Controls the clock for USART0. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
endif
wgroup.long 0x14++0x7
line.long 0x0 "ASYNCAPBCLKCTRLSET,Set bits in ASYNCAPBCLKCTRL"
hexmask.long 0x0 0.--31. 1. "ACLK_SET,Writing ones to this register sets the corresponding bit or bits in the ASYNCAPBCLKCTRL register  if they are implemented. Bits that do not correspond to defined bits in ASYNCPRESETCTRL are reserved and only zeroes should be written to them."
line.long 0x4 "ASYNCAPBCLKCTRLCLR,Clear bits in ASYNCAPBCLKCTRL"
hexmask.long 0x4 0.--31. 1. "ACLK_CLR,Writing ones to this register clears the corresponding bit or bits in the ASYNCAPBCLKCTRL register  if they are implemented. Bits that do not correspond to defined bits in ASYNCAPBCLKCTRL are reserved and only zeroes should be written to them."
group.long 0x20++0x3
line.long 0x0 "ASYNCAPBCLKSELA,Async APB clock source select A"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x0 0.--1. "SEL,Clock source for asynchronous clock source selector A" "0: Main clock (main_clk),1: FRO 12 MHz (fro_12m),2: Audio PLL clock.(AUDPLL_BYPASS),3: fc6 fclk (fc6_fclk)"
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x0 0.--1. "SEL,Clock source for asynchronous clock source selector A" "0: IRC Oscillator,1: Watchdog oscillator,?,?"
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x0 0.--1. "SEL,Clock source for asynchronous clock source selector A" "0: IRC Oscillator,1: Watchdog oscillator,?,?"
newline
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x0 0.--1. "SEL,Clock source for asynchronous clock source selector A" "0: Main clock,1: FRO 12 MHz,?,?"
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x0 0.--1. "SEL,Clock source for asynchronous clock source selector A" "0: Main clock,1: FRO 12 MHz,?,?"
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x0 0.--1. "SEL,Clock source for asynchronous clock source selector A" "0: Main clock (main_clk),1: FRO 12 MHz (fro_12m),2: Audio PLL clock.(AUDPLL_BYPASS),3: fc6 fclk (fc6_fclk)"
newline
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x0 0.--1. "SEL,Clock source for asynchronous clock source selector A" "0: Main clock (main_clk),1: FRO 12 MHz (fro_12m),2: Audio PLL clock.(AUDPLL_BYPASS),3: fc6 fclk (fc6_fclk)"
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x0 0.--1. "SEL,Clock source for asynchronous clock source selector A" "0: Main clock (main_clk),1: FRO 12 MHz (fro_12m),2: Audio PLL clock.(AUDPLL_BYPASS),3: fc6 fclk (fc6_fclk)"
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x0 0.--1. "SEL,Clock source for asynchronous clock source selector A" "0: Main clock (main_clk),1: FRO 12 MHz (fro_12m),2: Audio PLL clock.(AUDPLL_BYPASS),3: fc6 fclk (fc6_fclk)"
newline
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x0 0.--1. "SEL,Clock source for asynchronous clock source selector A" "0: Main clock (main_clk),1: FRO 12 MHz (fro_12m),2: Audio PLL clock.(AUDPLL_BYPASS),3: fc6 fclk (fc6_fclk)"
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x0 0.--1. "SEL,Clock source for asynchronous clock source selector A" "0: Main clock (main_clk),1: FRO 12 MHz (fro_12m),2: Audio PLL clock.(AUDPLL_BYPASS),3: fc6 fclk (fc6_fclk)"
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x0 0.--1. "SEL,Clock source for asynchronous clock source selector A" "0: Main clock (main_clk),1: FRO 12 MHz (fro_12m),2: Audio PLL clock.(AUDPLL_BYPASS),3: fc6 fclk (fc6_fclk)"
endif
sif (cpuis("LPC54101*"))
group.long 0x24++0x7
line.long 0x0 "ASYNCAPBCLKSELB,Async APB clock source select B"
bitfld.long 0x0 0.--1. "SEL,Clock source for asynchronous clock source selector B." "0: Main clock,1: CLKIN,2: System PLL output.,3: ASYNCAPBCLKSELA. Clock selected by the.."
line.long 0x4 "ASYNCCLKDIV,Async APB clock divider"
hexmask.long.byte 0x4 0.--7. 1. "DIV,Asynchronous APB clock divider value. 0: Clock disabled. 1: Divide by 1. to 255: Divide by 255."
group.long 0x30++0x3
line.long 0x0 "FRGCTRL,USART fractional rate generator control"
hexmask.long.byte 0x0 8.--15. 1. "MULT,Numerator of the fractional divider. MULT is equal to the programmed value."
hexmask.long.byte 0x0 0.--7. 1. "DIV,Denominator of the fractional divider. DIV is equal to the programmed value +1. Always set to 0xFF to use with the fractional baud rate generator."
endif
sif (cpuis("LPC54102*"))
group.long 0x24++0x7
line.long 0x0 "ASYNCAPBCLKSELB,Async APB clock source select B"
bitfld.long 0x0 0.--1. "SEL,Clock source for asynchronous clock source selector B." "0: Main clock,1: CLKIN,2: System PLL output.,3: ASYNCAPBCLKSELA. Clock selected by the.."
line.long 0x4 "ASYNCCLKDIV,Async APB clock divider"
hexmask.long.byte 0x4 0.--7. 1. "DIV,Asynchronous APB clock divider value. 0: Clock disabled. 1: Divide by 1. to 255: Divide by 255."
group.long 0x30++0x3
line.long 0x0 "FRGCTRL,USART fractional rate generator control"
hexmask.long.byte 0x0 8.--15. 1. "MULT,Numerator of the fractional divider. MULT is equal to the programmed value."
hexmask.long.byte 0x0 0.--7. 1. "DIV,Denominator of the fractional divider. DIV is equal to the programmed value +1. Always set to 0xFF to use with the fractional baud rate generator."
endif
tree.end
sif (cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54606*")||cpuis("LPC54608*")||cpuis("LPC54616*")||cpuis("LPC54618*")||cpuis("LPC54628*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
tree "CAN (Controller Area Network)"
base ad:0x0
sif (cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54606*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
tree "CAN0"
base ad:0x4009D000
sif (cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
group.long 0xC++0x3
line.long 0x0 "DBTP,Data Bit Timing Prescaler Register"
bitfld.long 0x0 23. "TDC,Transmitter delay compensation." "0,1"
hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data bit rate prescaler."
newline
hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point."
hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point."
newline
hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data (re)synchronization jump width."
endif
group.long 0x10++0x3
line.long 0x0 "TEST,Test Register"
bitfld.long 0x0 7. "RX,Monitors the actual value of the CAN_RXD." "0,1"
bitfld.long 0x0 5.--6. "TX,Control of transmit pin." "0,1,2,3"
bitfld.long 0x0 4. "LBCK,Loop back mode." "0,1"
group.long 0x18++0x13
line.long 0x0 "CCCR,CC Control Register"
sif (cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x0 15. "NISO,Non ISO operation." "0,1"
bitfld.long 0x0 9. "BRSE,When CAN FD operation is disabled  this bit is not evaluated." "0,1"
bitfld.long 0x0 8. "FDOE,CAN FD operation enable." "0,1"
endif
bitfld.long 0x0 14. "TXP,Transmit pause." "0,1"
bitfld.long 0x0 13. "EFBI,Edge filtering during bus integration." "0,1"
bitfld.long 0x0 12. "PXHD,Protocol exception handling disable." "0,1"
bitfld.long 0x0 7. "TEST,Test mode enable." "0,1"
bitfld.long 0x0 6. "DAR,Disable automatic retransmission." "0,1"
bitfld.long 0x0 5. "MON,Bus monitoring mode." "0,1"
newline
bitfld.long 0x0 4. "CSR,Clock Stop Request." "0,1"
bitfld.long 0x0 3. "CSA,Clock Stop Acknowledge." "0,1"
bitfld.long 0x0 2. "ASM,Restricted operational mode." "0,1"
bitfld.long 0x0 1. "CCE,Configuration change enable." "0,1"
bitfld.long 0x0 0. "INIT,Initialization." "0,1"
line.long 0x4 "NBTP,Nominal Bit Timing and Prescaler Register"
hexmask.long.byte 0x4 25.--31. 1. "NSJW,Nominal (re)synchronization jump width."
hexmask.long.word 0x4 16.--24. 1. "NBRP,Nominal bit rate prescaler."
hexmask.long.byte 0x4 8.--15. 1. "NTSEG1,Nominal time segment before sample point."
hexmask.long.byte 0x4 0.--6. 1. "NTSEG2,Nominal time segment after sample point."
line.long 0x8 "TSCC,Timestamp Counter Configuration"
hexmask.long.byte 0x8 16.--19. 1. "TCP,Timestamp counter prescaler Configures the timestamp and timeout counters time unit in multiple of CAN bit times."
bitfld.long 0x8 0.--1. "TSS,Timestamp select." "0,1,2,3"
line.long 0xC "TSCV,Timestamp Counter Value"
sif (cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
hexmask.long.word 0xC 0.--15. 1. "TSC,Timestamp counter."
endif
sif (cpuis("LPC54606*"))
hexmask.long.word 0xC 0.--15. 1. "TSC,Timestamp counter."
endif
line.long 0x10 "TOCC,Timeout Counter Configuration"
hexmask.long.word 0x10 16.--31. 1. "TOP,Timeout period."
bitfld.long 0x10 1.--2. "TOS,Timeout select." "0,1,2,3"
bitfld.long 0x10 0. "ETOC,Enable timeout counter." "0,1"
rgroup.long 0x2C++0x3
line.long 0x0 "TOCV,Timeout Counter Value"
hexmask.long.word 0x0 0.--15. 1. "TOC,Timeout counter."
rgroup.long 0x40++0x7
line.long 0x0 "ECR,Error Counter Register"
hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN error logging."
bitfld.long 0x0 15. "RP,Receive error passive." "0,1"
hexmask.long.byte 0x0 8.--14. 1. "REC,Receive error counter."
hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit error counter."
line.long 0x4 "PSR,Protocol Status Register"
hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter delay compensation value."
rbitfld.long 0x4 14. "PXE,Protocol exception event." "0,1"
sif (cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
rbitfld.long 0x4 13. "RFDF,Received a CAN FD message." "0,1"
rbitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD message." "0,1"
rbitfld.long 0x4 11. "RESI,ESI flag of the last received CAN FD message." "0,1"
rbitfld.long 0x4 8.--10. "DLEC,Data phase last error code." "0,1,2,3,4,5,6,7"
endif
rbitfld.long 0x4 7. "BO,Bus Off Status." "0,1"
rbitfld.long 0x4 6. "EW,Warning status." "0,1"
rbitfld.long 0x4 5. "EP,Error Passive." "0,1"
newline
rbitfld.long 0x4 3.--4. "ACT,Activity." "0,1,2,3"
rbitfld.long 0x4 0.--2. "LEC,Last error code." "0,1,2,3,4,5,6,7"
group.long 0x48++0x3
line.long 0x0 "TDCR,Transmitter Delay Compensator Register"
hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter delay compensation offset."
hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter delay compensation filter window length."
group.long 0x50++0xF
line.long 0x0 "IR,Interrupt Register"
bitfld.long 0x0 29. "ARA,Access to reserved address." "0,1"
bitfld.long 0x0 28. "PED,Protocol error in data phase." "0,1"
bitfld.long 0x0 27. "PEA,Protocol error in arbitration phase." "0,1"
bitfld.long 0x0 26. "WDI,Watchdog interrupt." "0,1"
bitfld.long 0x0 25. "BO,Bus_Off Status." "0,1"
bitfld.long 0x0 24. "EW,Warning status." "0,1"
bitfld.long 0x0 23. "EP,Error passive." "0,1"
bitfld.long 0x0 22. "ELO,Error logging overflow." "0,1"
bitfld.long 0x0 21. "BEU,Bit error uncorrected." "0,1"
newline
bitfld.long 0x0 20. "BEC,Bit error corrected." "0,1"
bitfld.long 0x0 19. "DRX,Message stored in dedicated Rx buffer." "0,1"
bitfld.long 0x0 18. "TOO,Timeout occurred." "0,1"
bitfld.long 0x0 17. "MRAF,Message RAM access failure." "0,1"
bitfld.long 0x0 16. "TSW,Timestamp wraparound." "0,1"
bitfld.long 0x0 15. "TEFL,Tx event FIFO element lost." "0,1"
bitfld.long 0x0 14. "TEFF,Tx event FIFO full." "0,1"
bitfld.long 0x0 13. "TEFW,Tx event FIFO watermark reached." "0,1"
bitfld.long 0x0 12. "TEFN,Tx event FIFO new entry." "0,1"
newline
bitfld.long 0x0 11. "TFE,Tx FIFO empty." "0,1"
bitfld.long 0x0 10. "TCF,Transmission cancellation finished." "0,1"
bitfld.long 0x0 9. "TC,Transmission completed." "0,1"
bitfld.long 0x0 8. "HPM,High priority message." "0,1"
bitfld.long 0x0 7. "RF1L,Rx FIFO 1 message lost." "0,1"
bitfld.long 0x0 6. "RF1F,Rx FIFO 1 full." "0,1"
bitfld.long 0x0 5. "RF1W,Rx FIFO 1 watermark reached." "0,1"
bitfld.long 0x0 4. "RF1N,Rx FIFO 1 new message." "0,1"
bitfld.long 0x0 3. "RF0L,Rx FIFO 0 message lost." "0,1"
newline
bitfld.long 0x0 2. "RF0F,Rx FIFO 0 full." "0,1"
bitfld.long 0x0 1. "RF0W,Rx FIFO 0 watermark reached." "0,1"
bitfld.long 0x0 0. "RF0N,Rx FIFO 0 new message." "0,1"
line.long 0x4 "IE,Interrupt Enable"
bitfld.long 0x4 29. "ARAE,Access to reserved address interrupt enable." "0,1"
bitfld.long 0x4 28. "PEDE,Protocol error in data phase interrupt enable." "0,1"
bitfld.long 0x4 27. "PEAE,Protocol error in arbitration phase interrupt enable." "0,1"
bitfld.long 0x4 26. "WDIE,Watchdog interrupt enable." "0,1"
bitfld.long 0x4 25. "BOE,Bus_Off Status interrupt enable." "0,1"
bitfld.long 0x4 24. "EWE,Warning status interrupt enable." "0,1"
bitfld.long 0x4 23. "EPE,Error passive interrupt enable." "0,1"
bitfld.long 0x4 22. "ELOE,Error logging overflow interrupt enable." "0,1"
bitfld.long 0x4 21. "BEUE,Bit error uncorrected interrupt enable." "0,1"
newline
bitfld.long 0x4 20. "BECE,Bit error corrected interrupt enable." "0,1"
bitfld.long 0x4 19. "DRXE,Message stored in dedicated Rx buffer interrupt enable." "0,1"
bitfld.long 0x4 18. "TOOE,Timeout occurred interrupt enable." "0,1"
bitfld.long 0x4 17. "MRAFE,Message RAM access failure interrupt enable." "0,1"
bitfld.long 0x4 16. "TSWE,Timestamp wraparound interrupt enable." "0,1"
bitfld.long 0x4 15. "TEFLE,Tx event FIFO element lost interrupt enable." "0,1"
bitfld.long 0x4 14. "TEFFE,Tx event FIFO full interrupt enable." "0,1"
bitfld.long 0x4 13. "TEFWE,Tx event FIFO watermark reached interrupt enable." "0,1"
bitfld.long 0x4 12. "TEFNE,Tx event FIFO new entry interrupt enable." "0,1"
newline
bitfld.long 0x4 11. "TFEE,Tx FIFO empty interrupt enable." "0,1"
bitfld.long 0x4 10. "TCFE,Transmission cancellation finished interrupt enable." "0,1"
bitfld.long 0x4 9. "TCE,Transmission completed interrupt enable." "0,1"
bitfld.long 0x4 8. "HPME,High priority message interrupt enable." "0,1"
bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 message lost interrupt enable." "0,1"
bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 full interrupt enable." "0,1"
bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 watermark reached interrupt enable." "0,1"
bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 new message interrupt enable." "0,1"
bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 message lost interrupt enable." "0,1"
newline
bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 full interrupt enable." "0,1"
bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 watermark reached interrupt enable." "0,1"
bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 new message interrupt enable." "0,1"
line.long 0x8 "ILS,Interrupt Line Select"
bitfld.long 0x8 29. "ARAL,Access to reserved address interrupt line." "0,1"
bitfld.long 0x8 28. "PEDL,Protocol error in data phase interrupt line." "0,1"
bitfld.long 0x8 27. "PEAL,Protocol error in arbitration phase interrupt line." "0,1"
bitfld.long 0x8 26. "WDIL,Watchdog interrupt line." "0,1"
bitfld.long 0x8 25. "BOL,Bus_Off Status interrupt line." "0,1"
bitfld.long 0x8 24. "EWL,Warning status interrupt line." "0,1"
bitfld.long 0x8 23. "EPL,Error passive interrupt line." "0,1"
bitfld.long 0x8 22. "ELOL,Error logging overflow interrupt line." "0,1"
bitfld.long 0x8 21. "BEUL,Bit error uncorrected interrupt line." "0,1"
newline
bitfld.long 0x8 20. "BECL,Bit error corrected interrupt line." "0,1"
bitfld.long 0x8 19. "DRXL,Message stored in dedicated Rx buffer interrupt line." "0,1"
bitfld.long 0x8 18. "TOOL,Timeout occurred interrupt line." "0,1"
bitfld.long 0x8 17. "MRAFL,Message RAM access failure interrupt line." "0,1"
bitfld.long 0x8 16. "TSWL,Timestamp wraparound interrupt line." "0,1"
bitfld.long 0x8 15. "TEFLL,Tx event FIFO element lost interrupt line." "0,1"
bitfld.long 0x8 14. "TEFFL,Tx event FIFO full interrupt line." "0,1"
bitfld.long 0x8 13. "TEFWL,Tx event FIFO watermark reached interrupt line." "0,1"
bitfld.long 0x8 12. "TEFNL,Tx event FIFO new entry interrupt line." "0,1"
newline
bitfld.long 0x8 11. "TFEL,Tx FIFO empty interrupt line." "0,1"
bitfld.long 0x8 10. "TCFL,Transmission cancellation finished interrupt line." "0,1"
bitfld.long 0x8 9. "TCL,Transmission completed interrupt line." "0,1"
bitfld.long 0x8 8. "HPML,High priority message interrupt line." "0,1"
bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 message lost interrupt line." "0,1"
bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 full interrupt line." "0,1"
bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 watermark reached interrupt line." "0,1"
bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 new message interrupt line." "0,1"
bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 message lost interrupt line." "0,1"
newline
bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 full interrupt line." "0,1"
bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 watermark reached interrupt line." "0,1"
bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 new message interrupt line." "0,1"
line.long 0xC "ILE,Interrupt Line Enable"
bitfld.long 0xC 1. "EINT1,Enable interrupt line 1." "0,1"
bitfld.long 0xC 0. "EINT0,Enable interrupt line 0." "0,1"
group.long 0x80++0xB
line.long 0x0 "GFC,Global Filter Configuration"
bitfld.long 0x0 4.--5. "ANFS,Accept non-matching frames standard." "0,1,2,3"
bitfld.long 0x0 2.--3. "ANFE,Accept non-matching frames extended." "0,1,2,3"
bitfld.long 0x0 1. "RRFS,Reject remote frames standard." "0,1"
bitfld.long 0x0 0. "RRFE,Reject remote frames extended." "0,1"
line.long 0x4 "SIDFC,Standard ID Filter Configuration"
hexmask.long.byte 0x4 16.--23. 1. "LSS,List size standard 0 = No standard message ID filter."
hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter list standard start address."
line.long 0x8 "XIDFC,Extended ID Filter Configuration"
hexmask.long.byte 0x8 16.--23. 1. "LSE,List size extended 0 = No extended message ID filter."
hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter list extended start address."
group.long 0x90++0x3
line.long 0x0 "XIDAM,Extended ID AND Mask"
hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID mask."
rgroup.long 0x94++0x3
line.long 0x0 "HPMS,High Priority Message Status"
bitfld.long 0x0 15. "FLST,Filter list." "0,1"
hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter index."
bitfld.long 0x0 6.--7. "MSI,Message storage indicator." "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer index."
group.long 0x98++0xB
line.long 0x0 "NDAT1,New Data 1"
hexmask.long 0x0 0.--31. 1. "ND,New Data."
line.long 0x4 "NDAT2,New Data 2"
hexmask.long 0x4 0.--31. 1. "ND,New Data."
line.long 0x8 "RXF0C,Rx FIFO 0 Configuration"
bitfld.long 0x8 31. "F0OM,FIFO 0 operation mode." "0,1"
hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 watermark 0 = Watermark interrupt disabled."
hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 size."
hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 start address."
rgroup.long 0xA4++0x3
line.long 0x0 "RXF0S,Rx FIFO 0 Status"
sif (cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x0 25. "RF0L,Rx FIFO 0 message lost." "0,1"
bitfld.long 0x0 24. "F0F,Rx FIFO 0 full." "0,1"
hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 put index."
hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 get index."
hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 fill level."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x0 25. "RF0L,Rx FIFO 0 message lost." "0,1"
bitfld.long 0x0 24. "F0F,Rx FIFO 0 full." "0,1"
endif
sif (cpuis("LPC54606*"))
hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 put index."
endif
sif (cpuis("LPC54606*"))
hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 get index."
newline
endif
sif (cpuis("LPC54606*"))
hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 fill level."
endif
group.long 0xA8++0xB
line.long 0x0 "RXF0A,Rx FIFO 0 Acknowledge"
hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 acknowledge index."
line.long 0x4 "RXBC,Rx Buffer Configuration"
hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx buffer start address."
line.long 0x8 "RXF1C,Rx FIFO 1 Configuration"
bitfld.long 0x8 31. "F1OM,FIFO 1 operation mode." "0,1"
hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 watermark 0 = Watermark interrupt disabled."
hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 1 size 0 = No Rx FIFO 1."
hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 start address."
rgroup.long 0xB4++0x3
line.long 0x0 "RXF1S,Rx FIFO 1 Status"
bitfld.long 0x0 25. "RF1L,Rx FIFO 1 message lost." "0,1"
bitfld.long 0x0 24. "F1F,Rx FIFO 1 full." "0,1"
hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 put index."
hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 get index."
hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 fill level."
group.long 0xB8++0x13
line.long 0x0 "RXF1A,Rx FIFO 1 Acknowledge"
hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 acknowledge index."
line.long 0x4 "RXESC,Rx Buffer and FIFO Element Size Configuration"
bitfld.long 0x4 8.--10. "RBDS,." "0,1,2,3,4,5,6,7"
bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 data field size." "0,1,2,3,4,5,6,7"
bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 data field size." "0,1,2,3,4,5,6,7"
line.long 0x8 "TXBC,Tx Buffer Configuration"
bitfld.long 0x8 30. "TFQM,Tx FIFO/queue mode." "0,1"
hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/queue size 0 = No tx FIFO/Queue."
hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of dedicated transmit buffers 0 = No dedicated Tx buffers."
hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx buffers start address."
line.long 0xC "TXFQS,Tx FIFO/Queue Status"
bitfld.long 0xC 21. "TFQF,Tx FIFO/queue full." "0,1"
hexmask.long.byte 0xC 16.--20. 1. "TFQPI,Tx FIFO/queue put index."
hexmask.long.byte 0xC 8.--12. 1. "TFGI,Tx FIFO get index."
line.long 0x10 "TXESC,Tx Buffer Element Size Configuration"
bitfld.long 0x10 0.--2. "TBDS,Tx buffer data field size." "0,1,2,3,4,5,6,7"
rgroup.long 0xCC++0x3
line.long 0x0 "TXBRP,Tx Buffer Request Pending"
sif (cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
hexmask.long 0x0 0.--31. 1. "TRP,Transmission request pending."
endif
sif (cpuis("LPC54606*"))
hexmask.long 0x0 0.--31. 1. "TRP,Transmission request pending."
endif
group.long 0xD0++0x7
line.long 0x0 "TXBAR,Tx Buffer Add Request"
hexmask.long 0x0 0.--31. 1. "AR,Add request."
line.long 0x4 "TXBCR,Tx Buffer Cancellation Request"
hexmask.long 0x4 0.--31. 1. "CR,Cancellation request."
rgroup.long 0xD8++0x7
line.long 0x0 "TXBTO,Tx Buffer Transmission Occurred"
sif (cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
hexmask.long 0x0 0.--31. 1. "TO,Transmission occurred."
endif
sif (cpuis("LPC54606*"))
hexmask.long 0x0 0.--31. 1. "TO,Transmission occurred."
endif
line.long 0x4 "TXBCF,Tx Buffer Cancellation Finished"
sif (cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
hexmask.long 0x4 0.--31. 1. "TO,Cancellation finished."
endif
sif (cpuis("LPC54606*"))
hexmask.long 0x4 0.--31. 1. "TO,Cancellation finished."
endif
group.long 0xE0++0x7
line.long 0x0 "TXBTIE,Tx Buffer Transmission Interrupt Enable"
hexmask.long 0x0 0.--31. 1. "TIE,Transmission interrupt enable."
line.long 0x4 "TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable"
hexmask.long 0x4 0.--31. 1. "CFIE,Cancellation finished interrupt enable."
group.long 0xF0++0x3
line.long 0x0 "TXEFC,Tx Event FIFO Configuration"
hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO watermark 0 = Watermark interrupt disabled."
hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO size 0 = Tx event FIFO disabled."
hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO start address."
rgroup.long 0xF4++0x3
line.long 0x0 "TXEFS,Tx Event FIFO Status"
bitfld.long 0x0 25. "TEFL,Tx event FIFO element lost." "0,1"
bitfld.long 0x0 24. "EFF,Event FIFO full." "0,1"
hexmask.long.byte 0x0 16.--21. 1. "EFPI,Event FIFO put index."
hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO get index."
hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO fill level."
group.long 0xF8++0x3
line.long 0x0 "TXEFA,Tx Event FIFO Acknowledge"
hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO acknowledge index."
group.long 0x200++0x3
line.long 0x0 "MRBA,CAN Message RAM Base Address"
hexmask.long.word 0x0 16.--31. 1. "BA,Base address for the message RAM in the chip memory map."
group.long 0x400++0x3
line.long 0x0 "ETSCC,External Timestamp Counter Configuration"
bitfld.long 0x0 31. "ETCE,External timestamp counter enable." "0,1"
hexmask.long.word 0x0 0.--10. 1. "ETCP,External timestamp prescaler value."
group.long 0x600++0x3
line.long 0x0 "ETSCV,External Timestamp Counter Value"
hexmask.long.word 0x0 0.--15. 1. "ETSC,External timestamp counter."
sif (cpuis("LPC54606*"))
group.long 0xCC++0x3
line.long 0x0 "TXBRP,Tx Buffer Request Pending"
endif
sif (cpuis("LPC54606*"))
group.long 0xD8++0x3
line.long 0x0 "TXBTO,Tx Buffer Transmission Occurred"
endif
sif (cpuis("LPC54606*"))
group.long 0xDC++0x3
line.long 0x0 "TXBCF,Tx Buffer Cancellation Finished"
endif
tree.end
endif
sif (cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54606*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
tree "CAN1"
base ad:0x4009E000
sif (cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
group.long 0xC++0x3
line.long 0x0 "DBTP,Data Bit Timing Prescaler Register"
bitfld.long 0x0 23. "TDC,Transmitter delay compensation." "0,1"
hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data bit rate prescaler."
newline
hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point."
hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point."
newline
hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data (re)synchronization jump width."
endif
group.long 0x10++0x3
line.long 0x0 "TEST,Test Register"
bitfld.long 0x0 7. "RX,Monitors the actual value of the CAN_RXD." "0,1"
bitfld.long 0x0 5.--6. "TX,Control of transmit pin." "0,1,2,3"
bitfld.long 0x0 4. "LBCK,Loop back mode." "0,1"
group.long 0x18++0x13
line.long 0x0 "CCCR,CC Control Register"
sif (cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x0 15. "NISO,Non ISO operation." "0,1"
bitfld.long 0x0 9. "BRSE,When CAN FD operation is disabled  this bit is not evaluated." "0,1"
bitfld.long 0x0 8. "FDOE,CAN FD operation enable." "0,1"
endif
bitfld.long 0x0 14. "TXP,Transmit pause." "0,1"
bitfld.long 0x0 13. "EFBI,Edge filtering during bus integration." "0,1"
bitfld.long 0x0 12. "PXHD,Protocol exception handling disable." "0,1"
bitfld.long 0x0 7. "TEST,Test mode enable." "0,1"
bitfld.long 0x0 6. "DAR,Disable automatic retransmission." "0,1"
bitfld.long 0x0 5. "MON,Bus monitoring mode." "0,1"
newline
bitfld.long 0x0 4. "CSR,Clock Stop Request." "0,1"
bitfld.long 0x0 3. "CSA,Clock Stop Acknowledge." "0,1"
bitfld.long 0x0 2. "ASM,Restricted operational mode." "0,1"
bitfld.long 0x0 1. "CCE,Configuration change enable." "0,1"
bitfld.long 0x0 0. "INIT,Initialization." "0,1"
line.long 0x4 "NBTP,Nominal Bit Timing and Prescaler Register"
hexmask.long.byte 0x4 25.--31. 1. "NSJW,Nominal (re)synchronization jump width."
hexmask.long.word 0x4 16.--24. 1. "NBRP,Nominal bit rate prescaler."
hexmask.long.byte 0x4 8.--15. 1. "NTSEG1,Nominal time segment before sample point."
hexmask.long.byte 0x4 0.--6. 1. "NTSEG2,Nominal time segment after sample point."
line.long 0x8 "TSCC,Timestamp Counter Configuration"
hexmask.long.byte 0x8 16.--19. 1. "TCP,Timestamp counter prescaler Configures the timestamp and timeout counters time unit in multiple of CAN bit times."
bitfld.long 0x8 0.--1. "TSS,Timestamp select." "0,1,2,3"
line.long 0xC "TSCV,Timestamp Counter Value"
sif (cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
hexmask.long.word 0xC 0.--15. 1. "TSC,Timestamp counter."
endif
sif (cpuis("LPC54606*"))
hexmask.long.word 0xC 0.--15. 1. "TSC,Timestamp counter."
endif
line.long 0x10 "TOCC,Timeout Counter Configuration"
hexmask.long.word 0x10 16.--31. 1. "TOP,Timeout period."
bitfld.long 0x10 1.--2. "TOS,Timeout select." "0,1,2,3"
bitfld.long 0x10 0. "ETOC,Enable timeout counter." "0,1"
rgroup.long 0x2C++0x3
line.long 0x0 "TOCV,Timeout Counter Value"
hexmask.long.word 0x0 0.--15. 1. "TOC,Timeout counter."
rgroup.long 0x40++0x7
line.long 0x0 "ECR,Error Counter Register"
hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN error logging."
bitfld.long 0x0 15. "RP,Receive error passive." "0,1"
hexmask.long.byte 0x0 8.--14. 1. "REC,Receive error counter."
hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit error counter."
line.long 0x4 "PSR,Protocol Status Register"
hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter delay compensation value."
rbitfld.long 0x4 14. "PXE,Protocol exception event." "0,1"
sif (cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
rbitfld.long 0x4 13. "RFDF,Received a CAN FD message." "0,1"
rbitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD message." "0,1"
rbitfld.long 0x4 11. "RESI,ESI flag of the last received CAN FD message." "0,1"
rbitfld.long 0x4 8.--10. "DLEC,Data phase last error code." "0,1,2,3,4,5,6,7"
endif
rbitfld.long 0x4 7. "BO,Bus Off Status." "0,1"
rbitfld.long 0x4 6. "EW,Warning status." "0,1"
rbitfld.long 0x4 5. "EP,Error Passive." "0,1"
newline
rbitfld.long 0x4 3.--4. "ACT,Activity." "0,1,2,3"
rbitfld.long 0x4 0.--2. "LEC,Last error code." "0,1,2,3,4,5,6,7"
group.long 0x48++0x3
line.long 0x0 "TDCR,Transmitter Delay Compensator Register"
hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter delay compensation offset."
hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter delay compensation filter window length."
group.long 0x50++0xF
line.long 0x0 "IR,Interrupt Register"
bitfld.long 0x0 29. "ARA,Access to reserved address." "0,1"
bitfld.long 0x0 28. "PED,Protocol error in data phase." "0,1"
bitfld.long 0x0 27. "PEA,Protocol error in arbitration phase." "0,1"
bitfld.long 0x0 26. "WDI,Watchdog interrupt." "0,1"
bitfld.long 0x0 25. "BO,Bus_Off Status." "0,1"
bitfld.long 0x0 24. "EW,Warning status." "0,1"
bitfld.long 0x0 23. "EP,Error passive." "0,1"
bitfld.long 0x0 22. "ELO,Error logging overflow." "0,1"
bitfld.long 0x0 21. "BEU,Bit error uncorrected." "0,1"
newline
bitfld.long 0x0 20. "BEC,Bit error corrected." "0,1"
bitfld.long 0x0 19. "DRX,Message stored in dedicated Rx buffer." "0,1"
bitfld.long 0x0 18. "TOO,Timeout occurred." "0,1"
bitfld.long 0x0 17. "MRAF,Message RAM access failure." "0,1"
bitfld.long 0x0 16. "TSW,Timestamp wraparound." "0,1"
bitfld.long 0x0 15. "TEFL,Tx event FIFO element lost." "0,1"
bitfld.long 0x0 14. "TEFF,Tx event FIFO full." "0,1"
bitfld.long 0x0 13. "TEFW,Tx event FIFO watermark reached." "0,1"
bitfld.long 0x0 12. "TEFN,Tx event FIFO new entry." "0,1"
newline
bitfld.long 0x0 11. "TFE,Tx FIFO empty." "0,1"
bitfld.long 0x0 10. "TCF,Transmission cancellation finished." "0,1"
bitfld.long 0x0 9. "TC,Transmission completed." "0,1"
bitfld.long 0x0 8. "HPM,High priority message." "0,1"
bitfld.long 0x0 7. "RF1L,Rx FIFO 1 message lost." "0,1"
bitfld.long 0x0 6. "RF1F,Rx FIFO 1 full." "0,1"
bitfld.long 0x0 5. "RF1W,Rx FIFO 1 watermark reached." "0,1"
bitfld.long 0x0 4. "RF1N,Rx FIFO 1 new message." "0,1"
bitfld.long 0x0 3. "RF0L,Rx FIFO 0 message lost." "0,1"
newline
bitfld.long 0x0 2. "RF0F,Rx FIFO 0 full." "0,1"
bitfld.long 0x0 1. "RF0W,Rx FIFO 0 watermark reached." "0,1"
bitfld.long 0x0 0. "RF0N,Rx FIFO 0 new message." "0,1"
line.long 0x4 "IE,Interrupt Enable"
bitfld.long 0x4 29. "ARAE,Access to reserved address interrupt enable." "0,1"
bitfld.long 0x4 28. "PEDE,Protocol error in data phase interrupt enable." "0,1"
bitfld.long 0x4 27. "PEAE,Protocol error in arbitration phase interrupt enable." "0,1"
bitfld.long 0x4 26. "WDIE,Watchdog interrupt enable." "0,1"
bitfld.long 0x4 25. "BOE,Bus_Off Status interrupt enable." "0,1"
bitfld.long 0x4 24. "EWE,Warning status interrupt enable." "0,1"
bitfld.long 0x4 23. "EPE,Error passive interrupt enable." "0,1"
bitfld.long 0x4 22. "ELOE,Error logging overflow interrupt enable." "0,1"
bitfld.long 0x4 21. "BEUE,Bit error uncorrected interrupt enable." "0,1"
newline
bitfld.long 0x4 20. "BECE,Bit error corrected interrupt enable." "0,1"
bitfld.long 0x4 19. "DRXE,Message stored in dedicated Rx buffer interrupt enable." "0,1"
bitfld.long 0x4 18. "TOOE,Timeout occurred interrupt enable." "0,1"
bitfld.long 0x4 17. "MRAFE,Message RAM access failure interrupt enable." "0,1"
bitfld.long 0x4 16. "TSWE,Timestamp wraparound interrupt enable." "0,1"
bitfld.long 0x4 15. "TEFLE,Tx event FIFO element lost interrupt enable." "0,1"
bitfld.long 0x4 14. "TEFFE,Tx event FIFO full interrupt enable." "0,1"
bitfld.long 0x4 13. "TEFWE,Tx event FIFO watermark reached interrupt enable." "0,1"
bitfld.long 0x4 12. "TEFNE,Tx event FIFO new entry interrupt enable." "0,1"
newline
bitfld.long 0x4 11. "TFEE,Tx FIFO empty interrupt enable." "0,1"
bitfld.long 0x4 10. "TCFE,Transmission cancellation finished interrupt enable." "0,1"
bitfld.long 0x4 9. "TCE,Transmission completed interrupt enable." "0,1"
bitfld.long 0x4 8. "HPME,High priority message interrupt enable." "0,1"
bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 message lost interrupt enable." "0,1"
bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 full interrupt enable." "0,1"
bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 watermark reached interrupt enable." "0,1"
bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 new message interrupt enable." "0,1"
bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 message lost interrupt enable." "0,1"
newline
bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 full interrupt enable." "0,1"
bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 watermark reached interrupt enable." "0,1"
bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 new message interrupt enable." "0,1"
line.long 0x8 "ILS,Interrupt Line Select"
bitfld.long 0x8 29. "ARAL,Access to reserved address interrupt line." "0,1"
bitfld.long 0x8 28. "PEDL,Protocol error in data phase interrupt line." "0,1"
bitfld.long 0x8 27. "PEAL,Protocol error in arbitration phase interrupt line." "0,1"
bitfld.long 0x8 26. "WDIL,Watchdog interrupt line." "0,1"
bitfld.long 0x8 25. "BOL,Bus_Off Status interrupt line." "0,1"
bitfld.long 0x8 24. "EWL,Warning status interrupt line." "0,1"
bitfld.long 0x8 23. "EPL,Error passive interrupt line." "0,1"
bitfld.long 0x8 22. "ELOL,Error logging overflow interrupt line." "0,1"
bitfld.long 0x8 21. "BEUL,Bit error uncorrected interrupt line." "0,1"
newline
bitfld.long 0x8 20. "BECL,Bit error corrected interrupt line." "0,1"
bitfld.long 0x8 19. "DRXL,Message stored in dedicated Rx buffer interrupt line." "0,1"
bitfld.long 0x8 18. "TOOL,Timeout occurred interrupt line." "0,1"
bitfld.long 0x8 17. "MRAFL,Message RAM access failure interrupt line." "0,1"
bitfld.long 0x8 16. "TSWL,Timestamp wraparound interrupt line." "0,1"
bitfld.long 0x8 15. "TEFLL,Tx event FIFO element lost interrupt line." "0,1"
bitfld.long 0x8 14. "TEFFL,Tx event FIFO full interrupt line." "0,1"
bitfld.long 0x8 13. "TEFWL,Tx event FIFO watermark reached interrupt line." "0,1"
bitfld.long 0x8 12. "TEFNL,Tx event FIFO new entry interrupt line." "0,1"
newline
bitfld.long 0x8 11. "TFEL,Tx FIFO empty interrupt line." "0,1"
bitfld.long 0x8 10. "TCFL,Transmission cancellation finished interrupt line." "0,1"
bitfld.long 0x8 9. "TCL,Transmission completed interrupt line." "0,1"
bitfld.long 0x8 8. "HPML,High priority message interrupt line." "0,1"
bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 message lost interrupt line." "0,1"
bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 full interrupt line." "0,1"
bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 watermark reached interrupt line." "0,1"
bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 new message interrupt line." "0,1"
bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 message lost interrupt line." "0,1"
newline
bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 full interrupt line." "0,1"
bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 watermark reached interrupt line." "0,1"
bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 new message interrupt line." "0,1"
line.long 0xC "ILE,Interrupt Line Enable"
bitfld.long 0xC 1. "EINT1,Enable interrupt line 1." "0,1"
bitfld.long 0xC 0. "EINT0,Enable interrupt line 0." "0,1"
group.long 0x80++0xB
line.long 0x0 "GFC,Global Filter Configuration"
bitfld.long 0x0 4.--5. "ANFS,Accept non-matching frames standard." "0,1,2,3"
bitfld.long 0x0 2.--3. "ANFE,Accept non-matching frames extended." "0,1,2,3"
bitfld.long 0x0 1. "RRFS,Reject remote frames standard." "0,1"
bitfld.long 0x0 0. "RRFE,Reject remote frames extended." "0,1"
line.long 0x4 "SIDFC,Standard ID Filter Configuration"
hexmask.long.byte 0x4 16.--23. 1. "LSS,List size standard 0 = No standard message ID filter."
hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter list standard start address."
line.long 0x8 "XIDFC,Extended ID Filter Configuration"
hexmask.long.byte 0x8 16.--23. 1. "LSE,List size extended 0 = No extended message ID filter."
hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter list extended start address."
group.long 0x90++0x3
line.long 0x0 "XIDAM,Extended ID AND Mask"
hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID mask."
rgroup.long 0x94++0x3
line.long 0x0 "HPMS,High Priority Message Status"
bitfld.long 0x0 15. "FLST,Filter list." "0,1"
hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter index."
bitfld.long 0x0 6.--7. "MSI,Message storage indicator." "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer index."
group.long 0x98++0xB
line.long 0x0 "NDAT1,New Data 1"
hexmask.long 0x0 0.--31. 1. "ND,New Data."
line.long 0x4 "NDAT2,New Data 2"
hexmask.long 0x4 0.--31. 1. "ND,New Data."
line.long 0x8 "RXF0C,Rx FIFO 0 Configuration"
bitfld.long 0x8 31. "F0OM,FIFO 0 operation mode." "0,1"
hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 watermark 0 = Watermark interrupt disabled."
hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 size."
hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 start address."
rgroup.long 0xA4++0x3
line.long 0x0 "RXF0S,Rx FIFO 0 Status"
sif (cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x0 25. "RF0L,Rx FIFO 0 message lost." "0,1"
bitfld.long 0x0 24. "F0F,Rx FIFO 0 full." "0,1"
hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 put index."
hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 get index."
hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 fill level."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x0 25. "RF0L,Rx FIFO 0 message lost." "0,1"
bitfld.long 0x0 24. "F0F,Rx FIFO 0 full." "0,1"
endif
sif (cpuis("LPC54606*"))
hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 put index."
endif
sif (cpuis("LPC54606*"))
hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 get index."
newline
endif
sif (cpuis("LPC54606*"))
hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 fill level."
endif
group.long 0xA8++0xB
line.long 0x0 "RXF0A,Rx FIFO 0 Acknowledge"
hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 acknowledge index."
line.long 0x4 "RXBC,Rx Buffer Configuration"
hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx buffer start address."
line.long 0x8 "RXF1C,Rx FIFO 1 Configuration"
bitfld.long 0x8 31. "F1OM,FIFO 1 operation mode." "0,1"
hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 watermark 0 = Watermark interrupt disabled."
hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 1 size 0 = No Rx FIFO 1."
hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 start address."
rgroup.long 0xB4++0x3
line.long 0x0 "RXF1S,Rx FIFO 1 Status"
bitfld.long 0x0 25. "RF1L,Rx FIFO 1 message lost." "0,1"
bitfld.long 0x0 24. "F1F,Rx FIFO 1 full." "0,1"
hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 put index."
hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 get index."
hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 fill level."
group.long 0xB8++0x13
line.long 0x0 "RXF1A,Rx FIFO 1 Acknowledge"
hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 acknowledge index."
line.long 0x4 "RXESC,Rx Buffer and FIFO Element Size Configuration"
bitfld.long 0x4 8.--10. "RBDS,." "0,1,2,3,4,5,6,7"
bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 data field size." "0,1,2,3,4,5,6,7"
bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 data field size." "0,1,2,3,4,5,6,7"
line.long 0x8 "TXBC,Tx Buffer Configuration"
bitfld.long 0x8 30. "TFQM,Tx FIFO/queue mode." "0,1"
hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/queue size 0 = No tx FIFO/Queue."
hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of dedicated transmit buffers 0 = No dedicated Tx buffers."
hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx buffers start address."
line.long 0xC "TXFQS,Tx FIFO/Queue Status"
bitfld.long 0xC 21. "TFQF,Tx FIFO/queue full." "0,1"
hexmask.long.byte 0xC 16.--20. 1. "TFQPI,Tx FIFO/queue put index."
hexmask.long.byte 0xC 8.--12. 1. "TFGI,Tx FIFO get index."
line.long 0x10 "TXESC,Tx Buffer Element Size Configuration"
bitfld.long 0x10 0.--2. "TBDS,Tx buffer data field size." "0,1,2,3,4,5,6,7"
rgroup.long 0xCC++0x3
line.long 0x0 "TXBRP,Tx Buffer Request Pending"
sif (cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
hexmask.long 0x0 0.--31. 1. "TRP,Transmission request pending."
endif
sif (cpuis("LPC54606*"))
hexmask.long 0x0 0.--31. 1. "TRP,Transmission request pending."
endif
group.long 0xD0++0x7
line.long 0x0 "TXBAR,Tx Buffer Add Request"
hexmask.long 0x0 0.--31. 1. "AR,Add request."
line.long 0x4 "TXBCR,Tx Buffer Cancellation Request"
hexmask.long 0x4 0.--31. 1. "CR,Cancellation request."
rgroup.long 0xD8++0x7
line.long 0x0 "TXBTO,Tx Buffer Transmission Occurred"
sif (cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
hexmask.long 0x0 0.--31. 1. "TO,Transmission occurred."
endif
sif (cpuis("LPC54606*"))
hexmask.long 0x0 0.--31. 1. "TO,Transmission occurred."
endif
line.long 0x4 "TXBCF,Tx Buffer Cancellation Finished"
sif (cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
hexmask.long 0x4 0.--31. 1. "TO,Cancellation finished."
endif
sif (cpuis("LPC54606*"))
hexmask.long 0x4 0.--31. 1. "TO,Cancellation finished."
endif
group.long 0xE0++0x7
line.long 0x0 "TXBTIE,Tx Buffer Transmission Interrupt Enable"
hexmask.long 0x0 0.--31. 1. "TIE,Transmission interrupt enable."
line.long 0x4 "TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable"
hexmask.long 0x4 0.--31. 1. "CFIE,Cancellation finished interrupt enable."
group.long 0xF0++0x3
line.long 0x0 "TXEFC,Tx Event FIFO Configuration"
hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO watermark 0 = Watermark interrupt disabled."
hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO size 0 = Tx event FIFO disabled."
hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO start address."
rgroup.long 0xF4++0x3
line.long 0x0 "TXEFS,Tx Event FIFO Status"
bitfld.long 0x0 25. "TEFL,Tx event FIFO element lost." "0,1"
bitfld.long 0x0 24. "EFF,Event FIFO full." "0,1"
hexmask.long.byte 0x0 16.--21. 1. "EFPI,Event FIFO put index."
hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO get index."
hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO fill level."
group.long 0xF8++0x3
line.long 0x0 "TXEFA,Tx Event FIFO Acknowledge"
hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO acknowledge index."
group.long 0x200++0x3
line.long 0x0 "MRBA,CAN Message RAM Base Address"
hexmask.long.word 0x0 16.--31. 1. "BA,Base address for the message RAM in the chip memory map."
group.long 0x400++0x3
line.long 0x0 "ETSCC,External Timestamp Counter Configuration"
bitfld.long 0x0 31. "ETCE,External timestamp counter enable." "0,1"
hexmask.long.word 0x0 0.--10. 1. "ETCP,External timestamp prescaler value."
group.long 0x600++0x3
line.long 0x0 "ETSCV,External Timestamp Counter Value"
hexmask.long.word 0x0 0.--15. 1. "ETSC,External timestamp counter."
sif (cpuis("LPC54606*"))
group.long 0xCC++0x3
line.long 0x0 "TXBRP,Tx Buffer Request Pending"
endif
sif (cpuis("LPC54606*"))
group.long 0xD8++0x3
line.long 0x0 "TXBTO,Tx Buffer Transmission Occurred"
endif
sif (cpuis("LPC54606*"))
group.long 0xDC++0x3
line.long 0x0 "TXBCF,Tx Buffer Cancellation Finished"
endif
tree.end
endif
sif (cpuis("LPC54608*"))
tree "CAN0"
base ad:0x4009D000
group.long 0x10++0x3
line.long 0x0 "TEST,Test Register"
bitfld.long 0x0 7. "RX,Monitors the actual value of the CAN_RXD." "0,1"
bitfld.long 0x0 5.--6. "TX,Control of transmit pin." "0,1,2,3"
bitfld.long 0x0 4. "LBCK,Loop back mode." "0,1"
group.long 0x18++0x13
line.long 0x0 "CCCR,CC Control Register"
bitfld.long 0x0 14. "TXP,Transmit pause." "0,1"
bitfld.long 0x0 13. "EFBI,Edge filtering during bus integration." "0,1"
bitfld.long 0x0 12. "PXHD,Protocol exception handling disable." "0,1"
bitfld.long 0x0 7. "TEST,Test mode enable." "0,1"
bitfld.long 0x0 6. "DAR,Disable automatic retransmission." "0,1"
bitfld.long 0x0 5. "MON,Bus monitoring mode." "0,1"
bitfld.long 0x0 4. "CSR,Clock Stop Request." "0,1"
bitfld.long 0x0 3. "CSA,Clock Stop Acknowledge." "0,1"
bitfld.long 0x0 2. "ASM,Restricted operational mode." "0,1"
bitfld.long 0x0 1. "CCE,Configuration change enable." "0,1"
newline
bitfld.long 0x0 0. "INIT,Initialization." "0,1"
line.long 0x4 "NBTP,Nominal Bit Timing and Prescaler Register"
hexmask.long.byte 0x4 25.--31. 1. "NSJW,Nominal (re)synchronization jump width."
hexmask.long.word 0x4 16.--24. 1. "NBRP,Nominal bit rate prescaler."
hexmask.long.byte 0x4 8.--15. 1. "NTSEG1,Nominal time segment before sample point."
hexmask.long.byte 0x4 0.--6. 1. "NTSEG2,Nominal time segment after sample point."
line.long 0x8 "TSCC,Timestamp Counter Configuration"
hexmask.long.byte 0x8 16.--19. 1. "TCP,Timestamp counter prescaler Configures the timestamp and timeout counters time unit in multiple of CAN bit times."
bitfld.long 0x8 0.--1. "TSS,Timestamp select." "0,1,2,3"
line.long 0xC "TSCV,Timestamp Counter Value"
hexmask.long.word 0xC 0.--15. 1. "TSC,Timestamp counter."
line.long 0x10 "TOCC,Timeout Counter Configuration"
hexmask.long.word 0x10 16.--31. 1. "TOP,Timeout period."
bitfld.long 0x10 1.--2. "TOS,Timeout select." "0,1,2,3"
bitfld.long 0x10 0. "ETOC,Enable timeout counter." "0,1"
rgroup.long 0x2C++0x3
line.long 0x0 "TOCV,Timeout Counter Value"
hexmask.long.word 0x0 0.--15. 1. "TOC,Timeout counter."
rgroup.long 0x40++0x7
line.long 0x0 "ECR,Error Counter Register"
hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN error logging."
bitfld.long 0x0 15. "RP,Receive error passive." "0,1"
hexmask.long.byte 0x0 8.--14. 1. "REC,Receive error counter."
hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit error counter."
line.long 0x4 "PSR,Protocol Status Register"
hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter delay compensation value."
bitfld.long 0x4 14. "PXE,Protocol exception event." "0,1"
bitfld.long 0x4 7. "BO,Bus Off Status." "0,1"
bitfld.long 0x4 6. "EW,Warning status." "0,1"
bitfld.long 0x4 5. "EP,Error Passive." "0,1"
bitfld.long 0x4 3.--4. "ACT,Activity." "0,1,2,3"
bitfld.long 0x4 0.--2. "LEC,Last error code." "0,1,2,3,4,5,6,7"
group.long 0x48++0x3
line.long 0x0 "TDCR,Transmitter Delay Compensator Register"
hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter delay compensation offset."
hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter delay compensation filter window length."
group.long 0x50++0xF
line.long 0x0 "IR,Interrupt Register"
bitfld.long 0x0 29. "ARA,Access to reserved address." "0,1"
bitfld.long 0x0 28. "PED,Protocol error in data phase." "0,1"
bitfld.long 0x0 27. "PEA,Protocol error in arbitration phase." "0,1"
bitfld.long 0x0 26. "WDI,Watchdog interrupt." "0,1"
bitfld.long 0x0 25. "BO,Bus_Off Status." "0,1"
bitfld.long 0x0 24. "EW,Warning status." "0,1"
bitfld.long 0x0 23. "EP,Error passive." "0,1"
bitfld.long 0x0 22. "ELO,Error logging overflow." "0,1"
bitfld.long 0x0 21. "BEU,Bit error uncorrected." "0,1"
bitfld.long 0x0 20. "BEC,Bit error corrected." "0,1"
newline
bitfld.long 0x0 19. "DRX,Message stored in dedicated Rx buffer." "0,1"
bitfld.long 0x0 18. "TOO,Timeout occurred." "0,1"
bitfld.long 0x0 17. "MRAF,Message RAM access failure." "0,1"
bitfld.long 0x0 16. "TSW,Timestamp wraparound." "0,1"
bitfld.long 0x0 15. "TEFL,Tx event FIFO element lost." "0,1"
bitfld.long 0x0 14. "TEFF,Tx event FIFO full." "0,1"
bitfld.long 0x0 13. "TEFW,Tx event FIFO watermark reached." "0,1"
bitfld.long 0x0 12. "TEFN,Tx event FIFO new entry." "0,1"
bitfld.long 0x0 11. "TFE,Tx FIFO empty." "0,1"
bitfld.long 0x0 10. "TCF,Transmission cancellation finished." "0,1"
newline
bitfld.long 0x0 9. "TC,Transmission completed." "0,1"
bitfld.long 0x0 8. "HPM,High priority message." "0,1"
bitfld.long 0x0 7. "RF1L,Rx FIFO 1 message lost." "0,1"
bitfld.long 0x0 6. "RF1F,Rx FIFO 1 full." "0,1"
bitfld.long 0x0 5. "RF1W,Rx FIFO 1 watermark reached." "0,1"
bitfld.long 0x0 4. "RF1N,Rx FIFO 1 new message." "0,1"
bitfld.long 0x0 3. "RF0L,Rx FIFO 0 message lost." "0,1"
bitfld.long 0x0 2. "RF0F,Rx FIFO 0 full." "0,1"
bitfld.long 0x0 1. "RF0W,Rx FIFO 0 watermark reached." "0,1"
bitfld.long 0x0 0. "RF0N,Rx FIFO 0 new message." "0,1"
line.long 0x4 "IE,Interrupt Enable"
bitfld.long 0x4 29. "ARAE,Access to reserved address interrupt enable." "0,1"
bitfld.long 0x4 28. "PEDE,Protocol error in data phase interrupt enable." "0,1"
bitfld.long 0x4 27. "PEAE,Protocol error in arbitration phase interrupt enable." "0,1"
bitfld.long 0x4 26. "WDIE,Watchdog interrupt enable." "0,1"
bitfld.long 0x4 25. "BOE,Bus_Off Status interrupt enable." "0,1"
bitfld.long 0x4 24. "EWE,Warning status interrupt enable." "0,1"
bitfld.long 0x4 23. "EPE,Error passive interrupt enable." "0,1"
bitfld.long 0x4 22. "ELOE,Error logging overflow interrupt enable." "0,1"
bitfld.long 0x4 21. "BEUE,Bit error uncorrected interrupt enable." "0,1"
bitfld.long 0x4 20. "BECE,Bit error corrected interrupt enable." "0,1"
newline
bitfld.long 0x4 19. "DRXE,Message stored in dedicated Rx buffer interrupt enable." "0,1"
bitfld.long 0x4 18. "TOOE,Timeout occurred interrupt enable." "0,1"
bitfld.long 0x4 17. "MRAFE,Message RAM access failure interrupt enable." "0,1"
bitfld.long 0x4 16. "TSWE,Timestamp wraparound interrupt enable." "0,1"
bitfld.long 0x4 15. "TEFLE,Tx event FIFO element lost interrupt enable." "0,1"
bitfld.long 0x4 14. "TEFFE,Tx event FIFO full interrupt enable." "0,1"
bitfld.long 0x4 13. "TEFWE,Tx event FIFO watermark reached interrupt enable." "0,1"
bitfld.long 0x4 12. "TEFNE,Tx event FIFO new entry interrupt enable." "0,1"
bitfld.long 0x4 11. "TFEE,Tx FIFO empty interrupt enable." "0,1"
bitfld.long 0x4 10. "TCFE,Transmission cancellation finished interrupt enable." "0,1"
newline
bitfld.long 0x4 9. "TCE,Transmission completed interrupt enable." "0,1"
bitfld.long 0x4 8. "HPME,High priority message interrupt enable." "0,1"
bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 message lost interrupt enable." "0,1"
bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 full interrupt enable." "0,1"
bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 watermark reached interrupt enable." "0,1"
bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 new message interrupt enable." "0,1"
bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 message lost interrupt enable." "0,1"
bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 full interrupt enable." "0,1"
bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 watermark reached interrupt enable." "0,1"
bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 new message interrupt enable." "0,1"
line.long 0x8 "ILS,Interrupt Line Select"
bitfld.long 0x8 29. "ARAL,Access to reserved address interrupt line." "0,1"
bitfld.long 0x8 28. "PEDL,Protocol error in data phase interrupt line." "0,1"
bitfld.long 0x8 27. "PEAL,Protocol error in arbitration phase interrupt line." "0,1"
bitfld.long 0x8 26. "WDIL,Watchdog interrupt line." "0,1"
bitfld.long 0x8 25. "BOL,Bus_Off Status interrupt line." "0,1"
bitfld.long 0x8 24. "EWL,Warning status interrupt line." "0,1"
bitfld.long 0x8 23. "EPL,Error passive interrupt line." "0,1"
bitfld.long 0x8 22. "ELOL,Error logging overflow interrupt line." "0,1"
bitfld.long 0x8 21. "BEUL,Bit error uncorrected interrupt line." "0,1"
bitfld.long 0x8 20. "BECL,Bit error corrected interrupt line." "0,1"
newline
bitfld.long 0x8 19. "DRXL,Message stored in dedicated Rx buffer interrupt line." "0,1"
bitfld.long 0x8 18. "TOOL,Timeout occurred interrupt line." "0,1"
bitfld.long 0x8 17. "MRAFL,Message RAM access failure interrupt line." "0,1"
bitfld.long 0x8 16. "TSWL,Timestamp wraparound interrupt line." "0,1"
bitfld.long 0x8 15. "TEFLL,Tx event FIFO element lost interrupt line." "0,1"
bitfld.long 0x8 14. "TEFFL,Tx event FIFO full interrupt line." "0,1"
bitfld.long 0x8 13. "TEFWL,Tx event FIFO watermark reached interrupt line." "0,1"
bitfld.long 0x8 12. "TEFNL,Tx event FIFO new entry interrupt line." "0,1"
bitfld.long 0x8 11. "TFEL,Tx FIFO empty interrupt line." "0,1"
bitfld.long 0x8 10. "TCFL,Transmission cancellation finished interrupt line." "0,1"
newline
bitfld.long 0x8 9. "TCL,Transmission completed interrupt line." "0,1"
bitfld.long 0x8 8. "HPML,High priority message interrupt line." "0,1"
bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 message lost interrupt line." "0,1"
bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 full interrupt line." "0,1"
bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 watermark reached interrupt line." "0,1"
bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 new message interrupt line." "0,1"
bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 message lost interrupt line." "0,1"
bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 full interrupt line." "0,1"
bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 watermark reached interrupt line." "0,1"
bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 new message interrupt line." "0,1"
line.long 0xC "ILE,Interrupt Line Enable"
bitfld.long 0xC 1. "EINT1,Enable interrupt line 1." "0,1"
bitfld.long 0xC 0. "EINT0,Enable interrupt line 0." "0,1"
group.long 0x80++0xB
line.long 0x0 "GFC,Global Filter Configuration"
bitfld.long 0x0 4.--5. "ANFS,Accept non-matching frames standard." "0,1,2,3"
bitfld.long 0x0 2.--3. "ANFE,Accept non-matching frames extended." "0,1,2,3"
bitfld.long 0x0 1. "RRFS,Reject remote frames standard." "0,1"
bitfld.long 0x0 0. "RRFE,Reject remote frames extended." "0,1"
line.long 0x4 "SIDFC,Standard ID Filter Configuration"
hexmask.long.byte 0x4 16.--23. 1. "LSS,List size standard 0 = No standard message ID filter."
hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter list standard start address."
line.long 0x8 "XIDFC,Extended ID Filter Configuration"
hexmask.long.byte 0x8 16.--23. 1. "LSE,List size extended 0 = No extended message ID filter."
hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter list extended start address."
group.long 0x90++0x3
line.long 0x0 "XIDAM,Extended ID AND Mask"
hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID mask."
rgroup.long 0x94++0x3
line.long 0x0 "HPMS,High Priority Message Status"
bitfld.long 0x0 15. "FLST,Filter list." "0,1"
hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter index."
bitfld.long 0x0 6.--7. "MSI,Message storage indicator." "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer index."
group.long 0x98++0x1B
line.long 0x0 "NDAT1,New Data 1"
hexmask.long 0x0 0.--31. 1. "ND,New Data."
line.long 0x4 "NDAT2,New Data 2"
hexmask.long 0x4 0.--31. 1. "ND,New Data."
line.long 0x8 "RXF0C,Rx FIFO 0 Configuration"
bitfld.long 0x8 31. "F0OM,FIFO 0 operation mode." "0,1"
hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 watermark 0 = Watermark interrupt disabled."
hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 size."
hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 start address."
line.long 0xC "RXF0S,Rx FIFO 0 Status"
bitfld.long 0xC 25. "RF0L,Rx FIFO 0 message lost." "0,1"
bitfld.long 0xC 24. "F0F,Rx FIFO 0 full." "0,1"
hexmask.long.byte 0xC 16.--21. 1. "F0PI,Rx FIFO 0 put index."
hexmask.long.byte 0xC 8.--13. 1. "F0GI,Rx FIFO 0 get index."
hexmask.long.byte 0xC 0.--6. 1. "F0FL,Rx FIFO 0 fill level."
line.long 0x10 "RXF0A,Rx FIFO 0 Acknowledge"
hexmask.long.byte 0x10 0.--5. 1. "F0AI,Rx FIFO 0 acknowledge index."
line.long 0x14 "RXBC,Rx Buffer Configuration"
hexmask.long.word 0x14 2.--15. 1. "RBSA,Rx buffer start address."
line.long 0x18 "RXF1C,Rx FIFO 1 Configuration"
bitfld.long 0x18 31. "F1OM,FIFO 1 operation mode." "0,1"
hexmask.long.byte 0x18 24.--30. 1. "F1WM,Rx FIFO 1 watermark 0 = Watermark interrupt disabled."
hexmask.long.byte 0x18 16.--22. 1. "F1S,Rx FIFO 1 size 0 = No Rx FIFO 1."
hexmask.long.word 0x18 2.--15. 1. "F1SA,Rx FIFO 1 start address."
rgroup.long 0xB4++0x3
line.long 0x0 "RXF1S,Rx FIFO 1 Status"
bitfld.long 0x0 25. "RF1L,Rx FIFO 1 message lost." "0,1"
bitfld.long 0x0 24. "F1F,Rx FIFO 1 full." "0,1"
hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 put index."
hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 get index."
hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 fill level."
group.long 0xB8++0x2F
line.long 0x0 "RXF1A,Rx FIFO 1 Acknowledge"
hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 acknowledge index."
line.long 0x4 "RXESC,Rx Buffer and FIFO Element Size Configuration"
bitfld.long 0x4 8.--10. "RBDS,." "0,1,2,3,4,5,6,7"
bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 data field size." "0,1,2,3,4,5,6,7"
bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 data field size." "0,1,2,3,4,5,6,7"
line.long 0x8 "TXBC,Tx Buffer Configuration"
bitfld.long 0x8 30. "TFQM,Tx FIFO/queue mode." "0,1"
hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/queue size 0 = No tx FIFO/Queue."
hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of dedicated transmit buffers 0 = No dedicated Tx buffers."
hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx buffers start address."
line.long 0xC "TXFQS,Tx FIFO/Queue Status"
bitfld.long 0xC 21. "TFQF,Tx FIFO/queue full." "0,1"
hexmask.long.byte 0xC 16.--20. 1. "TFQPI,Tx FIFO/queue put index."
hexmask.long.byte 0xC 8.--12. 1. "TFGI,Tx FIFO get index."
line.long 0x10 "TXESC,Tx Buffer Element Size Configuration"
bitfld.long 0x10 0.--2. "TBDS,Tx buffer data field size." "0,1,2,3,4,5,6,7"
line.long 0x14 "TXBRP,Tx Buffer Request Pending"
hexmask.long 0x14 0.--31. 1. "TRP,Transmission request pending."
line.long 0x18 "TXBAR,Tx Buffer Add Request"
hexmask.long 0x18 0.--31. 1. "AR,Add request."
line.long 0x1C "TXBCR,Tx Buffer Cancellation Request"
hexmask.long 0x1C 0.--31. 1. "CR,Cancellation request."
line.long 0x20 "TXBTO,Tx Buffer Transmission Occurred"
hexmask.long 0x20 0.--31. 1. "TO,Transmission occurred."
line.long 0x24 "TXBCF,Tx Buffer Cancellation Finished"
hexmask.long 0x24 0.--31. 1. "TO,Cancellation finished."
line.long 0x28 "TXBTIE,Tx Buffer Transmission Interrupt Enable"
hexmask.long 0x28 0.--31. 1. "TIE,Transmission interrupt enable."
line.long 0x2C "TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable"
hexmask.long 0x2C 0.--31. 1. "CFIE,Cancellation finished interrupt enable."
group.long 0xF0++0x3
line.long 0x0 "TXEFC,Tx Event FIFO Configuration"
hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO watermark 0 = Watermark interrupt disabled."
hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO size 0 = Tx event FIFO disabled."
hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO start address."
rgroup.long 0xF4++0x3
line.long 0x0 "TXEFS,Tx Event FIFO Status"
bitfld.long 0x0 25. "TEFL,Tx event FIFO element lost." "0,1"
bitfld.long 0x0 24. "EFF,Event FIFO full." "0,1"
hexmask.long.byte 0x0 16.--21. 1. "EFPI,Event FIFO put index."
hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO get index."
hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO fill level."
group.long 0xF8++0x3
line.long 0x0 "TXEFA,Tx Event FIFO Acknowledge"
hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO acknowledge index."
group.long 0x200++0x3
line.long 0x0 "MRBA,CAN Message RAM Base Address"
hexmask.long.word 0x0 16.--31. 1. "BA,Base address for the message RAM in the chip memory map."
group.long 0x400++0x3
line.long 0x0 "ETSCC,External Timestamp Counter Configuration"
bitfld.long 0x0 31. "ETCE,External timestamp counter enable." "0,1"
hexmask.long.word 0x0 0.--10. 1. "ETCP,External timestamp prescaler value."
group.long 0x600++0x3
line.long 0x0 "ETSCV,External Timestamp Counter Value"
hexmask.long.word 0x0 0.--15. 1. "ETSC,External timestamp counter."
tree.end
tree "CAN1"
base ad:0x4009E000
group.long 0x10++0x3
line.long 0x0 "TEST,Test Register"
bitfld.long 0x0 7. "RX,Monitors the actual value of the CAN_RXD." "0,1"
bitfld.long 0x0 5.--6. "TX,Control of transmit pin." "0,1,2,3"
bitfld.long 0x0 4. "LBCK,Loop back mode." "0,1"
group.long 0x18++0x13
line.long 0x0 "CCCR,CC Control Register"
bitfld.long 0x0 14. "TXP,Transmit pause." "0,1"
bitfld.long 0x0 13. "EFBI,Edge filtering during bus integration." "0,1"
bitfld.long 0x0 12. "PXHD,Protocol exception handling disable." "0,1"
bitfld.long 0x0 7. "TEST,Test mode enable." "0,1"
bitfld.long 0x0 6. "DAR,Disable automatic retransmission." "0,1"
bitfld.long 0x0 5. "MON,Bus monitoring mode." "0,1"
bitfld.long 0x0 4. "CSR,Clock Stop Request." "0,1"
bitfld.long 0x0 3. "CSA,Clock Stop Acknowledge." "0,1"
bitfld.long 0x0 2. "ASM,Restricted operational mode." "0,1"
bitfld.long 0x0 1. "CCE,Configuration change enable." "0,1"
newline
bitfld.long 0x0 0. "INIT,Initialization." "0,1"
line.long 0x4 "NBTP,Nominal Bit Timing and Prescaler Register"
hexmask.long.byte 0x4 25.--31. 1. "NSJW,Nominal (re)synchronization jump width."
hexmask.long.word 0x4 16.--24. 1. "NBRP,Nominal bit rate prescaler."
hexmask.long.byte 0x4 8.--15. 1. "NTSEG1,Nominal time segment before sample point."
hexmask.long.byte 0x4 0.--6. 1. "NTSEG2,Nominal time segment after sample point."
line.long 0x8 "TSCC,Timestamp Counter Configuration"
hexmask.long.byte 0x8 16.--19. 1. "TCP,Timestamp counter prescaler Configures the timestamp and timeout counters time unit in multiple of CAN bit times."
bitfld.long 0x8 0.--1. "TSS,Timestamp select." "0,1,2,3"
line.long 0xC "TSCV,Timestamp Counter Value"
hexmask.long.word 0xC 0.--15. 1. "TSC,Timestamp counter."
line.long 0x10 "TOCC,Timeout Counter Configuration"
hexmask.long.word 0x10 16.--31. 1. "TOP,Timeout period."
bitfld.long 0x10 1.--2. "TOS,Timeout select." "0,1,2,3"
bitfld.long 0x10 0. "ETOC,Enable timeout counter." "0,1"
rgroup.long 0x2C++0x3
line.long 0x0 "TOCV,Timeout Counter Value"
hexmask.long.word 0x0 0.--15. 1. "TOC,Timeout counter."
rgroup.long 0x40++0x7
line.long 0x0 "ECR,Error Counter Register"
hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN error logging."
bitfld.long 0x0 15. "RP,Receive error passive." "0,1"
hexmask.long.byte 0x0 8.--14. 1. "REC,Receive error counter."
hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit error counter."
line.long 0x4 "PSR,Protocol Status Register"
hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter delay compensation value."
bitfld.long 0x4 14. "PXE,Protocol exception event." "0,1"
bitfld.long 0x4 7. "BO,Bus Off Status." "0,1"
bitfld.long 0x4 6. "EW,Warning status." "0,1"
bitfld.long 0x4 5. "EP,Error Passive." "0,1"
bitfld.long 0x4 3.--4. "ACT,Activity." "0,1,2,3"
bitfld.long 0x4 0.--2. "LEC,Last error code." "0,1,2,3,4,5,6,7"
group.long 0x48++0x3
line.long 0x0 "TDCR,Transmitter Delay Compensator Register"
hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter delay compensation offset."
hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter delay compensation filter window length."
group.long 0x50++0xF
line.long 0x0 "IR,Interrupt Register"
bitfld.long 0x0 29. "ARA,Access to reserved address." "0,1"
bitfld.long 0x0 28. "PED,Protocol error in data phase." "0,1"
bitfld.long 0x0 27. "PEA,Protocol error in arbitration phase." "0,1"
bitfld.long 0x0 26. "WDI,Watchdog interrupt." "0,1"
bitfld.long 0x0 25. "BO,Bus_Off Status." "0,1"
bitfld.long 0x0 24. "EW,Warning status." "0,1"
bitfld.long 0x0 23. "EP,Error passive." "0,1"
bitfld.long 0x0 22. "ELO,Error logging overflow." "0,1"
bitfld.long 0x0 21. "BEU,Bit error uncorrected." "0,1"
bitfld.long 0x0 20. "BEC,Bit error corrected." "0,1"
newline
bitfld.long 0x0 19. "DRX,Message stored in dedicated Rx buffer." "0,1"
bitfld.long 0x0 18. "TOO,Timeout occurred." "0,1"
bitfld.long 0x0 17. "MRAF,Message RAM access failure." "0,1"
bitfld.long 0x0 16. "TSW,Timestamp wraparound." "0,1"
bitfld.long 0x0 15. "TEFL,Tx event FIFO element lost." "0,1"
bitfld.long 0x0 14. "TEFF,Tx event FIFO full." "0,1"
bitfld.long 0x0 13. "TEFW,Tx event FIFO watermark reached." "0,1"
bitfld.long 0x0 12. "TEFN,Tx event FIFO new entry." "0,1"
bitfld.long 0x0 11. "TFE,Tx FIFO empty." "0,1"
bitfld.long 0x0 10. "TCF,Transmission cancellation finished." "0,1"
newline
bitfld.long 0x0 9. "TC,Transmission completed." "0,1"
bitfld.long 0x0 8. "HPM,High priority message." "0,1"
bitfld.long 0x0 7. "RF1L,Rx FIFO 1 message lost." "0,1"
bitfld.long 0x0 6. "RF1F,Rx FIFO 1 full." "0,1"
bitfld.long 0x0 5. "RF1W,Rx FIFO 1 watermark reached." "0,1"
bitfld.long 0x0 4. "RF1N,Rx FIFO 1 new message." "0,1"
bitfld.long 0x0 3. "RF0L,Rx FIFO 0 message lost." "0,1"
bitfld.long 0x0 2. "RF0F,Rx FIFO 0 full." "0,1"
bitfld.long 0x0 1. "RF0W,Rx FIFO 0 watermark reached." "0,1"
bitfld.long 0x0 0. "RF0N,Rx FIFO 0 new message." "0,1"
line.long 0x4 "IE,Interrupt Enable"
bitfld.long 0x4 29. "ARAE,Access to reserved address interrupt enable." "0,1"
bitfld.long 0x4 28. "PEDE,Protocol error in data phase interrupt enable." "0,1"
bitfld.long 0x4 27. "PEAE,Protocol error in arbitration phase interrupt enable." "0,1"
bitfld.long 0x4 26. "WDIE,Watchdog interrupt enable." "0,1"
bitfld.long 0x4 25. "BOE,Bus_Off Status interrupt enable." "0,1"
bitfld.long 0x4 24. "EWE,Warning status interrupt enable." "0,1"
bitfld.long 0x4 23. "EPE,Error passive interrupt enable." "0,1"
bitfld.long 0x4 22. "ELOE,Error logging overflow interrupt enable." "0,1"
bitfld.long 0x4 21. "BEUE,Bit error uncorrected interrupt enable." "0,1"
bitfld.long 0x4 20. "BECE,Bit error corrected interrupt enable." "0,1"
newline
bitfld.long 0x4 19. "DRXE,Message stored in dedicated Rx buffer interrupt enable." "0,1"
bitfld.long 0x4 18. "TOOE,Timeout occurred interrupt enable." "0,1"
bitfld.long 0x4 17. "MRAFE,Message RAM access failure interrupt enable." "0,1"
bitfld.long 0x4 16. "TSWE,Timestamp wraparound interrupt enable." "0,1"
bitfld.long 0x4 15. "TEFLE,Tx event FIFO element lost interrupt enable." "0,1"
bitfld.long 0x4 14. "TEFFE,Tx event FIFO full interrupt enable." "0,1"
bitfld.long 0x4 13. "TEFWE,Tx event FIFO watermark reached interrupt enable." "0,1"
bitfld.long 0x4 12. "TEFNE,Tx event FIFO new entry interrupt enable." "0,1"
bitfld.long 0x4 11. "TFEE,Tx FIFO empty interrupt enable." "0,1"
bitfld.long 0x4 10. "TCFE,Transmission cancellation finished interrupt enable." "0,1"
newline
bitfld.long 0x4 9. "TCE,Transmission completed interrupt enable." "0,1"
bitfld.long 0x4 8. "HPME,High priority message interrupt enable." "0,1"
bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 message lost interrupt enable." "0,1"
bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 full interrupt enable." "0,1"
bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 watermark reached interrupt enable." "0,1"
bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 new message interrupt enable." "0,1"
bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 message lost interrupt enable." "0,1"
bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 full interrupt enable." "0,1"
bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 watermark reached interrupt enable." "0,1"
bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 new message interrupt enable." "0,1"
line.long 0x8 "ILS,Interrupt Line Select"
bitfld.long 0x8 29. "ARAL,Access to reserved address interrupt line." "0,1"
bitfld.long 0x8 28. "PEDL,Protocol error in data phase interrupt line." "0,1"
bitfld.long 0x8 27. "PEAL,Protocol error in arbitration phase interrupt line." "0,1"
bitfld.long 0x8 26. "WDIL,Watchdog interrupt line." "0,1"
bitfld.long 0x8 25. "BOL,Bus_Off Status interrupt line." "0,1"
bitfld.long 0x8 24. "EWL,Warning status interrupt line." "0,1"
bitfld.long 0x8 23. "EPL,Error passive interrupt line." "0,1"
bitfld.long 0x8 22. "ELOL,Error logging overflow interrupt line." "0,1"
bitfld.long 0x8 21. "BEUL,Bit error uncorrected interrupt line." "0,1"
bitfld.long 0x8 20. "BECL,Bit error corrected interrupt line." "0,1"
newline
bitfld.long 0x8 19. "DRXL,Message stored in dedicated Rx buffer interrupt line." "0,1"
bitfld.long 0x8 18. "TOOL,Timeout occurred interrupt line." "0,1"
bitfld.long 0x8 17. "MRAFL,Message RAM access failure interrupt line." "0,1"
bitfld.long 0x8 16. "TSWL,Timestamp wraparound interrupt line." "0,1"
bitfld.long 0x8 15. "TEFLL,Tx event FIFO element lost interrupt line." "0,1"
bitfld.long 0x8 14. "TEFFL,Tx event FIFO full interrupt line." "0,1"
bitfld.long 0x8 13. "TEFWL,Tx event FIFO watermark reached interrupt line." "0,1"
bitfld.long 0x8 12. "TEFNL,Tx event FIFO new entry interrupt line." "0,1"
bitfld.long 0x8 11. "TFEL,Tx FIFO empty interrupt line." "0,1"
bitfld.long 0x8 10. "TCFL,Transmission cancellation finished interrupt line." "0,1"
newline
bitfld.long 0x8 9. "TCL,Transmission completed interrupt line." "0,1"
bitfld.long 0x8 8. "HPML,High priority message interrupt line." "0,1"
bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 message lost interrupt line." "0,1"
bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 full interrupt line." "0,1"
bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 watermark reached interrupt line." "0,1"
bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 new message interrupt line." "0,1"
bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 message lost interrupt line." "0,1"
bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 full interrupt line." "0,1"
bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 watermark reached interrupt line." "0,1"
bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 new message interrupt line." "0,1"
line.long 0xC "ILE,Interrupt Line Enable"
bitfld.long 0xC 1. "EINT1,Enable interrupt line 1." "0,1"
bitfld.long 0xC 0. "EINT0,Enable interrupt line 0." "0,1"
group.long 0x80++0xB
line.long 0x0 "GFC,Global Filter Configuration"
bitfld.long 0x0 4.--5. "ANFS,Accept non-matching frames standard." "0,1,2,3"
bitfld.long 0x0 2.--3. "ANFE,Accept non-matching frames extended." "0,1,2,3"
bitfld.long 0x0 1. "RRFS,Reject remote frames standard." "0,1"
bitfld.long 0x0 0. "RRFE,Reject remote frames extended." "0,1"
line.long 0x4 "SIDFC,Standard ID Filter Configuration"
hexmask.long.byte 0x4 16.--23. 1. "LSS,List size standard 0 = No standard message ID filter."
hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter list standard start address."
line.long 0x8 "XIDFC,Extended ID Filter Configuration"
hexmask.long.byte 0x8 16.--23. 1. "LSE,List size extended 0 = No extended message ID filter."
hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter list extended start address."
group.long 0x90++0x3
line.long 0x0 "XIDAM,Extended ID AND Mask"
hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID mask."
rgroup.long 0x94++0x3
line.long 0x0 "HPMS,High Priority Message Status"
bitfld.long 0x0 15. "FLST,Filter list." "0,1"
hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter index."
bitfld.long 0x0 6.--7. "MSI,Message storage indicator." "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer index."
group.long 0x98++0x1B
line.long 0x0 "NDAT1,New Data 1"
hexmask.long 0x0 0.--31. 1. "ND,New Data."
line.long 0x4 "NDAT2,New Data 2"
hexmask.long 0x4 0.--31. 1. "ND,New Data."
line.long 0x8 "RXF0C,Rx FIFO 0 Configuration"
bitfld.long 0x8 31. "F0OM,FIFO 0 operation mode." "0,1"
hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 watermark 0 = Watermark interrupt disabled."
hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 size."
hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 start address."
line.long 0xC "RXF0S,Rx FIFO 0 Status"
bitfld.long 0xC 25. "RF0L,Rx FIFO 0 message lost." "0,1"
bitfld.long 0xC 24. "F0F,Rx FIFO 0 full." "0,1"
hexmask.long.byte 0xC 16.--21. 1. "F0PI,Rx FIFO 0 put index."
hexmask.long.byte 0xC 8.--13. 1. "F0GI,Rx FIFO 0 get index."
hexmask.long.byte 0xC 0.--6. 1. "F0FL,Rx FIFO 0 fill level."
line.long 0x10 "RXF0A,Rx FIFO 0 Acknowledge"
hexmask.long.byte 0x10 0.--5. 1. "F0AI,Rx FIFO 0 acknowledge index."
line.long 0x14 "RXBC,Rx Buffer Configuration"
hexmask.long.word 0x14 2.--15. 1. "RBSA,Rx buffer start address."
line.long 0x18 "RXF1C,Rx FIFO 1 Configuration"
bitfld.long 0x18 31. "F1OM,FIFO 1 operation mode." "0,1"
hexmask.long.byte 0x18 24.--30. 1. "F1WM,Rx FIFO 1 watermark 0 = Watermark interrupt disabled."
hexmask.long.byte 0x18 16.--22. 1. "F1S,Rx FIFO 1 size 0 = No Rx FIFO 1."
hexmask.long.word 0x18 2.--15. 1. "F1SA,Rx FIFO 1 start address."
rgroup.long 0xB4++0x3
line.long 0x0 "RXF1S,Rx FIFO 1 Status"
bitfld.long 0x0 25. "RF1L,Rx FIFO 1 message lost." "0,1"
bitfld.long 0x0 24. "F1F,Rx FIFO 1 full." "0,1"
hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 put index."
hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 get index."
hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 fill level."
group.long 0xB8++0x2F
line.long 0x0 "RXF1A,Rx FIFO 1 Acknowledge"
hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 acknowledge index."
line.long 0x4 "RXESC,Rx Buffer and FIFO Element Size Configuration"
bitfld.long 0x4 8.--10. "RBDS,." "0,1,2,3,4,5,6,7"
bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 data field size." "0,1,2,3,4,5,6,7"
bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 data field size." "0,1,2,3,4,5,6,7"
line.long 0x8 "TXBC,Tx Buffer Configuration"
bitfld.long 0x8 30. "TFQM,Tx FIFO/queue mode." "0,1"
hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/queue size 0 = No tx FIFO/Queue."
hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of dedicated transmit buffers 0 = No dedicated Tx buffers."
hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx buffers start address."
line.long 0xC "TXFQS,Tx FIFO/Queue Status"
bitfld.long 0xC 21. "TFQF,Tx FIFO/queue full." "0,1"
hexmask.long.byte 0xC 16.--20. 1. "TFQPI,Tx FIFO/queue put index."
hexmask.long.byte 0xC 8.--12. 1. "TFGI,Tx FIFO get index."
line.long 0x10 "TXESC,Tx Buffer Element Size Configuration"
bitfld.long 0x10 0.--2. "TBDS,Tx buffer data field size." "0,1,2,3,4,5,6,7"
line.long 0x14 "TXBRP,Tx Buffer Request Pending"
hexmask.long 0x14 0.--31. 1. "TRP,Transmission request pending."
line.long 0x18 "TXBAR,Tx Buffer Add Request"
hexmask.long 0x18 0.--31. 1. "AR,Add request."
line.long 0x1C "TXBCR,Tx Buffer Cancellation Request"
hexmask.long 0x1C 0.--31. 1. "CR,Cancellation request."
line.long 0x20 "TXBTO,Tx Buffer Transmission Occurred"
hexmask.long 0x20 0.--31. 1. "TO,Transmission occurred."
line.long 0x24 "TXBCF,Tx Buffer Cancellation Finished"
hexmask.long 0x24 0.--31. 1. "TO,Cancellation finished."
line.long 0x28 "TXBTIE,Tx Buffer Transmission Interrupt Enable"
hexmask.long 0x28 0.--31. 1. "TIE,Transmission interrupt enable."
line.long 0x2C "TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable"
hexmask.long 0x2C 0.--31. 1. "CFIE,Cancellation finished interrupt enable."
group.long 0xF0++0x3
line.long 0x0 "TXEFC,Tx Event FIFO Configuration"
hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO watermark 0 = Watermark interrupt disabled."
hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO size 0 = Tx event FIFO disabled."
hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO start address."
rgroup.long 0xF4++0x3
line.long 0x0 "TXEFS,Tx Event FIFO Status"
bitfld.long 0x0 25. "TEFL,Tx event FIFO element lost." "0,1"
bitfld.long 0x0 24. "EFF,Event FIFO full." "0,1"
hexmask.long.byte 0x0 16.--21. 1. "EFPI,Event FIFO put index."
hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO get index."
hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO fill level."
group.long 0xF8++0x3
line.long 0x0 "TXEFA,Tx Event FIFO Acknowledge"
hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO acknowledge index."
group.long 0x200++0x3
line.long 0x0 "MRBA,CAN Message RAM Base Address"
hexmask.long.word 0x0 16.--31. 1. "BA,Base address for the message RAM in the chip memory map."
group.long 0x400++0x3
line.long 0x0 "ETSCC,External Timestamp Counter Configuration"
bitfld.long 0x0 31. "ETCE,External timestamp counter enable." "0,1"
hexmask.long.word 0x0 0.--10. 1. "ETCP,External timestamp prescaler value."
group.long 0x600++0x3
line.long 0x0 "ETSCV,External Timestamp Counter Value"
hexmask.long.word 0x0 0.--15. 1. "ETSC,External timestamp counter."
tree.end
endif
sif (cpuis("LPC54616*"))
tree "CAN0"
base ad:0x4009D000
group.long 0xC++0x7
line.long 0x0 "DBTP,Data Bit Timing Prescaler Register"
bitfld.long 0x0 23. "TDC,Transmitter delay compensation." "0,1"
hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data bit rate prescaler."
hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point."
hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point."
hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data (re)synchronization jump width."
line.long 0x4 "TEST,Test Register"
bitfld.long 0x4 7. "RX,Monitors the actual value of the CAN_RXD." "0,1"
bitfld.long 0x4 5.--6. "TX,Control of transmit pin." "0,1,2,3"
bitfld.long 0x4 4. "LBCK,Loop back mode." "0,1"
group.long 0x18++0x13
line.long 0x0 "CCCR,CC Control Register"
bitfld.long 0x0 15. "NISO,Non ISO operation." "0,1"
bitfld.long 0x0 14. "TXP,Transmit pause." "0,1"
bitfld.long 0x0 13. "EFBI,Edge filtering during bus integration." "0,1"
bitfld.long 0x0 12. "PXHD,Protocol exception handling disable." "0,1"
bitfld.long 0x0 9. "BRSE,When CAN FD operation is disabled  this bit is not evaluated." "0,1"
bitfld.long 0x0 8. "FDOE,CAN FD operation enable." "0,1"
bitfld.long 0x0 7. "TEST,Test mode enable." "0,1"
bitfld.long 0x0 6. "DAR,Disable automatic retransmission." "0,1"
bitfld.long 0x0 5. "MON,Bus monitoring mode." "0,1"
bitfld.long 0x0 4. "CSR,Clock Stop Request." "0,1"
newline
bitfld.long 0x0 3. "CSA,Clock Stop Acknowledge." "0,1"
bitfld.long 0x0 2. "ASM,Restricted operational mode." "0,1"
bitfld.long 0x0 1. "CCE,Configuration change enable." "0,1"
bitfld.long 0x0 0. "INIT,Initialization." "0,1"
line.long 0x4 "NBTP,Nominal Bit Timing and Prescaler Register"
hexmask.long.byte 0x4 25.--31. 1. "NSJW,Nominal (re)synchronization jump width."
hexmask.long.word 0x4 16.--24. 1. "NBRP,Nominal bit rate prescaler."
hexmask.long.byte 0x4 8.--15. 1. "NTSEG1,Nominal time segment before sample point."
hexmask.long.byte 0x4 0.--6. 1. "NTSEG2,Nominal time segment after sample point."
line.long 0x8 "TSCC,Timestamp Counter Configuration"
hexmask.long.byte 0x8 16.--19. 1. "TCP,Timestamp counter prescaler Configures the timestamp and timeout counters time unit in multiple of CAN bit times."
bitfld.long 0x8 0.--1. "TSS,Timestamp select." "0,1,2,3"
line.long 0xC "TSCV,Timestamp Counter Value"
hexmask.long.word 0xC 0.--15. 1. "TSC,Timestamp counter."
line.long 0x10 "TOCC,Timeout Counter Configuration"
hexmask.long.word 0x10 16.--31. 1. "TOP,Timeout period."
bitfld.long 0x10 1.--2. "TOS,Timeout select." "0,1,2,3"
bitfld.long 0x10 0. "ETOC,Enable timeout counter." "0,1"
rgroup.long 0x2C++0x3
line.long 0x0 "TOCV,Timeout Counter Value"
hexmask.long.word 0x0 0.--15. 1. "TOC,Timeout counter."
rgroup.long 0x40++0x7
line.long 0x0 "ECR,Error Counter Register"
hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN error logging."
bitfld.long 0x0 15. "RP,Receive error passive." "0,1"
hexmask.long.byte 0x0 8.--14. 1. "REC,Receive error counter."
hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit error counter."
line.long 0x4 "PSR,Protocol Status Register"
hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter delay compensation value."
bitfld.long 0x4 14. "PXE,Protocol exception event." "0,1"
bitfld.long 0x4 13. "RFDF,Received a CAN FD message." "0,1"
bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD message." "0,1"
bitfld.long 0x4 11. "RESI,ESI flag of the last received CAN FD message." "0,1"
bitfld.long 0x4 8.--10. "DLEC,Data phase last error code." "0,1,2,3,4,5,6,7"
bitfld.long 0x4 7. "BO,Bus Off Status." "0,1"
bitfld.long 0x4 6. "EW,Warning status." "0,1"
bitfld.long 0x4 5. "EP,Error Passive." "0,1"
bitfld.long 0x4 3.--4. "ACT,Activity." "0,1,2,3"
newline
bitfld.long 0x4 0.--2. "LEC,Last error code." "0,1,2,3,4,5,6,7"
group.long 0x48++0x3
line.long 0x0 "TDCR,Transmitter Delay Compensator Register"
hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter delay compensation offset."
hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter delay compensation filter window length."
group.long 0x50++0xF
line.long 0x0 "IR,Interrupt Register"
bitfld.long 0x0 29. "ARA,Access to reserved address." "0,1"
bitfld.long 0x0 28. "PED,Protocol error in data phase." "0,1"
bitfld.long 0x0 27. "PEA,Protocol error in arbitration phase." "0,1"
bitfld.long 0x0 26. "WDI,Watchdog interrupt." "0,1"
bitfld.long 0x0 25. "BO,Bus_Off Status." "0,1"
bitfld.long 0x0 24. "EW,Warning status." "0,1"
bitfld.long 0x0 23. "EP,Error passive." "0,1"
bitfld.long 0x0 22. "ELO,Error logging overflow." "0,1"
bitfld.long 0x0 21. "BEU,Bit error uncorrected." "0,1"
bitfld.long 0x0 20. "BEC,Bit error corrected." "0,1"
newline
bitfld.long 0x0 19. "DRX,Message stored in dedicated Rx buffer." "0,1"
bitfld.long 0x0 18. "TOO,Timeout occurred." "0,1"
bitfld.long 0x0 17. "MRAF,Message RAM access failure." "0,1"
bitfld.long 0x0 16. "TSW,Timestamp wraparound." "0,1"
bitfld.long 0x0 15. "TEFL,Tx event FIFO element lost." "0,1"
bitfld.long 0x0 14. "TEFF,Tx event FIFO full." "0,1"
bitfld.long 0x0 13. "TEFW,Tx event FIFO watermark reached." "0,1"
bitfld.long 0x0 12. "TEFN,Tx event FIFO new entry." "0,1"
bitfld.long 0x0 11. "TFE,Tx FIFO empty." "0,1"
bitfld.long 0x0 10. "TCF,Transmission cancellation finished." "0,1"
newline
bitfld.long 0x0 9. "TC,Transmission completed." "0,1"
bitfld.long 0x0 8. "HPM,High priority message." "0,1"
bitfld.long 0x0 7. "RF1L,Rx FIFO 1 message lost." "0,1"
bitfld.long 0x0 6. "RF1F,Rx FIFO 1 full." "0,1"
bitfld.long 0x0 5. "RF1W,Rx FIFO 1 watermark reached." "0,1"
bitfld.long 0x0 4. "RF1N,Rx FIFO 1 new message." "0,1"
bitfld.long 0x0 3. "RF0L,Rx FIFO 0 message lost." "0,1"
bitfld.long 0x0 2. "RF0F,Rx FIFO 0 full." "0,1"
bitfld.long 0x0 1. "RF0W,Rx FIFO 0 watermark reached." "0,1"
bitfld.long 0x0 0. "RF0N,Rx FIFO 0 new message." "0,1"
line.long 0x4 "IE,Interrupt Enable"
bitfld.long 0x4 29. "ARAE,Access to reserved address interrupt enable." "0,1"
bitfld.long 0x4 28. "PEDE,Protocol error in data phase interrupt enable." "0,1"
bitfld.long 0x4 27. "PEAE,Protocol error in arbitration phase interrupt enable." "0,1"
bitfld.long 0x4 26. "WDIE,Watchdog interrupt enable." "0,1"
bitfld.long 0x4 25. "BOE,Bus_Off Status interrupt enable." "0,1"
bitfld.long 0x4 24. "EWE,Warning status interrupt enable." "0,1"
bitfld.long 0x4 23. "EPE,Error passive interrupt enable." "0,1"
bitfld.long 0x4 22. "ELOE,Error logging overflow interrupt enable." "0,1"
bitfld.long 0x4 21. "BEUE,Bit error uncorrected interrupt enable." "0,1"
bitfld.long 0x4 20. "BECE,Bit error corrected interrupt enable." "0,1"
newline
bitfld.long 0x4 19. "DRXE,Message stored in dedicated Rx buffer interrupt enable." "0,1"
bitfld.long 0x4 18. "TOOE,Timeout occurred interrupt enable." "0,1"
bitfld.long 0x4 17. "MRAFE,Message RAM access failure interrupt enable." "0,1"
bitfld.long 0x4 16. "TSWE,Timestamp wraparound interrupt enable." "0,1"
bitfld.long 0x4 15. "TEFLE,Tx event FIFO element lost interrupt enable." "0,1"
bitfld.long 0x4 14. "TEFFE,Tx event FIFO full interrupt enable." "0,1"
bitfld.long 0x4 13. "TEFWE,Tx event FIFO watermark reached interrupt enable." "0,1"
bitfld.long 0x4 12. "TEFNE,Tx event FIFO new entry interrupt enable." "0,1"
bitfld.long 0x4 11. "TFEE,Tx FIFO empty interrupt enable." "0,1"
bitfld.long 0x4 10. "TCFE,Transmission cancellation finished interrupt enable." "0,1"
newline
bitfld.long 0x4 9. "TCE,Transmission completed interrupt enable." "0,1"
bitfld.long 0x4 8. "HPME,High priority message interrupt enable." "0,1"
bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 message lost interrupt enable." "0,1"
bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 full interrupt enable." "0,1"
bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 watermark reached interrupt enable." "0,1"
bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 new message interrupt enable." "0,1"
bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 message lost interrupt enable." "0,1"
bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 full interrupt enable." "0,1"
bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 watermark reached interrupt enable." "0,1"
bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 new message interrupt enable." "0,1"
line.long 0x8 "ILS,Interrupt Line Select"
bitfld.long 0x8 29. "ARAL,Access to reserved address interrupt line." "0,1"
bitfld.long 0x8 28. "PEDL,Protocol error in data phase interrupt line." "0,1"
bitfld.long 0x8 27. "PEAL,Protocol error in arbitration phase interrupt line." "0,1"
bitfld.long 0x8 26. "WDIL,Watchdog interrupt line." "0,1"
bitfld.long 0x8 25. "BOL,Bus_Off Status interrupt line." "0,1"
bitfld.long 0x8 24. "EWL,Warning status interrupt line." "0,1"
bitfld.long 0x8 23. "EPL,Error passive interrupt line." "0,1"
bitfld.long 0x8 22. "ELOL,Error logging overflow interrupt line." "0,1"
bitfld.long 0x8 21. "BEUL,Bit error uncorrected interrupt line." "0,1"
bitfld.long 0x8 20. "BECL,Bit error corrected interrupt line." "0,1"
newline
bitfld.long 0x8 19. "DRXL,Message stored in dedicated Rx buffer interrupt line." "0,1"
bitfld.long 0x8 18. "TOOL,Timeout occurred interrupt line." "0,1"
bitfld.long 0x8 17. "MRAFL,Message RAM access failure interrupt line." "0,1"
bitfld.long 0x8 16. "TSWL,Timestamp wraparound interrupt line." "0,1"
bitfld.long 0x8 15. "TEFLL,Tx event FIFO element lost interrupt line." "0,1"
bitfld.long 0x8 14. "TEFFL,Tx event FIFO full interrupt line." "0,1"
bitfld.long 0x8 13. "TEFWL,Tx event FIFO watermark reached interrupt line." "0,1"
bitfld.long 0x8 12. "TEFNL,Tx event FIFO new entry interrupt line." "0,1"
bitfld.long 0x8 11. "TFEL,Tx FIFO empty interrupt line." "0,1"
bitfld.long 0x8 10. "TCFL,Transmission cancellation finished interrupt line." "0,1"
newline
bitfld.long 0x8 9. "TCL,Transmission completed interrupt line." "0,1"
bitfld.long 0x8 8. "HPML,High priority message interrupt line." "0,1"
bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 message lost interrupt line." "0,1"
bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 full interrupt line." "0,1"
bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 watermark reached interrupt line." "0,1"
bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 new message interrupt line." "0,1"
bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 message lost interrupt line." "0,1"
bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 full interrupt line." "0,1"
bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 watermark reached interrupt line." "0,1"
bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 new message interrupt line." "0,1"
line.long 0xC "ILE,Interrupt Line Enable"
bitfld.long 0xC 1. "EINT1,Enable interrupt line 1." "0,1"
bitfld.long 0xC 0. "EINT0,Enable interrupt line 0." "0,1"
group.long 0x80++0xB
line.long 0x0 "GFC,Global Filter Configuration"
bitfld.long 0x0 4.--5. "ANFS,Accept non-matching frames standard." "0,1,2,3"
bitfld.long 0x0 2.--3. "ANFE,Accept non-matching frames extended." "0,1,2,3"
bitfld.long 0x0 1. "RRFS,Reject remote frames standard." "0,1"
bitfld.long 0x0 0. "RRFE,Reject remote frames extended." "0,1"
line.long 0x4 "SIDFC,Standard ID Filter Configuration"
hexmask.long.byte 0x4 16.--23. 1. "LSS,List size standard 0 = No standard message ID filter."
hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter list standard start address."
line.long 0x8 "XIDFC,Extended ID Filter Configuration"
hexmask.long.byte 0x8 16.--23. 1. "LSE,List size extended 0 = No extended message ID filter."
hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter list extended start address."
group.long 0x90++0x3
line.long 0x0 "XIDAM,Extended ID AND Mask"
hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID mask."
rgroup.long 0x94++0x3
line.long 0x0 "HPMS,High Priority Message Status"
bitfld.long 0x0 15. "FLST,Filter list." "0,1"
hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter index."
bitfld.long 0x0 6.--7. "MSI,Message storage indicator." "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer index."
group.long 0x98++0x1B
line.long 0x0 "NDAT1,New Data 1"
hexmask.long 0x0 0.--31. 1. "ND,New Data."
line.long 0x4 "NDAT2,New Data 2"
hexmask.long 0x4 0.--31. 1. "ND,New Data."
line.long 0x8 "RXF0C,Rx FIFO 0 Configuration"
bitfld.long 0x8 31. "F0OM,FIFO 0 operation mode." "0,1"
hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 watermark 0 = Watermark interrupt disabled."
hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 size."
hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 start address."
line.long 0xC "RXF0S,Rx FIFO 0 Status"
bitfld.long 0xC 25. "RF0L,Rx FIFO 0 message lost." "0,1"
bitfld.long 0xC 24. "F0F,Rx FIFO 0 full." "0,1"
hexmask.long.byte 0xC 16.--21. 1. "F0PI,Rx FIFO 0 put index."
hexmask.long.byte 0xC 8.--13. 1. "F0GI,Rx FIFO 0 get index."
hexmask.long.byte 0xC 0.--6. 1. "F0FL,Rx FIFO 0 fill level."
line.long 0x10 "RXF0A,Rx FIFO 0 Acknowledge"
hexmask.long.byte 0x10 0.--5. 1. "F0AI,Rx FIFO 0 acknowledge index."
line.long 0x14 "RXBC,Rx Buffer Configuration"
hexmask.long.word 0x14 2.--15. 1. "RBSA,Rx buffer start address."
line.long 0x18 "RXF1C,Rx FIFO 1 Configuration"
bitfld.long 0x18 31. "F1OM,FIFO 1 operation mode." "0,1"
hexmask.long.byte 0x18 24.--30. 1. "F1WM,Rx FIFO 1 watermark 0 = Watermark interrupt disabled."
hexmask.long.byte 0x18 16.--22. 1. "F1S,Rx FIFO 1 size 0 = No Rx FIFO 1."
hexmask.long.word 0x18 2.--15. 1. "F1SA,Rx FIFO 1 start address."
rgroup.long 0xB4++0x3
line.long 0x0 "RXF1S,Rx FIFO 1 Status"
bitfld.long 0x0 25. "RF1L,Rx FIFO 1 message lost." "0,1"
bitfld.long 0x0 24. "F1F,Rx FIFO 1 full." "0,1"
hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 put index."
hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 get index."
hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 fill level."
group.long 0xB8++0x2F
line.long 0x0 "RXF1A,Rx FIFO 1 Acknowledge"
hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 acknowledge index."
line.long 0x4 "RXESC,Rx Buffer and FIFO Element Size Configuration"
bitfld.long 0x4 8.--10. "RBDS,." "0,1,2,3,4,5,6,7"
bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 data field size." "0,1,2,3,4,5,6,7"
bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 data field size." "0,1,2,3,4,5,6,7"
line.long 0x8 "TXBC,Tx Buffer Configuration"
bitfld.long 0x8 30. "TFQM,Tx FIFO/queue mode." "0,1"
hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/queue size 0 = No tx FIFO/Queue."
hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of dedicated transmit buffers 0 = No dedicated Tx buffers."
hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx buffers start address."
line.long 0xC "TXFQS,Tx FIFO/Queue Status"
bitfld.long 0xC 21. "TFQF,Tx FIFO/queue full." "0,1"
hexmask.long.byte 0xC 16.--20. 1. "TFQPI,Tx FIFO/queue put index."
hexmask.long.byte 0xC 8.--12. 1. "TFGI,Tx FIFO get index."
line.long 0x10 "TXESC,Tx Buffer Element Size Configuration"
bitfld.long 0x10 0.--2. "TBDS,Tx buffer data field size." "0,1,2,3,4,5,6,7"
line.long 0x14 "TXBRP,Tx Buffer Request Pending"
hexmask.long 0x14 0.--31. 1. "TRP,Transmission request pending."
line.long 0x18 "TXBAR,Tx Buffer Add Request"
hexmask.long 0x18 0.--31. 1. "AR,Add request."
line.long 0x1C "TXBCR,Tx Buffer Cancellation Request"
hexmask.long 0x1C 0.--31. 1. "CR,Cancellation request."
line.long 0x20 "TXBTO,Tx Buffer Transmission Occurred"
hexmask.long 0x20 0.--31. 1. "TO,Transmission occurred."
line.long 0x24 "TXBCF,Tx Buffer Cancellation Finished"
hexmask.long 0x24 0.--31. 1. "TO,Cancellation finished."
line.long 0x28 "TXBTIE,Tx Buffer Transmission Interrupt Enable"
hexmask.long 0x28 0.--31. 1. "TIE,Transmission interrupt enable."
line.long 0x2C "TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable"
hexmask.long 0x2C 0.--31. 1. "CFIE,Cancellation finished interrupt enable."
group.long 0xF0++0x3
line.long 0x0 "TXEFC,Tx Event FIFO Configuration"
hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO watermark 0 = Watermark interrupt disabled."
hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO size 0 = Tx event FIFO disabled."
hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO start address."
rgroup.long 0xF4++0x3
line.long 0x0 "TXEFS,Tx Event FIFO Status"
bitfld.long 0x0 25. "TEFL,Tx event FIFO element lost." "0,1"
bitfld.long 0x0 24. "EFF,Event FIFO full." "0,1"
hexmask.long.byte 0x0 16.--21. 1. "EFPI,Event FIFO put index."
hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO get index."
hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO fill level."
group.long 0xF8++0x3
line.long 0x0 "TXEFA,Tx Event FIFO Acknowledge"
hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO acknowledge index."
group.long 0x200++0x3
line.long 0x0 "MRBA,CAN Message RAM Base Address"
hexmask.long.word 0x0 16.--31. 1. "BA,Base address for the message RAM in the chip memory map."
group.long 0x400++0x3
line.long 0x0 "ETSCC,External Timestamp Counter Configuration"
bitfld.long 0x0 31. "ETCE,External timestamp counter enable." "0,1"
hexmask.long.word 0x0 0.--10. 1. "ETCP,External timestamp prescaler value."
group.long 0x600++0x3
line.long 0x0 "ETSCV,External Timestamp Counter Value"
hexmask.long.word 0x0 0.--15. 1. "ETSC,External timestamp counter."
tree.end
tree "CAN1"
base ad:0x4009E000
group.long 0xC++0x7
line.long 0x0 "DBTP,Data Bit Timing Prescaler Register"
bitfld.long 0x0 23. "TDC,Transmitter delay compensation." "0,1"
hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data bit rate prescaler."
hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point."
hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point."
hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data (re)synchronization jump width."
line.long 0x4 "TEST,Test Register"
bitfld.long 0x4 7. "RX,Monitors the actual value of the CAN_RXD." "0,1"
bitfld.long 0x4 5.--6. "TX,Control of transmit pin." "0,1,2,3"
bitfld.long 0x4 4. "LBCK,Loop back mode." "0,1"
group.long 0x18++0x13
line.long 0x0 "CCCR,CC Control Register"
bitfld.long 0x0 15. "NISO,Non ISO operation." "0,1"
bitfld.long 0x0 14. "TXP,Transmit pause." "0,1"
bitfld.long 0x0 13. "EFBI,Edge filtering during bus integration." "0,1"
bitfld.long 0x0 12. "PXHD,Protocol exception handling disable." "0,1"
bitfld.long 0x0 9. "BRSE,When CAN FD operation is disabled  this bit is not evaluated." "0,1"
bitfld.long 0x0 8. "FDOE,CAN FD operation enable." "0,1"
bitfld.long 0x0 7. "TEST,Test mode enable." "0,1"
bitfld.long 0x0 6. "DAR,Disable automatic retransmission." "0,1"
bitfld.long 0x0 5. "MON,Bus monitoring mode." "0,1"
bitfld.long 0x0 4. "CSR,Clock Stop Request." "0,1"
newline
bitfld.long 0x0 3. "CSA,Clock Stop Acknowledge." "0,1"
bitfld.long 0x0 2. "ASM,Restricted operational mode." "0,1"
bitfld.long 0x0 1. "CCE,Configuration change enable." "0,1"
bitfld.long 0x0 0. "INIT,Initialization." "0,1"
line.long 0x4 "NBTP,Nominal Bit Timing and Prescaler Register"
hexmask.long.byte 0x4 25.--31. 1. "NSJW,Nominal (re)synchronization jump width."
hexmask.long.word 0x4 16.--24. 1. "NBRP,Nominal bit rate prescaler."
hexmask.long.byte 0x4 8.--15. 1. "NTSEG1,Nominal time segment before sample point."
hexmask.long.byte 0x4 0.--6. 1. "NTSEG2,Nominal time segment after sample point."
line.long 0x8 "TSCC,Timestamp Counter Configuration"
hexmask.long.byte 0x8 16.--19. 1. "TCP,Timestamp counter prescaler Configures the timestamp and timeout counters time unit in multiple of CAN bit times."
bitfld.long 0x8 0.--1. "TSS,Timestamp select." "0,1,2,3"
line.long 0xC "TSCV,Timestamp Counter Value"
hexmask.long.word 0xC 0.--15. 1. "TSC,Timestamp counter."
line.long 0x10 "TOCC,Timeout Counter Configuration"
hexmask.long.word 0x10 16.--31. 1. "TOP,Timeout period."
bitfld.long 0x10 1.--2. "TOS,Timeout select." "0,1,2,3"
bitfld.long 0x10 0. "ETOC,Enable timeout counter." "0,1"
rgroup.long 0x2C++0x3
line.long 0x0 "TOCV,Timeout Counter Value"
hexmask.long.word 0x0 0.--15. 1. "TOC,Timeout counter."
rgroup.long 0x40++0x7
line.long 0x0 "ECR,Error Counter Register"
hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN error logging."
bitfld.long 0x0 15. "RP,Receive error passive." "0,1"
hexmask.long.byte 0x0 8.--14. 1. "REC,Receive error counter."
hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit error counter."
line.long 0x4 "PSR,Protocol Status Register"
hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter delay compensation value."
bitfld.long 0x4 14. "PXE,Protocol exception event." "0,1"
bitfld.long 0x4 13. "RFDF,Received a CAN FD message." "0,1"
bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD message." "0,1"
bitfld.long 0x4 11. "RESI,ESI flag of the last received CAN FD message." "0,1"
bitfld.long 0x4 8.--10. "DLEC,Data phase last error code." "0,1,2,3,4,5,6,7"
bitfld.long 0x4 7. "BO,Bus Off Status." "0,1"
bitfld.long 0x4 6. "EW,Warning status." "0,1"
bitfld.long 0x4 5. "EP,Error Passive." "0,1"
bitfld.long 0x4 3.--4. "ACT,Activity." "0,1,2,3"
newline
bitfld.long 0x4 0.--2. "LEC,Last error code." "0,1,2,3,4,5,6,7"
group.long 0x48++0x3
line.long 0x0 "TDCR,Transmitter Delay Compensator Register"
hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter delay compensation offset."
hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter delay compensation filter window length."
group.long 0x50++0xF
line.long 0x0 "IR,Interrupt Register"
bitfld.long 0x0 29. "ARA,Access to reserved address." "0,1"
bitfld.long 0x0 28. "PED,Protocol error in data phase." "0,1"
bitfld.long 0x0 27. "PEA,Protocol error in arbitration phase." "0,1"
bitfld.long 0x0 26. "WDI,Watchdog interrupt." "0,1"
bitfld.long 0x0 25. "BO,Bus_Off Status." "0,1"
bitfld.long 0x0 24. "EW,Warning status." "0,1"
bitfld.long 0x0 23. "EP,Error passive." "0,1"
bitfld.long 0x0 22. "ELO,Error logging overflow." "0,1"
bitfld.long 0x0 21. "BEU,Bit error uncorrected." "0,1"
bitfld.long 0x0 20. "BEC,Bit error corrected." "0,1"
newline
bitfld.long 0x0 19. "DRX,Message stored in dedicated Rx buffer." "0,1"
bitfld.long 0x0 18. "TOO,Timeout occurred." "0,1"
bitfld.long 0x0 17. "MRAF,Message RAM access failure." "0,1"
bitfld.long 0x0 16. "TSW,Timestamp wraparound." "0,1"
bitfld.long 0x0 15. "TEFL,Tx event FIFO element lost." "0,1"
bitfld.long 0x0 14. "TEFF,Tx event FIFO full." "0,1"
bitfld.long 0x0 13. "TEFW,Tx event FIFO watermark reached." "0,1"
bitfld.long 0x0 12. "TEFN,Tx event FIFO new entry." "0,1"
bitfld.long 0x0 11. "TFE,Tx FIFO empty." "0,1"
bitfld.long 0x0 10. "TCF,Transmission cancellation finished." "0,1"
newline
bitfld.long 0x0 9. "TC,Transmission completed." "0,1"
bitfld.long 0x0 8. "HPM,High priority message." "0,1"
bitfld.long 0x0 7. "RF1L,Rx FIFO 1 message lost." "0,1"
bitfld.long 0x0 6. "RF1F,Rx FIFO 1 full." "0,1"
bitfld.long 0x0 5. "RF1W,Rx FIFO 1 watermark reached." "0,1"
bitfld.long 0x0 4. "RF1N,Rx FIFO 1 new message." "0,1"
bitfld.long 0x0 3. "RF0L,Rx FIFO 0 message lost." "0,1"
bitfld.long 0x0 2. "RF0F,Rx FIFO 0 full." "0,1"
bitfld.long 0x0 1. "RF0W,Rx FIFO 0 watermark reached." "0,1"
bitfld.long 0x0 0. "RF0N,Rx FIFO 0 new message." "0,1"
line.long 0x4 "IE,Interrupt Enable"
bitfld.long 0x4 29. "ARAE,Access to reserved address interrupt enable." "0,1"
bitfld.long 0x4 28. "PEDE,Protocol error in data phase interrupt enable." "0,1"
bitfld.long 0x4 27. "PEAE,Protocol error in arbitration phase interrupt enable." "0,1"
bitfld.long 0x4 26. "WDIE,Watchdog interrupt enable." "0,1"
bitfld.long 0x4 25. "BOE,Bus_Off Status interrupt enable." "0,1"
bitfld.long 0x4 24. "EWE,Warning status interrupt enable." "0,1"
bitfld.long 0x4 23. "EPE,Error passive interrupt enable." "0,1"
bitfld.long 0x4 22. "ELOE,Error logging overflow interrupt enable." "0,1"
bitfld.long 0x4 21. "BEUE,Bit error uncorrected interrupt enable." "0,1"
bitfld.long 0x4 20. "BECE,Bit error corrected interrupt enable." "0,1"
newline
bitfld.long 0x4 19. "DRXE,Message stored in dedicated Rx buffer interrupt enable." "0,1"
bitfld.long 0x4 18. "TOOE,Timeout occurred interrupt enable." "0,1"
bitfld.long 0x4 17. "MRAFE,Message RAM access failure interrupt enable." "0,1"
bitfld.long 0x4 16. "TSWE,Timestamp wraparound interrupt enable." "0,1"
bitfld.long 0x4 15. "TEFLE,Tx event FIFO element lost interrupt enable." "0,1"
bitfld.long 0x4 14. "TEFFE,Tx event FIFO full interrupt enable." "0,1"
bitfld.long 0x4 13. "TEFWE,Tx event FIFO watermark reached interrupt enable." "0,1"
bitfld.long 0x4 12. "TEFNE,Tx event FIFO new entry interrupt enable." "0,1"
bitfld.long 0x4 11. "TFEE,Tx FIFO empty interrupt enable." "0,1"
bitfld.long 0x4 10. "TCFE,Transmission cancellation finished interrupt enable." "0,1"
newline
bitfld.long 0x4 9. "TCE,Transmission completed interrupt enable." "0,1"
bitfld.long 0x4 8. "HPME,High priority message interrupt enable." "0,1"
bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 message lost interrupt enable." "0,1"
bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 full interrupt enable." "0,1"
bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 watermark reached interrupt enable." "0,1"
bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 new message interrupt enable." "0,1"
bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 message lost interrupt enable." "0,1"
bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 full interrupt enable." "0,1"
bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 watermark reached interrupt enable." "0,1"
bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 new message interrupt enable." "0,1"
line.long 0x8 "ILS,Interrupt Line Select"
bitfld.long 0x8 29. "ARAL,Access to reserved address interrupt line." "0,1"
bitfld.long 0x8 28. "PEDL,Protocol error in data phase interrupt line." "0,1"
bitfld.long 0x8 27. "PEAL,Protocol error in arbitration phase interrupt line." "0,1"
bitfld.long 0x8 26. "WDIL,Watchdog interrupt line." "0,1"
bitfld.long 0x8 25. "BOL,Bus_Off Status interrupt line." "0,1"
bitfld.long 0x8 24. "EWL,Warning status interrupt line." "0,1"
bitfld.long 0x8 23. "EPL,Error passive interrupt line." "0,1"
bitfld.long 0x8 22. "ELOL,Error logging overflow interrupt line." "0,1"
bitfld.long 0x8 21. "BEUL,Bit error uncorrected interrupt line." "0,1"
bitfld.long 0x8 20. "BECL,Bit error corrected interrupt line." "0,1"
newline
bitfld.long 0x8 19. "DRXL,Message stored in dedicated Rx buffer interrupt line." "0,1"
bitfld.long 0x8 18. "TOOL,Timeout occurred interrupt line." "0,1"
bitfld.long 0x8 17. "MRAFL,Message RAM access failure interrupt line." "0,1"
bitfld.long 0x8 16. "TSWL,Timestamp wraparound interrupt line." "0,1"
bitfld.long 0x8 15. "TEFLL,Tx event FIFO element lost interrupt line." "0,1"
bitfld.long 0x8 14. "TEFFL,Tx event FIFO full interrupt line." "0,1"
bitfld.long 0x8 13. "TEFWL,Tx event FIFO watermark reached interrupt line." "0,1"
bitfld.long 0x8 12. "TEFNL,Tx event FIFO new entry interrupt line." "0,1"
bitfld.long 0x8 11. "TFEL,Tx FIFO empty interrupt line." "0,1"
bitfld.long 0x8 10. "TCFL,Transmission cancellation finished interrupt line." "0,1"
newline
bitfld.long 0x8 9. "TCL,Transmission completed interrupt line." "0,1"
bitfld.long 0x8 8. "HPML,High priority message interrupt line." "0,1"
bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 message lost interrupt line." "0,1"
bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 full interrupt line." "0,1"
bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 watermark reached interrupt line." "0,1"
bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 new message interrupt line." "0,1"
bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 message lost interrupt line." "0,1"
bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 full interrupt line." "0,1"
bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 watermark reached interrupt line." "0,1"
bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 new message interrupt line." "0,1"
line.long 0xC "ILE,Interrupt Line Enable"
bitfld.long 0xC 1. "EINT1,Enable interrupt line 1." "0,1"
bitfld.long 0xC 0. "EINT0,Enable interrupt line 0." "0,1"
group.long 0x80++0xB
line.long 0x0 "GFC,Global Filter Configuration"
bitfld.long 0x0 4.--5. "ANFS,Accept non-matching frames standard." "0,1,2,3"
bitfld.long 0x0 2.--3. "ANFE,Accept non-matching frames extended." "0,1,2,3"
bitfld.long 0x0 1. "RRFS,Reject remote frames standard." "0,1"
bitfld.long 0x0 0. "RRFE,Reject remote frames extended." "0,1"
line.long 0x4 "SIDFC,Standard ID Filter Configuration"
hexmask.long.byte 0x4 16.--23. 1. "LSS,List size standard 0 = No standard message ID filter."
hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter list standard start address."
line.long 0x8 "XIDFC,Extended ID Filter Configuration"
hexmask.long.byte 0x8 16.--23. 1. "LSE,List size extended 0 = No extended message ID filter."
hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter list extended start address."
group.long 0x90++0x3
line.long 0x0 "XIDAM,Extended ID AND Mask"
hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID mask."
rgroup.long 0x94++0x3
line.long 0x0 "HPMS,High Priority Message Status"
bitfld.long 0x0 15. "FLST,Filter list." "0,1"
hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter index."
bitfld.long 0x0 6.--7. "MSI,Message storage indicator." "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer index."
group.long 0x98++0x1B
line.long 0x0 "NDAT1,New Data 1"
hexmask.long 0x0 0.--31. 1. "ND,New Data."
line.long 0x4 "NDAT2,New Data 2"
hexmask.long 0x4 0.--31. 1. "ND,New Data."
line.long 0x8 "RXF0C,Rx FIFO 0 Configuration"
bitfld.long 0x8 31. "F0OM,FIFO 0 operation mode." "0,1"
hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 watermark 0 = Watermark interrupt disabled."
hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 size."
hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 start address."
line.long 0xC "RXF0S,Rx FIFO 0 Status"
bitfld.long 0xC 25. "RF0L,Rx FIFO 0 message lost." "0,1"
bitfld.long 0xC 24. "F0F,Rx FIFO 0 full." "0,1"
hexmask.long.byte 0xC 16.--21. 1. "F0PI,Rx FIFO 0 put index."
hexmask.long.byte 0xC 8.--13. 1. "F0GI,Rx FIFO 0 get index."
hexmask.long.byte 0xC 0.--6. 1. "F0FL,Rx FIFO 0 fill level."
line.long 0x10 "RXF0A,Rx FIFO 0 Acknowledge"
hexmask.long.byte 0x10 0.--5. 1. "F0AI,Rx FIFO 0 acknowledge index."
line.long 0x14 "RXBC,Rx Buffer Configuration"
hexmask.long.word 0x14 2.--15. 1. "RBSA,Rx buffer start address."
line.long 0x18 "RXF1C,Rx FIFO 1 Configuration"
bitfld.long 0x18 31. "F1OM,FIFO 1 operation mode." "0,1"
hexmask.long.byte 0x18 24.--30. 1. "F1WM,Rx FIFO 1 watermark 0 = Watermark interrupt disabled."
hexmask.long.byte 0x18 16.--22. 1. "F1S,Rx FIFO 1 size 0 = No Rx FIFO 1."
hexmask.long.word 0x18 2.--15. 1. "F1SA,Rx FIFO 1 start address."
rgroup.long 0xB4++0x3
line.long 0x0 "RXF1S,Rx FIFO 1 Status"
bitfld.long 0x0 25. "RF1L,Rx FIFO 1 message lost." "0,1"
bitfld.long 0x0 24. "F1F,Rx FIFO 1 full." "0,1"
hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 put index."
hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 get index."
hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 fill level."
group.long 0xB8++0x2F
line.long 0x0 "RXF1A,Rx FIFO 1 Acknowledge"
hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 acknowledge index."
line.long 0x4 "RXESC,Rx Buffer and FIFO Element Size Configuration"
bitfld.long 0x4 8.--10. "RBDS,." "0,1,2,3,4,5,6,7"
bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 data field size." "0,1,2,3,4,5,6,7"
bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 data field size." "0,1,2,3,4,5,6,7"
line.long 0x8 "TXBC,Tx Buffer Configuration"
bitfld.long 0x8 30. "TFQM,Tx FIFO/queue mode." "0,1"
hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/queue size 0 = No tx FIFO/Queue."
hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of dedicated transmit buffers 0 = No dedicated Tx buffers."
hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx buffers start address."
line.long 0xC "TXFQS,Tx FIFO/Queue Status"
bitfld.long 0xC 21. "TFQF,Tx FIFO/queue full." "0,1"
hexmask.long.byte 0xC 16.--20. 1. "TFQPI,Tx FIFO/queue put index."
hexmask.long.byte 0xC 8.--12. 1. "TFGI,Tx FIFO get index."
line.long 0x10 "TXESC,Tx Buffer Element Size Configuration"
bitfld.long 0x10 0.--2. "TBDS,Tx buffer data field size." "0,1,2,3,4,5,6,7"
line.long 0x14 "TXBRP,Tx Buffer Request Pending"
hexmask.long 0x14 0.--31. 1. "TRP,Transmission request pending."
line.long 0x18 "TXBAR,Tx Buffer Add Request"
hexmask.long 0x18 0.--31. 1. "AR,Add request."
line.long 0x1C "TXBCR,Tx Buffer Cancellation Request"
hexmask.long 0x1C 0.--31. 1. "CR,Cancellation request."
line.long 0x20 "TXBTO,Tx Buffer Transmission Occurred"
hexmask.long 0x20 0.--31. 1. "TO,Transmission occurred."
line.long 0x24 "TXBCF,Tx Buffer Cancellation Finished"
hexmask.long 0x24 0.--31. 1. "TO,Cancellation finished."
line.long 0x28 "TXBTIE,Tx Buffer Transmission Interrupt Enable"
hexmask.long 0x28 0.--31. 1. "TIE,Transmission interrupt enable."
line.long 0x2C "TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable"
hexmask.long 0x2C 0.--31. 1. "CFIE,Cancellation finished interrupt enable."
group.long 0xF0++0x3
line.long 0x0 "TXEFC,Tx Event FIFO Configuration"
hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO watermark 0 = Watermark interrupt disabled."
hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO size 0 = Tx event FIFO disabled."
hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO start address."
rgroup.long 0xF4++0x3
line.long 0x0 "TXEFS,Tx Event FIFO Status"
bitfld.long 0x0 25. "TEFL,Tx event FIFO element lost." "0,1"
bitfld.long 0x0 24. "EFF,Event FIFO full." "0,1"
hexmask.long.byte 0x0 16.--21. 1. "EFPI,Event FIFO put index."
hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO get index."
hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO fill level."
group.long 0xF8++0x3
line.long 0x0 "TXEFA,Tx Event FIFO Acknowledge"
hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO acknowledge index."
group.long 0x200++0x3
line.long 0x0 "MRBA,CAN Message RAM Base Address"
hexmask.long.word 0x0 16.--31. 1. "BA,Base address for the message RAM in the chip memory map."
group.long 0x400++0x3
line.long 0x0 "ETSCC,External Timestamp Counter Configuration"
bitfld.long 0x0 31. "ETCE,External timestamp counter enable." "0,1"
hexmask.long.word 0x0 0.--10. 1. "ETCP,External timestamp prescaler value."
group.long 0x600++0x3
line.long 0x0 "ETSCV,External Timestamp Counter Value"
hexmask.long.word 0x0 0.--15. 1. "ETSC,External timestamp counter."
tree.end
endif
sif (cpuis("LPC54618*"))
tree "CAN0"
base ad:0x4009D000
group.long 0xC++0x7
line.long 0x0 "DBTP,Data Bit Timing Prescaler Register"
bitfld.long 0x0 23. "TDC,Transmitter delay compensation." "0,1"
hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data bit rate prescaler."
hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point."
hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point."
hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data (re)synchronization jump width."
line.long 0x4 "TEST,Test Register"
bitfld.long 0x4 7. "RX,Monitors the actual value of the CAN_RXD." "0,1"
bitfld.long 0x4 5.--6. "TX,Control of transmit pin." "0,1,2,3"
bitfld.long 0x4 4. "LBCK,Loop back mode." "0,1"
group.long 0x18++0x13
line.long 0x0 "CCCR,CC Control Register"
bitfld.long 0x0 15. "NISO,Non ISO operation." "0,1"
bitfld.long 0x0 14. "TXP,Transmit pause." "0,1"
bitfld.long 0x0 13. "EFBI,Edge filtering during bus integration." "0,1"
bitfld.long 0x0 12. "PXHD,Protocol exception handling disable." "0,1"
bitfld.long 0x0 9. "BRSE,When CAN FD operation is disabled  this bit is not evaluated." "0,1"
bitfld.long 0x0 8. "FDOE,CAN FD operation enable." "0,1"
bitfld.long 0x0 7. "TEST,Test mode enable." "0,1"
bitfld.long 0x0 6. "DAR,Disable automatic retransmission." "0,1"
bitfld.long 0x0 5. "MON,Bus monitoring mode." "0,1"
bitfld.long 0x0 4. "CSR,Clock Stop Request." "0,1"
newline
bitfld.long 0x0 3. "CSA,Clock Stop Acknowledge." "0,1"
bitfld.long 0x0 2. "ASM,Restricted operational mode." "0,1"
bitfld.long 0x0 1. "CCE,Configuration change enable." "0,1"
bitfld.long 0x0 0. "INIT,Initialization." "0,1"
line.long 0x4 "NBTP,Nominal Bit Timing and Prescaler Register"
hexmask.long.byte 0x4 25.--31. 1. "NSJW,Nominal (re)synchronization jump width."
hexmask.long.word 0x4 16.--24. 1. "NBRP,Nominal bit rate prescaler."
hexmask.long.byte 0x4 8.--15. 1. "NTSEG1,Nominal time segment before sample point."
hexmask.long.byte 0x4 0.--6. 1. "NTSEG2,Nominal time segment after sample point."
line.long 0x8 "TSCC,Timestamp Counter Configuration"
hexmask.long.byte 0x8 16.--19. 1. "TCP,Timestamp counter prescaler Configures the timestamp and timeout counters time unit in multiple of CAN bit times."
bitfld.long 0x8 0.--1. "TSS,Timestamp select." "0,1,2,3"
line.long 0xC "TSCV,Timestamp Counter Value"
hexmask.long.word 0xC 0.--15. 1. "TSC,Timestamp counter."
line.long 0x10 "TOCC,Timeout Counter Configuration"
hexmask.long.word 0x10 16.--31. 1. "TOP,Timeout period."
bitfld.long 0x10 1.--2. "TOS,Timeout select." "0,1,2,3"
bitfld.long 0x10 0. "ETOC,Enable timeout counter." "0,1"
rgroup.long 0x2C++0x3
line.long 0x0 "TOCV,Timeout Counter Value"
hexmask.long.word 0x0 0.--15. 1. "TOC,Timeout counter."
rgroup.long 0x40++0x7
line.long 0x0 "ECR,Error Counter Register"
hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN error logging."
bitfld.long 0x0 15. "RP,Receive error passive." "0,1"
hexmask.long.byte 0x0 8.--14. 1. "REC,Receive error counter."
hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit error counter."
line.long 0x4 "PSR,Protocol Status Register"
hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter delay compensation value."
bitfld.long 0x4 14. "PXE,Protocol exception event." "0,1"
bitfld.long 0x4 13. "RFDF,Received a CAN FD message." "0,1"
bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD message." "0,1"
bitfld.long 0x4 11. "RESI,ESI flag of the last received CAN FD message." "0,1"
bitfld.long 0x4 8.--10. "DLEC,Data phase last error code." "0,1,2,3,4,5,6,7"
bitfld.long 0x4 7. "BO,Bus Off Status." "0,1"
bitfld.long 0x4 6. "EW,Warning status." "0,1"
bitfld.long 0x4 5. "EP,Error Passive." "0,1"
bitfld.long 0x4 3.--4. "ACT,Activity." "0,1,2,3"
newline
bitfld.long 0x4 0.--2. "LEC,Last error code." "0,1,2,3,4,5,6,7"
group.long 0x48++0x3
line.long 0x0 "TDCR,Transmitter Delay Compensator Register"
hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter delay compensation offset."
hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter delay compensation filter window length."
group.long 0x50++0xF
line.long 0x0 "IR,Interrupt Register"
bitfld.long 0x0 29. "ARA,Access to reserved address." "0,1"
bitfld.long 0x0 28. "PED,Protocol error in data phase." "0,1"
bitfld.long 0x0 27. "PEA,Protocol error in arbitration phase." "0,1"
bitfld.long 0x0 26. "WDI,Watchdog interrupt." "0,1"
bitfld.long 0x0 25. "BO,Bus_Off Status." "0,1"
bitfld.long 0x0 24. "EW,Warning status." "0,1"
bitfld.long 0x0 23. "EP,Error passive." "0,1"
bitfld.long 0x0 22. "ELO,Error logging overflow." "0,1"
bitfld.long 0x0 21. "BEU,Bit error uncorrected." "0,1"
bitfld.long 0x0 20. "BEC,Bit error corrected." "0,1"
newline
bitfld.long 0x0 19. "DRX,Message stored in dedicated Rx buffer." "0,1"
bitfld.long 0x0 18. "TOO,Timeout occurred." "0,1"
bitfld.long 0x0 17. "MRAF,Message RAM access failure." "0,1"
bitfld.long 0x0 16. "TSW,Timestamp wraparound." "0,1"
bitfld.long 0x0 15. "TEFL,Tx event FIFO element lost." "0,1"
bitfld.long 0x0 14. "TEFF,Tx event FIFO full." "0,1"
bitfld.long 0x0 13. "TEFW,Tx event FIFO watermark reached." "0,1"
bitfld.long 0x0 12. "TEFN,Tx event FIFO new entry." "0,1"
bitfld.long 0x0 11. "TFE,Tx FIFO empty." "0,1"
bitfld.long 0x0 10. "TCF,Transmission cancellation finished." "0,1"
newline
bitfld.long 0x0 9. "TC,Transmission completed." "0,1"
bitfld.long 0x0 8. "HPM,High priority message." "0,1"
bitfld.long 0x0 7. "RF1L,Rx FIFO 1 message lost." "0,1"
bitfld.long 0x0 6. "RF1F,Rx FIFO 1 full." "0,1"
bitfld.long 0x0 5. "RF1W,Rx FIFO 1 watermark reached." "0,1"
bitfld.long 0x0 4. "RF1N,Rx FIFO 1 new message." "0,1"
bitfld.long 0x0 3. "RF0L,Rx FIFO 0 message lost." "0,1"
bitfld.long 0x0 2. "RF0F,Rx FIFO 0 full." "0,1"
bitfld.long 0x0 1. "RF0W,Rx FIFO 0 watermark reached." "0,1"
bitfld.long 0x0 0. "RF0N,Rx FIFO 0 new message." "0,1"
line.long 0x4 "IE,Interrupt Enable"
bitfld.long 0x4 29. "ARAE,Access to reserved address interrupt enable." "0,1"
bitfld.long 0x4 28. "PEDE,Protocol error in data phase interrupt enable." "0,1"
bitfld.long 0x4 27. "PEAE,Protocol error in arbitration phase interrupt enable." "0,1"
bitfld.long 0x4 26. "WDIE,Watchdog interrupt enable." "0,1"
bitfld.long 0x4 25. "BOE,Bus_Off Status interrupt enable." "0,1"
bitfld.long 0x4 24. "EWE,Warning status interrupt enable." "0,1"
bitfld.long 0x4 23. "EPE,Error passive interrupt enable." "0,1"
bitfld.long 0x4 22. "ELOE,Error logging overflow interrupt enable." "0,1"
bitfld.long 0x4 21. "BEUE,Bit error uncorrected interrupt enable." "0,1"
bitfld.long 0x4 20. "BECE,Bit error corrected interrupt enable." "0,1"
newline
bitfld.long 0x4 19. "DRXE,Message stored in dedicated Rx buffer interrupt enable." "0,1"
bitfld.long 0x4 18. "TOOE,Timeout occurred interrupt enable." "0,1"
bitfld.long 0x4 17. "MRAFE,Message RAM access failure interrupt enable." "0,1"
bitfld.long 0x4 16. "TSWE,Timestamp wraparound interrupt enable." "0,1"
bitfld.long 0x4 15. "TEFLE,Tx event FIFO element lost interrupt enable." "0,1"
bitfld.long 0x4 14. "TEFFE,Tx event FIFO full interrupt enable." "0,1"
bitfld.long 0x4 13. "TEFWE,Tx event FIFO watermark reached interrupt enable." "0,1"
bitfld.long 0x4 12. "TEFNE,Tx event FIFO new entry interrupt enable." "0,1"
bitfld.long 0x4 11. "TFEE,Tx FIFO empty interrupt enable." "0,1"
bitfld.long 0x4 10. "TCFE,Transmission cancellation finished interrupt enable." "0,1"
newline
bitfld.long 0x4 9. "TCE,Transmission completed interrupt enable." "0,1"
bitfld.long 0x4 8. "HPME,High priority message interrupt enable." "0,1"
bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 message lost interrupt enable." "0,1"
bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 full interrupt enable." "0,1"
bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 watermark reached interrupt enable." "0,1"
bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 new message interrupt enable." "0,1"
bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 message lost interrupt enable." "0,1"
bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 full interrupt enable." "0,1"
bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 watermark reached interrupt enable." "0,1"
bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 new message interrupt enable." "0,1"
line.long 0x8 "ILS,Interrupt Line Select"
bitfld.long 0x8 29. "ARAL,Access to reserved address interrupt line." "0,1"
bitfld.long 0x8 28. "PEDL,Protocol error in data phase interrupt line." "0,1"
bitfld.long 0x8 27. "PEAL,Protocol error in arbitration phase interrupt line." "0,1"
bitfld.long 0x8 26. "WDIL,Watchdog interrupt line." "0,1"
bitfld.long 0x8 25. "BOL,Bus_Off Status interrupt line." "0,1"
bitfld.long 0x8 24. "EWL,Warning status interrupt line." "0,1"
bitfld.long 0x8 23. "EPL,Error passive interrupt line." "0,1"
bitfld.long 0x8 22. "ELOL,Error logging overflow interrupt line." "0,1"
bitfld.long 0x8 21. "BEUL,Bit error uncorrected interrupt line." "0,1"
bitfld.long 0x8 20. "BECL,Bit error corrected interrupt line." "0,1"
newline
bitfld.long 0x8 19. "DRXL,Message stored in dedicated Rx buffer interrupt line." "0,1"
bitfld.long 0x8 18. "TOOL,Timeout occurred interrupt line." "0,1"
bitfld.long 0x8 17. "MRAFL,Message RAM access failure interrupt line." "0,1"
bitfld.long 0x8 16. "TSWL,Timestamp wraparound interrupt line." "0,1"
bitfld.long 0x8 15. "TEFLL,Tx event FIFO element lost interrupt line." "0,1"
bitfld.long 0x8 14. "TEFFL,Tx event FIFO full interrupt line." "0,1"
bitfld.long 0x8 13. "TEFWL,Tx event FIFO watermark reached interrupt line." "0,1"
bitfld.long 0x8 12. "TEFNL,Tx event FIFO new entry interrupt line." "0,1"
bitfld.long 0x8 11. "TFEL,Tx FIFO empty interrupt line." "0,1"
bitfld.long 0x8 10. "TCFL,Transmission cancellation finished interrupt line." "0,1"
newline
bitfld.long 0x8 9. "TCL,Transmission completed interrupt line." "0,1"
bitfld.long 0x8 8. "HPML,High priority message interrupt line." "0,1"
bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 message lost interrupt line." "0,1"
bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 full interrupt line." "0,1"
bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 watermark reached interrupt line." "0,1"
bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 new message interrupt line." "0,1"
bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 message lost interrupt line." "0,1"
bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 full interrupt line." "0,1"
bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 watermark reached interrupt line." "0,1"
bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 new message interrupt line." "0,1"
line.long 0xC "ILE,Interrupt Line Enable"
bitfld.long 0xC 1. "EINT1,Enable interrupt line 1." "0,1"
bitfld.long 0xC 0. "EINT0,Enable interrupt line 0." "0,1"
group.long 0x80++0xB
line.long 0x0 "GFC,Global Filter Configuration"
bitfld.long 0x0 4.--5. "ANFS,Accept non-matching frames standard." "0,1,2,3"
bitfld.long 0x0 2.--3. "ANFE,Accept non-matching frames extended." "0,1,2,3"
bitfld.long 0x0 1. "RRFS,Reject remote frames standard." "0,1"
bitfld.long 0x0 0. "RRFE,Reject remote frames extended." "0,1"
line.long 0x4 "SIDFC,Standard ID Filter Configuration"
hexmask.long.byte 0x4 16.--23. 1. "LSS,List size standard 0 = No standard message ID filter."
hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter list standard start address."
line.long 0x8 "XIDFC,Extended ID Filter Configuration"
hexmask.long.byte 0x8 16.--23. 1. "LSE,List size extended 0 = No extended message ID filter."
hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter list extended start address."
group.long 0x90++0x3
line.long 0x0 "XIDAM,Extended ID AND Mask"
hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID mask."
rgroup.long 0x94++0x3
line.long 0x0 "HPMS,High Priority Message Status"
bitfld.long 0x0 15. "FLST,Filter list." "0,1"
hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter index."
bitfld.long 0x0 6.--7. "MSI,Message storage indicator." "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer index."
group.long 0x98++0x1B
line.long 0x0 "NDAT1,New Data 1"
hexmask.long 0x0 0.--31. 1. "ND,New Data."
line.long 0x4 "NDAT2,New Data 2"
hexmask.long 0x4 0.--31. 1. "ND,New Data."
line.long 0x8 "RXF0C,Rx FIFO 0 Configuration"
bitfld.long 0x8 31. "F0OM,FIFO 0 operation mode." "0,1"
hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 watermark 0 = Watermark interrupt disabled."
hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 size."
hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 start address."
line.long 0xC "RXF0S,Rx FIFO 0 Status"
bitfld.long 0xC 25. "RF0L,Rx FIFO 0 message lost." "0,1"
bitfld.long 0xC 24. "F0F,Rx FIFO 0 full." "0,1"
hexmask.long.byte 0xC 16.--21. 1. "F0PI,Rx FIFO 0 put index."
hexmask.long.byte 0xC 8.--13. 1. "F0GI,Rx FIFO 0 get index."
hexmask.long.byte 0xC 0.--6. 1. "F0FL,Rx FIFO 0 fill level."
line.long 0x10 "RXF0A,Rx FIFO 0 Acknowledge"
hexmask.long.byte 0x10 0.--5. 1. "F0AI,Rx FIFO 0 acknowledge index."
line.long 0x14 "RXBC,Rx Buffer Configuration"
hexmask.long.word 0x14 2.--15. 1. "RBSA,Rx buffer start address."
line.long 0x18 "RXF1C,Rx FIFO 1 Configuration"
bitfld.long 0x18 31. "F1OM,FIFO 1 operation mode." "0,1"
hexmask.long.byte 0x18 24.--30. 1. "F1WM,Rx FIFO 1 watermark 0 = Watermark interrupt disabled."
hexmask.long.byte 0x18 16.--22. 1. "F1S,Rx FIFO 1 size 0 = No Rx FIFO 1."
hexmask.long.word 0x18 2.--15. 1. "F1SA,Rx FIFO 1 start address."
rgroup.long 0xB4++0x3
line.long 0x0 "RXF1S,Rx FIFO 1 Status"
bitfld.long 0x0 25. "RF1L,Rx FIFO 1 message lost." "0,1"
bitfld.long 0x0 24. "F1F,Rx FIFO 1 full." "0,1"
hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 put index."
hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 get index."
hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 fill level."
group.long 0xB8++0x2F
line.long 0x0 "RXF1A,Rx FIFO 1 Acknowledge"
hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 acknowledge index."
line.long 0x4 "RXESC,Rx Buffer and FIFO Element Size Configuration"
bitfld.long 0x4 8.--10. "RBDS,." "0,1,2,3,4,5,6,7"
bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 data field size." "0,1,2,3,4,5,6,7"
bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 data field size." "0,1,2,3,4,5,6,7"
line.long 0x8 "TXBC,Tx Buffer Configuration"
bitfld.long 0x8 30. "TFQM,Tx FIFO/queue mode." "0,1"
hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/queue size 0 = No tx FIFO/Queue."
hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of dedicated transmit buffers 0 = No dedicated Tx buffers."
hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx buffers start address."
line.long 0xC "TXFQS,Tx FIFO/Queue Status"
bitfld.long 0xC 21. "TFQF,Tx FIFO/queue full." "0,1"
hexmask.long.byte 0xC 16.--20. 1. "TFQPI,Tx FIFO/queue put index."
hexmask.long.byte 0xC 8.--12. 1. "TFGI,Tx FIFO get index."
line.long 0x10 "TXESC,Tx Buffer Element Size Configuration"
bitfld.long 0x10 0.--2. "TBDS,Tx buffer data field size." "0,1,2,3,4,5,6,7"
line.long 0x14 "TXBRP,Tx Buffer Request Pending"
hexmask.long 0x14 0.--31. 1. "TRP,Transmission request pending."
line.long 0x18 "TXBAR,Tx Buffer Add Request"
hexmask.long 0x18 0.--31. 1. "AR,Add request."
line.long 0x1C "TXBCR,Tx Buffer Cancellation Request"
hexmask.long 0x1C 0.--31. 1. "CR,Cancellation request."
line.long 0x20 "TXBTO,Tx Buffer Transmission Occurred"
hexmask.long 0x20 0.--31. 1. "TO,Transmission occurred."
line.long 0x24 "TXBCF,Tx Buffer Cancellation Finished"
hexmask.long 0x24 0.--31. 1. "TO,Cancellation finished."
line.long 0x28 "TXBTIE,Tx Buffer Transmission Interrupt Enable"
hexmask.long 0x28 0.--31. 1. "TIE,Transmission interrupt enable."
line.long 0x2C "TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable"
hexmask.long 0x2C 0.--31. 1. "CFIE,Cancellation finished interrupt enable."
group.long 0xF0++0x3
line.long 0x0 "TXEFC,Tx Event FIFO Configuration"
hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO watermark 0 = Watermark interrupt disabled."
hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO size 0 = Tx event FIFO disabled."
hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO start address."
rgroup.long 0xF4++0x3
line.long 0x0 "TXEFS,Tx Event FIFO Status"
bitfld.long 0x0 25. "TEFL,Tx event FIFO element lost." "0,1"
bitfld.long 0x0 24. "EFF,Event FIFO full." "0,1"
hexmask.long.byte 0x0 16.--21. 1. "EFPI,Event FIFO put index."
hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO get index."
hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO fill level."
group.long 0xF8++0x3
line.long 0x0 "TXEFA,Tx Event FIFO Acknowledge"
hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO acknowledge index."
group.long 0x200++0x3
line.long 0x0 "MRBA,CAN Message RAM Base Address"
hexmask.long.word 0x0 16.--31. 1. "BA,Base address for the message RAM in the chip memory map."
group.long 0x400++0x3
line.long 0x0 "ETSCC,External Timestamp Counter Configuration"
bitfld.long 0x0 31. "ETCE,External timestamp counter enable." "0,1"
hexmask.long.word 0x0 0.--10. 1. "ETCP,External timestamp prescaler value."
group.long 0x600++0x3
line.long 0x0 "ETSCV,External Timestamp Counter Value"
hexmask.long.word 0x0 0.--15. 1. "ETSC,External timestamp counter."
tree.end
tree "CAN1"
base ad:0x4009E000
group.long 0xC++0x7
line.long 0x0 "DBTP,Data Bit Timing Prescaler Register"
bitfld.long 0x0 23. "TDC,Transmitter delay compensation." "0,1"
hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data bit rate prescaler."
hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point."
hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point."
hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data (re)synchronization jump width."
line.long 0x4 "TEST,Test Register"
bitfld.long 0x4 7. "RX,Monitors the actual value of the CAN_RXD." "0,1"
bitfld.long 0x4 5.--6. "TX,Control of transmit pin." "0,1,2,3"
bitfld.long 0x4 4. "LBCK,Loop back mode." "0,1"
group.long 0x18++0x13
line.long 0x0 "CCCR,CC Control Register"
bitfld.long 0x0 15. "NISO,Non ISO operation." "0,1"
bitfld.long 0x0 14. "TXP,Transmit pause." "0,1"
bitfld.long 0x0 13. "EFBI,Edge filtering during bus integration." "0,1"
bitfld.long 0x0 12. "PXHD,Protocol exception handling disable." "0,1"
bitfld.long 0x0 9. "BRSE,When CAN FD operation is disabled  this bit is not evaluated." "0,1"
bitfld.long 0x0 8. "FDOE,CAN FD operation enable." "0,1"
bitfld.long 0x0 7. "TEST,Test mode enable." "0,1"
bitfld.long 0x0 6. "DAR,Disable automatic retransmission." "0,1"
bitfld.long 0x0 5. "MON,Bus monitoring mode." "0,1"
bitfld.long 0x0 4. "CSR,Clock Stop Request." "0,1"
newline
bitfld.long 0x0 3. "CSA,Clock Stop Acknowledge." "0,1"
bitfld.long 0x0 2. "ASM,Restricted operational mode." "0,1"
bitfld.long 0x0 1. "CCE,Configuration change enable." "0,1"
bitfld.long 0x0 0. "INIT,Initialization." "0,1"
line.long 0x4 "NBTP,Nominal Bit Timing and Prescaler Register"
hexmask.long.byte 0x4 25.--31. 1. "NSJW,Nominal (re)synchronization jump width."
hexmask.long.word 0x4 16.--24. 1. "NBRP,Nominal bit rate prescaler."
hexmask.long.byte 0x4 8.--15. 1. "NTSEG1,Nominal time segment before sample point."
hexmask.long.byte 0x4 0.--6. 1. "NTSEG2,Nominal time segment after sample point."
line.long 0x8 "TSCC,Timestamp Counter Configuration"
hexmask.long.byte 0x8 16.--19. 1. "TCP,Timestamp counter prescaler Configures the timestamp and timeout counters time unit in multiple of CAN bit times."
bitfld.long 0x8 0.--1. "TSS,Timestamp select." "0,1,2,3"
line.long 0xC "TSCV,Timestamp Counter Value"
hexmask.long.word 0xC 0.--15. 1. "TSC,Timestamp counter."
line.long 0x10 "TOCC,Timeout Counter Configuration"
hexmask.long.word 0x10 16.--31. 1. "TOP,Timeout period."
bitfld.long 0x10 1.--2. "TOS,Timeout select." "0,1,2,3"
bitfld.long 0x10 0. "ETOC,Enable timeout counter." "0,1"
rgroup.long 0x2C++0x3
line.long 0x0 "TOCV,Timeout Counter Value"
hexmask.long.word 0x0 0.--15. 1. "TOC,Timeout counter."
rgroup.long 0x40++0x7
line.long 0x0 "ECR,Error Counter Register"
hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN error logging."
bitfld.long 0x0 15. "RP,Receive error passive." "0,1"
hexmask.long.byte 0x0 8.--14. 1. "REC,Receive error counter."
hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit error counter."
line.long 0x4 "PSR,Protocol Status Register"
hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter delay compensation value."
bitfld.long 0x4 14. "PXE,Protocol exception event." "0,1"
bitfld.long 0x4 13. "RFDF,Received a CAN FD message." "0,1"
bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD message." "0,1"
bitfld.long 0x4 11. "RESI,ESI flag of the last received CAN FD message." "0,1"
bitfld.long 0x4 8.--10. "DLEC,Data phase last error code." "0,1,2,3,4,5,6,7"
bitfld.long 0x4 7. "BO,Bus Off Status." "0,1"
bitfld.long 0x4 6. "EW,Warning status." "0,1"
bitfld.long 0x4 5. "EP,Error Passive." "0,1"
bitfld.long 0x4 3.--4. "ACT,Activity." "0,1,2,3"
newline
bitfld.long 0x4 0.--2. "LEC,Last error code." "0,1,2,3,4,5,6,7"
group.long 0x48++0x3
line.long 0x0 "TDCR,Transmitter Delay Compensator Register"
hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter delay compensation offset."
hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter delay compensation filter window length."
group.long 0x50++0xF
line.long 0x0 "IR,Interrupt Register"
bitfld.long 0x0 29. "ARA,Access to reserved address." "0,1"
bitfld.long 0x0 28. "PED,Protocol error in data phase." "0,1"
bitfld.long 0x0 27. "PEA,Protocol error in arbitration phase." "0,1"
bitfld.long 0x0 26. "WDI,Watchdog interrupt." "0,1"
bitfld.long 0x0 25. "BO,Bus_Off Status." "0,1"
bitfld.long 0x0 24. "EW,Warning status." "0,1"
bitfld.long 0x0 23. "EP,Error passive." "0,1"
bitfld.long 0x0 22. "ELO,Error logging overflow." "0,1"
bitfld.long 0x0 21. "BEU,Bit error uncorrected." "0,1"
bitfld.long 0x0 20. "BEC,Bit error corrected." "0,1"
newline
bitfld.long 0x0 19. "DRX,Message stored in dedicated Rx buffer." "0,1"
bitfld.long 0x0 18. "TOO,Timeout occurred." "0,1"
bitfld.long 0x0 17. "MRAF,Message RAM access failure." "0,1"
bitfld.long 0x0 16. "TSW,Timestamp wraparound." "0,1"
bitfld.long 0x0 15. "TEFL,Tx event FIFO element lost." "0,1"
bitfld.long 0x0 14. "TEFF,Tx event FIFO full." "0,1"
bitfld.long 0x0 13. "TEFW,Tx event FIFO watermark reached." "0,1"
bitfld.long 0x0 12. "TEFN,Tx event FIFO new entry." "0,1"
bitfld.long 0x0 11. "TFE,Tx FIFO empty." "0,1"
bitfld.long 0x0 10. "TCF,Transmission cancellation finished." "0,1"
newline
bitfld.long 0x0 9. "TC,Transmission completed." "0,1"
bitfld.long 0x0 8. "HPM,High priority message." "0,1"
bitfld.long 0x0 7. "RF1L,Rx FIFO 1 message lost." "0,1"
bitfld.long 0x0 6. "RF1F,Rx FIFO 1 full." "0,1"
bitfld.long 0x0 5. "RF1W,Rx FIFO 1 watermark reached." "0,1"
bitfld.long 0x0 4. "RF1N,Rx FIFO 1 new message." "0,1"
bitfld.long 0x0 3. "RF0L,Rx FIFO 0 message lost." "0,1"
bitfld.long 0x0 2. "RF0F,Rx FIFO 0 full." "0,1"
bitfld.long 0x0 1. "RF0W,Rx FIFO 0 watermark reached." "0,1"
bitfld.long 0x0 0. "RF0N,Rx FIFO 0 new message." "0,1"
line.long 0x4 "IE,Interrupt Enable"
bitfld.long 0x4 29. "ARAE,Access to reserved address interrupt enable." "0,1"
bitfld.long 0x4 28. "PEDE,Protocol error in data phase interrupt enable." "0,1"
bitfld.long 0x4 27. "PEAE,Protocol error in arbitration phase interrupt enable." "0,1"
bitfld.long 0x4 26. "WDIE,Watchdog interrupt enable." "0,1"
bitfld.long 0x4 25. "BOE,Bus_Off Status interrupt enable." "0,1"
bitfld.long 0x4 24. "EWE,Warning status interrupt enable." "0,1"
bitfld.long 0x4 23. "EPE,Error passive interrupt enable." "0,1"
bitfld.long 0x4 22. "ELOE,Error logging overflow interrupt enable." "0,1"
bitfld.long 0x4 21. "BEUE,Bit error uncorrected interrupt enable." "0,1"
bitfld.long 0x4 20. "BECE,Bit error corrected interrupt enable." "0,1"
newline
bitfld.long 0x4 19. "DRXE,Message stored in dedicated Rx buffer interrupt enable." "0,1"
bitfld.long 0x4 18. "TOOE,Timeout occurred interrupt enable." "0,1"
bitfld.long 0x4 17. "MRAFE,Message RAM access failure interrupt enable." "0,1"
bitfld.long 0x4 16. "TSWE,Timestamp wraparound interrupt enable." "0,1"
bitfld.long 0x4 15. "TEFLE,Tx event FIFO element lost interrupt enable." "0,1"
bitfld.long 0x4 14. "TEFFE,Tx event FIFO full interrupt enable." "0,1"
bitfld.long 0x4 13. "TEFWE,Tx event FIFO watermark reached interrupt enable." "0,1"
bitfld.long 0x4 12. "TEFNE,Tx event FIFO new entry interrupt enable." "0,1"
bitfld.long 0x4 11. "TFEE,Tx FIFO empty interrupt enable." "0,1"
bitfld.long 0x4 10. "TCFE,Transmission cancellation finished interrupt enable." "0,1"
newline
bitfld.long 0x4 9. "TCE,Transmission completed interrupt enable." "0,1"
bitfld.long 0x4 8. "HPME,High priority message interrupt enable." "0,1"
bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 message lost interrupt enable." "0,1"
bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 full interrupt enable." "0,1"
bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 watermark reached interrupt enable." "0,1"
bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 new message interrupt enable." "0,1"
bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 message lost interrupt enable." "0,1"
bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 full interrupt enable." "0,1"
bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 watermark reached interrupt enable." "0,1"
bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 new message interrupt enable." "0,1"
line.long 0x8 "ILS,Interrupt Line Select"
bitfld.long 0x8 29. "ARAL,Access to reserved address interrupt line." "0,1"
bitfld.long 0x8 28. "PEDL,Protocol error in data phase interrupt line." "0,1"
bitfld.long 0x8 27. "PEAL,Protocol error in arbitration phase interrupt line." "0,1"
bitfld.long 0x8 26. "WDIL,Watchdog interrupt line." "0,1"
bitfld.long 0x8 25. "BOL,Bus_Off Status interrupt line." "0,1"
bitfld.long 0x8 24. "EWL,Warning status interrupt line." "0,1"
bitfld.long 0x8 23. "EPL,Error passive interrupt line." "0,1"
bitfld.long 0x8 22. "ELOL,Error logging overflow interrupt line." "0,1"
bitfld.long 0x8 21. "BEUL,Bit error uncorrected interrupt line." "0,1"
bitfld.long 0x8 20. "BECL,Bit error corrected interrupt line." "0,1"
newline
bitfld.long 0x8 19. "DRXL,Message stored in dedicated Rx buffer interrupt line." "0,1"
bitfld.long 0x8 18. "TOOL,Timeout occurred interrupt line." "0,1"
bitfld.long 0x8 17. "MRAFL,Message RAM access failure interrupt line." "0,1"
bitfld.long 0x8 16. "TSWL,Timestamp wraparound interrupt line." "0,1"
bitfld.long 0x8 15. "TEFLL,Tx event FIFO element lost interrupt line." "0,1"
bitfld.long 0x8 14. "TEFFL,Tx event FIFO full interrupt line." "0,1"
bitfld.long 0x8 13. "TEFWL,Tx event FIFO watermark reached interrupt line." "0,1"
bitfld.long 0x8 12. "TEFNL,Tx event FIFO new entry interrupt line." "0,1"
bitfld.long 0x8 11. "TFEL,Tx FIFO empty interrupt line." "0,1"
bitfld.long 0x8 10. "TCFL,Transmission cancellation finished interrupt line." "0,1"
newline
bitfld.long 0x8 9. "TCL,Transmission completed interrupt line." "0,1"
bitfld.long 0x8 8. "HPML,High priority message interrupt line." "0,1"
bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 message lost interrupt line." "0,1"
bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 full interrupt line." "0,1"
bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 watermark reached interrupt line." "0,1"
bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 new message interrupt line." "0,1"
bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 message lost interrupt line." "0,1"
bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 full interrupt line." "0,1"
bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 watermark reached interrupt line." "0,1"
bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 new message interrupt line." "0,1"
line.long 0xC "ILE,Interrupt Line Enable"
bitfld.long 0xC 1. "EINT1,Enable interrupt line 1." "0,1"
bitfld.long 0xC 0. "EINT0,Enable interrupt line 0." "0,1"
group.long 0x80++0xB
line.long 0x0 "GFC,Global Filter Configuration"
bitfld.long 0x0 4.--5. "ANFS,Accept non-matching frames standard." "0,1,2,3"
bitfld.long 0x0 2.--3. "ANFE,Accept non-matching frames extended." "0,1,2,3"
bitfld.long 0x0 1. "RRFS,Reject remote frames standard." "0,1"
bitfld.long 0x0 0. "RRFE,Reject remote frames extended." "0,1"
line.long 0x4 "SIDFC,Standard ID Filter Configuration"
hexmask.long.byte 0x4 16.--23. 1. "LSS,List size standard 0 = No standard message ID filter."
hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter list standard start address."
line.long 0x8 "XIDFC,Extended ID Filter Configuration"
hexmask.long.byte 0x8 16.--23. 1. "LSE,List size extended 0 = No extended message ID filter."
hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter list extended start address."
group.long 0x90++0x3
line.long 0x0 "XIDAM,Extended ID AND Mask"
hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID mask."
rgroup.long 0x94++0x3
line.long 0x0 "HPMS,High Priority Message Status"
bitfld.long 0x0 15. "FLST,Filter list." "0,1"
hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter index."
bitfld.long 0x0 6.--7. "MSI,Message storage indicator." "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer index."
group.long 0x98++0x1B
line.long 0x0 "NDAT1,New Data 1"
hexmask.long 0x0 0.--31. 1. "ND,New Data."
line.long 0x4 "NDAT2,New Data 2"
hexmask.long 0x4 0.--31. 1. "ND,New Data."
line.long 0x8 "RXF0C,Rx FIFO 0 Configuration"
bitfld.long 0x8 31. "F0OM,FIFO 0 operation mode." "0,1"
hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 watermark 0 = Watermark interrupt disabled."
hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 size."
hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 start address."
line.long 0xC "RXF0S,Rx FIFO 0 Status"
bitfld.long 0xC 25. "RF0L,Rx FIFO 0 message lost." "0,1"
bitfld.long 0xC 24. "F0F,Rx FIFO 0 full." "0,1"
hexmask.long.byte 0xC 16.--21. 1. "F0PI,Rx FIFO 0 put index."
hexmask.long.byte 0xC 8.--13. 1. "F0GI,Rx FIFO 0 get index."
hexmask.long.byte 0xC 0.--6. 1. "F0FL,Rx FIFO 0 fill level."
line.long 0x10 "RXF0A,Rx FIFO 0 Acknowledge"
hexmask.long.byte 0x10 0.--5. 1. "F0AI,Rx FIFO 0 acknowledge index."
line.long 0x14 "RXBC,Rx Buffer Configuration"
hexmask.long.word 0x14 2.--15. 1. "RBSA,Rx buffer start address."
line.long 0x18 "RXF1C,Rx FIFO 1 Configuration"
bitfld.long 0x18 31. "F1OM,FIFO 1 operation mode." "0,1"
hexmask.long.byte 0x18 24.--30. 1. "F1WM,Rx FIFO 1 watermark 0 = Watermark interrupt disabled."
hexmask.long.byte 0x18 16.--22. 1. "F1S,Rx FIFO 1 size 0 = No Rx FIFO 1."
hexmask.long.word 0x18 2.--15. 1. "F1SA,Rx FIFO 1 start address."
rgroup.long 0xB4++0x3
line.long 0x0 "RXF1S,Rx FIFO 1 Status"
bitfld.long 0x0 25. "RF1L,Rx FIFO 1 message lost." "0,1"
bitfld.long 0x0 24. "F1F,Rx FIFO 1 full." "0,1"
hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 put index."
hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 get index."
hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 fill level."
group.long 0xB8++0x2F
line.long 0x0 "RXF1A,Rx FIFO 1 Acknowledge"
hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 acknowledge index."
line.long 0x4 "RXESC,Rx Buffer and FIFO Element Size Configuration"
bitfld.long 0x4 8.--10. "RBDS,." "0,1,2,3,4,5,6,7"
bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 data field size." "0,1,2,3,4,5,6,7"
bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 data field size." "0,1,2,3,4,5,6,7"
line.long 0x8 "TXBC,Tx Buffer Configuration"
bitfld.long 0x8 30. "TFQM,Tx FIFO/queue mode." "0,1"
hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/queue size 0 = No tx FIFO/Queue."
hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of dedicated transmit buffers 0 = No dedicated Tx buffers."
hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx buffers start address."
line.long 0xC "TXFQS,Tx FIFO/Queue Status"
bitfld.long 0xC 21. "TFQF,Tx FIFO/queue full." "0,1"
hexmask.long.byte 0xC 16.--20. 1. "TFQPI,Tx FIFO/queue put index."
hexmask.long.byte 0xC 8.--12. 1. "TFGI,Tx FIFO get index."
line.long 0x10 "TXESC,Tx Buffer Element Size Configuration"
bitfld.long 0x10 0.--2. "TBDS,Tx buffer data field size." "0,1,2,3,4,5,6,7"
line.long 0x14 "TXBRP,Tx Buffer Request Pending"
hexmask.long 0x14 0.--31. 1. "TRP,Transmission request pending."
line.long 0x18 "TXBAR,Tx Buffer Add Request"
hexmask.long 0x18 0.--31. 1. "AR,Add request."
line.long 0x1C "TXBCR,Tx Buffer Cancellation Request"
hexmask.long 0x1C 0.--31. 1. "CR,Cancellation request."
line.long 0x20 "TXBTO,Tx Buffer Transmission Occurred"
hexmask.long 0x20 0.--31. 1. "TO,Transmission occurred."
line.long 0x24 "TXBCF,Tx Buffer Cancellation Finished"
hexmask.long 0x24 0.--31. 1. "TO,Cancellation finished."
line.long 0x28 "TXBTIE,Tx Buffer Transmission Interrupt Enable"
hexmask.long 0x28 0.--31. 1. "TIE,Transmission interrupt enable."
line.long 0x2C "TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable"
hexmask.long 0x2C 0.--31. 1. "CFIE,Cancellation finished interrupt enable."
group.long 0xF0++0x3
line.long 0x0 "TXEFC,Tx Event FIFO Configuration"
hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO watermark 0 = Watermark interrupt disabled."
hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO size 0 = Tx event FIFO disabled."
hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO start address."
rgroup.long 0xF4++0x3
line.long 0x0 "TXEFS,Tx Event FIFO Status"
bitfld.long 0x0 25. "TEFL,Tx event FIFO element lost." "0,1"
bitfld.long 0x0 24. "EFF,Event FIFO full." "0,1"
hexmask.long.byte 0x0 16.--21. 1. "EFPI,Event FIFO put index."
hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO get index."
hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO fill level."
group.long 0xF8++0x3
line.long 0x0 "TXEFA,Tx Event FIFO Acknowledge"
hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO acknowledge index."
group.long 0x200++0x3
line.long 0x0 "MRBA,CAN Message RAM Base Address"
hexmask.long.word 0x0 16.--31. 1. "BA,Base address for the message RAM in the chip memory map."
group.long 0x400++0x3
line.long 0x0 "ETSCC,External Timestamp Counter Configuration"
bitfld.long 0x0 31. "ETCE,External timestamp counter enable." "0,1"
hexmask.long.word 0x0 0.--10. 1. "ETCP,External timestamp prescaler value."
group.long 0x600++0x3
line.long 0x0 "ETSCV,External Timestamp Counter Value"
hexmask.long.word 0x0 0.--15. 1. "ETSC,External timestamp counter."
tree.end
endif
sif (cpuis("LPC54628*"))
tree "CAN0"
base ad:0x4009D000
group.long 0xC++0x7
line.long 0x0 "DBTP,Data Bit Timing Prescaler Register"
bitfld.long 0x0 23. "TDC,Transmitter delay compensation." "0,1"
hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data bit rate prescaler."
hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point."
hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point."
hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data (re)synchronization jump width."
line.long 0x4 "TEST,Test Register"
bitfld.long 0x4 7. "RX,Monitors the actual value of the CAN_RXD." "0,1"
bitfld.long 0x4 5.--6. "TX,Control of transmit pin." "0,1,2,3"
bitfld.long 0x4 4. "LBCK,Loop back mode." "0,1"
group.long 0x18++0x13
line.long 0x0 "CCCR,CC Control Register"
bitfld.long 0x0 15. "NISO,Non ISO operation." "0,1"
bitfld.long 0x0 14. "TXP,Transmit pause." "0,1"
bitfld.long 0x0 13. "EFBI,Edge filtering during bus integration." "0,1"
bitfld.long 0x0 12. "PXHD,Protocol exception handling disable." "0,1"
bitfld.long 0x0 9. "BRSE,When CAN FD operation is disabled  this bit is not evaluated." "0,1"
bitfld.long 0x0 8. "FDOE,CAN FD operation enable." "0,1"
bitfld.long 0x0 7. "TEST,Test mode enable." "0,1"
bitfld.long 0x0 6. "DAR,Disable automatic retransmission." "0,1"
bitfld.long 0x0 5. "MON,Bus monitoring mode." "0,1"
bitfld.long 0x0 4. "CSR,Clock Stop Request." "0,1"
newline
bitfld.long 0x0 3. "CSA,Clock Stop Acknowledge." "0,1"
bitfld.long 0x0 2. "ASM,Restricted operational mode." "0,1"
bitfld.long 0x0 1. "CCE,Configuration change enable." "0,1"
bitfld.long 0x0 0. "INIT,Initialization." "0,1"
line.long 0x4 "NBTP,Nominal Bit Timing and Prescaler Register"
hexmask.long.byte 0x4 25.--31. 1. "NSJW,Nominal (re)synchronization jump width."
hexmask.long.word 0x4 16.--24. 1. "NBRP,Nominal bit rate prescaler."
hexmask.long.byte 0x4 8.--15. 1. "NTSEG1,Nominal time segment before sample point."
hexmask.long.byte 0x4 0.--6. 1. "NTSEG2,Nominal time segment after sample point."
line.long 0x8 "TSCC,Timestamp Counter Configuration"
hexmask.long.byte 0x8 16.--19. 1. "TCP,Timestamp counter prescaler Configures the timestamp and timeout counters time unit in multiple of CAN bit times."
bitfld.long 0x8 0.--1. "TSS,Timestamp select." "0,1,2,3"
line.long 0xC "TSCV,Timestamp Counter Value"
hexmask.long.word 0xC 0.--15. 1. "TSC,Timestamp counter."
line.long 0x10 "TOCC,Timeout Counter Configuration"
hexmask.long.word 0x10 16.--31. 1. "TOP,Timeout period."
bitfld.long 0x10 1.--2. "TOS,Timeout select." "0,1,2,3"
bitfld.long 0x10 0. "ETOC,Enable timeout counter." "0,1"
rgroup.long 0x2C++0x3
line.long 0x0 "TOCV,Timeout Counter Value"
hexmask.long.word 0x0 0.--15. 1. "TOC,Timeout counter."
rgroup.long 0x40++0x7
line.long 0x0 "ECR,Error Counter Register"
hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN error logging."
bitfld.long 0x0 15. "RP,Receive error passive." "0,1"
hexmask.long.byte 0x0 8.--14. 1. "REC,Receive error counter."
hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit error counter."
line.long 0x4 "PSR,Protocol Status Register"
hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter delay compensation value."
bitfld.long 0x4 14. "PXE,Protocol exception event." "0,1"
bitfld.long 0x4 13. "RFDF,Received a CAN FD message." "0,1"
bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD message." "0,1"
bitfld.long 0x4 11. "RESI,ESI flag of the last received CAN FD message." "0,1"
bitfld.long 0x4 8.--10. "DLEC,Data phase last error code." "0,1,2,3,4,5,6,7"
bitfld.long 0x4 7. "BO,Bus Off Status." "0,1"
bitfld.long 0x4 6. "EW,Warning status." "0,1"
bitfld.long 0x4 5. "EP,Error Passive." "0,1"
bitfld.long 0x4 3.--4. "ACT,Activity." "0,1,2,3"
newline
bitfld.long 0x4 0.--2. "LEC,Last error code." "0,1,2,3,4,5,6,7"
group.long 0x48++0x3
line.long 0x0 "TDCR,Transmitter Delay Compensator Register"
hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter delay compensation offset."
hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter delay compensation filter window length."
group.long 0x50++0xF
line.long 0x0 "IR,Interrupt Register"
bitfld.long 0x0 29. "ARA,Access to reserved address." "0,1"
bitfld.long 0x0 28. "PED,Protocol error in data phase." "0,1"
bitfld.long 0x0 27. "PEA,Protocol error in arbitration phase." "0,1"
bitfld.long 0x0 26. "WDI,Watchdog interrupt." "0,1"
bitfld.long 0x0 25. "BO,Bus_Off Status." "0,1"
bitfld.long 0x0 24. "EW,Warning status." "0,1"
bitfld.long 0x0 23. "EP,Error passive." "0,1"
bitfld.long 0x0 22. "ELO,Error logging overflow." "0,1"
bitfld.long 0x0 21. "BEU,Bit error uncorrected." "0,1"
bitfld.long 0x0 20. "BEC,Bit error corrected." "0,1"
newline
bitfld.long 0x0 19. "DRX,Message stored in dedicated Rx buffer." "0,1"
bitfld.long 0x0 18. "TOO,Timeout occurred." "0,1"
bitfld.long 0x0 17. "MRAF,Message RAM access failure." "0,1"
bitfld.long 0x0 16. "TSW,Timestamp wraparound." "0,1"
bitfld.long 0x0 15. "TEFL,Tx event FIFO element lost." "0,1"
bitfld.long 0x0 14. "TEFF,Tx event FIFO full." "0,1"
bitfld.long 0x0 13. "TEFW,Tx event FIFO watermark reached." "0,1"
bitfld.long 0x0 12. "TEFN,Tx event FIFO new entry." "0,1"
bitfld.long 0x0 11. "TFE,Tx FIFO empty." "0,1"
bitfld.long 0x0 10. "TCF,Transmission cancellation finished." "0,1"
newline
bitfld.long 0x0 9. "TC,Transmission completed." "0,1"
bitfld.long 0x0 8. "HPM,High priority message." "0,1"
bitfld.long 0x0 7. "RF1L,Rx FIFO 1 message lost." "0,1"
bitfld.long 0x0 6. "RF1F,Rx FIFO 1 full." "0,1"
bitfld.long 0x0 5. "RF1W,Rx FIFO 1 watermark reached." "0,1"
bitfld.long 0x0 4. "RF1N,Rx FIFO 1 new message." "0,1"
bitfld.long 0x0 3. "RF0L,Rx FIFO 0 message lost." "0,1"
bitfld.long 0x0 2. "RF0F,Rx FIFO 0 full." "0,1"
bitfld.long 0x0 1. "RF0W,Rx FIFO 0 watermark reached." "0,1"
bitfld.long 0x0 0. "RF0N,Rx FIFO 0 new message." "0,1"
line.long 0x4 "IE,Interrupt Enable"
bitfld.long 0x4 29. "ARAE,Access to reserved address interrupt enable." "0,1"
bitfld.long 0x4 28. "PEDE,Protocol error in data phase interrupt enable." "0,1"
bitfld.long 0x4 27. "PEAE,Protocol error in arbitration phase interrupt enable." "0,1"
bitfld.long 0x4 26. "WDIE,Watchdog interrupt enable." "0,1"
bitfld.long 0x4 25. "BOE,Bus_Off Status interrupt enable." "0,1"
bitfld.long 0x4 24. "EWE,Warning status interrupt enable." "0,1"
bitfld.long 0x4 23. "EPE,Error passive interrupt enable." "0,1"
bitfld.long 0x4 22. "ELOE,Error logging overflow interrupt enable." "0,1"
bitfld.long 0x4 21. "BEUE,Bit error uncorrected interrupt enable." "0,1"
bitfld.long 0x4 20. "BECE,Bit error corrected interrupt enable." "0,1"
newline
bitfld.long 0x4 19. "DRXE,Message stored in dedicated Rx buffer interrupt enable." "0,1"
bitfld.long 0x4 18. "TOOE,Timeout occurred interrupt enable." "0,1"
bitfld.long 0x4 17. "MRAFE,Message RAM access failure interrupt enable." "0,1"
bitfld.long 0x4 16. "TSWE,Timestamp wraparound interrupt enable." "0,1"
bitfld.long 0x4 15. "TEFLE,Tx event FIFO element lost interrupt enable." "0,1"
bitfld.long 0x4 14. "TEFFE,Tx event FIFO full interrupt enable." "0,1"
bitfld.long 0x4 13. "TEFWE,Tx event FIFO watermark reached interrupt enable." "0,1"
bitfld.long 0x4 12. "TEFNE,Tx event FIFO new entry interrupt enable." "0,1"
bitfld.long 0x4 11. "TFEE,Tx FIFO empty interrupt enable." "0,1"
bitfld.long 0x4 10. "TCFE,Transmission cancellation finished interrupt enable." "0,1"
newline
bitfld.long 0x4 9. "TCE,Transmission completed interrupt enable." "0,1"
bitfld.long 0x4 8. "HPME,High priority message interrupt enable." "0,1"
bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 message lost interrupt enable." "0,1"
bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 full interrupt enable." "0,1"
bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 watermark reached interrupt enable." "0,1"
bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 new message interrupt enable." "0,1"
bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 message lost interrupt enable." "0,1"
bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 full interrupt enable." "0,1"
bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 watermark reached interrupt enable." "0,1"
bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 new message interrupt enable." "0,1"
line.long 0x8 "ILS,Interrupt Line Select"
bitfld.long 0x8 29. "ARAL,Access to reserved address interrupt line." "0,1"
bitfld.long 0x8 28. "PEDL,Protocol error in data phase interrupt line." "0,1"
bitfld.long 0x8 27. "PEAL,Protocol error in arbitration phase interrupt line." "0,1"
bitfld.long 0x8 26. "WDIL,Watchdog interrupt line." "0,1"
bitfld.long 0x8 25. "BOL,Bus_Off Status interrupt line." "0,1"
bitfld.long 0x8 24. "EWL,Warning status interrupt line." "0,1"
bitfld.long 0x8 23. "EPL,Error passive interrupt line." "0,1"
bitfld.long 0x8 22. "ELOL,Error logging overflow interrupt line." "0,1"
bitfld.long 0x8 21. "BEUL,Bit error uncorrected interrupt line." "0,1"
bitfld.long 0x8 20. "BECL,Bit error corrected interrupt line." "0,1"
newline
bitfld.long 0x8 19. "DRXL,Message stored in dedicated Rx buffer interrupt line." "0,1"
bitfld.long 0x8 18. "TOOL,Timeout occurred interrupt line." "0,1"
bitfld.long 0x8 17. "MRAFL,Message RAM access failure interrupt line." "0,1"
bitfld.long 0x8 16. "TSWL,Timestamp wraparound interrupt line." "0,1"
bitfld.long 0x8 15. "TEFLL,Tx event FIFO element lost interrupt line." "0,1"
bitfld.long 0x8 14. "TEFFL,Tx event FIFO full interrupt line." "0,1"
bitfld.long 0x8 13. "TEFWL,Tx event FIFO watermark reached interrupt line." "0,1"
bitfld.long 0x8 12. "TEFNL,Tx event FIFO new entry interrupt line." "0,1"
bitfld.long 0x8 11. "TFEL,Tx FIFO empty interrupt line." "0,1"
bitfld.long 0x8 10. "TCFL,Transmission cancellation finished interrupt line." "0,1"
newline
bitfld.long 0x8 9. "TCL,Transmission completed interrupt line." "0,1"
bitfld.long 0x8 8. "HPML,High priority message interrupt line." "0,1"
bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 message lost interrupt line." "0,1"
bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 full interrupt line." "0,1"
bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 watermark reached interrupt line." "0,1"
bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 new message interrupt line." "0,1"
bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 message lost interrupt line." "0,1"
bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 full interrupt line." "0,1"
bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 watermark reached interrupt line." "0,1"
bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 new message interrupt line." "0,1"
line.long 0xC "ILE,Interrupt Line Enable"
bitfld.long 0xC 1. "EINT1,Enable interrupt line 1." "0,1"
bitfld.long 0xC 0. "EINT0,Enable interrupt line 0." "0,1"
group.long 0x80++0xB
line.long 0x0 "GFC,Global Filter Configuration"
bitfld.long 0x0 4.--5. "ANFS,Accept non-matching frames standard." "0,1,2,3"
bitfld.long 0x0 2.--3. "ANFE,Accept non-matching frames extended." "0,1,2,3"
bitfld.long 0x0 1. "RRFS,Reject remote frames standard." "0,1"
bitfld.long 0x0 0. "RRFE,Reject remote frames extended." "0,1"
line.long 0x4 "SIDFC,Standard ID Filter Configuration"
hexmask.long.byte 0x4 16.--23. 1. "LSS,List size standard 0 = No standard message ID filter."
hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter list standard start address."
line.long 0x8 "XIDFC,Extended ID Filter Configuration"
hexmask.long.byte 0x8 16.--23. 1. "LSE,List size extended 0 = No extended message ID filter."
hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter list extended start address."
group.long 0x90++0x3
line.long 0x0 "XIDAM,Extended ID AND Mask"
hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID mask."
rgroup.long 0x94++0x3
line.long 0x0 "HPMS,High Priority Message Status"
bitfld.long 0x0 15. "FLST,Filter list." "0,1"
hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter index."
bitfld.long 0x0 6.--7. "MSI,Message storage indicator." "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer index."
group.long 0x98++0x1B
line.long 0x0 "NDAT1,New Data 1"
hexmask.long 0x0 0.--31. 1. "ND,New Data."
line.long 0x4 "NDAT2,New Data 2"
hexmask.long 0x4 0.--31. 1. "ND,New Data."
line.long 0x8 "RXF0C,Rx FIFO 0 Configuration"
bitfld.long 0x8 31. "F0OM,FIFO 0 operation mode." "0,1"
hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 watermark 0 = Watermark interrupt disabled."
hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 size."
hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 start address."
line.long 0xC "RXF0S,Rx FIFO 0 Status"
bitfld.long 0xC 25. "RF0L,Rx FIFO 0 message lost." "0,1"
bitfld.long 0xC 24. "F0F,Rx FIFO 0 full." "0,1"
hexmask.long.byte 0xC 16.--21. 1. "F0PI,Rx FIFO 0 put index."
hexmask.long.byte 0xC 8.--13. 1. "F0GI,Rx FIFO 0 get index."
hexmask.long.byte 0xC 0.--6. 1. "F0FL,Rx FIFO 0 fill level."
line.long 0x10 "RXF0A,Rx FIFO 0 Acknowledge"
hexmask.long.byte 0x10 0.--5. 1. "F0AI,Rx FIFO 0 acknowledge index."
line.long 0x14 "RXBC,Rx Buffer Configuration"
hexmask.long.word 0x14 2.--15. 1. "RBSA,Rx buffer start address."
line.long 0x18 "RXF1C,Rx FIFO 1 Configuration"
bitfld.long 0x18 31. "F1OM,FIFO 1 operation mode." "0,1"
hexmask.long.byte 0x18 24.--30. 1. "F1WM,Rx FIFO 1 watermark 0 = Watermark interrupt disabled."
hexmask.long.byte 0x18 16.--22. 1. "F1S,Rx FIFO 1 size 0 = No Rx FIFO 1."
hexmask.long.word 0x18 2.--15. 1. "F1SA,Rx FIFO 1 start address."
rgroup.long 0xB4++0x3
line.long 0x0 "RXF1S,Rx FIFO 1 Status"
bitfld.long 0x0 25. "RF1L,Rx FIFO 1 message lost." "0,1"
bitfld.long 0x0 24. "F1F,Rx FIFO 1 full." "0,1"
hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 put index."
hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 get index."
hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 fill level."
group.long 0xB8++0x2F
line.long 0x0 "RXF1A,Rx FIFO 1 Acknowledge"
hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 acknowledge index."
line.long 0x4 "RXESC,Rx Buffer and FIFO Element Size Configuration"
bitfld.long 0x4 8.--10. "RBDS,." "0,1,2,3,4,5,6,7"
bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 data field size." "0,1,2,3,4,5,6,7"
bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 data field size." "0,1,2,3,4,5,6,7"
line.long 0x8 "TXBC,Tx Buffer Configuration"
bitfld.long 0x8 30. "TFQM,Tx FIFO/queue mode." "0,1"
hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/queue size 0 = No tx FIFO/Queue."
hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of dedicated transmit buffers 0 = No dedicated Tx buffers."
hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx buffers start address."
line.long 0xC "TXFQS,Tx FIFO/Queue Status"
bitfld.long 0xC 21. "TFQF,Tx FIFO/queue full." "0,1"
hexmask.long.byte 0xC 16.--20. 1. "TFQPI,Tx FIFO/queue put index."
hexmask.long.byte 0xC 8.--12. 1. "TFGI,Tx FIFO get index."
line.long 0x10 "TXESC,Tx Buffer Element Size Configuration"
bitfld.long 0x10 0.--2. "TBDS,Tx buffer data field size." "0,1,2,3,4,5,6,7"
line.long 0x14 "TXBRP,Tx Buffer Request Pending"
hexmask.long 0x14 0.--31. 1. "TRP,Transmission request pending."
line.long 0x18 "TXBAR,Tx Buffer Add Request"
hexmask.long 0x18 0.--31. 1. "AR,Add request."
line.long 0x1C "TXBCR,Tx Buffer Cancellation Request"
hexmask.long 0x1C 0.--31. 1. "CR,Cancellation request."
line.long 0x20 "TXBTO,Tx Buffer Transmission Occurred"
hexmask.long 0x20 0.--31. 1. "TO,Transmission occurred."
line.long 0x24 "TXBCF,Tx Buffer Cancellation Finished"
hexmask.long 0x24 0.--31. 1. "TO,Cancellation finished."
line.long 0x28 "TXBTIE,Tx Buffer Transmission Interrupt Enable"
hexmask.long 0x28 0.--31. 1. "TIE,Transmission interrupt enable."
line.long 0x2C "TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable"
hexmask.long 0x2C 0.--31. 1. "CFIE,Cancellation finished interrupt enable."
group.long 0xF0++0x3
line.long 0x0 "TXEFC,Tx Event FIFO Configuration"
hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO watermark 0 = Watermark interrupt disabled."
hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO size 0 = Tx event FIFO disabled."
hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO start address."
rgroup.long 0xF4++0x3
line.long 0x0 "TXEFS,Tx Event FIFO Status"
bitfld.long 0x0 25. "TEFL,Tx event FIFO element lost." "0,1"
bitfld.long 0x0 24. "EFF,Event FIFO full." "0,1"
hexmask.long.byte 0x0 16.--21. 1. "EFPI,Event FIFO put index."
hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO get index."
hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO fill level."
group.long 0xF8++0x3
line.long 0x0 "TXEFA,Tx Event FIFO Acknowledge"
hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO acknowledge index."
group.long 0x200++0x3
line.long 0x0 "MRBA,CAN Message RAM Base Address"
hexmask.long.word 0x0 16.--31. 1. "BA,Base address for the message RAM in the chip memory map."
group.long 0x400++0x3
line.long 0x0 "ETSCC,External Timestamp Counter Configuration"
bitfld.long 0x0 31. "ETCE,External timestamp counter enable." "0,1"
hexmask.long.word 0x0 0.--10. 1. "ETCP,External timestamp prescaler value."
group.long 0x600++0x3
line.long 0x0 "ETSCV,External Timestamp Counter Value"
hexmask.long.word 0x0 0.--15. 1. "ETSC,External timestamp counter."
tree.end
tree "CAN1"
base ad:0x4009E000
group.long 0xC++0x7
line.long 0x0 "DBTP,Data Bit Timing Prescaler Register"
bitfld.long 0x0 23. "TDC,Transmitter delay compensation." "0,1"
hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data bit rate prescaler."
hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point."
hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point."
hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data (re)synchronization jump width."
line.long 0x4 "TEST,Test Register"
bitfld.long 0x4 7. "RX,Monitors the actual value of the CAN_RXD." "0,1"
bitfld.long 0x4 5.--6. "TX,Control of transmit pin." "0,1,2,3"
bitfld.long 0x4 4. "LBCK,Loop back mode." "0,1"
group.long 0x18++0x13
line.long 0x0 "CCCR,CC Control Register"
bitfld.long 0x0 15. "NISO,Non ISO operation." "0,1"
bitfld.long 0x0 14. "TXP,Transmit pause." "0,1"
bitfld.long 0x0 13. "EFBI,Edge filtering during bus integration." "0,1"
bitfld.long 0x0 12. "PXHD,Protocol exception handling disable." "0,1"
bitfld.long 0x0 9. "BRSE,When CAN FD operation is disabled  this bit is not evaluated." "0,1"
bitfld.long 0x0 8. "FDOE,CAN FD operation enable." "0,1"
bitfld.long 0x0 7. "TEST,Test mode enable." "0,1"
bitfld.long 0x0 6. "DAR,Disable automatic retransmission." "0,1"
bitfld.long 0x0 5. "MON,Bus monitoring mode." "0,1"
bitfld.long 0x0 4. "CSR,Clock Stop Request." "0,1"
newline
bitfld.long 0x0 3. "CSA,Clock Stop Acknowledge." "0,1"
bitfld.long 0x0 2. "ASM,Restricted operational mode." "0,1"
bitfld.long 0x0 1. "CCE,Configuration change enable." "0,1"
bitfld.long 0x0 0. "INIT,Initialization." "0,1"
line.long 0x4 "NBTP,Nominal Bit Timing and Prescaler Register"
hexmask.long.byte 0x4 25.--31. 1. "NSJW,Nominal (re)synchronization jump width."
hexmask.long.word 0x4 16.--24. 1. "NBRP,Nominal bit rate prescaler."
hexmask.long.byte 0x4 8.--15. 1. "NTSEG1,Nominal time segment before sample point."
hexmask.long.byte 0x4 0.--6. 1. "NTSEG2,Nominal time segment after sample point."
line.long 0x8 "TSCC,Timestamp Counter Configuration"
hexmask.long.byte 0x8 16.--19. 1. "TCP,Timestamp counter prescaler Configures the timestamp and timeout counters time unit in multiple of CAN bit times."
bitfld.long 0x8 0.--1. "TSS,Timestamp select." "0,1,2,3"
line.long 0xC "TSCV,Timestamp Counter Value"
hexmask.long.word 0xC 0.--15. 1. "TSC,Timestamp counter."
line.long 0x10 "TOCC,Timeout Counter Configuration"
hexmask.long.word 0x10 16.--31. 1. "TOP,Timeout period."
bitfld.long 0x10 1.--2. "TOS,Timeout select." "0,1,2,3"
bitfld.long 0x10 0. "ETOC,Enable timeout counter." "0,1"
rgroup.long 0x2C++0x3
line.long 0x0 "TOCV,Timeout Counter Value"
hexmask.long.word 0x0 0.--15. 1. "TOC,Timeout counter."
rgroup.long 0x40++0x7
line.long 0x0 "ECR,Error Counter Register"
hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN error logging."
bitfld.long 0x0 15. "RP,Receive error passive." "0,1"
hexmask.long.byte 0x0 8.--14. 1. "REC,Receive error counter."
hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit error counter."
line.long 0x4 "PSR,Protocol Status Register"
hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter delay compensation value."
bitfld.long 0x4 14. "PXE,Protocol exception event." "0,1"
bitfld.long 0x4 13. "RFDF,Received a CAN FD message." "0,1"
bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD message." "0,1"
bitfld.long 0x4 11. "RESI,ESI flag of the last received CAN FD message." "0,1"
bitfld.long 0x4 8.--10. "DLEC,Data phase last error code." "0,1,2,3,4,5,6,7"
bitfld.long 0x4 7. "BO,Bus Off Status." "0,1"
bitfld.long 0x4 6. "EW,Warning status." "0,1"
bitfld.long 0x4 5. "EP,Error Passive." "0,1"
bitfld.long 0x4 3.--4. "ACT,Activity." "0,1,2,3"
newline
bitfld.long 0x4 0.--2. "LEC,Last error code." "0,1,2,3,4,5,6,7"
group.long 0x48++0x3
line.long 0x0 "TDCR,Transmitter Delay Compensator Register"
hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter delay compensation offset."
hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter delay compensation filter window length."
group.long 0x50++0xF
line.long 0x0 "IR,Interrupt Register"
bitfld.long 0x0 29. "ARA,Access to reserved address." "0,1"
bitfld.long 0x0 28. "PED,Protocol error in data phase." "0,1"
bitfld.long 0x0 27. "PEA,Protocol error in arbitration phase." "0,1"
bitfld.long 0x0 26. "WDI,Watchdog interrupt." "0,1"
bitfld.long 0x0 25. "BO,Bus_Off Status." "0,1"
bitfld.long 0x0 24. "EW,Warning status." "0,1"
bitfld.long 0x0 23. "EP,Error passive." "0,1"
bitfld.long 0x0 22. "ELO,Error logging overflow." "0,1"
bitfld.long 0x0 21. "BEU,Bit error uncorrected." "0,1"
bitfld.long 0x0 20. "BEC,Bit error corrected." "0,1"
newline
bitfld.long 0x0 19. "DRX,Message stored in dedicated Rx buffer." "0,1"
bitfld.long 0x0 18. "TOO,Timeout occurred." "0,1"
bitfld.long 0x0 17. "MRAF,Message RAM access failure." "0,1"
bitfld.long 0x0 16. "TSW,Timestamp wraparound." "0,1"
bitfld.long 0x0 15. "TEFL,Tx event FIFO element lost." "0,1"
bitfld.long 0x0 14. "TEFF,Tx event FIFO full." "0,1"
bitfld.long 0x0 13. "TEFW,Tx event FIFO watermark reached." "0,1"
bitfld.long 0x0 12. "TEFN,Tx event FIFO new entry." "0,1"
bitfld.long 0x0 11. "TFE,Tx FIFO empty." "0,1"
bitfld.long 0x0 10. "TCF,Transmission cancellation finished." "0,1"
newline
bitfld.long 0x0 9. "TC,Transmission completed." "0,1"
bitfld.long 0x0 8. "HPM,High priority message." "0,1"
bitfld.long 0x0 7. "RF1L,Rx FIFO 1 message lost." "0,1"
bitfld.long 0x0 6. "RF1F,Rx FIFO 1 full." "0,1"
bitfld.long 0x0 5. "RF1W,Rx FIFO 1 watermark reached." "0,1"
bitfld.long 0x0 4. "RF1N,Rx FIFO 1 new message." "0,1"
bitfld.long 0x0 3. "RF0L,Rx FIFO 0 message lost." "0,1"
bitfld.long 0x0 2. "RF0F,Rx FIFO 0 full." "0,1"
bitfld.long 0x0 1. "RF0W,Rx FIFO 0 watermark reached." "0,1"
bitfld.long 0x0 0. "RF0N,Rx FIFO 0 new message." "0,1"
line.long 0x4 "IE,Interrupt Enable"
bitfld.long 0x4 29. "ARAE,Access to reserved address interrupt enable." "0,1"
bitfld.long 0x4 28. "PEDE,Protocol error in data phase interrupt enable." "0,1"
bitfld.long 0x4 27. "PEAE,Protocol error in arbitration phase interrupt enable." "0,1"
bitfld.long 0x4 26. "WDIE,Watchdog interrupt enable." "0,1"
bitfld.long 0x4 25. "BOE,Bus_Off Status interrupt enable." "0,1"
bitfld.long 0x4 24. "EWE,Warning status interrupt enable." "0,1"
bitfld.long 0x4 23. "EPE,Error passive interrupt enable." "0,1"
bitfld.long 0x4 22. "ELOE,Error logging overflow interrupt enable." "0,1"
bitfld.long 0x4 21. "BEUE,Bit error uncorrected interrupt enable." "0,1"
bitfld.long 0x4 20. "BECE,Bit error corrected interrupt enable." "0,1"
newline
bitfld.long 0x4 19. "DRXE,Message stored in dedicated Rx buffer interrupt enable." "0,1"
bitfld.long 0x4 18. "TOOE,Timeout occurred interrupt enable." "0,1"
bitfld.long 0x4 17. "MRAFE,Message RAM access failure interrupt enable." "0,1"
bitfld.long 0x4 16. "TSWE,Timestamp wraparound interrupt enable." "0,1"
bitfld.long 0x4 15. "TEFLE,Tx event FIFO element lost interrupt enable." "0,1"
bitfld.long 0x4 14. "TEFFE,Tx event FIFO full interrupt enable." "0,1"
bitfld.long 0x4 13. "TEFWE,Tx event FIFO watermark reached interrupt enable." "0,1"
bitfld.long 0x4 12. "TEFNE,Tx event FIFO new entry interrupt enable." "0,1"
bitfld.long 0x4 11. "TFEE,Tx FIFO empty interrupt enable." "0,1"
bitfld.long 0x4 10. "TCFE,Transmission cancellation finished interrupt enable." "0,1"
newline
bitfld.long 0x4 9. "TCE,Transmission completed interrupt enable." "0,1"
bitfld.long 0x4 8. "HPME,High priority message interrupt enable." "0,1"
bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 message lost interrupt enable." "0,1"
bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 full interrupt enable." "0,1"
bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 watermark reached interrupt enable." "0,1"
bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 new message interrupt enable." "0,1"
bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 message lost interrupt enable." "0,1"
bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 full interrupt enable." "0,1"
bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 watermark reached interrupt enable." "0,1"
bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 new message interrupt enable." "0,1"
line.long 0x8 "ILS,Interrupt Line Select"
bitfld.long 0x8 29. "ARAL,Access to reserved address interrupt line." "0,1"
bitfld.long 0x8 28. "PEDL,Protocol error in data phase interrupt line." "0,1"
bitfld.long 0x8 27. "PEAL,Protocol error in arbitration phase interrupt line." "0,1"
bitfld.long 0x8 26. "WDIL,Watchdog interrupt line." "0,1"
bitfld.long 0x8 25. "BOL,Bus_Off Status interrupt line." "0,1"
bitfld.long 0x8 24. "EWL,Warning status interrupt line." "0,1"
bitfld.long 0x8 23. "EPL,Error passive interrupt line." "0,1"
bitfld.long 0x8 22. "ELOL,Error logging overflow interrupt line." "0,1"
bitfld.long 0x8 21. "BEUL,Bit error uncorrected interrupt line." "0,1"
bitfld.long 0x8 20. "BECL,Bit error corrected interrupt line." "0,1"
newline
bitfld.long 0x8 19. "DRXL,Message stored in dedicated Rx buffer interrupt line." "0,1"
bitfld.long 0x8 18. "TOOL,Timeout occurred interrupt line." "0,1"
bitfld.long 0x8 17. "MRAFL,Message RAM access failure interrupt line." "0,1"
bitfld.long 0x8 16. "TSWL,Timestamp wraparound interrupt line." "0,1"
bitfld.long 0x8 15. "TEFLL,Tx event FIFO element lost interrupt line." "0,1"
bitfld.long 0x8 14. "TEFFL,Tx event FIFO full interrupt line." "0,1"
bitfld.long 0x8 13. "TEFWL,Tx event FIFO watermark reached interrupt line." "0,1"
bitfld.long 0x8 12. "TEFNL,Tx event FIFO new entry interrupt line." "0,1"
bitfld.long 0x8 11. "TFEL,Tx FIFO empty interrupt line." "0,1"
bitfld.long 0x8 10. "TCFL,Transmission cancellation finished interrupt line." "0,1"
newline
bitfld.long 0x8 9. "TCL,Transmission completed interrupt line." "0,1"
bitfld.long 0x8 8. "HPML,High priority message interrupt line." "0,1"
bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 message lost interrupt line." "0,1"
bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 full interrupt line." "0,1"
bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 watermark reached interrupt line." "0,1"
bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 new message interrupt line." "0,1"
bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 message lost interrupt line." "0,1"
bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 full interrupt line." "0,1"
bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 watermark reached interrupt line." "0,1"
bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 new message interrupt line." "0,1"
line.long 0xC "ILE,Interrupt Line Enable"
bitfld.long 0xC 1. "EINT1,Enable interrupt line 1." "0,1"
bitfld.long 0xC 0. "EINT0,Enable interrupt line 0." "0,1"
group.long 0x80++0xB
line.long 0x0 "GFC,Global Filter Configuration"
bitfld.long 0x0 4.--5. "ANFS,Accept non-matching frames standard." "0,1,2,3"
bitfld.long 0x0 2.--3. "ANFE,Accept non-matching frames extended." "0,1,2,3"
bitfld.long 0x0 1. "RRFS,Reject remote frames standard." "0,1"
bitfld.long 0x0 0. "RRFE,Reject remote frames extended." "0,1"
line.long 0x4 "SIDFC,Standard ID Filter Configuration"
hexmask.long.byte 0x4 16.--23. 1. "LSS,List size standard 0 = No standard message ID filter."
hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter list standard start address."
line.long 0x8 "XIDFC,Extended ID Filter Configuration"
hexmask.long.byte 0x8 16.--23. 1. "LSE,List size extended 0 = No extended message ID filter."
hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter list extended start address."
group.long 0x90++0x3
line.long 0x0 "XIDAM,Extended ID AND Mask"
hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID mask."
rgroup.long 0x94++0x3
line.long 0x0 "HPMS,High Priority Message Status"
bitfld.long 0x0 15. "FLST,Filter list." "0,1"
hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter index."
bitfld.long 0x0 6.--7. "MSI,Message storage indicator." "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer index."
group.long 0x98++0x1B
line.long 0x0 "NDAT1,New Data 1"
hexmask.long 0x0 0.--31. 1. "ND,New Data."
line.long 0x4 "NDAT2,New Data 2"
hexmask.long 0x4 0.--31. 1. "ND,New Data."
line.long 0x8 "RXF0C,Rx FIFO 0 Configuration"
bitfld.long 0x8 31. "F0OM,FIFO 0 operation mode." "0,1"
hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 watermark 0 = Watermark interrupt disabled."
hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 size."
hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 start address."
line.long 0xC "RXF0S,Rx FIFO 0 Status"
bitfld.long 0xC 25. "RF0L,Rx FIFO 0 message lost." "0,1"
bitfld.long 0xC 24. "F0F,Rx FIFO 0 full." "0,1"
hexmask.long.byte 0xC 16.--21. 1. "F0PI,Rx FIFO 0 put index."
hexmask.long.byte 0xC 8.--13. 1. "F0GI,Rx FIFO 0 get index."
hexmask.long.byte 0xC 0.--6. 1. "F0FL,Rx FIFO 0 fill level."
line.long 0x10 "RXF0A,Rx FIFO 0 Acknowledge"
hexmask.long.byte 0x10 0.--5. 1. "F0AI,Rx FIFO 0 acknowledge index."
line.long 0x14 "RXBC,Rx Buffer Configuration"
hexmask.long.word 0x14 2.--15. 1. "RBSA,Rx buffer start address."
line.long 0x18 "RXF1C,Rx FIFO 1 Configuration"
bitfld.long 0x18 31. "F1OM,FIFO 1 operation mode." "0,1"
hexmask.long.byte 0x18 24.--30. 1. "F1WM,Rx FIFO 1 watermark 0 = Watermark interrupt disabled."
hexmask.long.byte 0x18 16.--22. 1. "F1S,Rx FIFO 1 size 0 = No Rx FIFO 1."
hexmask.long.word 0x18 2.--15. 1. "F1SA,Rx FIFO 1 start address."
rgroup.long 0xB4++0x3
line.long 0x0 "RXF1S,Rx FIFO 1 Status"
bitfld.long 0x0 25. "RF1L,Rx FIFO 1 message lost." "0,1"
bitfld.long 0x0 24. "F1F,Rx FIFO 1 full." "0,1"
hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 put index."
hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 get index."
hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 fill level."
group.long 0xB8++0x2F
line.long 0x0 "RXF1A,Rx FIFO 1 Acknowledge"
hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 acknowledge index."
line.long 0x4 "RXESC,Rx Buffer and FIFO Element Size Configuration"
bitfld.long 0x4 8.--10. "RBDS,." "0,1,2,3,4,5,6,7"
bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 data field size." "0,1,2,3,4,5,6,7"
bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 data field size." "0,1,2,3,4,5,6,7"
line.long 0x8 "TXBC,Tx Buffer Configuration"
bitfld.long 0x8 30. "TFQM,Tx FIFO/queue mode." "0,1"
hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/queue size 0 = No tx FIFO/Queue."
hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of dedicated transmit buffers 0 = No dedicated Tx buffers."
hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx buffers start address."
line.long 0xC "TXFQS,Tx FIFO/Queue Status"
bitfld.long 0xC 21. "TFQF,Tx FIFO/queue full." "0,1"
hexmask.long.byte 0xC 16.--20. 1. "TFQPI,Tx FIFO/queue put index."
hexmask.long.byte 0xC 8.--12. 1. "TFGI,Tx FIFO get index."
line.long 0x10 "TXESC,Tx Buffer Element Size Configuration"
bitfld.long 0x10 0.--2. "TBDS,Tx buffer data field size." "0,1,2,3,4,5,6,7"
line.long 0x14 "TXBRP,Tx Buffer Request Pending"
hexmask.long 0x14 0.--31. 1. "TRP,Transmission request pending."
line.long 0x18 "TXBAR,Tx Buffer Add Request"
hexmask.long 0x18 0.--31. 1. "AR,Add request."
line.long 0x1C "TXBCR,Tx Buffer Cancellation Request"
hexmask.long 0x1C 0.--31. 1. "CR,Cancellation request."
line.long 0x20 "TXBTO,Tx Buffer Transmission Occurred"
hexmask.long 0x20 0.--31. 1. "TO,Transmission occurred."
line.long 0x24 "TXBCF,Tx Buffer Cancellation Finished"
hexmask.long 0x24 0.--31. 1. "TO,Cancellation finished."
line.long 0x28 "TXBTIE,Tx Buffer Transmission Interrupt Enable"
hexmask.long 0x28 0.--31. 1. "TIE,Transmission interrupt enable."
line.long 0x2C "TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable"
hexmask.long 0x2C 0.--31. 1. "CFIE,Cancellation finished interrupt enable."
group.long 0xF0++0x3
line.long 0x0 "TXEFC,Tx Event FIFO Configuration"
hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO watermark 0 = Watermark interrupt disabled."
hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO size 0 = Tx event FIFO disabled."
hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO start address."
rgroup.long 0xF4++0x3
line.long 0x0 "TXEFS,Tx Event FIFO Status"
bitfld.long 0x0 25. "TEFL,Tx event FIFO element lost." "0,1"
bitfld.long 0x0 24. "EFF,Event FIFO full." "0,1"
hexmask.long.byte 0x0 16.--21. 1. "EFPI,Event FIFO put index."
hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO get index."
hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO fill level."
group.long 0xF8++0x3
line.long 0x0 "TXEFA,Tx Event FIFO Acknowledge"
hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO acknowledge index."
group.long 0x200++0x3
line.long 0x0 "MRBA,CAN Message RAM Base Address"
hexmask.long.word 0x0 16.--31. 1. "BA,Base address for the message RAM in the chip memory map."
group.long 0x400++0x3
line.long 0x0 "ETSCC,External Timestamp Counter Configuration"
bitfld.long 0x0 31. "ETCE,External timestamp counter enable." "0,1"
hexmask.long.word 0x0 0.--10. 1. "ETCP,External timestamp prescaler value."
group.long 0x600++0x3
line.long 0x0 "ETSCV,External Timestamp Counter Value"
hexmask.long.word 0x0 0.--15. 1. "ETSC,External timestamp counter."
tree.end
endif
tree.end
endif
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54113*")||cpuis("LPC54114*")||cpuis("LPC54605*")||cpuis("LPC54606*")||cpuis("LPC54607*")||cpuis("LPC54608*")||cpuis("LPC54616*")||cpuis("LPC54618*")||cpuis("LPC54628*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
base ad:0x40095000
elif (cpuis("LPC54101*")||cpuis("LPC54102*"))
base ad:0x1C010000
endif
tree "CRC (CRC Engine)"
group.long 0x0++0x7
line.long 0x0 "MODE,CRC mode register"
bitfld.long 0x0 5. "CMPL_SUM,CRC sum complement: 1 = 1's complement for CRC_SUM 0 = No 1's complement for CRC_SUM" "0: No 1's complement for CRC_SUM,1: 1's complement for CRC_SUM"
bitfld.long 0x0 4. "BIT_RVS_SUM,CRC sum bit order: 1 = Bit order reverse for CRC_SUM 0 = No bit order reverse for CRC_SUM" "0: No bit order reverse for CRC_SUM,1: Bit order reverse for CRC_SUM"
newline
bitfld.long 0x0 3. "CMPL_WR,Data complement: 1 = 1's complement for CRC_WR_DATA 0 = No 1's complement for CRC_WR_DATA" "0: No 1's complement for CRC_WR_DATA,1: 1's complement for CRC_WR_DATA"
bitfld.long 0x0 2. "BIT_RVS_WR,Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for CRC_WR_DATA (per byte)" "0: No bit order reverse for CRC_WR_DATA,1: Bit order reverse for CRC_WR_DATA"
newline
bitfld.long 0x0 0.--1. "CRC_POLY,CRC polynomial: 1X = CRC-32 polynomial 01 = CRC-16 polynomial 00 = CRC-CCITT polynomial" "0: CRC-CCITT polynomial,1: CRC-16 polynomial,?,?"
line.long 0x4 "SEED,CRC seed register"
hexmask.long 0x4 0.--31. 1. "CRC_SEED,A write access to this register will load CRC seed value to CRC_SUM register with selected bit order and 1's complement pre-processes. A write access to this register will overrule the CRC calculation in progresses."
rgroup.long 0x8++0x3
line.long 0x0 "SUM,CRC checksum register"
hexmask.long 0x0 0.--31. 1. "CRC_SUM,The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes."
wgroup.long 0x8++0x3
line.long 0x0 "WR_DATA,CRC data register"
hexmask.long 0x0 0.--31. 1. "CRC_WR_DATA,Data written to this register will be taken to perform CRC calculation with selected bit order and 1's complement pre-process. Any write size 8  16 or 32-bit are allowed and accept back-to-back transactions."
tree.end
tree "CTIMER (Standard Counter/Timers)"
base ad:0x0
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
base ad:0x40008000
elif (cpuis("LPC54101*"))
base ad:0x400B4000
endif
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54101*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
tree "CTIMER0"
group.long 0x0++0x17
line.long 0x0 "IR,Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending."
bitfld.long 0x0 7. "CR3INT,Interrupt flag for capture channel 3 event." "0,1"
bitfld.long 0x0 6. "CR2INT,Interrupt flag for capture channel 2 event." "0,1"
newline
bitfld.long 0x0 5. "CR1INT,Interrupt flag for capture channel 1 event." "0,1"
bitfld.long 0x0 4. "CR0INT,Interrupt flag for capture channel 0 event." "0,1"
newline
bitfld.long 0x0 3. "MR3INT,Interrupt flag for match channel 3." "0,1"
bitfld.long 0x0 2. "MR2INT,Interrupt flag for match channel 2." "0,1"
newline
bitfld.long 0x0 1. "MR1INT,Interrupt flag for match channel 1." "0,1"
bitfld.long 0x0 0. "MR0INT,Interrupt flag for match channel 0." "0,1"
line.long 0x4 "TCR,Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."
bitfld.long 0x4 1. "CRST,Counter reset." "0: Disabled. Do nothing.,1: Enabled. The Timer Counter and the Prescale.."
bitfld.long 0x4 0. "CEN,Counter enable." "0: Disabled.The counters are disabled.,1: Enabled. The Timer Counter and Prescale Counter.."
line.long 0x8 "TC,Timer Counter"
hexmask.long 0x8 0.--31. 1. "TCVAL,Timer counter value."
line.long 0xC "PR,Prescale Register"
hexmask.long 0xC 0.--31. 1. "PRVAL,Prescale counter value."
line.long 0x10 "PC,Prescale Counter"
hexmask.long 0x10 0.--31. 1. "PCVAL,Prescale counter value."
line.long 0x14 "MCR,Match Control Register"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x14 27. "MR3RL,Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 26. "MR2RL,Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 25. "MR1RL,Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 24. "MR0RL,Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
endif
bitfld.long 0x14 11. "MR3S,Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." "0,1"
bitfld.long 0x14 10. "MR3R,Reset on MR3: the TC will be reset if MR3 matches it." "0,1"
newline
bitfld.long 0x14 9. "MR3I,Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC." "0,1"
bitfld.long 0x14 8. "MR2S,Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC." "0,1"
newline
bitfld.long 0x14 7. "MR2R,Reset on MR2: the TC will be reset if MR2 matches it." "0,1"
bitfld.long 0x14 6. "MR2I,Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC." "0,1"
newline
bitfld.long 0x14 5. "MR1S,Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." "0,1"
bitfld.long 0x14 4. "MR1R,Reset on MR1: the TC will be reset if MR1 matches it." "0,1"
newline
bitfld.long 0x14 3. "MR1I,Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC." "0,1"
bitfld.long 0x14 2. "MR0S,Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." "0,1"
newline
bitfld.long 0x14 1. "MR0R,Reset on MR0: the TC will be reset if MR0 matches it." "0,1"
bitfld.long 0x14 0. "MR0I,Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC." "0,1"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x18)++0x3
line.long 0x0 "MR[$1],Match Register . MR can be enabled through the MCR to reset the TC. stop both the TC and PC. and/or generate an interrupt every time MR matches the TC."
hexmask.long 0x0 0.--31. 1. "MATCH,Timer counter match value."
repeat.end
group.long 0x28++0x3
line.long 0x0 "CCR,Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."
bitfld.long 0x0 11. "CAP3I,Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt." "0,1"
bitfld.long 0x0 10. "CAP3FE,Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 9. "CAP3RE,Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 8. "CAP2I,Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 7. "CAP2FE,Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 6. "CAP2RE,Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 5. "CAP1I,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt." "0,1"
bitfld.long 0x0 4. "CAP1FE,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 3. "CAP1RE,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 2. "CAP0I,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 1. "CAP0FE,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 0. "CAP0RE,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x2C)++0x3
line.long 0x0 "CR[$1],Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input."
hexmask.long 0x0 0.--31. 1. "CAP,Timer counter capture value."
repeat.end
group.long 0x3C++0x3
line.long 0x0 "EMR,External Match Register. The EMR controls the match function and the external match pins."
bitfld.long 0x0 10.--11. "EMC3,External Match Control 3. Determines the functionality of External Match 3." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 8.--9. "EMC2,External Match Control 2. Determines the functionality of External Match 2." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 6.--7. "EMC1,External Match Control 1. Determines the functionality of External Match 1." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 4.--5. "EMC0,External Match Control 0. Determines the functionality of External Match 0." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 3. "EM3,External Match 3. This bit reflects the state of output MAT3  whether or not this output is connected to a pin. When a match occurs between the TC and MR3  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by MR[11:10]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 2. "EM2,External Match 2. This bit reflects the state of output MAT2  whether or not this output is connected to a pin. When a match occurs between the TC and MR2  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[9:8]. This bit.." "0: LOW,1: HIGH"
newline
bitfld.long 0x0 1. "EM1,External Match 1. This bit reflects the state of output MAT1  whether or not this output is connected to a pin. When a match occurs between the TC and MR1  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[7:6]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 0. "EM0,External Match 0. This bit reflects the state of output MAT0  whether or not this output is connected to a pin. When a match occurs between the TC and MR0  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[5:4]. This bit.." "0: LOW,1: HIGH"
group.long 0x70++0x7
line.long 0x0 "CTCR,Count Control Register. The CTCR selects between Timer and Counter mode. and in Counter mode selects the signal and edge(s) for counting."
bitfld.long 0x0 5.--7. "SELCC,Edge select. When bit 4 is 1  these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved." "0: Channel 0 Rising Edge. Rising edge of the signal..,1: Channel 0 Falling Edge. Falling edge of the..,2: Channel 1 Rising Edge. Rising edge of the signal..,3: Channel 1 Falling Edge. Falling edge of the..,4: Channel 2 Rising Edge. Rising edge of the signal..,5: Channel 2 Falling Edge. Falling edge of the..,?,?"
bitfld.long 0x0 4. "ENCC,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." "0,1"
newline
bitfld.long 0x0 2.--3. "CINSEL,Count Input Select When bits 1:0 in this register are not 00  these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR  the 3 bits for that input in the Capture Control.." "0: Channel 0. CAPn.0 for CTIMERn,1: 0 in this register are not 00,2: Channel 2. CAPn.2 for CTIMERn,3: Channel 3. CAPn.3 for CTIMERn"
bitfld.long 0x0 0.--1. "CTMODE,Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC)  or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale.." "0: Timer Mode. Incremented every rising APB bus..,1: Counter Mode rising edge. TC is incremented on..,2: Counter Mode falling edge. TC is incremented on..,3: Counter Mode dual edge. TC is incremented on.."
line.long 0x4 "PWMC,PWM Control Register. The PWMCON enables PWM mode for the external match pins."
bitfld.long 0x4 3. "PWMEN3,PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle." "0: Match. CTIMERn_MAT3 is controlled by EM3.,1: PWM. PWM mode is enabled for CT132Bn_MAT3."
bitfld.long 0x4 2. "PWMEN2,PWM mode enable for channel2." "0: Match. CTIMERn_MAT2 is controlled by EM2.,1: PWM. PWM mode is enabled for CTIMERn_MAT2."
newline
bitfld.long 0x4 1. "PWMEN1,PWM mode enable for channel1." "0: Match. CTIMERn_MAT01 is controlled by EM1.,1: PWM. PWM mode is enabled for CTIMERn_MAT1."
bitfld.long 0x4 0. "PWMEN0,PWM mode enable for channel0." "0: Match. CTIMERn_MAT0 is controlled by EM0.,1: PWM. PWM mode is enabled for CTIMERn_MAT0."
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x78)++0x3
line.long 0x0 "MSR[$1],Match Shadow Register"
hexmask.long 0x0 0.--31. 1. "SHADOWW,Timer counter match shadow value."
repeat.end
endif
tree.end
endif
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
base ad:0x40009000
elif (cpuis("LPC54101*"))
base ad:0x400B8000
endif
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54101*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
tree "CTIMER1"
group.long 0x0++0x17
line.long 0x0 "IR,Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending."
bitfld.long 0x0 7. "CR3INT,Interrupt flag for capture channel 3 event." "0,1"
bitfld.long 0x0 6. "CR2INT,Interrupt flag for capture channel 2 event." "0,1"
newline
bitfld.long 0x0 5. "CR1INT,Interrupt flag for capture channel 1 event." "0,1"
bitfld.long 0x0 4. "CR0INT,Interrupt flag for capture channel 0 event." "0,1"
newline
bitfld.long 0x0 3. "MR3INT,Interrupt flag for match channel 3." "0,1"
bitfld.long 0x0 2. "MR2INT,Interrupt flag for match channel 2." "0,1"
newline
bitfld.long 0x0 1. "MR1INT,Interrupt flag for match channel 1." "0,1"
bitfld.long 0x0 0. "MR0INT,Interrupt flag for match channel 0." "0,1"
line.long 0x4 "TCR,Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."
bitfld.long 0x4 1. "CRST,Counter reset." "0: Disabled. Do nothing.,1: Enabled. The Timer Counter and the Prescale.."
bitfld.long 0x4 0. "CEN,Counter enable." "0: Disabled.The counters are disabled.,1: Enabled. The Timer Counter and Prescale Counter.."
line.long 0x8 "TC,Timer Counter"
hexmask.long 0x8 0.--31. 1. "TCVAL,Timer counter value."
line.long 0xC "PR,Prescale Register"
hexmask.long 0xC 0.--31. 1. "PRVAL,Prescale counter value."
line.long 0x10 "PC,Prescale Counter"
hexmask.long 0x10 0.--31. 1. "PCVAL,Prescale counter value."
line.long 0x14 "MCR,Match Control Register"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x14 27. "MR3RL,Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 26. "MR2RL,Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 25. "MR1RL,Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 24. "MR0RL,Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
endif
bitfld.long 0x14 11. "MR3S,Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." "0,1"
bitfld.long 0x14 10. "MR3R,Reset on MR3: the TC will be reset if MR3 matches it." "0,1"
newline
bitfld.long 0x14 9. "MR3I,Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC." "0,1"
bitfld.long 0x14 8. "MR2S,Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC." "0,1"
newline
bitfld.long 0x14 7. "MR2R,Reset on MR2: the TC will be reset if MR2 matches it." "0,1"
bitfld.long 0x14 6. "MR2I,Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC." "0,1"
newline
bitfld.long 0x14 5. "MR1S,Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." "0,1"
bitfld.long 0x14 4. "MR1R,Reset on MR1: the TC will be reset if MR1 matches it." "0,1"
newline
bitfld.long 0x14 3. "MR1I,Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC." "0,1"
bitfld.long 0x14 2. "MR0S,Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." "0,1"
newline
bitfld.long 0x14 1. "MR0R,Reset on MR0: the TC will be reset if MR0 matches it." "0,1"
bitfld.long 0x14 0. "MR0I,Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC." "0,1"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x18)++0x3
line.long 0x0 "MR[$1],Match Register . MR can be enabled through the MCR to reset the TC. stop both the TC and PC. and/or generate an interrupt every time MR matches the TC."
hexmask.long 0x0 0.--31. 1. "MATCH,Timer counter match value."
repeat.end
group.long 0x28++0x3
line.long 0x0 "CCR,Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."
bitfld.long 0x0 11. "CAP3I,Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt." "0,1"
bitfld.long 0x0 10. "CAP3FE,Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 9. "CAP3RE,Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 8. "CAP2I,Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 7. "CAP2FE,Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 6. "CAP2RE,Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 5. "CAP1I,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt." "0,1"
bitfld.long 0x0 4. "CAP1FE,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 3. "CAP1RE,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 2. "CAP0I,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 1. "CAP0FE,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 0. "CAP0RE,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x2C)++0x3
line.long 0x0 "CR[$1],Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input."
hexmask.long 0x0 0.--31. 1. "CAP,Timer counter capture value."
repeat.end
group.long 0x3C++0x3
line.long 0x0 "EMR,External Match Register. The EMR controls the match function and the external match pins."
bitfld.long 0x0 10.--11. "EMC3,External Match Control 3. Determines the functionality of External Match 3." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 8.--9. "EMC2,External Match Control 2. Determines the functionality of External Match 2." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 6.--7. "EMC1,External Match Control 1. Determines the functionality of External Match 1." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 4.--5. "EMC0,External Match Control 0. Determines the functionality of External Match 0." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 3. "EM3,External Match 3. This bit reflects the state of output MAT3  whether or not this output is connected to a pin. When a match occurs between the TC and MR3  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by MR[11:10]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 2. "EM2,External Match 2. This bit reflects the state of output MAT2  whether or not this output is connected to a pin. When a match occurs between the TC and MR2  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[9:8]. This bit.." "0: LOW,1: HIGH"
newline
bitfld.long 0x0 1. "EM1,External Match 1. This bit reflects the state of output MAT1  whether or not this output is connected to a pin. When a match occurs between the TC and MR1  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[7:6]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 0. "EM0,External Match 0. This bit reflects the state of output MAT0  whether or not this output is connected to a pin. When a match occurs between the TC and MR0  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[5:4]. This bit.." "0: LOW,1: HIGH"
group.long 0x70++0x7
line.long 0x0 "CTCR,Count Control Register. The CTCR selects between Timer and Counter mode. and in Counter mode selects the signal and edge(s) for counting."
bitfld.long 0x0 5.--7. "SELCC,Edge select. When bit 4 is 1  these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved." "0: Channel 0 Rising Edge. Rising edge of the signal..,1: Channel 0 Falling Edge. Falling edge of the..,2: Channel 1 Rising Edge. Rising edge of the signal..,3: Channel 1 Falling Edge. Falling edge of the..,4: Channel 2 Rising Edge. Rising edge of the signal..,5: Channel 2 Falling Edge. Falling edge of the..,?,?"
bitfld.long 0x0 4. "ENCC,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." "0,1"
newline
bitfld.long 0x0 2.--3. "CINSEL,Count Input Select When bits 1:0 in this register are not 00  these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR  the 3 bits for that input in the Capture Control.." "0: Channel 0. CAPn.0 for CTIMERn,1: 0 in this register are not 00,2: Channel 2. CAPn.2 for CTIMERn,3: Channel 3. CAPn.3 for CTIMERn"
bitfld.long 0x0 0.--1. "CTMODE,Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC)  or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale.." "0: Timer Mode. Incremented every rising APB bus..,1: Counter Mode rising edge. TC is incremented on..,2: Counter Mode falling edge. TC is incremented on..,3: Counter Mode dual edge. TC is incremented on.."
line.long 0x4 "PWMC,PWM Control Register. The PWMCON enables PWM mode for the external match pins."
bitfld.long 0x4 3. "PWMEN3,PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle." "0: Match. CTIMERn_MAT3 is controlled by EM3.,1: PWM. PWM mode is enabled for CT132Bn_MAT3."
bitfld.long 0x4 2. "PWMEN2,PWM mode enable for channel2." "0: Match. CTIMERn_MAT2 is controlled by EM2.,1: PWM. PWM mode is enabled for CTIMERn_MAT2."
newline
bitfld.long 0x4 1. "PWMEN1,PWM mode enable for channel1." "0: Match. CTIMERn_MAT01 is controlled by EM1.,1: PWM. PWM mode is enabled for CTIMERn_MAT1."
bitfld.long 0x4 0. "PWMEN0,PWM mode enable for channel0." "0: Match. CTIMERn_MAT0 is controlled by EM0.,1: PWM. PWM mode is enabled for CTIMERn_MAT0."
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x78)++0x3
line.long 0x0 "MSR[$1],Match Shadow Register"
hexmask.long 0x0 0.--31. 1. "SHADOWW,Timer counter match shadow value."
repeat.end
endif
tree.end
endif
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
base ad:0x40028000
elif (cpuis("LPC54101*"))
base ad:0x40004000
endif
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54101*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
tree "CTIMER2"
group.long 0x0++0x17
line.long 0x0 "IR,Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending."
bitfld.long 0x0 7. "CR3INT,Interrupt flag for capture channel 3 event." "0,1"
bitfld.long 0x0 6. "CR2INT,Interrupt flag for capture channel 2 event." "0,1"
newline
bitfld.long 0x0 5. "CR1INT,Interrupt flag for capture channel 1 event." "0,1"
bitfld.long 0x0 4. "CR0INT,Interrupt flag for capture channel 0 event." "0,1"
newline
bitfld.long 0x0 3. "MR3INT,Interrupt flag for match channel 3." "0,1"
bitfld.long 0x0 2. "MR2INT,Interrupt flag for match channel 2." "0,1"
newline
bitfld.long 0x0 1. "MR1INT,Interrupt flag for match channel 1." "0,1"
bitfld.long 0x0 0. "MR0INT,Interrupt flag for match channel 0." "0,1"
line.long 0x4 "TCR,Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."
bitfld.long 0x4 1. "CRST,Counter reset." "0: Disabled. Do nothing.,1: Enabled. The Timer Counter and the Prescale.."
bitfld.long 0x4 0. "CEN,Counter enable." "0: Disabled.The counters are disabled.,1: Enabled. The Timer Counter and Prescale Counter.."
line.long 0x8 "TC,Timer Counter"
hexmask.long 0x8 0.--31. 1. "TCVAL,Timer counter value."
line.long 0xC "PR,Prescale Register"
hexmask.long 0xC 0.--31. 1. "PRVAL,Prescale counter value."
line.long 0x10 "PC,Prescale Counter"
hexmask.long 0x10 0.--31. 1. "PCVAL,Prescale counter value."
line.long 0x14 "MCR,Match Control Register"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x14 27. "MR3RL,Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 26. "MR2RL,Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 25. "MR1RL,Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 24. "MR0RL,Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
endif
bitfld.long 0x14 11. "MR3S,Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." "0,1"
bitfld.long 0x14 10. "MR3R,Reset on MR3: the TC will be reset if MR3 matches it." "0,1"
newline
bitfld.long 0x14 9. "MR3I,Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC." "0,1"
bitfld.long 0x14 8. "MR2S,Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC." "0,1"
newline
bitfld.long 0x14 7. "MR2R,Reset on MR2: the TC will be reset if MR2 matches it." "0,1"
bitfld.long 0x14 6. "MR2I,Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC." "0,1"
newline
bitfld.long 0x14 5. "MR1S,Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." "0,1"
bitfld.long 0x14 4. "MR1R,Reset on MR1: the TC will be reset if MR1 matches it." "0,1"
newline
bitfld.long 0x14 3. "MR1I,Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC." "0,1"
bitfld.long 0x14 2. "MR0S,Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." "0,1"
newline
bitfld.long 0x14 1. "MR0R,Reset on MR0: the TC will be reset if MR0 matches it." "0,1"
bitfld.long 0x14 0. "MR0I,Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC." "0,1"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x18)++0x3
line.long 0x0 "MR[$1],Match Register . MR can be enabled through the MCR to reset the TC. stop both the TC and PC. and/or generate an interrupt every time MR matches the TC."
hexmask.long 0x0 0.--31. 1. "MATCH,Timer counter match value."
repeat.end
group.long 0x28++0x3
line.long 0x0 "CCR,Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."
bitfld.long 0x0 11. "CAP3I,Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt." "0,1"
bitfld.long 0x0 10. "CAP3FE,Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 9. "CAP3RE,Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 8. "CAP2I,Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 7. "CAP2FE,Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 6. "CAP2RE,Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 5. "CAP1I,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt." "0,1"
bitfld.long 0x0 4. "CAP1FE,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 3. "CAP1RE,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 2. "CAP0I,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 1. "CAP0FE,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 0. "CAP0RE,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x2C)++0x3
line.long 0x0 "CR[$1],Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input."
hexmask.long 0x0 0.--31. 1. "CAP,Timer counter capture value."
repeat.end
group.long 0x3C++0x3
line.long 0x0 "EMR,External Match Register. The EMR controls the match function and the external match pins."
bitfld.long 0x0 10.--11. "EMC3,External Match Control 3. Determines the functionality of External Match 3." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 8.--9. "EMC2,External Match Control 2. Determines the functionality of External Match 2." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 6.--7. "EMC1,External Match Control 1. Determines the functionality of External Match 1." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 4.--5. "EMC0,External Match Control 0. Determines the functionality of External Match 0." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 3. "EM3,External Match 3. This bit reflects the state of output MAT3  whether or not this output is connected to a pin. When a match occurs between the TC and MR3  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by MR[11:10]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 2. "EM2,External Match 2. This bit reflects the state of output MAT2  whether or not this output is connected to a pin. When a match occurs between the TC and MR2  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[9:8]. This bit.." "0: LOW,1: HIGH"
newline
bitfld.long 0x0 1. "EM1,External Match 1. This bit reflects the state of output MAT1  whether or not this output is connected to a pin. When a match occurs between the TC and MR1  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[7:6]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 0. "EM0,External Match 0. This bit reflects the state of output MAT0  whether or not this output is connected to a pin. When a match occurs between the TC and MR0  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[5:4]. This bit.." "0: LOW,1: HIGH"
group.long 0x70++0x7
line.long 0x0 "CTCR,Count Control Register. The CTCR selects between Timer and Counter mode. and in Counter mode selects the signal and edge(s) for counting."
bitfld.long 0x0 5.--7. "SELCC,Edge select. When bit 4 is 1  these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved." "0: Channel 0 Rising Edge. Rising edge of the signal..,1: Channel 0 Falling Edge. Falling edge of the..,2: Channel 1 Rising Edge. Rising edge of the signal..,3: Channel 1 Falling Edge. Falling edge of the..,4: Channel 2 Rising Edge. Rising edge of the signal..,5: Channel 2 Falling Edge. Falling edge of the..,?,?"
bitfld.long 0x0 4. "ENCC,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." "0,1"
newline
bitfld.long 0x0 2.--3. "CINSEL,Count Input Select When bits 1:0 in this register are not 00  these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR  the 3 bits for that input in the Capture Control.." "0: Channel 0. CAPn.0 for CTIMERn,1: 0 in this register are not 00,2: Channel 2. CAPn.2 for CTIMERn,3: Channel 3. CAPn.3 for CTIMERn"
bitfld.long 0x0 0.--1. "CTMODE,Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC)  or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale.." "0: Timer Mode. Incremented every rising APB bus..,1: Counter Mode rising edge. TC is incremented on..,2: Counter Mode falling edge. TC is incremented on..,3: Counter Mode dual edge. TC is incremented on.."
line.long 0x4 "PWMC,PWM Control Register. The PWMCON enables PWM mode for the external match pins."
bitfld.long 0x4 3. "PWMEN3,PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle." "0: Match. CTIMERn_MAT3 is controlled by EM3.,1: PWM. PWM mode is enabled for CT132Bn_MAT3."
bitfld.long 0x4 2. "PWMEN2,PWM mode enable for channel2." "0: Match. CTIMERn_MAT2 is controlled by EM2.,1: PWM. PWM mode is enabled for CTIMERn_MAT2."
newline
bitfld.long 0x4 1. "PWMEN1,PWM mode enable for channel1." "0: Match. CTIMERn_MAT01 is controlled by EM1.,1: PWM. PWM mode is enabled for CTIMERn_MAT1."
bitfld.long 0x4 0. "PWMEN0,PWM mode enable for channel0." "0: Match. CTIMERn_MAT0 is controlled by EM0.,1: PWM. PWM mode is enabled for CTIMERn_MAT0."
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x78)++0x3
line.long 0x0 "MSR[$1],Match Shadow Register"
hexmask.long 0x0 0.--31. 1. "SHADOWW,Timer counter match shadow value."
repeat.end
endif
tree.end
endif
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
base ad:0x40048000
elif (cpuis("LPC54101*"))
base ad:0x40008000
endif
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54101*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
tree "CTIMER3"
group.long 0x0++0x17
line.long 0x0 "IR,Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending."
bitfld.long 0x0 7. "CR3INT,Interrupt flag for capture channel 3 event." "0,1"
bitfld.long 0x0 6. "CR2INT,Interrupt flag for capture channel 2 event." "0,1"
newline
bitfld.long 0x0 5. "CR1INT,Interrupt flag for capture channel 1 event." "0,1"
bitfld.long 0x0 4. "CR0INT,Interrupt flag for capture channel 0 event." "0,1"
newline
bitfld.long 0x0 3. "MR3INT,Interrupt flag for match channel 3." "0,1"
bitfld.long 0x0 2. "MR2INT,Interrupt flag for match channel 2." "0,1"
newline
bitfld.long 0x0 1. "MR1INT,Interrupt flag for match channel 1." "0,1"
bitfld.long 0x0 0. "MR0INT,Interrupt flag for match channel 0." "0,1"
line.long 0x4 "TCR,Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."
bitfld.long 0x4 1. "CRST,Counter reset." "0: Disabled. Do nothing.,1: Enabled. The Timer Counter and the Prescale.."
bitfld.long 0x4 0. "CEN,Counter enable." "0: Disabled.The counters are disabled.,1: Enabled. The Timer Counter and Prescale Counter.."
line.long 0x8 "TC,Timer Counter"
hexmask.long 0x8 0.--31. 1. "TCVAL,Timer counter value."
line.long 0xC "PR,Prescale Register"
hexmask.long 0xC 0.--31. 1. "PRVAL,Prescale counter value."
line.long 0x10 "PC,Prescale Counter"
hexmask.long 0x10 0.--31. 1. "PCVAL,Prescale counter value."
line.long 0x14 "MCR,Match Control Register"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x14 27. "MR3RL,Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 26. "MR2RL,Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 25. "MR1RL,Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 24. "MR0RL,Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
endif
bitfld.long 0x14 11. "MR3S,Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." "0,1"
bitfld.long 0x14 10. "MR3R,Reset on MR3: the TC will be reset if MR3 matches it." "0,1"
newline
bitfld.long 0x14 9. "MR3I,Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC." "0,1"
bitfld.long 0x14 8. "MR2S,Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC." "0,1"
newline
bitfld.long 0x14 7. "MR2R,Reset on MR2: the TC will be reset if MR2 matches it." "0,1"
bitfld.long 0x14 6. "MR2I,Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC." "0,1"
newline
bitfld.long 0x14 5. "MR1S,Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." "0,1"
bitfld.long 0x14 4. "MR1R,Reset on MR1: the TC will be reset if MR1 matches it." "0,1"
newline
bitfld.long 0x14 3. "MR1I,Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC." "0,1"
bitfld.long 0x14 2. "MR0S,Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." "0,1"
newline
bitfld.long 0x14 1. "MR0R,Reset on MR0: the TC will be reset if MR0 matches it." "0,1"
bitfld.long 0x14 0. "MR0I,Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC." "0,1"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x18)++0x3
line.long 0x0 "MR[$1],Match Register . MR can be enabled through the MCR to reset the TC. stop both the TC and PC. and/or generate an interrupt every time MR matches the TC."
hexmask.long 0x0 0.--31. 1. "MATCH,Timer counter match value."
repeat.end
group.long 0x28++0x3
line.long 0x0 "CCR,Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."
bitfld.long 0x0 11. "CAP3I,Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt." "0,1"
bitfld.long 0x0 10. "CAP3FE,Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 9. "CAP3RE,Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 8. "CAP2I,Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 7. "CAP2FE,Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 6. "CAP2RE,Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 5. "CAP1I,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt." "0,1"
bitfld.long 0x0 4. "CAP1FE,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 3. "CAP1RE,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 2. "CAP0I,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 1. "CAP0FE,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 0. "CAP0RE,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x2C)++0x3
line.long 0x0 "CR[$1],Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input."
hexmask.long 0x0 0.--31. 1. "CAP,Timer counter capture value."
repeat.end
group.long 0x3C++0x3
line.long 0x0 "EMR,External Match Register. The EMR controls the match function and the external match pins."
bitfld.long 0x0 10.--11. "EMC3,External Match Control 3. Determines the functionality of External Match 3." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 8.--9. "EMC2,External Match Control 2. Determines the functionality of External Match 2." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 6.--7. "EMC1,External Match Control 1. Determines the functionality of External Match 1." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 4.--5. "EMC0,External Match Control 0. Determines the functionality of External Match 0." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 3. "EM3,External Match 3. This bit reflects the state of output MAT3  whether or not this output is connected to a pin. When a match occurs between the TC and MR3  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by MR[11:10]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 2. "EM2,External Match 2. This bit reflects the state of output MAT2  whether or not this output is connected to a pin. When a match occurs between the TC and MR2  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[9:8]. This bit.." "0: LOW,1: HIGH"
newline
bitfld.long 0x0 1. "EM1,External Match 1. This bit reflects the state of output MAT1  whether or not this output is connected to a pin. When a match occurs between the TC and MR1  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[7:6]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 0. "EM0,External Match 0. This bit reflects the state of output MAT0  whether or not this output is connected to a pin. When a match occurs between the TC and MR0  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[5:4]. This bit.." "0: LOW,1: HIGH"
group.long 0x70++0x7
line.long 0x0 "CTCR,Count Control Register. The CTCR selects between Timer and Counter mode. and in Counter mode selects the signal and edge(s) for counting."
bitfld.long 0x0 5.--7. "SELCC,Edge select. When bit 4 is 1  these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved." "0: Channel 0 Rising Edge. Rising edge of the signal..,1: Channel 0 Falling Edge. Falling edge of the..,2: Channel 1 Rising Edge. Rising edge of the signal..,3: Channel 1 Falling Edge. Falling edge of the..,4: Channel 2 Rising Edge. Rising edge of the signal..,5: Channel 2 Falling Edge. Falling edge of the..,?,?"
bitfld.long 0x0 4. "ENCC,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." "0,1"
newline
bitfld.long 0x0 2.--3. "CINSEL,Count Input Select When bits 1:0 in this register are not 00  these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR  the 3 bits for that input in the Capture Control.." "0: Channel 0. CAPn.0 for CTIMERn,1: 0 in this register are not 00,2: Channel 2. CAPn.2 for CTIMERn,3: Channel 3. CAPn.3 for CTIMERn"
bitfld.long 0x0 0.--1. "CTMODE,Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC)  or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale.." "0: Timer Mode. Incremented every rising APB bus..,1: Counter Mode rising edge. TC is incremented on..,2: Counter Mode falling edge. TC is incremented on..,3: Counter Mode dual edge. TC is incremented on.."
line.long 0x4 "PWMC,PWM Control Register. The PWMCON enables PWM mode for the external match pins."
bitfld.long 0x4 3. "PWMEN3,PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle." "0: Match. CTIMERn_MAT3 is controlled by EM3.,1: PWM. PWM mode is enabled for CT132Bn_MAT3."
bitfld.long 0x4 2. "PWMEN2,PWM mode enable for channel2." "0: Match. CTIMERn_MAT2 is controlled by EM2.,1: PWM. PWM mode is enabled for CTIMERn_MAT2."
newline
bitfld.long 0x4 1. "PWMEN1,PWM mode enable for channel1." "0: Match. CTIMERn_MAT01 is controlled by EM1.,1: PWM. PWM mode is enabled for CTIMERn_MAT1."
bitfld.long 0x4 0. "PWMEN0,PWM mode enable for channel0." "0: Match. CTIMERn_MAT0 is controlled by EM0.,1: PWM. PWM mode is enabled for CTIMERn_MAT0."
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x78)++0x3
line.long 0x0 "MSR[$1],Match Shadow Register"
hexmask.long 0x0 0.--31. 1. "SHADOWW,Timer counter match shadow value."
repeat.end
endif
tree.end
endif
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
base ad:0x40049000
elif (cpuis("LPC54101*"))
base ad:0x4000C000
endif
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54101*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
tree "CTIMER4"
group.long 0x0++0x17
line.long 0x0 "IR,Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending."
bitfld.long 0x0 7. "CR3INT,Interrupt flag for capture channel 3 event." "0,1"
bitfld.long 0x0 6. "CR2INT,Interrupt flag for capture channel 2 event." "0,1"
newline
bitfld.long 0x0 5. "CR1INT,Interrupt flag for capture channel 1 event." "0,1"
bitfld.long 0x0 4. "CR0INT,Interrupt flag for capture channel 0 event." "0,1"
newline
bitfld.long 0x0 3. "MR3INT,Interrupt flag for match channel 3." "0,1"
bitfld.long 0x0 2. "MR2INT,Interrupt flag for match channel 2." "0,1"
newline
bitfld.long 0x0 1. "MR1INT,Interrupt flag for match channel 1." "0,1"
bitfld.long 0x0 0. "MR0INT,Interrupt flag for match channel 0." "0,1"
line.long 0x4 "TCR,Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."
bitfld.long 0x4 1. "CRST,Counter reset." "0: Disabled. Do nothing.,1: Enabled. The Timer Counter and the Prescale.."
bitfld.long 0x4 0. "CEN,Counter enable." "0: Disabled.The counters are disabled.,1: Enabled. The Timer Counter and Prescale Counter.."
line.long 0x8 "TC,Timer Counter"
hexmask.long 0x8 0.--31. 1. "TCVAL,Timer counter value."
line.long 0xC "PR,Prescale Register"
hexmask.long 0xC 0.--31. 1. "PRVAL,Prescale counter value."
line.long 0x10 "PC,Prescale Counter"
hexmask.long 0x10 0.--31. 1. "PCVAL,Prescale counter value."
line.long 0x14 "MCR,Match Control Register"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x14 27. "MR3RL,Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 26. "MR2RL,Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 25. "MR1RL,Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 24. "MR0RL,Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
endif
bitfld.long 0x14 11. "MR3S,Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." "0,1"
bitfld.long 0x14 10. "MR3R,Reset on MR3: the TC will be reset if MR3 matches it." "0,1"
newline
bitfld.long 0x14 9. "MR3I,Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC." "0,1"
bitfld.long 0x14 8. "MR2S,Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC." "0,1"
newline
bitfld.long 0x14 7. "MR2R,Reset on MR2: the TC will be reset if MR2 matches it." "0,1"
bitfld.long 0x14 6. "MR2I,Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC." "0,1"
newline
bitfld.long 0x14 5. "MR1S,Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." "0,1"
bitfld.long 0x14 4. "MR1R,Reset on MR1: the TC will be reset if MR1 matches it." "0,1"
newline
bitfld.long 0x14 3. "MR1I,Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC." "0,1"
bitfld.long 0x14 2. "MR0S,Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." "0,1"
newline
bitfld.long 0x14 1. "MR0R,Reset on MR0: the TC will be reset if MR0 matches it." "0,1"
bitfld.long 0x14 0. "MR0I,Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC." "0,1"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x18)++0x3
line.long 0x0 "MR[$1],Match Register . MR can be enabled through the MCR to reset the TC. stop both the TC and PC. and/or generate an interrupt every time MR matches the TC."
hexmask.long 0x0 0.--31. 1. "MATCH,Timer counter match value."
repeat.end
group.long 0x28++0x3
line.long 0x0 "CCR,Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."
bitfld.long 0x0 11. "CAP3I,Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt." "0,1"
bitfld.long 0x0 10. "CAP3FE,Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 9. "CAP3RE,Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 8. "CAP2I,Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 7. "CAP2FE,Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 6. "CAP2RE,Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 5. "CAP1I,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt." "0,1"
bitfld.long 0x0 4. "CAP1FE,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 3. "CAP1RE,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 2. "CAP0I,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 1. "CAP0FE,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 0. "CAP0RE,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x2C)++0x3
line.long 0x0 "CR[$1],Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input."
hexmask.long 0x0 0.--31. 1. "CAP,Timer counter capture value."
repeat.end
group.long 0x3C++0x3
line.long 0x0 "EMR,External Match Register. The EMR controls the match function and the external match pins."
bitfld.long 0x0 10.--11. "EMC3,External Match Control 3. Determines the functionality of External Match 3." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 8.--9. "EMC2,External Match Control 2. Determines the functionality of External Match 2." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 6.--7. "EMC1,External Match Control 1. Determines the functionality of External Match 1." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 4.--5. "EMC0,External Match Control 0. Determines the functionality of External Match 0." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 3. "EM3,External Match 3. This bit reflects the state of output MAT3  whether or not this output is connected to a pin. When a match occurs between the TC and MR3  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by MR[11:10]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 2. "EM2,External Match 2. This bit reflects the state of output MAT2  whether or not this output is connected to a pin. When a match occurs between the TC and MR2  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[9:8]. This bit.." "0: LOW,1: HIGH"
newline
bitfld.long 0x0 1. "EM1,External Match 1. This bit reflects the state of output MAT1  whether or not this output is connected to a pin. When a match occurs between the TC and MR1  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[7:6]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 0. "EM0,External Match 0. This bit reflects the state of output MAT0  whether or not this output is connected to a pin. When a match occurs between the TC and MR0  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[5:4]. This bit.." "0: LOW,1: HIGH"
group.long 0x70++0x7
line.long 0x0 "CTCR,Count Control Register. The CTCR selects between Timer and Counter mode. and in Counter mode selects the signal and edge(s) for counting."
bitfld.long 0x0 5.--7. "SELCC,Edge select. When bit 4 is 1  these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved." "0: Channel 0 Rising Edge. Rising edge of the signal..,1: Channel 0 Falling Edge. Falling edge of the..,2: Channel 1 Rising Edge. Rising edge of the signal..,3: Channel 1 Falling Edge. Falling edge of the..,4: Channel 2 Rising Edge. Rising edge of the signal..,5: Channel 2 Falling Edge. Falling edge of the..,?,?"
bitfld.long 0x0 4. "ENCC,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." "0,1"
newline
bitfld.long 0x0 2.--3. "CINSEL,Count Input Select When bits 1:0 in this register are not 00  these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR  the 3 bits for that input in the Capture Control.." "0: Channel 0. CAPn.0 for CTIMERn,1: 0 in this register are not 00,2: Channel 2. CAPn.2 for CTIMERn,3: Channel 3. CAPn.3 for CTIMERn"
bitfld.long 0x0 0.--1. "CTMODE,Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC)  or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale.." "0: Timer Mode. Incremented every rising APB bus..,1: Counter Mode rising edge. TC is incremented on..,2: Counter Mode falling edge. TC is incremented on..,3: Counter Mode dual edge. TC is incremented on.."
line.long 0x4 "PWMC,PWM Control Register. The PWMCON enables PWM mode for the external match pins."
bitfld.long 0x4 3. "PWMEN3,PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle." "0: Match. CTIMERn_MAT3 is controlled by EM3.,1: PWM. PWM mode is enabled for CT132Bn_MAT3."
bitfld.long 0x4 2. "PWMEN2,PWM mode enable for channel2." "0: Match. CTIMERn_MAT2 is controlled by EM2.,1: PWM. PWM mode is enabled for CTIMERn_MAT2."
newline
bitfld.long 0x4 1. "PWMEN1,PWM mode enable for channel1." "0: Match. CTIMERn_MAT01 is controlled by EM1.,1: PWM. PWM mode is enabled for CTIMERn_MAT1."
bitfld.long 0x4 0. "PWMEN0,PWM mode enable for channel0." "0: Match. CTIMERn_MAT0 is controlled by EM0.,1: PWM. PWM mode is enabled for CTIMERn_MAT0."
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x78)++0x3
line.long 0x0 "MSR[$1],Match Shadow Register"
hexmask.long 0x0 0.--31. 1. "SHADOWW,Timer counter match shadow value."
repeat.end
endif
tree.end
endif
sif (cpuis("LPC54102*"))
tree "CTIMER0"
base ad:0x400B4000
group.long 0x0++0x17
line.long 0x0 "IR,Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending."
bitfld.long 0x0 7. "CR3INT,Interrupt flag for capture channel 3 event." "0,1"
bitfld.long 0x0 6. "CR2INT,Interrupt flag for capture channel 2 event." "0,1"
newline
bitfld.long 0x0 5. "CR1INT,Interrupt flag for capture channel 1 event." "0,1"
bitfld.long 0x0 4. "CR0INT,Interrupt flag for capture channel 0 event." "0,1"
newline
bitfld.long 0x0 3. "MR3INT,Interrupt flag for match channel 3." "0,1"
bitfld.long 0x0 2. "MR2INT,Interrupt flag for match channel 2." "0,1"
newline
bitfld.long 0x0 1. "MR1INT,Interrupt flag for match channel 1." "0,1"
bitfld.long 0x0 0. "MR0INT,Interrupt flag for match channel 0." "0,1"
line.long 0x4 "TCR,Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."
bitfld.long 0x4 1. "CRST,Counter reset." "0: Disabled. Do nothing.,1: Enabled. The Timer Counter and the Prescale.."
bitfld.long 0x4 0. "CEN,Counter enable." "0: Disabled.The counters are disabled.,1: Enabled. The Timer Counter and Prescale Counter.."
line.long 0x8 "TC,Timer Counter. The 32 bit TC is incremented every PR+1 cycles of the APB bus clock. The TC is controlled through the TCR."
hexmask.long 0x8 0.--31. 1. "TCVAL,Timer counter value."
line.long 0xC "PR,Prescale Register. When the Prescale Counter (PC) is equal to this value. the next clock increments the TC and clears the PC."
hexmask.long 0xC 0.--31. 1. "PRVAL,Prescale counter value."
line.long 0x10 "PC,Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached. the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface."
hexmask.long 0x10 0.--31. 1. "PCVAL,Prescale counter value."
line.long 0x14 "MCR,Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs."
bitfld.long 0x14 11. "MR3S,Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 10. "MR3R,Reset on MR3: the TC will be reset if MR3 matches it. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 9. "MR3I,Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 8. "MR2S,Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 7. "MR2R,Reset on MR2: the TC will be reset if MR2 matches it. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 6. "MR2I,Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 5. "MR1S,Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 4. "MR1R,Reset on MR1: the TC will be reset if MR1 matches it. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 3. "MR1I,Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. 0 = disabled. 1 = enabled. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 2. "MR0S,Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 1. "MR0R,Reset on MR0: the TC will be reset if MR0 matches it. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 0. "MR0I,Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x18)++0x3
line.long 0x0 "MR[$1],Match Register . MR can be enabled through the MCR to reset the TC. stop both the TC and PC. and/or generate an interrupt every time MR matches the TC."
hexmask.long 0x0 0.--31. 1. "MATCH,Timer counter match value."
repeat.end
group.long 0x28++0x3
line.long 0x0 "CCR,Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."
bitfld.long 0x0 11. "CAP3I,Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt." "0,1"
bitfld.long 0x0 10. "CAP3FE,Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 9. "CAP3RE,Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 8. "CAP2I,Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 7. "CAP2FE,Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 6. "CAP2RE,Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 5. "CAP1I,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt." "0,1"
bitfld.long 0x0 4. "CAP1FE,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 3. "CAP1RE,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 2. "CAP0I,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 1. "CAP0FE,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 0. "CAP0RE,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x2C)++0x3
line.long 0x0 "CR[$1],Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input."
hexmask.long 0x0 0.--31. 1. "CAP,Timer counter capture value."
repeat.end
group.long 0x3C++0x3
line.long 0x0 "EMR,External Match Register. The EMR controls the match function and the external match pins."
bitfld.long 0x0 10.--11. "EMC3,External Match Control 3. Determines the functionality of External Match 3." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 8.--9. "EMC2,External Match Control 2. Determines the functionality of External Match 2." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 6.--7. "EMC1,External Match Control 1. Determines the functionality of External Match 1." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 4.--5. "EMC0,External Match Control 0. Determines the functionality of External Match 0." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 3. "EM3,External Match 3. This bit reflects the state of output MAT3  whether or not this output is connected to a pin. When a match occurs between the TC and MR3  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by MR[11:10]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 2. "EM2,External Match 2. This bit reflects the state of output MAT2  whether or not this output is connected to a pin. When a match occurs between the TC and MR2  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[9:8]. This bit.." "0: LOW,1: HIGH"
newline
bitfld.long 0x0 1. "EM1,External Match 1. This bit reflects the state of output MAT1  whether or not this output is connected to a pin. When a match occurs between the TC and MR1  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[7:6]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 0. "EM0,External Match 0. This bit reflects the state of output MAT0  whether or not this output is connected to a pin. When a match occurs between the TC and MR0  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[5:4]. This bit.." "0: LOW,1: HIGH"
group.long 0x70++0x7
line.long 0x0 "CTCR,Count Control Register. The CTCR selects between Timer and Counter mode. and in Counter mode selects the signal and edge(s) for counting."
bitfld.long 0x0 5.--7. "SELCC,Edge select. When bit 4 is 1  these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved." "0: Channel 0 Rising Edge. Rising edge of the signal..,1: Channel 0 Falling Edge. Falling edge of the..,2: Channel 1 Rising Edge. Rising edge of the signal..,3: Channel 1 Falling Edge. Falling edge of the..,4: Channel 2 Rising Edge. Rising edge of the signal..,5: Channel 2 Falling Edge. Falling edge of the..,?,?"
bitfld.long 0x0 4. "ENCC,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." "0,1"
newline
bitfld.long 0x0 2.--3. "CINSEL,Count Input Select When bits 1:0 in this register are not 00  these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR  the 3 bits for that input in the Capture Control.." "0: Channel 0. CAPn.0 for CTIMERn,1: 0 in this register are not 00,2: Channel 2. CAPn.2 for CTIMERn,3: Channel 3. CAPn.3 for CTIMERn"
bitfld.long 0x0 0.--1. "CTMODE,Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC)  or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale.." "0: Timer Mode. Incremented every rising APB bus..,1: Counter Mode rising edge. TC is incremented on..,2: Counter Mode falling edge. TC is incremented on..,3: Counter Mode dual edge. TC is incremented on.."
line.long 0x4 "PWMC,PWM Control Register. The PWMCON enables PWM mode for the external match pins."
bitfld.long 0x4 3. "PWMEN3,PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle." "0: Match. CTIMERn_MAT3 is controlled by EM3.,1: PWM. PWM mode is enabled for CT132Bn_MAT3."
bitfld.long 0x4 2. "PWMEN2,PWM mode enable for channel2." "0: Match. CTIMERn_MAT2 is controlled by EM2.,1: PWM. PWM mode is enabled for CTIMERn_MAT2."
newline
bitfld.long 0x4 1. "PWMEN1,PWM mode enable for channel1." "0: Match. CTIMERn_MAT01 is controlled by EM1.,1: PWM. PWM mode is enabled for CTIMERn_MAT1."
bitfld.long 0x4 0. "PWMEN0,PWM mode enable for channel0." "0: Match. CTIMERn_MAT0 is controlled by EM0.,1: PWM. PWM mode is enabled for CTIMERn_MAT0."
tree.end
endif
sif (cpuis("LPC54102*"))
tree "CTIMER2"
base ad:0x40004000
group.long 0x0++0x17
line.long 0x0 "IR,Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending."
bitfld.long 0x0 7. "CR3INT,Interrupt flag for capture channel 3 event." "0,1"
bitfld.long 0x0 6. "CR2INT,Interrupt flag for capture channel 2 event." "0,1"
newline
bitfld.long 0x0 5. "CR1INT,Interrupt flag for capture channel 1 event." "0,1"
bitfld.long 0x0 4. "CR0INT,Interrupt flag for capture channel 0 event." "0,1"
newline
bitfld.long 0x0 3. "MR3INT,Interrupt flag for match channel 3." "0,1"
bitfld.long 0x0 2. "MR2INT,Interrupt flag for match channel 2." "0,1"
newline
bitfld.long 0x0 1. "MR1INT,Interrupt flag for match channel 1." "0,1"
bitfld.long 0x0 0. "MR0INT,Interrupt flag for match channel 0." "0,1"
line.long 0x4 "TCR,Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."
bitfld.long 0x4 1. "CRST,Counter reset." "0: Disabled. Do nothing.,1: Enabled. The Timer Counter and the Prescale.."
bitfld.long 0x4 0. "CEN,Counter enable." "0: Disabled.The counters are disabled.,1: Enabled. The Timer Counter and Prescale Counter.."
line.long 0x8 "TC,Timer Counter. The 32 bit TC is incremented every PR+1 cycles of the APB bus clock. The TC is controlled through the TCR."
hexmask.long 0x8 0.--31. 1. "TCVAL,Timer counter value."
line.long 0xC "PR,Prescale Register. When the Prescale Counter (PC) is equal to this value. the next clock increments the TC and clears the PC."
hexmask.long 0xC 0.--31. 1. "PRVAL,Prescale counter value."
line.long 0x10 "PC,Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached. the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface."
hexmask.long 0x10 0.--31. 1. "PCVAL,Prescale counter value."
line.long 0x14 "MCR,Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs."
bitfld.long 0x14 11. "MR3S,Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 10. "MR3R,Reset on MR3: the TC will be reset if MR3 matches it. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 9. "MR3I,Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 8. "MR2S,Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 7. "MR2R,Reset on MR2: the TC will be reset if MR2 matches it. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 6. "MR2I,Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 5. "MR1S,Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 4. "MR1R,Reset on MR1: the TC will be reset if MR1 matches it. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 3. "MR1I,Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. 0 = disabled. 1 = enabled. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 2. "MR0S,Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 1. "MR0R,Reset on MR0: the TC will be reset if MR0 matches it. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 0. "MR0I,Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x18)++0x3
line.long 0x0 "MR[$1],Match Register . MR can be enabled through the MCR to reset the TC. stop both the TC and PC. and/or generate an interrupt every time MR matches the TC."
hexmask.long 0x0 0.--31. 1. "MATCH,Timer counter match value."
repeat.end
group.long 0x28++0x3
line.long 0x0 "CCR,Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."
bitfld.long 0x0 11. "CAP3I,Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt." "0,1"
bitfld.long 0x0 10. "CAP3FE,Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 9. "CAP3RE,Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 8. "CAP2I,Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 7. "CAP2FE,Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 6. "CAP2RE,Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 5. "CAP1I,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt." "0,1"
bitfld.long 0x0 4. "CAP1FE,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 3. "CAP1RE,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 2. "CAP0I,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 1. "CAP0FE,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 0. "CAP0RE,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x2C)++0x3
line.long 0x0 "CR[$1],Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input."
hexmask.long 0x0 0.--31. 1. "CAP,Timer counter capture value."
repeat.end
group.long 0x3C++0x3
line.long 0x0 "EMR,External Match Register. The EMR controls the match function and the external match pins."
bitfld.long 0x0 10.--11. "EMC3,External Match Control 3. Determines the functionality of External Match 3." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 8.--9. "EMC2,External Match Control 2. Determines the functionality of External Match 2." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 6.--7. "EMC1,External Match Control 1. Determines the functionality of External Match 1." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 4.--5. "EMC0,External Match Control 0. Determines the functionality of External Match 0." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 3. "EM3,External Match 3. This bit reflects the state of output MAT3  whether or not this output is connected to a pin. When a match occurs between the TC and MR3  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by MR[11:10]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 2. "EM2,External Match 2. This bit reflects the state of output MAT2  whether or not this output is connected to a pin. When a match occurs between the TC and MR2  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[9:8]. This bit.." "0: LOW,1: HIGH"
newline
bitfld.long 0x0 1. "EM1,External Match 1. This bit reflects the state of output MAT1  whether or not this output is connected to a pin. When a match occurs between the TC and MR1  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[7:6]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 0. "EM0,External Match 0. This bit reflects the state of output MAT0  whether or not this output is connected to a pin. When a match occurs between the TC and MR0  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[5:4]. This bit.." "0: LOW,1: HIGH"
group.long 0x70++0x7
line.long 0x0 "CTCR,Count Control Register. The CTCR selects between Timer and Counter mode. and in Counter mode selects the signal and edge(s) for counting."
bitfld.long 0x0 5.--7. "SELCC,Edge select. When bit 4 is 1  these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved." "0: Channel 0 Rising Edge. Rising edge of the signal..,1: Channel 0 Falling Edge. Falling edge of the..,2: Channel 1 Rising Edge. Rising edge of the signal..,3: Channel 1 Falling Edge. Falling edge of the..,4: Channel 2 Rising Edge. Rising edge of the signal..,5: Channel 2 Falling Edge. Falling edge of the..,?,?"
bitfld.long 0x0 4. "ENCC,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." "0,1"
newline
bitfld.long 0x0 2.--3. "CINSEL,Count Input Select When bits 1:0 in this register are not 00  these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR  the 3 bits for that input in the Capture Control.." "0: Channel 0. CAPn.0 for CTIMERn,1: 0 in this register are not 00,2: Channel 2. CAPn.2 for CTIMERn,3: Channel 3. CAPn.3 for CTIMERn"
bitfld.long 0x0 0.--1. "CTMODE,Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC)  or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale.." "0: Timer Mode. Incremented every rising APB bus..,1: Counter Mode rising edge. TC is incremented on..,2: Counter Mode falling edge. TC is incremented on..,3: Counter Mode dual edge. TC is incremented on.."
line.long 0x4 "PWMC,PWM Control Register. The PWMCON enables PWM mode for the external match pins."
bitfld.long 0x4 3. "PWMEN3,PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle." "0: Match. CTIMERn_MAT3 is controlled by EM3.,1: PWM. PWM mode is enabled for CT132Bn_MAT3."
bitfld.long 0x4 2. "PWMEN2,PWM mode enable for channel2." "0: Match. CTIMERn_MAT2 is controlled by EM2.,1: PWM. PWM mode is enabled for CTIMERn_MAT2."
newline
bitfld.long 0x4 1. "PWMEN1,PWM mode enable for channel1." "0: Match. CTIMERn_MAT01 is controlled by EM1.,1: PWM. PWM mode is enabled for CTIMERn_MAT1."
bitfld.long 0x4 0. "PWMEN0,PWM mode enable for channel0." "0: Match. CTIMERn_MAT0 is controlled by EM0.,1: PWM. PWM mode is enabled for CTIMERn_MAT0."
tree.end
tree "CTIMER3"
base ad:0x40008000
group.long 0x0++0x17
line.long 0x0 "IR,Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending."
bitfld.long 0x0 7. "CR3INT,Interrupt flag for capture channel 3 event." "0,1"
bitfld.long 0x0 6. "CR2INT,Interrupt flag for capture channel 2 event." "0,1"
newline
bitfld.long 0x0 5. "CR1INT,Interrupt flag for capture channel 1 event." "0,1"
bitfld.long 0x0 4. "CR0INT,Interrupt flag for capture channel 0 event." "0,1"
newline
bitfld.long 0x0 3. "MR3INT,Interrupt flag for match channel 3." "0,1"
bitfld.long 0x0 2. "MR2INT,Interrupt flag for match channel 2." "0,1"
newline
bitfld.long 0x0 1. "MR1INT,Interrupt flag for match channel 1." "0,1"
bitfld.long 0x0 0. "MR0INT,Interrupt flag for match channel 0." "0,1"
line.long 0x4 "TCR,Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."
bitfld.long 0x4 1. "CRST,Counter reset." "0: Disabled. Do nothing.,1: Enabled. The Timer Counter and the Prescale.."
bitfld.long 0x4 0. "CEN,Counter enable." "0: Disabled.The counters are disabled.,1: Enabled. The Timer Counter and Prescale Counter.."
line.long 0x8 "TC,Timer Counter. The 32 bit TC is incremented every PR+1 cycles of the APB bus clock. The TC is controlled through the TCR."
hexmask.long 0x8 0.--31. 1. "TCVAL,Timer counter value."
line.long 0xC "PR,Prescale Register. When the Prescale Counter (PC) is equal to this value. the next clock increments the TC and clears the PC."
hexmask.long 0xC 0.--31. 1. "PRVAL,Prescale counter value."
line.long 0x10 "PC,Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached. the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface."
hexmask.long 0x10 0.--31. 1. "PCVAL,Prescale counter value."
line.long 0x14 "MCR,Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs."
bitfld.long 0x14 11. "MR3S,Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 10. "MR3R,Reset on MR3: the TC will be reset if MR3 matches it. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 9. "MR3I,Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 8. "MR2S,Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 7. "MR2R,Reset on MR2: the TC will be reset if MR2 matches it. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 6. "MR2I,Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 5. "MR1S,Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 4. "MR1R,Reset on MR1: the TC will be reset if MR1 matches it. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 3. "MR1I,Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. 0 = disabled. 1 = enabled. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 2. "MR0S,Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 1. "MR0R,Reset on MR0: the TC will be reset if MR0 matches it. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 0. "MR0I,Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x18)++0x3
line.long 0x0 "MR[$1],Match Register . MR can be enabled through the MCR to reset the TC. stop both the TC and PC. and/or generate an interrupt every time MR matches the TC."
hexmask.long 0x0 0.--31. 1. "MATCH,Timer counter match value."
repeat.end
group.long 0x28++0x3
line.long 0x0 "CCR,Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."
bitfld.long 0x0 11. "CAP3I,Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt." "0,1"
bitfld.long 0x0 10. "CAP3FE,Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 9. "CAP3RE,Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 8. "CAP2I,Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 7. "CAP2FE,Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 6. "CAP2RE,Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 5. "CAP1I,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt." "0,1"
bitfld.long 0x0 4. "CAP1FE,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 3. "CAP1RE,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 2. "CAP0I,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 1. "CAP0FE,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 0. "CAP0RE,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x2C)++0x3
line.long 0x0 "CR[$1],Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input."
hexmask.long 0x0 0.--31. 1. "CAP,Timer counter capture value."
repeat.end
group.long 0x3C++0x3
line.long 0x0 "EMR,External Match Register. The EMR controls the match function and the external match pins."
bitfld.long 0x0 10.--11. "EMC3,External Match Control 3. Determines the functionality of External Match 3." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 8.--9. "EMC2,External Match Control 2. Determines the functionality of External Match 2." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 6.--7. "EMC1,External Match Control 1. Determines the functionality of External Match 1." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 4.--5. "EMC0,External Match Control 0. Determines the functionality of External Match 0." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 3. "EM3,External Match 3. This bit reflects the state of output MAT3  whether or not this output is connected to a pin. When a match occurs between the TC and MR3  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by MR[11:10]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 2. "EM2,External Match 2. This bit reflects the state of output MAT2  whether or not this output is connected to a pin. When a match occurs between the TC and MR2  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[9:8]. This bit.." "0: LOW,1: HIGH"
newline
bitfld.long 0x0 1. "EM1,External Match 1. This bit reflects the state of output MAT1  whether or not this output is connected to a pin. When a match occurs between the TC and MR1  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[7:6]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 0. "EM0,External Match 0. This bit reflects the state of output MAT0  whether or not this output is connected to a pin. When a match occurs between the TC and MR0  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[5:4]. This bit.." "0: LOW,1: HIGH"
group.long 0x70++0x7
line.long 0x0 "CTCR,Count Control Register. The CTCR selects between Timer and Counter mode. and in Counter mode selects the signal and edge(s) for counting."
bitfld.long 0x0 5.--7. "SELCC,Edge select. When bit 4 is 1  these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved." "0: Channel 0 Rising Edge. Rising edge of the signal..,1: Channel 0 Falling Edge. Falling edge of the..,2: Channel 1 Rising Edge. Rising edge of the signal..,3: Channel 1 Falling Edge. Falling edge of the..,4: Channel 2 Rising Edge. Rising edge of the signal..,5: Channel 2 Falling Edge. Falling edge of the..,?,?"
bitfld.long 0x0 4. "ENCC,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." "0,1"
newline
bitfld.long 0x0 2.--3. "CINSEL,Count Input Select When bits 1:0 in this register are not 00  these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR  the 3 bits for that input in the Capture Control.." "0: Channel 0. CAPn.0 for CTIMERn,1: 0 in this register are not 00,2: Channel 2. CAPn.2 for CTIMERn,3: Channel 3. CAPn.3 for CTIMERn"
bitfld.long 0x0 0.--1. "CTMODE,Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC)  or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale.." "0: Timer Mode. Incremented every rising APB bus..,1: Counter Mode rising edge. TC is incremented on..,2: Counter Mode falling edge. TC is incremented on..,3: Counter Mode dual edge. TC is incremented on.."
line.long 0x4 "PWMC,PWM Control Register. The PWMCON enables PWM mode for the external match pins."
bitfld.long 0x4 3. "PWMEN3,PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle." "0: Match. CTIMERn_MAT3 is controlled by EM3.,1: PWM. PWM mode is enabled for CT132Bn_MAT3."
bitfld.long 0x4 2. "PWMEN2,PWM mode enable for channel2." "0: Match. CTIMERn_MAT2 is controlled by EM2.,1: PWM. PWM mode is enabled for CTIMERn_MAT2."
newline
bitfld.long 0x4 1. "PWMEN1,PWM mode enable for channel1." "0: Match. CTIMERn_MAT01 is controlled by EM1.,1: PWM. PWM mode is enabled for CTIMERn_MAT1."
bitfld.long 0x4 0. "PWMEN0,PWM mode enable for channel0." "0: Match. CTIMERn_MAT0 is controlled by EM0.,1: PWM. PWM mode is enabled for CTIMERn_MAT0."
tree.end
tree "CTIMER4"
base ad:0x4000C000
group.long 0x0++0x17
line.long 0x0 "IR,Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending."
bitfld.long 0x0 7. "CR3INT,Interrupt flag for capture channel 3 event." "0,1"
bitfld.long 0x0 6. "CR2INT,Interrupt flag for capture channel 2 event." "0,1"
newline
bitfld.long 0x0 5. "CR1INT,Interrupt flag for capture channel 1 event." "0,1"
bitfld.long 0x0 4. "CR0INT,Interrupt flag for capture channel 0 event." "0,1"
newline
bitfld.long 0x0 3. "MR3INT,Interrupt flag for match channel 3." "0,1"
bitfld.long 0x0 2. "MR2INT,Interrupt flag for match channel 2." "0,1"
newline
bitfld.long 0x0 1. "MR1INT,Interrupt flag for match channel 1." "0,1"
bitfld.long 0x0 0. "MR0INT,Interrupt flag for match channel 0." "0,1"
line.long 0x4 "TCR,Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."
bitfld.long 0x4 1. "CRST,Counter reset." "0: Disabled. Do nothing.,1: Enabled. The Timer Counter and the Prescale.."
bitfld.long 0x4 0. "CEN,Counter enable." "0: Disabled.The counters are disabled.,1: Enabled. The Timer Counter and Prescale Counter.."
line.long 0x8 "TC,Timer Counter. The 32 bit TC is incremented every PR+1 cycles of the APB bus clock. The TC is controlled through the TCR."
hexmask.long 0x8 0.--31. 1. "TCVAL,Timer counter value."
line.long 0xC "PR,Prescale Register. When the Prescale Counter (PC) is equal to this value. the next clock increments the TC and clears the PC."
hexmask.long 0xC 0.--31. 1. "PRVAL,Prescale counter value."
line.long 0x10 "PC,Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached. the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface."
hexmask.long 0x10 0.--31. 1. "PCVAL,Prescale counter value."
line.long 0x14 "MCR,Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs."
bitfld.long 0x14 11. "MR3S,Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 10. "MR3R,Reset on MR3: the TC will be reset if MR3 matches it. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 9. "MR3I,Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 8. "MR2S,Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 7. "MR2R,Reset on MR2: the TC will be reset if MR2 matches it. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 6. "MR2I,Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 5. "MR1S,Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 4. "MR1R,Reset on MR1: the TC will be reset if MR1 matches it. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 3. "MR1I,Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. 0 = disabled. 1 = enabled. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 2. "MR0S,Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 1. "MR0R,Reset on MR0: the TC will be reset if MR0 matches it. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 0. "MR0I,Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x18)++0x3
line.long 0x0 "MR[$1],Match Register . MR can be enabled through the MCR to reset the TC. stop both the TC and PC. and/or generate an interrupt every time MR matches the TC."
hexmask.long 0x0 0.--31. 1. "MATCH,Timer counter match value."
repeat.end
group.long 0x28++0x3
line.long 0x0 "CCR,Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."
bitfld.long 0x0 11. "CAP3I,Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt." "0,1"
bitfld.long 0x0 10. "CAP3FE,Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 9. "CAP3RE,Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 8. "CAP2I,Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 7. "CAP2FE,Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 6. "CAP2RE,Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 5. "CAP1I,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt." "0,1"
bitfld.long 0x0 4. "CAP1FE,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 3. "CAP1RE,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 2. "CAP0I,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 1. "CAP0FE,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 0. "CAP0RE,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x2C)++0x3
line.long 0x0 "CR[$1],Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input."
hexmask.long 0x0 0.--31. 1. "CAP,Timer counter capture value."
repeat.end
group.long 0x3C++0x3
line.long 0x0 "EMR,External Match Register. The EMR controls the match function and the external match pins."
bitfld.long 0x0 10.--11. "EMC3,External Match Control 3. Determines the functionality of External Match 3." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 8.--9. "EMC2,External Match Control 2. Determines the functionality of External Match 2." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 6.--7. "EMC1,External Match Control 1. Determines the functionality of External Match 1." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 4.--5. "EMC0,External Match Control 0. Determines the functionality of External Match 0." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 3. "EM3,External Match 3. This bit reflects the state of output MAT3  whether or not this output is connected to a pin. When a match occurs between the TC and MR3  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by MR[11:10]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 2. "EM2,External Match 2. This bit reflects the state of output MAT2  whether or not this output is connected to a pin. When a match occurs between the TC and MR2  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[9:8]. This bit.." "0: LOW,1: HIGH"
newline
bitfld.long 0x0 1. "EM1,External Match 1. This bit reflects the state of output MAT1  whether or not this output is connected to a pin. When a match occurs between the TC and MR1  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[7:6]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 0. "EM0,External Match 0. This bit reflects the state of output MAT0  whether or not this output is connected to a pin. When a match occurs between the TC and MR0  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[5:4]. This bit.." "0: LOW,1: HIGH"
group.long 0x70++0x7
line.long 0x0 "CTCR,Count Control Register. The CTCR selects between Timer and Counter mode. and in Counter mode selects the signal and edge(s) for counting."
bitfld.long 0x0 5.--7. "SELCC,Edge select. When bit 4 is 1  these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved." "0: Channel 0 Rising Edge. Rising edge of the signal..,1: Channel 0 Falling Edge. Falling edge of the..,2: Channel 1 Rising Edge. Rising edge of the signal..,3: Channel 1 Falling Edge. Falling edge of the..,4: Channel 2 Rising Edge. Rising edge of the signal..,5: Channel 2 Falling Edge. Falling edge of the..,?,?"
bitfld.long 0x0 4. "ENCC,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." "0,1"
newline
bitfld.long 0x0 2.--3. "CINSEL,Count Input Select When bits 1:0 in this register are not 00  these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR  the 3 bits for that input in the Capture Control.." "0: Channel 0. CAPn.0 for CTIMERn,1: 0 in this register are not 00,2: Channel 2. CAPn.2 for CTIMERn,3: Channel 3. CAPn.3 for CTIMERn"
bitfld.long 0x0 0.--1. "CTMODE,Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC)  or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale.." "0: Timer Mode. Incremented every rising APB bus..,1: Counter Mode rising edge. TC is incremented on..,2: Counter Mode falling edge. TC is incremented on..,3: Counter Mode dual edge. TC is incremented on.."
line.long 0x4 "PWMC,PWM Control Register. The PWMCON enables PWM mode for the external match pins."
bitfld.long 0x4 3. "PWMEN3,PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle." "0: Match. CTIMERn_MAT3 is controlled by EM3.,1: PWM. PWM mode is enabled for CT132Bn_MAT3."
bitfld.long 0x4 2. "PWMEN2,PWM mode enable for channel2." "0: Match. CTIMERn_MAT2 is controlled by EM2.,1: PWM. PWM mode is enabled for CTIMERn_MAT2."
newline
bitfld.long 0x4 1. "PWMEN1,PWM mode enable for channel1." "0: Match. CTIMERn_MAT01 is controlled by EM1.,1: PWM. PWM mode is enabled for CTIMERn_MAT1."
bitfld.long 0x4 0. "PWMEN0,PWM mode enable for channel0." "0: Match. CTIMERn_MAT0 is controlled by EM0.,1: PWM. PWM mode is enabled for CTIMERn_MAT0."
tree.end
tree "CTIMER1"
base ad:0x400B8000
group.long 0x0++0x17
line.long 0x0 "IR,Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending."
bitfld.long 0x0 7. "CR3INT,Interrupt flag for capture channel 3 event." "0,1"
bitfld.long 0x0 6. "CR2INT,Interrupt flag for capture channel 2 event." "0,1"
newline
bitfld.long 0x0 5. "CR1INT,Interrupt flag for capture channel 1 event." "0,1"
bitfld.long 0x0 4. "CR0INT,Interrupt flag for capture channel 0 event." "0,1"
newline
bitfld.long 0x0 3. "MR3INT,Interrupt flag for match channel 3." "0,1"
bitfld.long 0x0 2. "MR2INT,Interrupt flag for match channel 2." "0,1"
newline
bitfld.long 0x0 1. "MR1INT,Interrupt flag for match channel 1." "0,1"
bitfld.long 0x0 0. "MR0INT,Interrupt flag for match channel 0." "0,1"
line.long 0x4 "TCR,Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."
bitfld.long 0x4 1. "CRST,Counter reset." "0: Disabled. Do nothing.,1: Enabled. The Timer Counter and the Prescale.."
bitfld.long 0x4 0. "CEN,Counter enable." "0: Disabled.The counters are disabled.,1: Enabled. The Timer Counter and Prescale Counter.."
line.long 0x8 "TC,Timer Counter. The 32 bit TC is incremented every PR+1 cycles of the APB bus clock. The TC is controlled through the TCR."
hexmask.long 0x8 0.--31. 1. "TCVAL,Timer counter value."
line.long 0xC "PR,Prescale Register. When the Prescale Counter (PC) is equal to this value. the next clock increments the TC and clears the PC."
hexmask.long 0xC 0.--31. 1. "PRVAL,Prescale counter value."
line.long 0x10 "PC,Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached. the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface."
hexmask.long 0x10 0.--31. 1. "PCVAL,Prescale counter value."
line.long 0x14 "MCR,Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs."
bitfld.long 0x14 11. "MR3S,Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 10. "MR3R,Reset on MR3: the TC will be reset if MR3 matches it. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 9. "MR3I,Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 8. "MR2S,Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 7. "MR2R,Reset on MR2: the TC will be reset if MR2 matches it. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 6. "MR2I,Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 5. "MR1S,Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 4. "MR1R,Reset on MR1: the TC will be reset if MR1 matches it. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 3. "MR1I,Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. 0 = disabled. 1 = enabled. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 2. "MR0S,Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 1. "MR0R,Reset on MR0: the TC will be reset if MR0 matches it. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 0. "MR0I,Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x18)++0x3
line.long 0x0 "MR[$1],Match Register . MR can be enabled through the MCR to reset the TC. stop both the TC and PC. and/or generate an interrupt every time MR matches the TC."
hexmask.long 0x0 0.--31. 1. "MATCH,Timer counter match value."
repeat.end
group.long 0x28++0x3
line.long 0x0 "CCR,Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."
bitfld.long 0x0 11. "CAP3I,Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt." "0,1"
bitfld.long 0x0 10. "CAP3FE,Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 9. "CAP3RE,Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 8. "CAP2I,Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 7. "CAP2FE,Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 6. "CAP2RE,Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 5. "CAP1I,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt." "0,1"
bitfld.long 0x0 4. "CAP1FE,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 3. "CAP1RE,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 2. "CAP0I,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 1. "CAP0FE,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 0. "CAP0RE,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x2C)++0x3
line.long 0x0 "CR[$1],Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input."
hexmask.long 0x0 0.--31. 1. "CAP,Timer counter capture value."
repeat.end
group.long 0x3C++0x3
line.long 0x0 "EMR,External Match Register. The EMR controls the match function and the external match pins."
bitfld.long 0x0 10.--11. "EMC3,External Match Control 3. Determines the functionality of External Match 3." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 8.--9. "EMC2,External Match Control 2. Determines the functionality of External Match 2." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 6.--7. "EMC1,External Match Control 1. Determines the functionality of External Match 1." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 4.--5. "EMC0,External Match Control 0. Determines the functionality of External Match 0." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 3. "EM3,External Match 3. This bit reflects the state of output MAT3  whether or not this output is connected to a pin. When a match occurs between the TC and MR3  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by MR[11:10]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 2. "EM2,External Match 2. This bit reflects the state of output MAT2  whether or not this output is connected to a pin. When a match occurs between the TC and MR2  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[9:8]. This bit.." "0: LOW,1: HIGH"
newline
bitfld.long 0x0 1. "EM1,External Match 1. This bit reflects the state of output MAT1  whether or not this output is connected to a pin. When a match occurs between the TC and MR1  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[7:6]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 0. "EM0,External Match 0. This bit reflects the state of output MAT0  whether or not this output is connected to a pin. When a match occurs between the TC and MR0  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[5:4]. This bit.." "0: LOW,1: HIGH"
group.long 0x70++0x7
line.long 0x0 "CTCR,Count Control Register. The CTCR selects between Timer and Counter mode. and in Counter mode selects the signal and edge(s) for counting."
bitfld.long 0x0 5.--7. "SELCC,Edge select. When bit 4 is 1  these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved." "0: Channel 0 Rising Edge. Rising edge of the signal..,1: Channel 0 Falling Edge. Falling edge of the..,2: Channel 1 Rising Edge. Rising edge of the signal..,3: Channel 1 Falling Edge. Falling edge of the..,4: Channel 2 Rising Edge. Rising edge of the signal..,5: Channel 2 Falling Edge. Falling edge of the..,?,?"
bitfld.long 0x0 4. "ENCC,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." "0,1"
newline
bitfld.long 0x0 2.--3. "CINSEL,Count Input Select When bits 1:0 in this register are not 00  these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR  the 3 bits for that input in the Capture Control.." "0: Channel 0. CAPn.0 for CTIMERn,1: 0 in this register are not 00,2: Channel 2. CAPn.2 for CTIMERn,3: Channel 3. CAPn.3 for CTIMERn"
bitfld.long 0x0 0.--1. "CTMODE,Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC)  or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale.." "0: Timer Mode. Incremented every rising APB bus..,1: Counter Mode rising edge. TC is incremented on..,2: Counter Mode falling edge. TC is incremented on..,3: Counter Mode dual edge. TC is incremented on.."
line.long 0x4 "PWMC,PWM Control Register. The PWMCON enables PWM mode for the external match pins."
bitfld.long 0x4 3. "PWMEN3,PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle." "0: Match. CTIMERn_MAT3 is controlled by EM3.,1: PWM. PWM mode is enabled for CT132Bn_MAT3."
bitfld.long 0x4 2. "PWMEN2,PWM mode enable for channel2." "0: Match. CTIMERn_MAT2 is controlled by EM2.,1: PWM. PWM mode is enabled for CTIMERn_MAT2."
newline
bitfld.long 0x4 1. "PWMEN1,PWM mode enable for channel1." "0: Match. CTIMERn_MAT01 is controlled by EM1.,1: PWM. PWM mode is enabled for CTIMERn_MAT1."
bitfld.long 0x4 0. "PWMEN0,PWM mode enable for channel0." "0: Match. CTIMERn_MAT0 is controlled by EM0.,1: PWM. PWM mode is enabled for CTIMERn_MAT0."
tree.end
endif
sif (cpuis("LPC54113*"))
tree "CTIMER0"
base ad:0x40008000
group.long 0x0++0x17
line.long 0x0 "IR,Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending."
bitfld.long 0x0 7. "CR3INT,Interrupt flag for capture channel 3 event." "0,1"
bitfld.long 0x0 6. "CR2INT,Interrupt flag for capture channel 2 event." "0,1"
newline
bitfld.long 0x0 5. "CR1INT,Interrupt flag for capture channel 1 event." "0,1"
bitfld.long 0x0 4. "CR0INT,Interrupt flag for capture channel 0 event." "0,1"
newline
bitfld.long 0x0 3. "MR3INT,Interrupt flag for match channel 3." "0,1"
bitfld.long 0x0 2. "MR2INT,Interrupt flag for match channel 2." "0,1"
newline
bitfld.long 0x0 1. "MR1INT,Interrupt flag for match channel 1." "0,1"
bitfld.long 0x0 0. "MR0INT,Interrupt flag for match channel 0." "0,1"
line.long 0x4 "TCR,Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."
bitfld.long 0x4 1. "CRST,Counter reset." "0: Disabled. Do nothing.,1: Enabled. The Timer Counter and the Prescale.."
bitfld.long 0x4 0. "CEN,Counter enable." "0: Disabled.The counters are disabled.,1: Enabled. The Timer Counter and Prescale Counter.."
line.long 0x8 "TC,Timer Counter. The 32 bit TC is incremented every PR+1 cycles of the APB bus clock. The TC is controlled through the TCR."
hexmask.long 0x8 0.--31. 1. "TCVAL,Timer counter value."
line.long 0xC "PR,Prescale Register. When the Prescale Counter (PC) is equal to this value. the next clock increments the TC and clears the PC."
hexmask.long 0xC 0.--31. 1. "PRVAL,Prescale counter value."
line.long 0x10 "PC,Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached. the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface."
hexmask.long 0x10 0.--31. 1. "PCVAL,Prescale counter value."
line.long 0x14 "MCR,Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs."
bitfld.long 0x14 11. "MR3S,Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 10. "MR3R,Reset on MR3: the TC will be reset if MR3 matches it. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 9. "MR3I,Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 8. "MR2S,Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 7. "MR2R,Reset on MR2: the TC will be reset if MR2 matches it. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 6. "MR2I,Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 5. "MR1S,Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 4. "MR1R,Reset on MR1: the TC will be reset if MR1 matches it. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 3. "MR1I,Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. 0 = disabled. 1 = enabled. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 2. "MR0S,Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 1. "MR0R,Reset on MR0: the TC will be reset if MR0 matches it. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 0. "MR0I,Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x18)++0x3
line.long 0x0 "MR[$1],Match Register . MR can be enabled through the MCR to reset the TC. stop both the TC and PC. and/or generate an interrupt every time MR matches the TC."
hexmask.long 0x0 0.--31. 1. "MATCH,Timer counter match value."
repeat.end
group.long 0x28++0x3
line.long 0x0 "CCR,Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."
bitfld.long 0x0 11. "CAP3I,Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt." "0,1"
bitfld.long 0x0 10. "CAP3FE,Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 9. "CAP3RE,Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 8. "CAP2I,Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 7. "CAP2FE,Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 6. "CAP2RE,Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 5. "CAP1I,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt." "0,1"
bitfld.long 0x0 4. "CAP1FE,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 3. "CAP1RE,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 2. "CAP0I,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 1. "CAP0FE,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 0. "CAP0RE,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x2C)++0x3
line.long 0x0 "CR[$1],Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input."
hexmask.long 0x0 0.--31. 1. "CAP,Timer counter capture value."
repeat.end
group.long 0x3C++0x3
line.long 0x0 "EMR,External Match Register. The EMR controls the match function and the external match pins."
bitfld.long 0x0 10.--11. "EMC3,External Match Control 3. Determines the functionality of External Match 3." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 8.--9. "EMC2,External Match Control 2. Determines the functionality of External Match 2." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
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bitfld.long 0x0 6.--7. "EMC1,External Match Control 1. Determines the functionality of External Match 1." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 4.--5. "EMC0,External Match Control 0. Determines the functionality of External Match 0." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 3. "EM3,External Match 3. This bit reflects the state of output MAT3  whether or not this output is connected to a pin. When a match occurs between the TC and MR3  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by MR[11:10]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 2. "EM2,External Match 2. This bit reflects the state of output MAT2  whether or not this output is connected to a pin. When a match occurs between the TC and MR2  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[9:8]. This bit.." "0: LOW,1: HIGH"
newline
bitfld.long 0x0 1. "EM1,External Match 1. This bit reflects the state of output MAT1  whether or not this output is connected to a pin. When a match occurs between the TC and MR1  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[7:6]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 0. "EM0,External Match 0. This bit reflects the state of output MAT0  whether or not this output is connected to a pin. When a match occurs between the TC and MR0  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[5:4]. This bit.." "0: LOW,1: HIGH"
group.long 0x70++0x7
line.long 0x0 "CTCR,Count Control Register. The CTCR selects between Timer and Counter mode. and in Counter mode selects the signal and edge(s) for counting."
bitfld.long 0x0 5.--7. "SELCC,Edge select. When bit 4 is 1  these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved." "0: Channel 0 Rising Edge. Rising edge of the signal..,1: Channel 0 Falling Edge. Falling edge of the..,2: Channel 1 Rising Edge. Rising edge of the signal..,3: Channel 1 Falling Edge. Falling edge of the..,4: Channel 2 Rising Edge. Rising edge of the signal..,5: Channel 2 Falling Edge. Falling edge of the..,?,?"
bitfld.long 0x0 4. "ENCC,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." "0,1"
newline
bitfld.long 0x0 2.--3. "CINSEL,Count Input Select When bits 1:0 in this register are not 00  these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR  the 3 bits for that input in the Capture Control.." "0: Channel 0. CAPn.0 for CTIMERn,1: 0 in this register are not 00,2: Channel 2. CAPn.2 for CTIMERn,3: Channel 3. CAPn.3 for CTIMERn"
bitfld.long 0x0 0.--1. "CTMODE,Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC)  or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale.." "0: Timer Mode. Incremented every rising APB bus..,1: Counter Mode rising edge. TC is incremented on..,2: Counter Mode falling edge. TC is incremented on..,3: Counter Mode dual edge. TC is incremented on.."
line.long 0x4 "PWMC,PWM Control Register. The PWMCON enables PWM mode for the external match pins."
bitfld.long 0x4 3. "PWMEN3,PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle." "0: Match. CTIMERn_MAT3 is controlled by EM3.,1: PWM. PWM mode is enabled for CT132Bn_MAT3."
bitfld.long 0x4 2. "PWMEN2,PWM mode enable for channel2." "0: Match. CTIMERn_MAT2 is controlled by EM2.,1: PWM. PWM mode is enabled for CTIMERn_MAT2."
newline
bitfld.long 0x4 1. "PWMEN1,PWM mode enable for channel1." "0: Match. CTIMERn_MAT01 is controlled by EM1.,1: PWM. PWM mode is enabled for CTIMERn_MAT1."
bitfld.long 0x4 0. "PWMEN0,PWM mode enable for channel0." "0: Match. CTIMERn_MAT0 is controlled by EM0.,1: PWM. PWM mode is enabled for CTIMERn_MAT0."
tree.end
tree "CTIMER1"
base ad:0x40009000
group.long 0x0++0x17
line.long 0x0 "IR,Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending."
bitfld.long 0x0 7. "CR3INT,Interrupt flag for capture channel 3 event." "0,1"
bitfld.long 0x0 6. "CR2INT,Interrupt flag for capture channel 2 event." "0,1"
newline
bitfld.long 0x0 5. "CR1INT,Interrupt flag for capture channel 1 event." "0,1"
bitfld.long 0x0 4. "CR0INT,Interrupt flag for capture channel 0 event." "0,1"
newline
bitfld.long 0x0 3. "MR3INT,Interrupt flag for match channel 3." "0,1"
bitfld.long 0x0 2. "MR2INT,Interrupt flag for match channel 2." "0,1"
newline
bitfld.long 0x0 1. "MR1INT,Interrupt flag for match channel 1." "0,1"
bitfld.long 0x0 0. "MR0INT,Interrupt flag for match channel 0." "0,1"
line.long 0x4 "TCR,Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."
bitfld.long 0x4 1. "CRST,Counter reset." "0: Disabled. Do nothing.,1: Enabled. The Timer Counter and the Prescale.."
bitfld.long 0x4 0. "CEN,Counter enable." "0: Disabled.The counters are disabled.,1: Enabled. The Timer Counter and Prescale Counter.."
line.long 0x8 "TC,Timer Counter. The 32 bit TC is incremented every PR+1 cycles of the APB bus clock. The TC is controlled through the TCR."
hexmask.long 0x8 0.--31. 1. "TCVAL,Timer counter value."
line.long 0xC "PR,Prescale Register. When the Prescale Counter (PC) is equal to this value. the next clock increments the TC and clears the PC."
hexmask.long 0xC 0.--31. 1. "PRVAL,Prescale counter value."
line.long 0x10 "PC,Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached. the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface."
hexmask.long 0x10 0.--31. 1. "PCVAL,Prescale counter value."
line.long 0x14 "MCR,Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs."
bitfld.long 0x14 11. "MR3S,Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 10. "MR3R,Reset on MR3: the TC will be reset if MR3 matches it. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 9. "MR3I,Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 8. "MR2S,Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 7. "MR2R,Reset on MR2: the TC will be reset if MR2 matches it. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 6. "MR2I,Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 5. "MR1S,Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 4. "MR1R,Reset on MR1: the TC will be reset if MR1 matches it. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 3. "MR1I,Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. 0 = disabled. 1 = enabled. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 2. "MR0S,Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 1. "MR0R,Reset on MR0: the TC will be reset if MR0 matches it. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 0. "MR0I,Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x18)++0x3
line.long 0x0 "MR[$1],Match Register . MR can be enabled through the MCR to reset the TC. stop both the TC and PC. and/or generate an interrupt every time MR matches the TC."
hexmask.long 0x0 0.--31. 1. "MATCH,Timer counter match value."
repeat.end
group.long 0x28++0x3
line.long 0x0 "CCR,Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."
bitfld.long 0x0 11. "CAP3I,Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt." "0,1"
bitfld.long 0x0 10. "CAP3FE,Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 9. "CAP3RE,Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 8. "CAP2I,Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 7. "CAP2FE,Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 6. "CAP2RE,Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 5. "CAP1I,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt." "0,1"
bitfld.long 0x0 4. "CAP1FE,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 3. "CAP1RE,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 2. "CAP0I,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 1. "CAP0FE,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 0. "CAP0RE,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x2C)++0x3
line.long 0x0 "CR[$1],Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input."
hexmask.long 0x0 0.--31. 1. "CAP,Timer counter capture value."
repeat.end
group.long 0x3C++0x3
line.long 0x0 "EMR,External Match Register. The EMR controls the match function and the external match pins."
bitfld.long 0x0 10.--11. "EMC3,External Match Control 3. Determines the functionality of External Match 3." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 8.--9. "EMC2,External Match Control 2. Determines the functionality of External Match 2." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 6.--7. "EMC1,External Match Control 1. Determines the functionality of External Match 1." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 4.--5. "EMC0,External Match Control 0. Determines the functionality of External Match 0." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 3. "EM3,External Match 3. This bit reflects the state of output MAT3  whether or not this output is connected to a pin. When a match occurs between the TC and MR3  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by MR[11:10]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 2. "EM2,External Match 2. This bit reflects the state of output MAT2  whether or not this output is connected to a pin. When a match occurs between the TC and MR2  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[9:8]. This bit.." "0: LOW,1: HIGH"
newline
bitfld.long 0x0 1. "EM1,External Match 1. This bit reflects the state of output MAT1  whether or not this output is connected to a pin. When a match occurs between the TC and MR1  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[7:6]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 0. "EM0,External Match 0. This bit reflects the state of output MAT0  whether or not this output is connected to a pin. When a match occurs between the TC and MR0  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[5:4]. This bit.." "0: LOW,1: HIGH"
group.long 0x70++0x7
line.long 0x0 "CTCR,Count Control Register. The CTCR selects between Timer and Counter mode. and in Counter mode selects the signal and edge(s) for counting."
bitfld.long 0x0 5.--7. "SELCC,Edge select. When bit 4 is 1  these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved." "0: Channel 0 Rising Edge. Rising edge of the signal..,1: Channel 0 Falling Edge. Falling edge of the..,2: Channel 1 Rising Edge. Rising edge of the signal..,3: Channel 1 Falling Edge. Falling edge of the..,4: Channel 2 Rising Edge. Rising edge of the signal..,5: Channel 2 Falling Edge. Falling edge of the..,?,?"
bitfld.long 0x0 4. "ENCC,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." "0,1"
newline
bitfld.long 0x0 2.--3. "CINSEL,Count Input Select When bits 1:0 in this register are not 00  these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR  the 3 bits for that input in the Capture Control.." "0: Channel 0. CAPn.0 for CTIMERn,1: 0 in this register are not 00,2: Channel 2. CAPn.2 for CTIMERn,3: Channel 3. CAPn.3 for CTIMERn"
bitfld.long 0x0 0.--1. "CTMODE,Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC)  or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale.." "0: Timer Mode. Incremented every rising APB bus..,1: Counter Mode rising edge. TC is incremented on..,2: Counter Mode falling edge. TC is incremented on..,3: Counter Mode dual edge. TC is incremented on.."
line.long 0x4 "PWMC,PWM Control Register. The PWMCON enables PWM mode for the external match pins."
bitfld.long 0x4 3. "PWMEN3,PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle." "0: Match. CTIMERn_MAT3 is controlled by EM3.,1: PWM. PWM mode is enabled for CT132Bn_MAT3."
bitfld.long 0x4 2. "PWMEN2,PWM mode enable for channel2." "0: Match. CTIMERn_MAT2 is controlled by EM2.,1: PWM. PWM mode is enabled for CTIMERn_MAT2."
newline
bitfld.long 0x4 1. "PWMEN1,PWM mode enable for channel1." "0: Match. CTIMERn_MAT01 is controlled by EM1.,1: PWM. PWM mode is enabled for CTIMERn_MAT1."
bitfld.long 0x4 0. "PWMEN0,PWM mode enable for channel0." "0: Match. CTIMERn_MAT0 is controlled by EM0.,1: PWM. PWM mode is enabled for CTIMERn_MAT0."
tree.end
tree "CTIMER2"
base ad:0x40028000
group.long 0x0++0x17
line.long 0x0 "IR,Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending."
bitfld.long 0x0 7. "CR3INT,Interrupt flag for capture channel 3 event." "0,1"
bitfld.long 0x0 6. "CR2INT,Interrupt flag for capture channel 2 event." "0,1"
newline
bitfld.long 0x0 5. "CR1INT,Interrupt flag for capture channel 1 event." "0,1"
bitfld.long 0x0 4. "CR0INT,Interrupt flag for capture channel 0 event." "0,1"
newline
bitfld.long 0x0 3. "MR3INT,Interrupt flag for match channel 3." "0,1"
bitfld.long 0x0 2. "MR2INT,Interrupt flag for match channel 2." "0,1"
newline
bitfld.long 0x0 1. "MR1INT,Interrupt flag for match channel 1." "0,1"
bitfld.long 0x0 0. "MR0INT,Interrupt flag for match channel 0." "0,1"
line.long 0x4 "TCR,Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."
bitfld.long 0x4 1. "CRST,Counter reset." "0: Disabled. Do nothing.,1: Enabled. The Timer Counter and the Prescale.."
bitfld.long 0x4 0. "CEN,Counter enable." "0: Disabled.The counters are disabled.,1: Enabled. The Timer Counter and Prescale Counter.."
line.long 0x8 "TC,Timer Counter. The 32 bit TC is incremented every PR+1 cycles of the APB bus clock. The TC is controlled through the TCR."
hexmask.long 0x8 0.--31. 1. "TCVAL,Timer counter value."
line.long 0xC "PR,Prescale Register. When the Prescale Counter (PC) is equal to this value. the next clock increments the TC and clears the PC."
hexmask.long 0xC 0.--31. 1. "PRVAL,Prescale counter value."
line.long 0x10 "PC,Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached. the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface."
hexmask.long 0x10 0.--31. 1. "PCVAL,Prescale counter value."
line.long 0x14 "MCR,Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs."
bitfld.long 0x14 11. "MR3S,Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 10. "MR3R,Reset on MR3: the TC will be reset if MR3 matches it. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 9. "MR3I,Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 8. "MR2S,Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 7. "MR2R,Reset on MR2: the TC will be reset if MR2 matches it. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 6. "MR2I,Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 5. "MR1S,Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 4. "MR1R,Reset on MR1: the TC will be reset if MR1 matches it. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 3. "MR1I,Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. 0 = disabled. 1 = enabled. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 2. "MR0S,Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 1. "MR0R,Reset on MR0: the TC will be reset if MR0 matches it. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 0. "MR0I,Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x18)++0x3
line.long 0x0 "MR[$1],Match Register . MR can be enabled through the MCR to reset the TC. stop both the TC and PC. and/or generate an interrupt every time MR matches the TC."
hexmask.long 0x0 0.--31. 1. "MATCH,Timer counter match value."
repeat.end
group.long 0x28++0x3
line.long 0x0 "CCR,Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."
bitfld.long 0x0 11. "CAP3I,Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt." "0,1"
bitfld.long 0x0 10. "CAP3FE,Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 9. "CAP3RE,Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 8. "CAP2I,Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 7. "CAP2FE,Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 6. "CAP2RE,Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 5. "CAP1I,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt." "0,1"
bitfld.long 0x0 4. "CAP1FE,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 3. "CAP1RE,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 2. "CAP0I,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 1. "CAP0FE,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 0. "CAP0RE,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x2C)++0x3
line.long 0x0 "CR[$1],Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input."
hexmask.long 0x0 0.--31. 1. "CAP,Timer counter capture value."
repeat.end
group.long 0x3C++0x3
line.long 0x0 "EMR,External Match Register. The EMR controls the match function and the external match pins."
bitfld.long 0x0 10.--11. "EMC3,External Match Control 3. Determines the functionality of External Match 3." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 8.--9. "EMC2,External Match Control 2. Determines the functionality of External Match 2." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 6.--7. "EMC1,External Match Control 1. Determines the functionality of External Match 1." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 4.--5. "EMC0,External Match Control 0. Determines the functionality of External Match 0." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 3. "EM3,External Match 3. This bit reflects the state of output MAT3  whether or not this output is connected to a pin. When a match occurs between the TC and MR3  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by MR[11:10]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 2. "EM2,External Match 2. This bit reflects the state of output MAT2  whether or not this output is connected to a pin. When a match occurs between the TC and MR2  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[9:8]. This bit.." "0: LOW,1: HIGH"
newline
bitfld.long 0x0 1. "EM1,External Match 1. This bit reflects the state of output MAT1  whether or not this output is connected to a pin. When a match occurs between the TC and MR1  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[7:6]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 0. "EM0,External Match 0. This bit reflects the state of output MAT0  whether or not this output is connected to a pin. When a match occurs between the TC and MR0  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[5:4]. This bit.." "0: LOW,1: HIGH"
group.long 0x70++0x7
line.long 0x0 "CTCR,Count Control Register. The CTCR selects between Timer and Counter mode. and in Counter mode selects the signal and edge(s) for counting."
bitfld.long 0x0 5.--7. "SELCC,Edge select. When bit 4 is 1  these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved." "0: Channel 0 Rising Edge. Rising edge of the signal..,1: Channel 0 Falling Edge. Falling edge of the..,2: Channel 1 Rising Edge. Rising edge of the signal..,3: Channel 1 Falling Edge. Falling edge of the..,4: Channel 2 Rising Edge. Rising edge of the signal..,5: Channel 2 Falling Edge. Falling edge of the..,?,?"
bitfld.long 0x0 4. "ENCC,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." "0,1"
newline
bitfld.long 0x0 2.--3. "CINSEL,Count Input Select When bits 1:0 in this register are not 00  these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR  the 3 bits for that input in the Capture Control.." "0: Channel 0. CAPn.0 for CTIMERn,1: 0 in this register are not 00,2: Channel 2. CAPn.2 for CTIMERn,3: Channel 3. CAPn.3 for CTIMERn"
bitfld.long 0x0 0.--1. "CTMODE,Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC)  or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale.." "0: Timer Mode. Incremented every rising APB bus..,1: Counter Mode rising edge. TC is incremented on..,2: Counter Mode falling edge. TC is incremented on..,3: Counter Mode dual edge. TC is incremented on.."
line.long 0x4 "PWMC,PWM Control Register. The PWMCON enables PWM mode for the external match pins."
bitfld.long 0x4 3. "PWMEN3,PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle." "0: Match. CTIMERn_MAT3 is controlled by EM3.,1: PWM. PWM mode is enabled for CT132Bn_MAT3."
bitfld.long 0x4 2. "PWMEN2,PWM mode enable for channel2." "0: Match. CTIMERn_MAT2 is controlled by EM2.,1: PWM. PWM mode is enabled for CTIMERn_MAT2."
newline
bitfld.long 0x4 1. "PWMEN1,PWM mode enable for channel1." "0: Match. CTIMERn_MAT01 is controlled by EM1.,1: PWM. PWM mode is enabled for CTIMERn_MAT1."
bitfld.long 0x4 0. "PWMEN0,PWM mode enable for channel0." "0: Match. CTIMERn_MAT0 is controlled by EM0.,1: PWM. PWM mode is enabled for CTIMERn_MAT0."
tree.end
tree "CTIMER3"
base ad:0x40048000
group.long 0x0++0x17
line.long 0x0 "IR,Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending."
bitfld.long 0x0 7. "CR3INT,Interrupt flag for capture channel 3 event." "0,1"
bitfld.long 0x0 6. "CR2INT,Interrupt flag for capture channel 2 event." "0,1"
newline
bitfld.long 0x0 5. "CR1INT,Interrupt flag for capture channel 1 event." "0,1"
bitfld.long 0x0 4. "CR0INT,Interrupt flag for capture channel 0 event." "0,1"
newline
bitfld.long 0x0 3. "MR3INT,Interrupt flag for match channel 3." "0,1"
bitfld.long 0x0 2. "MR2INT,Interrupt flag for match channel 2." "0,1"
newline
bitfld.long 0x0 1. "MR1INT,Interrupt flag for match channel 1." "0,1"
bitfld.long 0x0 0. "MR0INT,Interrupt flag for match channel 0." "0,1"
line.long 0x4 "TCR,Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."
bitfld.long 0x4 1. "CRST,Counter reset." "0: Disabled. Do nothing.,1: Enabled. The Timer Counter and the Prescale.."
bitfld.long 0x4 0. "CEN,Counter enable." "0: Disabled.The counters are disabled.,1: Enabled. The Timer Counter and Prescale Counter.."
line.long 0x8 "TC,Timer Counter. The 32 bit TC is incremented every PR+1 cycles of the APB bus clock. The TC is controlled through the TCR."
hexmask.long 0x8 0.--31. 1. "TCVAL,Timer counter value."
line.long 0xC "PR,Prescale Register. When the Prescale Counter (PC) is equal to this value. the next clock increments the TC and clears the PC."
hexmask.long 0xC 0.--31. 1. "PRVAL,Prescale counter value."
line.long 0x10 "PC,Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached. the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface."
hexmask.long 0x10 0.--31. 1. "PCVAL,Prescale counter value."
line.long 0x14 "MCR,Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs."
bitfld.long 0x14 11. "MR3S,Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 10. "MR3R,Reset on MR3: the TC will be reset if MR3 matches it. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 9. "MR3I,Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 8. "MR2S,Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 7. "MR2R,Reset on MR2: the TC will be reset if MR2 matches it. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 6. "MR2I,Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 5. "MR1S,Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 4. "MR1R,Reset on MR1: the TC will be reset if MR1 matches it. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 3. "MR1I,Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. 0 = disabled. 1 = enabled. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 2. "MR0S,Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 1. "MR0R,Reset on MR0: the TC will be reset if MR0 matches it. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 0. "MR0I,Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x18)++0x3
line.long 0x0 "MR[$1],Match Register . MR can be enabled through the MCR to reset the TC. stop both the TC and PC. and/or generate an interrupt every time MR matches the TC."
hexmask.long 0x0 0.--31. 1. "MATCH,Timer counter match value."
repeat.end
group.long 0x28++0x3
line.long 0x0 "CCR,Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."
bitfld.long 0x0 11. "CAP3I,Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt." "0,1"
bitfld.long 0x0 10. "CAP3FE,Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 9. "CAP3RE,Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 8. "CAP2I,Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 7. "CAP2FE,Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 6. "CAP2RE,Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 5. "CAP1I,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt." "0,1"
bitfld.long 0x0 4. "CAP1FE,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 3. "CAP1RE,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 2. "CAP0I,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 1. "CAP0FE,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 0. "CAP0RE,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x2C)++0x3
line.long 0x0 "CR[$1],Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input."
hexmask.long 0x0 0.--31. 1. "CAP,Timer counter capture value."
repeat.end
group.long 0x3C++0x3
line.long 0x0 "EMR,External Match Register. The EMR controls the match function and the external match pins."
bitfld.long 0x0 10.--11. "EMC3,External Match Control 3. Determines the functionality of External Match 3." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 8.--9. "EMC2,External Match Control 2. Determines the functionality of External Match 2." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 6.--7. "EMC1,External Match Control 1. Determines the functionality of External Match 1." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 4.--5. "EMC0,External Match Control 0. Determines the functionality of External Match 0." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 3. "EM3,External Match 3. This bit reflects the state of output MAT3  whether or not this output is connected to a pin. When a match occurs between the TC and MR3  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by MR[11:10]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 2. "EM2,External Match 2. This bit reflects the state of output MAT2  whether or not this output is connected to a pin. When a match occurs between the TC and MR2  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[9:8]. This bit.." "0: LOW,1: HIGH"
newline
bitfld.long 0x0 1. "EM1,External Match 1. This bit reflects the state of output MAT1  whether or not this output is connected to a pin. When a match occurs between the TC and MR1  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[7:6]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 0. "EM0,External Match 0. This bit reflects the state of output MAT0  whether or not this output is connected to a pin. When a match occurs between the TC and MR0  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[5:4]. This bit.." "0: LOW,1: HIGH"
group.long 0x70++0x7
line.long 0x0 "CTCR,Count Control Register. The CTCR selects between Timer and Counter mode. and in Counter mode selects the signal and edge(s) for counting."
bitfld.long 0x0 5.--7. "SELCC,Edge select. When bit 4 is 1  these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved." "0: Channel 0 Rising Edge. Rising edge of the signal..,1: Channel 0 Falling Edge. Falling edge of the..,2: Channel 1 Rising Edge. Rising edge of the signal..,3: Channel 1 Falling Edge. Falling edge of the..,4: Channel 2 Rising Edge. Rising edge of the signal..,5: Channel 2 Falling Edge. Falling edge of the..,?,?"
bitfld.long 0x0 4. "ENCC,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." "0,1"
newline
bitfld.long 0x0 2.--3. "CINSEL,Count Input Select When bits 1:0 in this register are not 00  these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR  the 3 bits for that input in the Capture Control.." "0: Channel 0. CAPn.0 for CTIMERn,1: 0 in this register are not 00,2: Channel 2. CAPn.2 for CTIMERn,3: Channel 3. CAPn.3 for CTIMERn"
bitfld.long 0x0 0.--1. "CTMODE,Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC)  or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale.." "0: Timer Mode. Incremented every rising APB bus..,1: Counter Mode rising edge. TC is incremented on..,2: Counter Mode falling edge. TC is incremented on..,3: Counter Mode dual edge. TC is incremented on.."
line.long 0x4 "PWMC,PWM Control Register. The PWMCON enables PWM mode for the external match pins."
bitfld.long 0x4 3. "PWMEN3,PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle." "0: Match. CTIMERn_MAT3 is controlled by EM3.,1: PWM. PWM mode is enabled for CT132Bn_MAT3."
bitfld.long 0x4 2. "PWMEN2,PWM mode enable for channel2." "0: Match. CTIMERn_MAT2 is controlled by EM2.,1: PWM. PWM mode is enabled for CTIMERn_MAT2."
newline
bitfld.long 0x4 1. "PWMEN1,PWM mode enable for channel1." "0: Match. CTIMERn_MAT01 is controlled by EM1.,1: PWM. PWM mode is enabled for CTIMERn_MAT1."
bitfld.long 0x4 0. "PWMEN0,PWM mode enable for channel0." "0: Match. CTIMERn_MAT0 is controlled by EM0.,1: PWM. PWM mode is enabled for CTIMERn_MAT0."
tree.end
tree "CTIMER4"
base ad:0x40049000
group.long 0x0++0x17
line.long 0x0 "IR,Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending."
bitfld.long 0x0 7. "CR3INT,Interrupt flag for capture channel 3 event." "0,1"
bitfld.long 0x0 6. "CR2INT,Interrupt flag for capture channel 2 event." "0,1"
newline
bitfld.long 0x0 5. "CR1INT,Interrupt flag for capture channel 1 event." "0,1"
bitfld.long 0x0 4. "CR0INT,Interrupt flag for capture channel 0 event." "0,1"
newline
bitfld.long 0x0 3. "MR3INT,Interrupt flag for match channel 3." "0,1"
bitfld.long 0x0 2. "MR2INT,Interrupt flag for match channel 2." "0,1"
newline
bitfld.long 0x0 1. "MR1INT,Interrupt flag for match channel 1." "0,1"
bitfld.long 0x0 0. "MR0INT,Interrupt flag for match channel 0." "0,1"
line.long 0x4 "TCR,Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."
bitfld.long 0x4 1. "CRST,Counter reset." "0: Disabled. Do nothing.,1: Enabled. The Timer Counter and the Prescale.."
bitfld.long 0x4 0. "CEN,Counter enable." "0: Disabled.The counters are disabled.,1: Enabled. The Timer Counter and Prescale Counter.."
line.long 0x8 "TC,Timer Counter. The 32 bit TC is incremented every PR+1 cycles of the APB bus clock. The TC is controlled through the TCR."
hexmask.long 0x8 0.--31. 1. "TCVAL,Timer counter value."
line.long 0xC "PR,Prescale Register. When the Prescale Counter (PC) is equal to this value. the next clock increments the TC and clears the PC."
hexmask.long 0xC 0.--31. 1. "PRVAL,Prescale counter value."
line.long 0x10 "PC,Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached. the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface."
hexmask.long 0x10 0.--31. 1. "PCVAL,Prescale counter value."
line.long 0x14 "MCR,Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs."
bitfld.long 0x14 11. "MR3S,Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 10. "MR3R,Reset on MR3: the TC will be reset if MR3 matches it. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 9. "MR3I,Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 8. "MR2S,Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 7. "MR2R,Reset on MR2: the TC will be reset if MR2 matches it. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 6. "MR2I,Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 5. "MR1S,Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 4. "MR1R,Reset on MR1: the TC will be reset if MR1 matches it. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 3. "MR1I,Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. 0 = disabled. 1 = enabled. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 2. "MR0S,Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 1. "MR0R,Reset on MR0: the TC will be reset if MR0 matches it. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 0. "MR0I,Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x18)++0x3
line.long 0x0 "MR[$1],Match Register . MR can be enabled through the MCR to reset the TC. stop both the TC and PC. and/or generate an interrupt every time MR matches the TC."
hexmask.long 0x0 0.--31. 1. "MATCH,Timer counter match value."
repeat.end
group.long 0x28++0x3
line.long 0x0 "CCR,Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."
bitfld.long 0x0 11. "CAP3I,Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt." "0,1"
bitfld.long 0x0 10. "CAP3FE,Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 9. "CAP3RE,Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 8. "CAP2I,Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 7. "CAP2FE,Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 6. "CAP2RE,Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 5. "CAP1I,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt." "0,1"
bitfld.long 0x0 4. "CAP1FE,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 3. "CAP1RE,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 2. "CAP0I,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 1. "CAP0FE,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 0. "CAP0RE,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x2C)++0x3
line.long 0x0 "CR[$1],Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input."
hexmask.long 0x0 0.--31. 1. "CAP,Timer counter capture value."
repeat.end
group.long 0x3C++0x3
line.long 0x0 "EMR,External Match Register. The EMR controls the match function and the external match pins."
bitfld.long 0x0 10.--11. "EMC3,External Match Control 3. Determines the functionality of External Match 3." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 8.--9. "EMC2,External Match Control 2. Determines the functionality of External Match 2." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 6.--7. "EMC1,External Match Control 1. Determines the functionality of External Match 1." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 4.--5. "EMC0,External Match Control 0. Determines the functionality of External Match 0." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 3. "EM3,External Match 3. This bit reflects the state of output MAT3  whether or not this output is connected to a pin. When a match occurs between the TC and MR3  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by MR[11:10]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 2. "EM2,External Match 2. This bit reflects the state of output MAT2  whether or not this output is connected to a pin. When a match occurs between the TC and MR2  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[9:8]. This bit.." "0: LOW,1: HIGH"
newline
bitfld.long 0x0 1. "EM1,External Match 1. This bit reflects the state of output MAT1  whether or not this output is connected to a pin. When a match occurs between the TC and MR1  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[7:6]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 0. "EM0,External Match 0. This bit reflects the state of output MAT0  whether or not this output is connected to a pin. When a match occurs between the TC and MR0  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[5:4]. This bit.." "0: LOW,1: HIGH"
group.long 0x70++0x7
line.long 0x0 "CTCR,Count Control Register. The CTCR selects between Timer and Counter mode. and in Counter mode selects the signal and edge(s) for counting."
bitfld.long 0x0 5.--7. "SELCC,Edge select. When bit 4 is 1  these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved." "0: Channel 0 Rising Edge. Rising edge of the signal..,1: Channel 0 Falling Edge. Falling edge of the..,2: Channel 1 Rising Edge. Rising edge of the signal..,3: Channel 1 Falling Edge. Falling edge of the..,4: Channel 2 Rising Edge. Rising edge of the signal..,5: Channel 2 Falling Edge. Falling edge of the..,?,?"
bitfld.long 0x0 4. "ENCC,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." "0,1"
newline
bitfld.long 0x0 2.--3. "CINSEL,Count Input Select When bits 1:0 in this register are not 00  these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR  the 3 bits for that input in the Capture Control.." "0: Channel 0. CAPn.0 for CTIMERn,1: 0 in this register are not 00,2: Channel 2. CAPn.2 for CTIMERn,3: Channel 3. CAPn.3 for CTIMERn"
bitfld.long 0x0 0.--1. "CTMODE,Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC)  or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale.." "0: Timer Mode. Incremented every rising APB bus..,1: Counter Mode rising edge. TC is incremented on..,2: Counter Mode falling edge. TC is incremented on..,3: Counter Mode dual edge. TC is incremented on.."
line.long 0x4 "PWMC,PWM Control Register. The PWMCON enables PWM mode for the external match pins."
bitfld.long 0x4 3. "PWMEN3,PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle." "0: Match. CTIMERn_MAT3 is controlled by EM3.,1: PWM. PWM mode is enabled for CT132Bn_MAT3."
bitfld.long 0x4 2. "PWMEN2,PWM mode enable for channel2." "0: Match. CTIMERn_MAT2 is controlled by EM2.,1: PWM. PWM mode is enabled for CTIMERn_MAT2."
newline
bitfld.long 0x4 1. "PWMEN1,PWM mode enable for channel1." "0: Match. CTIMERn_MAT01 is controlled by EM1.,1: PWM. PWM mode is enabled for CTIMERn_MAT1."
bitfld.long 0x4 0. "PWMEN0,PWM mode enable for channel0." "0: Match. CTIMERn_MAT0 is controlled by EM0.,1: PWM. PWM mode is enabled for CTIMERn_MAT0."
tree.end
endif
sif (cpuis("LPC54114*"))
tree "CTIMER0"
base ad:0x40008000
group.long 0x0++0x17
line.long 0x0 "IR,Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending."
bitfld.long 0x0 7. "CR3INT,Interrupt flag for capture channel 3 event." "0,1"
bitfld.long 0x0 6. "CR2INT,Interrupt flag for capture channel 2 event." "0,1"
newline
bitfld.long 0x0 5. "CR1INT,Interrupt flag for capture channel 1 event." "0,1"
bitfld.long 0x0 4. "CR0INT,Interrupt flag for capture channel 0 event." "0,1"
newline
bitfld.long 0x0 3. "MR3INT,Interrupt flag for match channel 3." "0,1"
bitfld.long 0x0 2. "MR2INT,Interrupt flag for match channel 2." "0,1"
newline
bitfld.long 0x0 1. "MR1INT,Interrupt flag for match channel 1." "0,1"
bitfld.long 0x0 0. "MR0INT,Interrupt flag for match channel 0." "0,1"
line.long 0x4 "TCR,Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."
bitfld.long 0x4 1. "CRST,Counter reset." "0: Disabled. Do nothing.,1: Enabled. The Timer Counter and the Prescale.."
bitfld.long 0x4 0. "CEN,Counter enable." "0: Disabled.The counters are disabled.,1: Enabled. The Timer Counter and Prescale Counter.."
line.long 0x8 "TC,Timer Counter. The 32 bit TC is incremented every PR+1 cycles of the APB bus clock. The TC is controlled through the TCR."
hexmask.long 0x8 0.--31. 1. "TCVAL,Timer counter value."
line.long 0xC "PR,Prescale Register. When the Prescale Counter (PC) is equal to this value. the next clock increments the TC and clears the PC."
hexmask.long 0xC 0.--31. 1. "PRVAL,Prescale counter value."
line.long 0x10 "PC,Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached. the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface."
hexmask.long 0x10 0.--31. 1. "PCVAL,Prescale counter value."
line.long 0x14 "MCR,Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs."
bitfld.long 0x14 11. "MR3S,Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 10. "MR3R,Reset on MR3: the TC will be reset if MR3 matches it. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 9. "MR3I,Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 8. "MR2S,Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 7. "MR2R,Reset on MR2: the TC will be reset if MR2 matches it. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 6. "MR2I,Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 5. "MR1S,Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 4. "MR1R,Reset on MR1: the TC will be reset if MR1 matches it. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 3. "MR1I,Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. 0 = disabled. 1 = enabled. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 2. "MR0S,Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 1. "MR0R,Reset on MR0: the TC will be reset if MR0 matches it. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 0. "MR0I,Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x18)++0x3
line.long 0x0 "MR[$1],Match Register . MR can be enabled through the MCR to reset the TC. stop both the TC and PC. and/or generate an interrupt every time MR matches the TC."
hexmask.long 0x0 0.--31. 1. "MATCH,Timer counter match value."
repeat.end
group.long 0x28++0x3
line.long 0x0 "CCR,Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."
bitfld.long 0x0 11. "CAP3I,Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt." "0,1"
bitfld.long 0x0 10. "CAP3FE,Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 9. "CAP3RE,Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 8. "CAP2I,Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 7. "CAP2FE,Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 6. "CAP2RE,Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 5. "CAP1I,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt." "0,1"
bitfld.long 0x0 4. "CAP1FE,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 3. "CAP1RE,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 2. "CAP0I,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 1. "CAP0FE,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 0. "CAP0RE,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x2C)++0x3
line.long 0x0 "CR[$1],Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input."
hexmask.long 0x0 0.--31. 1. "CAP,Timer counter capture value."
repeat.end
group.long 0x3C++0x3
line.long 0x0 "EMR,External Match Register. The EMR controls the match function and the external match pins."
bitfld.long 0x0 10.--11. "EMC3,External Match Control 3. Determines the functionality of External Match 3." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 8.--9. "EMC2,External Match Control 2. Determines the functionality of External Match 2." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 6.--7. "EMC1,External Match Control 1. Determines the functionality of External Match 1." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 4.--5. "EMC0,External Match Control 0. Determines the functionality of External Match 0." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 3. "EM3,External Match 3. This bit reflects the state of output MAT3  whether or not this output is connected to a pin. When a match occurs between the TC and MR3  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by MR[11:10]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 2. "EM2,External Match 2. This bit reflects the state of output MAT2  whether or not this output is connected to a pin. When a match occurs between the TC and MR2  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[9:8]. This bit.." "0: LOW,1: HIGH"
newline
bitfld.long 0x0 1. "EM1,External Match 1. This bit reflects the state of output MAT1  whether or not this output is connected to a pin. When a match occurs between the TC and MR1  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[7:6]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 0. "EM0,External Match 0. This bit reflects the state of output MAT0  whether or not this output is connected to a pin. When a match occurs between the TC and MR0  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[5:4]. This bit.." "0: LOW,1: HIGH"
group.long 0x70++0x7
line.long 0x0 "CTCR,Count Control Register. The CTCR selects between Timer and Counter mode. and in Counter mode selects the signal and edge(s) for counting."
bitfld.long 0x0 5.--7. "SELCC,Edge select. When bit 4 is 1  these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved." "0: Channel 0 Rising Edge. Rising edge of the signal..,1: Channel 0 Falling Edge. Falling edge of the..,2: Channel 1 Rising Edge. Rising edge of the signal..,3: Channel 1 Falling Edge. Falling edge of the..,4: Channel 2 Rising Edge. Rising edge of the signal..,5: Channel 2 Falling Edge. Falling edge of the..,?,?"
bitfld.long 0x0 4. "ENCC,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." "0,1"
newline
bitfld.long 0x0 2.--3. "CINSEL,Count Input Select When bits 1:0 in this register are not 00  these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR  the 3 bits for that input in the Capture Control.." "0: Channel 0. CAPn.0 for CTIMERn,1: 0 in this register are not 00,2: Channel 2. CAPn.2 for CTIMERn,3: Channel 3. CAPn.3 for CTIMERn"
bitfld.long 0x0 0.--1. "CTMODE,Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC)  or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale.." "0: Timer Mode. Incremented every rising APB bus..,1: Counter Mode rising edge. TC is incremented on..,2: Counter Mode falling edge. TC is incremented on..,3: Counter Mode dual edge. TC is incremented on.."
line.long 0x4 "PWMC,PWM Control Register. The PWMCON enables PWM mode for the external match pins."
bitfld.long 0x4 3. "PWMEN3,PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle." "0: Match. CTIMERn_MAT3 is controlled by EM3.,1: PWM. PWM mode is enabled for CT132Bn_MAT3."
bitfld.long 0x4 2. "PWMEN2,PWM mode enable for channel2." "0: Match. CTIMERn_MAT2 is controlled by EM2.,1: PWM. PWM mode is enabled for CTIMERn_MAT2."
newline
bitfld.long 0x4 1. "PWMEN1,PWM mode enable for channel1." "0: Match. CTIMERn_MAT01 is controlled by EM1.,1: PWM. PWM mode is enabled for CTIMERn_MAT1."
bitfld.long 0x4 0. "PWMEN0,PWM mode enable for channel0." "0: Match. CTIMERn_MAT0 is controlled by EM0.,1: PWM. PWM mode is enabled for CTIMERn_MAT0."
tree.end
tree "CTIMER1"
base ad:0x40009000
group.long 0x0++0x17
line.long 0x0 "IR,Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending."
bitfld.long 0x0 7. "CR3INT,Interrupt flag for capture channel 3 event." "0,1"
bitfld.long 0x0 6. "CR2INT,Interrupt flag for capture channel 2 event." "0,1"
newline
bitfld.long 0x0 5. "CR1INT,Interrupt flag for capture channel 1 event." "0,1"
bitfld.long 0x0 4. "CR0INT,Interrupt flag for capture channel 0 event." "0,1"
newline
bitfld.long 0x0 3. "MR3INT,Interrupt flag for match channel 3." "0,1"
bitfld.long 0x0 2. "MR2INT,Interrupt flag for match channel 2." "0,1"
newline
bitfld.long 0x0 1. "MR1INT,Interrupt flag for match channel 1." "0,1"
bitfld.long 0x0 0. "MR0INT,Interrupt flag for match channel 0." "0,1"
line.long 0x4 "TCR,Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."
bitfld.long 0x4 1. "CRST,Counter reset." "0: Disabled. Do nothing.,1: Enabled. The Timer Counter and the Prescale.."
bitfld.long 0x4 0. "CEN,Counter enable." "0: Disabled.The counters are disabled.,1: Enabled. The Timer Counter and Prescale Counter.."
line.long 0x8 "TC,Timer Counter. The 32 bit TC is incremented every PR+1 cycles of the APB bus clock. The TC is controlled through the TCR."
hexmask.long 0x8 0.--31. 1. "TCVAL,Timer counter value."
line.long 0xC "PR,Prescale Register. When the Prescale Counter (PC) is equal to this value. the next clock increments the TC and clears the PC."
hexmask.long 0xC 0.--31. 1. "PRVAL,Prescale counter value."
line.long 0x10 "PC,Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached. the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface."
hexmask.long 0x10 0.--31. 1. "PCVAL,Prescale counter value."
line.long 0x14 "MCR,Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs."
bitfld.long 0x14 11. "MR3S,Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 10. "MR3R,Reset on MR3: the TC will be reset if MR3 matches it. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 9. "MR3I,Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 8. "MR2S,Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 7. "MR2R,Reset on MR2: the TC will be reset if MR2 matches it. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 6. "MR2I,Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 5. "MR1S,Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 4. "MR1R,Reset on MR1: the TC will be reset if MR1 matches it. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 3. "MR1I,Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. 0 = disabled. 1 = enabled. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 2. "MR0S,Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 1. "MR0R,Reset on MR0: the TC will be reset if MR0 matches it. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 0. "MR0I,Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x18)++0x3
line.long 0x0 "MR[$1],Match Register . MR can be enabled through the MCR to reset the TC. stop both the TC and PC. and/or generate an interrupt every time MR matches the TC."
hexmask.long 0x0 0.--31. 1. "MATCH,Timer counter match value."
repeat.end
group.long 0x28++0x3
line.long 0x0 "CCR,Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."
bitfld.long 0x0 11. "CAP3I,Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt." "0,1"
bitfld.long 0x0 10. "CAP3FE,Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 9. "CAP3RE,Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 8. "CAP2I,Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 7. "CAP2FE,Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 6. "CAP2RE,Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 5. "CAP1I,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt." "0,1"
bitfld.long 0x0 4. "CAP1FE,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 3. "CAP1RE,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 2. "CAP0I,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 1. "CAP0FE,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 0. "CAP0RE,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x2C)++0x3
line.long 0x0 "CR[$1],Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input."
hexmask.long 0x0 0.--31. 1. "CAP,Timer counter capture value."
repeat.end
group.long 0x3C++0x3
line.long 0x0 "EMR,External Match Register. The EMR controls the match function and the external match pins."
bitfld.long 0x0 10.--11. "EMC3,External Match Control 3. Determines the functionality of External Match 3." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 8.--9. "EMC2,External Match Control 2. Determines the functionality of External Match 2." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 6.--7. "EMC1,External Match Control 1. Determines the functionality of External Match 1." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 4.--5. "EMC0,External Match Control 0. Determines the functionality of External Match 0." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 3. "EM3,External Match 3. This bit reflects the state of output MAT3  whether or not this output is connected to a pin. When a match occurs between the TC and MR3  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by MR[11:10]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 2. "EM2,External Match 2. This bit reflects the state of output MAT2  whether or not this output is connected to a pin. When a match occurs between the TC and MR2  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[9:8]. This bit.." "0: LOW,1: HIGH"
newline
bitfld.long 0x0 1. "EM1,External Match 1. This bit reflects the state of output MAT1  whether or not this output is connected to a pin. When a match occurs between the TC and MR1  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[7:6]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 0. "EM0,External Match 0. This bit reflects the state of output MAT0  whether or not this output is connected to a pin. When a match occurs between the TC and MR0  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[5:4]. This bit.." "0: LOW,1: HIGH"
group.long 0x70++0x7
line.long 0x0 "CTCR,Count Control Register. The CTCR selects between Timer and Counter mode. and in Counter mode selects the signal and edge(s) for counting."
bitfld.long 0x0 5.--7. "SELCC,Edge select. When bit 4 is 1  these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved." "0: Channel 0 Rising Edge. Rising edge of the signal..,1: Channel 0 Falling Edge. Falling edge of the..,2: Channel 1 Rising Edge. Rising edge of the signal..,3: Channel 1 Falling Edge. Falling edge of the..,4: Channel 2 Rising Edge. Rising edge of the signal..,5: Channel 2 Falling Edge. Falling edge of the..,?,?"
bitfld.long 0x0 4. "ENCC,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." "0,1"
newline
bitfld.long 0x0 2.--3. "CINSEL,Count Input Select When bits 1:0 in this register are not 00  these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR  the 3 bits for that input in the Capture Control.." "0: Channel 0. CAPn.0 for CTIMERn,1: 0 in this register are not 00,2: Channel 2. CAPn.2 for CTIMERn,3: Channel 3. CAPn.3 for CTIMERn"
bitfld.long 0x0 0.--1. "CTMODE,Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC)  or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale.." "0: Timer Mode. Incremented every rising APB bus..,1: Counter Mode rising edge. TC is incremented on..,2: Counter Mode falling edge. TC is incremented on..,3: Counter Mode dual edge. TC is incremented on.."
line.long 0x4 "PWMC,PWM Control Register. The PWMCON enables PWM mode for the external match pins."
bitfld.long 0x4 3. "PWMEN3,PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle." "0: Match. CTIMERn_MAT3 is controlled by EM3.,1: PWM. PWM mode is enabled for CT132Bn_MAT3."
bitfld.long 0x4 2. "PWMEN2,PWM mode enable for channel2." "0: Match. CTIMERn_MAT2 is controlled by EM2.,1: PWM. PWM mode is enabled for CTIMERn_MAT2."
newline
bitfld.long 0x4 1. "PWMEN1,PWM mode enable for channel1." "0: Match. CTIMERn_MAT01 is controlled by EM1.,1: PWM. PWM mode is enabled for CTIMERn_MAT1."
bitfld.long 0x4 0. "PWMEN0,PWM mode enable for channel0." "0: Match. CTIMERn_MAT0 is controlled by EM0.,1: PWM. PWM mode is enabled for CTIMERn_MAT0."
tree.end
tree "CTIMER2"
base ad:0x40028000
group.long 0x0++0x17
line.long 0x0 "IR,Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending."
bitfld.long 0x0 7. "CR3INT,Interrupt flag for capture channel 3 event." "0,1"
bitfld.long 0x0 6. "CR2INT,Interrupt flag for capture channel 2 event." "0,1"
newline
bitfld.long 0x0 5. "CR1INT,Interrupt flag for capture channel 1 event." "0,1"
bitfld.long 0x0 4. "CR0INT,Interrupt flag for capture channel 0 event." "0,1"
newline
bitfld.long 0x0 3. "MR3INT,Interrupt flag for match channel 3." "0,1"
bitfld.long 0x0 2. "MR2INT,Interrupt flag for match channel 2." "0,1"
newline
bitfld.long 0x0 1. "MR1INT,Interrupt flag for match channel 1." "0,1"
bitfld.long 0x0 0. "MR0INT,Interrupt flag for match channel 0." "0,1"
line.long 0x4 "TCR,Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."
bitfld.long 0x4 1. "CRST,Counter reset." "0: Disabled. Do nothing.,1: Enabled. The Timer Counter and the Prescale.."
bitfld.long 0x4 0. "CEN,Counter enable." "0: Disabled.The counters are disabled.,1: Enabled. The Timer Counter and Prescale Counter.."
line.long 0x8 "TC,Timer Counter. The 32 bit TC is incremented every PR+1 cycles of the APB bus clock. The TC is controlled through the TCR."
hexmask.long 0x8 0.--31. 1. "TCVAL,Timer counter value."
line.long 0xC "PR,Prescale Register. When the Prescale Counter (PC) is equal to this value. the next clock increments the TC and clears the PC."
hexmask.long 0xC 0.--31. 1. "PRVAL,Prescale counter value."
line.long 0x10 "PC,Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached. the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface."
hexmask.long 0x10 0.--31. 1. "PCVAL,Prescale counter value."
line.long 0x14 "MCR,Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs."
bitfld.long 0x14 11. "MR3S,Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 10. "MR3R,Reset on MR3: the TC will be reset if MR3 matches it. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 9. "MR3I,Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 8. "MR2S,Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 7. "MR2R,Reset on MR2: the TC will be reset if MR2 matches it. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 6. "MR2I,Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 5. "MR1S,Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 4. "MR1R,Reset on MR1: the TC will be reset if MR1 matches it. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 3. "MR1I,Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. 0 = disabled. 1 = enabled. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 2. "MR0S,Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 1. "MR0R,Reset on MR0: the TC will be reset if MR0 matches it. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 0. "MR0I,Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x18)++0x3
line.long 0x0 "MR[$1],Match Register . MR can be enabled through the MCR to reset the TC. stop both the TC and PC. and/or generate an interrupt every time MR matches the TC."
hexmask.long 0x0 0.--31. 1. "MATCH,Timer counter match value."
repeat.end
group.long 0x28++0x3
line.long 0x0 "CCR,Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."
bitfld.long 0x0 11. "CAP3I,Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt." "0,1"
bitfld.long 0x0 10. "CAP3FE,Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 9. "CAP3RE,Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 8. "CAP2I,Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 7. "CAP2FE,Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 6. "CAP2RE,Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 5. "CAP1I,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt." "0,1"
bitfld.long 0x0 4. "CAP1FE,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 3. "CAP1RE,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 2. "CAP0I,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 1. "CAP0FE,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 0. "CAP0RE,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x2C)++0x3
line.long 0x0 "CR[$1],Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input."
hexmask.long 0x0 0.--31. 1. "CAP,Timer counter capture value."
repeat.end
group.long 0x3C++0x3
line.long 0x0 "EMR,External Match Register. The EMR controls the match function and the external match pins."
bitfld.long 0x0 10.--11. "EMC3,External Match Control 3. Determines the functionality of External Match 3." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 8.--9. "EMC2,External Match Control 2. Determines the functionality of External Match 2." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 6.--7. "EMC1,External Match Control 1. Determines the functionality of External Match 1." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 4.--5. "EMC0,External Match Control 0. Determines the functionality of External Match 0." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 3. "EM3,External Match 3. This bit reflects the state of output MAT3  whether or not this output is connected to a pin. When a match occurs between the TC and MR3  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by MR[11:10]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 2. "EM2,External Match 2. This bit reflects the state of output MAT2  whether or not this output is connected to a pin. When a match occurs between the TC and MR2  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[9:8]. This bit.." "0: LOW,1: HIGH"
newline
bitfld.long 0x0 1. "EM1,External Match 1. This bit reflects the state of output MAT1  whether or not this output is connected to a pin. When a match occurs between the TC and MR1  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[7:6]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 0. "EM0,External Match 0. This bit reflects the state of output MAT0  whether or not this output is connected to a pin. When a match occurs between the TC and MR0  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[5:4]. This bit.." "0: LOW,1: HIGH"
group.long 0x70++0x7
line.long 0x0 "CTCR,Count Control Register. The CTCR selects between Timer and Counter mode. and in Counter mode selects the signal and edge(s) for counting."
bitfld.long 0x0 5.--7. "SELCC,Edge select. When bit 4 is 1  these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved." "0: Channel 0 Rising Edge. Rising edge of the signal..,1: Channel 0 Falling Edge. Falling edge of the..,2: Channel 1 Rising Edge. Rising edge of the signal..,3: Channel 1 Falling Edge. Falling edge of the..,4: Channel 2 Rising Edge. Rising edge of the signal..,5: Channel 2 Falling Edge. Falling edge of the..,?,?"
bitfld.long 0x0 4. "ENCC,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." "0,1"
newline
bitfld.long 0x0 2.--3. "CINSEL,Count Input Select When bits 1:0 in this register are not 00  these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR  the 3 bits for that input in the Capture Control.." "0: Channel 0. CAPn.0 for CTIMERn,1: 0 in this register are not 00,2: Channel 2. CAPn.2 for CTIMERn,3: Channel 3. CAPn.3 for CTIMERn"
bitfld.long 0x0 0.--1. "CTMODE,Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC)  or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale.." "0: Timer Mode. Incremented every rising APB bus..,1: Counter Mode rising edge. TC is incremented on..,2: Counter Mode falling edge. TC is incremented on..,3: Counter Mode dual edge. TC is incremented on.."
line.long 0x4 "PWMC,PWM Control Register. The PWMCON enables PWM mode for the external match pins."
bitfld.long 0x4 3. "PWMEN3,PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle." "0: Match. CTIMERn_MAT3 is controlled by EM3.,1: PWM. PWM mode is enabled for CT132Bn_MAT3."
bitfld.long 0x4 2. "PWMEN2,PWM mode enable for channel2." "0: Match. CTIMERn_MAT2 is controlled by EM2.,1: PWM. PWM mode is enabled for CTIMERn_MAT2."
newline
bitfld.long 0x4 1. "PWMEN1,PWM mode enable for channel1." "0: Match. CTIMERn_MAT01 is controlled by EM1.,1: PWM. PWM mode is enabled for CTIMERn_MAT1."
bitfld.long 0x4 0. "PWMEN0,PWM mode enable for channel0." "0: Match. CTIMERn_MAT0 is controlled by EM0.,1: PWM. PWM mode is enabled for CTIMERn_MAT0."
tree.end
tree "CTIMER3"
base ad:0x40048000
group.long 0x0++0x17
line.long 0x0 "IR,Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending."
bitfld.long 0x0 7. "CR3INT,Interrupt flag for capture channel 3 event." "0,1"
bitfld.long 0x0 6. "CR2INT,Interrupt flag for capture channel 2 event." "0,1"
newline
bitfld.long 0x0 5. "CR1INT,Interrupt flag for capture channel 1 event." "0,1"
bitfld.long 0x0 4. "CR0INT,Interrupt flag for capture channel 0 event." "0,1"
newline
bitfld.long 0x0 3. "MR3INT,Interrupt flag for match channel 3." "0,1"
bitfld.long 0x0 2. "MR2INT,Interrupt flag for match channel 2." "0,1"
newline
bitfld.long 0x0 1. "MR1INT,Interrupt flag for match channel 1." "0,1"
bitfld.long 0x0 0. "MR0INT,Interrupt flag for match channel 0." "0,1"
line.long 0x4 "TCR,Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."
bitfld.long 0x4 1. "CRST,Counter reset." "0: Disabled. Do nothing.,1: Enabled. The Timer Counter and the Prescale.."
bitfld.long 0x4 0. "CEN,Counter enable." "0: Disabled.The counters are disabled.,1: Enabled. The Timer Counter and Prescale Counter.."
line.long 0x8 "TC,Timer Counter. The 32 bit TC is incremented every PR+1 cycles of the APB bus clock. The TC is controlled through the TCR."
hexmask.long 0x8 0.--31. 1. "TCVAL,Timer counter value."
line.long 0xC "PR,Prescale Register. When the Prescale Counter (PC) is equal to this value. the next clock increments the TC and clears the PC."
hexmask.long 0xC 0.--31. 1. "PRVAL,Prescale counter value."
line.long 0x10 "PC,Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached. the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface."
hexmask.long 0x10 0.--31. 1. "PCVAL,Prescale counter value."
line.long 0x14 "MCR,Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs."
bitfld.long 0x14 11. "MR3S,Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 10. "MR3R,Reset on MR3: the TC will be reset if MR3 matches it. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 9. "MR3I,Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 8. "MR2S,Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 7. "MR2R,Reset on MR2: the TC will be reset if MR2 matches it. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 6. "MR2I,Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 5. "MR1S,Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 4. "MR1R,Reset on MR1: the TC will be reset if MR1 matches it. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 3. "MR1I,Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. 0 = disabled. 1 = enabled. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 2. "MR0S,Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 1. "MR0R,Reset on MR0: the TC will be reset if MR0 matches it. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 0. "MR0I,Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x18)++0x3
line.long 0x0 "MR[$1],Match Register . MR can be enabled through the MCR to reset the TC. stop both the TC and PC. and/or generate an interrupt every time MR matches the TC."
hexmask.long 0x0 0.--31. 1. "MATCH,Timer counter match value."
repeat.end
group.long 0x28++0x3
line.long 0x0 "CCR,Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."
bitfld.long 0x0 11. "CAP3I,Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt." "0,1"
bitfld.long 0x0 10. "CAP3FE,Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 9. "CAP3RE,Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 8. "CAP2I,Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 7. "CAP2FE,Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 6. "CAP2RE,Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 5. "CAP1I,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt." "0,1"
bitfld.long 0x0 4. "CAP1FE,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 3. "CAP1RE,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 2. "CAP0I,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 1. "CAP0FE,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 0. "CAP0RE,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x2C)++0x3
line.long 0x0 "CR[$1],Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input."
hexmask.long 0x0 0.--31. 1. "CAP,Timer counter capture value."
repeat.end
group.long 0x3C++0x3
line.long 0x0 "EMR,External Match Register. The EMR controls the match function and the external match pins."
bitfld.long 0x0 10.--11. "EMC3,External Match Control 3. Determines the functionality of External Match 3." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 8.--9. "EMC2,External Match Control 2. Determines the functionality of External Match 2." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 6.--7. "EMC1,External Match Control 1. Determines the functionality of External Match 1." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 4.--5. "EMC0,External Match Control 0. Determines the functionality of External Match 0." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 3. "EM3,External Match 3. This bit reflects the state of output MAT3  whether or not this output is connected to a pin. When a match occurs between the TC and MR3  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by MR[11:10]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 2. "EM2,External Match 2. This bit reflects the state of output MAT2  whether or not this output is connected to a pin. When a match occurs between the TC and MR2  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[9:8]. This bit.." "0: LOW,1: HIGH"
newline
bitfld.long 0x0 1. "EM1,External Match 1. This bit reflects the state of output MAT1  whether or not this output is connected to a pin. When a match occurs between the TC and MR1  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[7:6]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 0. "EM0,External Match 0. This bit reflects the state of output MAT0  whether or not this output is connected to a pin. When a match occurs between the TC and MR0  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[5:4]. This bit.." "0: LOW,1: HIGH"
group.long 0x70++0x7
line.long 0x0 "CTCR,Count Control Register. The CTCR selects between Timer and Counter mode. and in Counter mode selects the signal and edge(s) for counting."
bitfld.long 0x0 5.--7. "SELCC,Edge select. When bit 4 is 1  these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved." "0: Channel 0 Rising Edge. Rising edge of the signal..,1: Channel 0 Falling Edge. Falling edge of the..,2: Channel 1 Rising Edge. Rising edge of the signal..,3: Channel 1 Falling Edge. Falling edge of the..,4: Channel 2 Rising Edge. Rising edge of the signal..,5: Channel 2 Falling Edge. Falling edge of the..,?,?"
bitfld.long 0x0 4. "ENCC,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." "0,1"
newline
bitfld.long 0x0 2.--3. "CINSEL,Count Input Select When bits 1:0 in this register are not 00  these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR  the 3 bits for that input in the Capture Control.." "0: Channel 0. CAPn.0 for CTIMERn,1: 0 in this register are not 00,2: Channel 2. CAPn.2 for CTIMERn,3: Channel 3. CAPn.3 for CTIMERn"
bitfld.long 0x0 0.--1. "CTMODE,Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC)  or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale.." "0: Timer Mode. Incremented every rising APB bus..,1: Counter Mode rising edge. TC is incremented on..,2: Counter Mode falling edge. TC is incremented on..,3: Counter Mode dual edge. TC is incremented on.."
line.long 0x4 "PWMC,PWM Control Register. The PWMCON enables PWM mode for the external match pins."
bitfld.long 0x4 3. "PWMEN3,PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle." "0: Match. CTIMERn_MAT3 is controlled by EM3.,1: PWM. PWM mode is enabled for CT132Bn_MAT3."
bitfld.long 0x4 2. "PWMEN2,PWM mode enable for channel2." "0: Match. CTIMERn_MAT2 is controlled by EM2.,1: PWM. PWM mode is enabled for CTIMERn_MAT2."
newline
bitfld.long 0x4 1. "PWMEN1,PWM mode enable for channel1." "0: Match. CTIMERn_MAT01 is controlled by EM1.,1: PWM. PWM mode is enabled for CTIMERn_MAT1."
bitfld.long 0x4 0. "PWMEN0,PWM mode enable for channel0." "0: Match. CTIMERn_MAT0 is controlled by EM0.,1: PWM. PWM mode is enabled for CTIMERn_MAT0."
tree.end
tree "CTIMER4"
base ad:0x40049000
group.long 0x0++0x17
line.long 0x0 "IR,Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending."
bitfld.long 0x0 7. "CR3INT,Interrupt flag for capture channel 3 event." "0,1"
bitfld.long 0x0 6. "CR2INT,Interrupt flag for capture channel 2 event." "0,1"
newline
bitfld.long 0x0 5. "CR1INT,Interrupt flag for capture channel 1 event." "0,1"
bitfld.long 0x0 4. "CR0INT,Interrupt flag for capture channel 0 event." "0,1"
newline
bitfld.long 0x0 3. "MR3INT,Interrupt flag for match channel 3." "0,1"
bitfld.long 0x0 2. "MR2INT,Interrupt flag for match channel 2." "0,1"
newline
bitfld.long 0x0 1. "MR1INT,Interrupt flag for match channel 1." "0,1"
bitfld.long 0x0 0. "MR0INT,Interrupt flag for match channel 0." "0,1"
line.long 0x4 "TCR,Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."
bitfld.long 0x4 1. "CRST,Counter reset." "0: Disabled. Do nothing.,1: Enabled. The Timer Counter and the Prescale.."
bitfld.long 0x4 0. "CEN,Counter enable." "0: Disabled.The counters are disabled.,1: Enabled. The Timer Counter and Prescale Counter.."
line.long 0x8 "TC,Timer Counter. The 32 bit TC is incremented every PR+1 cycles of the APB bus clock. The TC is controlled through the TCR."
hexmask.long 0x8 0.--31. 1. "TCVAL,Timer counter value."
line.long 0xC "PR,Prescale Register. When the Prescale Counter (PC) is equal to this value. the next clock increments the TC and clears the PC."
hexmask.long 0xC 0.--31. 1. "PRVAL,Prescale counter value."
line.long 0x10 "PC,Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached. the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface."
hexmask.long 0x10 0.--31. 1. "PCVAL,Prescale counter value."
line.long 0x14 "MCR,Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs."
bitfld.long 0x14 11. "MR3S,Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 10. "MR3R,Reset on MR3: the TC will be reset if MR3 matches it. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 9. "MR3I,Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 8. "MR2S,Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 7. "MR2R,Reset on MR2: the TC will be reset if MR2 matches it. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 6. "MR2I,Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 5. "MR1S,Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 4. "MR1R,Reset on MR1: the TC will be reset if MR1 matches it. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 3. "MR1I,Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. 0 = disabled. 1 = enabled. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 2. "MR0S,Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x14 1. "MR0R,Reset on MR0: the TC will be reset if MR0 matches it. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x14 0. "MR0I,Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x18)++0x3
line.long 0x0 "MR[$1],Match Register . MR can be enabled through the MCR to reset the TC. stop both the TC and PC. and/or generate an interrupt every time MR matches the TC."
hexmask.long 0x0 0.--31. 1. "MATCH,Timer counter match value."
repeat.end
group.long 0x28++0x3
line.long 0x0 "CCR,Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."
bitfld.long 0x0 11. "CAP3I,Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt." "0,1"
bitfld.long 0x0 10. "CAP3FE,Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 9. "CAP3RE,Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 8. "CAP2I,Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 7. "CAP2FE,Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 6. "CAP2RE,Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 5. "CAP1I,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt." "0,1"
bitfld.long 0x0 4. "CAP1FE,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 3. "CAP1RE,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 2. "CAP0I,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 1. "CAP0FE,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 0. "CAP0RE,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x2C)++0x3
line.long 0x0 "CR[$1],Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input."
hexmask.long 0x0 0.--31. 1. "CAP,Timer counter capture value."
repeat.end
group.long 0x3C++0x3
line.long 0x0 "EMR,External Match Register. The EMR controls the match function and the external match pins."
bitfld.long 0x0 10.--11. "EMC3,External Match Control 3. Determines the functionality of External Match 3." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 8.--9. "EMC2,External Match Control 2. Determines the functionality of External Match 2." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 6.--7. "EMC1,External Match Control 1. Determines the functionality of External Match 1." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 4.--5. "EMC0,External Match Control 0. Determines the functionality of External Match 0." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 3. "EM3,External Match 3. This bit reflects the state of output MAT3  whether or not this output is connected to a pin. When a match occurs between the TC and MR3  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by MR[11:10]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 2. "EM2,External Match 2. This bit reflects the state of output MAT2  whether or not this output is connected to a pin. When a match occurs between the TC and MR2  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[9:8]. This bit.." "0: LOW,1: HIGH"
newline
bitfld.long 0x0 1. "EM1,External Match 1. This bit reflects the state of output MAT1  whether or not this output is connected to a pin. When a match occurs between the TC and MR1  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[7:6]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 0. "EM0,External Match 0. This bit reflects the state of output MAT0  whether or not this output is connected to a pin. When a match occurs between the TC and MR0  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[5:4]. This bit.." "0: LOW,1: HIGH"
group.long 0x70++0x7
line.long 0x0 "CTCR,Count Control Register. The CTCR selects between Timer and Counter mode. and in Counter mode selects the signal and edge(s) for counting."
bitfld.long 0x0 5.--7. "SELCC,Edge select. When bit 4 is 1  these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved." "0: Channel 0 Rising Edge. Rising edge of the signal..,1: Channel 0 Falling Edge. Falling edge of the..,2: Channel 1 Rising Edge. Rising edge of the signal..,3: Channel 1 Falling Edge. Falling edge of the..,4: Channel 2 Rising Edge. Rising edge of the signal..,5: Channel 2 Falling Edge. Falling edge of the..,?,?"
bitfld.long 0x0 4. "ENCC,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." "0,1"
newline
bitfld.long 0x0 2.--3. "CINSEL,Count Input Select When bits 1:0 in this register are not 00  these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR  the 3 bits for that input in the Capture Control.." "0: Channel 0. CAPn.0 for CTIMERn,1: 0 in this register are not 00,2: Channel 2. CAPn.2 for CTIMERn,3: Channel 3. CAPn.3 for CTIMERn"
bitfld.long 0x0 0.--1. "CTMODE,Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC)  or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale.." "0: Timer Mode. Incremented every rising APB bus..,1: Counter Mode rising edge. TC is incremented on..,2: Counter Mode falling edge. TC is incremented on..,3: Counter Mode dual edge. TC is incremented on.."
line.long 0x4 "PWMC,PWM Control Register. The PWMCON enables PWM mode for the external match pins."
bitfld.long 0x4 3. "PWMEN3,PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle." "0: Match. CTIMERn_MAT3 is controlled by EM3.,1: PWM. PWM mode is enabled for CT132Bn_MAT3."
bitfld.long 0x4 2. "PWMEN2,PWM mode enable for channel2." "0: Match. CTIMERn_MAT2 is controlled by EM2.,1: PWM. PWM mode is enabled for CTIMERn_MAT2."
newline
bitfld.long 0x4 1. "PWMEN1,PWM mode enable for channel1." "0: Match. CTIMERn_MAT01 is controlled by EM1.,1: PWM. PWM mode is enabled for CTIMERn_MAT1."
bitfld.long 0x4 0. "PWMEN0,PWM mode enable for channel0." "0: Match. CTIMERn_MAT0 is controlled by EM0.,1: PWM. PWM mode is enabled for CTIMERn_MAT0."
tree.end
endif
sif (cpuis("LPC54605*"))
tree "CTIMER0"
base ad:0x40008000
group.long 0x0++0x17
line.long 0x0 "IR,Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending."
bitfld.long 0x0 7. "CR3INT,Interrupt flag for capture channel 3 event." "0,1"
bitfld.long 0x0 6. "CR2INT,Interrupt flag for capture channel 2 event." "0,1"
newline
bitfld.long 0x0 5. "CR1INT,Interrupt flag for capture channel 1 event." "0,1"
bitfld.long 0x0 4. "CR0INT,Interrupt flag for capture channel 0 event." "0,1"
newline
bitfld.long 0x0 3. "MR3INT,Interrupt flag for match channel 3." "0,1"
bitfld.long 0x0 2. "MR2INT,Interrupt flag for match channel 2." "0,1"
newline
bitfld.long 0x0 1. "MR1INT,Interrupt flag for match channel 1." "0,1"
bitfld.long 0x0 0. "MR0INT,Interrupt flag for match channel 0." "0,1"
line.long 0x4 "TCR,Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."
bitfld.long 0x4 1. "CRST,Counter reset." "0: Disabled. Do nothing.,1: Enabled. The Timer Counter and the Prescale.."
bitfld.long 0x4 0. "CEN,Counter enable." "0: Disabled.The counters are disabled.,1: Enabled. The Timer Counter and Prescale Counter.."
line.long 0x8 "TC,Timer Counter"
hexmask.long 0x8 0.--31. 1. "TCVAL,Timer counter value."
line.long 0xC "PR,Prescale Register"
hexmask.long 0xC 0.--31. 1. "PRVAL,Prescale counter value."
line.long 0x10 "PC,Prescale Counter"
hexmask.long 0x10 0.--31. 1. "PCVAL,Prescale counter value."
line.long 0x14 "MCR,Match Control Register"
bitfld.long 0x14 27. "MR3RL,Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 26. "MR2RL,Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 25. "MR1RL,Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 24. "MR0RL,Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 11. "MR3S,Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." "0,1"
bitfld.long 0x14 10. "MR3R,Reset on MR3: the TC will be reset if MR3 matches it." "0,1"
newline
bitfld.long 0x14 9. "MR3I,Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC." "0,1"
bitfld.long 0x14 8. "MR2S,Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC." "0,1"
newline
bitfld.long 0x14 7. "MR2R,Reset on MR2: the TC will be reset if MR2 matches it." "0,1"
bitfld.long 0x14 6. "MR2I,Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC." "0,1"
newline
bitfld.long 0x14 5. "MR1S,Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." "0,1"
bitfld.long 0x14 4. "MR1R,Reset on MR1: the TC will be reset if MR1 matches it." "0,1"
newline
bitfld.long 0x14 3. "MR1I,Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC." "0,1"
bitfld.long 0x14 2. "MR0S,Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." "0,1"
newline
bitfld.long 0x14 1. "MR0R,Reset on MR0: the TC will be reset if MR0 matches it." "0,1"
bitfld.long 0x14 0. "MR0I,Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC." "0,1"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x18)++0x3
line.long 0x0 "MR[$1],Match Register . MR can be enabled through the MCR to reset the TC. stop both the TC and PC. and/or generate an interrupt every time MR matches the TC."
hexmask.long 0x0 0.--31. 1. "MATCH,Timer counter match value."
repeat.end
group.long 0x28++0x3
line.long 0x0 "CCR,Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."
bitfld.long 0x0 11. "CAP3I,Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt." "0,1"
bitfld.long 0x0 10. "CAP3FE,Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 9. "CAP3RE,Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 8. "CAP2I,Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 7. "CAP2FE,Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 6. "CAP2RE,Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 5. "CAP1I,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt." "0,1"
bitfld.long 0x0 4. "CAP1FE,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 3. "CAP1RE,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 2. "CAP0I,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 1. "CAP0FE,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 0. "CAP0RE,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x2C)++0x3
line.long 0x0 "CR[$1],Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input."
hexmask.long 0x0 0.--31. 1. "CAP,Timer counter capture value."
repeat.end
group.long 0x3C++0x3
line.long 0x0 "EMR,External Match Register. The EMR controls the match function and the external match pins."
bitfld.long 0x0 10.--11. "EMC3,External Match Control 3. Determines the functionality of External Match 3." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 8.--9. "EMC2,External Match Control 2. Determines the functionality of External Match 2." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 6.--7. "EMC1,External Match Control 1. Determines the functionality of External Match 1." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 4.--5. "EMC0,External Match Control 0. Determines the functionality of External Match 0." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 3. "EM3,External Match 3. This bit reflects the state of output MAT3  whether or not this output is connected to a pin. When a match occurs between the TC and MR3  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by MR[11:10]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 2. "EM2,External Match 2. This bit reflects the state of output MAT2  whether or not this output is connected to a pin. When a match occurs between the TC and MR2  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[9:8]. This bit.." "0: LOW,1: HIGH"
newline
bitfld.long 0x0 1. "EM1,External Match 1. This bit reflects the state of output MAT1  whether or not this output is connected to a pin. When a match occurs between the TC and MR1  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[7:6]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 0. "EM0,External Match 0. This bit reflects the state of output MAT0  whether or not this output is connected to a pin. When a match occurs between the TC and MR0  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[5:4]. This bit.." "0: LOW,1: HIGH"
group.long 0x70++0x7
line.long 0x0 "CTCR,Count Control Register. The CTCR selects between Timer and Counter mode. and in Counter mode selects the signal and edge(s) for counting."
bitfld.long 0x0 5.--7. "SELCC,Edge select. When bit 4 is 1  these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved." "0: Channel 0 Rising Edge. Rising edge of the signal..,1: Channel 0 Falling Edge. Falling edge of the..,2: Channel 1 Rising Edge. Rising edge of the signal..,3: Channel 1 Falling Edge. Falling edge of the..,4: Channel 2 Rising Edge. Rising edge of the signal..,5: Channel 2 Falling Edge. Falling edge of the..,?,?"
bitfld.long 0x0 4. "ENCC,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." "0,1"
newline
bitfld.long 0x0 2.--3. "CINSEL,Count Input Select When bits 1:0 in this register are not 00  these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR  the 3 bits for that input in the Capture Control.." "0: Channel 0. CAPn.0 for CTIMERn,1: 0 in this register are not 00,2: Channel 2. CAPn.2 for CTIMERn,3: Channel 3. CAPn.3 for CTIMERn"
bitfld.long 0x0 0.--1. "CTMODE,Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC)  or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale.." "0: Timer Mode. Incremented every rising APB bus..,1: Counter Mode rising edge. TC is incremented on..,2: Counter Mode falling edge. TC is incremented on..,3: Counter Mode dual edge. TC is incremented on.."
line.long 0x4 "PWMC,PWM Control Register. The PWMCON enables PWM mode for the external match pins."
bitfld.long 0x4 3. "PWMEN3,PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle." "0: Match. CTIMERn_MAT3 is controlled by EM3.,1: PWM. PWM mode is enabled for CT132Bn_MAT3."
bitfld.long 0x4 2. "PWMEN2,PWM mode enable for channel2." "0: Match. CTIMERn_MAT2 is controlled by EM2.,1: PWM. PWM mode is enabled for CTIMERn_MAT2."
newline
bitfld.long 0x4 1. "PWMEN1,PWM mode enable for channel1." "0: Match. CTIMERn_MAT01 is controlled by EM1.,1: PWM. PWM mode is enabled for CTIMERn_MAT1."
bitfld.long 0x4 0. "PWMEN0,PWM mode enable for channel0." "0: Match. CTIMERn_MAT0 is controlled by EM0.,1: PWM. PWM mode is enabled for CTIMERn_MAT0."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x78)++0x3
line.long 0x0 "MSR[$1],Match Shadow Register"
hexmask.long 0x0 0.--31. 1. "SHADOWW,Timer counter match shadow value."
repeat.end
tree.end
tree "CTIMER1"
base ad:0x40009000
group.long 0x0++0x17
line.long 0x0 "IR,Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending."
bitfld.long 0x0 7. "CR3INT,Interrupt flag for capture channel 3 event." "0,1"
bitfld.long 0x0 6. "CR2INT,Interrupt flag for capture channel 2 event." "0,1"
newline
bitfld.long 0x0 5. "CR1INT,Interrupt flag for capture channel 1 event." "0,1"
bitfld.long 0x0 4. "CR0INT,Interrupt flag for capture channel 0 event." "0,1"
newline
bitfld.long 0x0 3. "MR3INT,Interrupt flag for match channel 3." "0,1"
bitfld.long 0x0 2. "MR2INT,Interrupt flag for match channel 2." "0,1"
newline
bitfld.long 0x0 1. "MR1INT,Interrupt flag for match channel 1." "0,1"
bitfld.long 0x0 0. "MR0INT,Interrupt flag for match channel 0." "0,1"
line.long 0x4 "TCR,Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."
bitfld.long 0x4 1. "CRST,Counter reset." "0: Disabled. Do nothing.,1: Enabled. The Timer Counter and the Prescale.."
bitfld.long 0x4 0. "CEN,Counter enable." "0: Disabled.The counters are disabled.,1: Enabled. The Timer Counter and Prescale Counter.."
line.long 0x8 "TC,Timer Counter"
hexmask.long 0x8 0.--31. 1. "TCVAL,Timer counter value."
line.long 0xC "PR,Prescale Register"
hexmask.long 0xC 0.--31. 1. "PRVAL,Prescale counter value."
line.long 0x10 "PC,Prescale Counter"
hexmask.long 0x10 0.--31. 1. "PCVAL,Prescale counter value."
line.long 0x14 "MCR,Match Control Register"
bitfld.long 0x14 27. "MR3RL,Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 26. "MR2RL,Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 25. "MR1RL,Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 24. "MR0RL,Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 11. "MR3S,Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." "0,1"
bitfld.long 0x14 10. "MR3R,Reset on MR3: the TC will be reset if MR3 matches it." "0,1"
newline
bitfld.long 0x14 9. "MR3I,Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC." "0,1"
bitfld.long 0x14 8. "MR2S,Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC." "0,1"
newline
bitfld.long 0x14 7. "MR2R,Reset on MR2: the TC will be reset if MR2 matches it." "0,1"
bitfld.long 0x14 6. "MR2I,Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC." "0,1"
newline
bitfld.long 0x14 5. "MR1S,Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." "0,1"
bitfld.long 0x14 4. "MR1R,Reset on MR1: the TC will be reset if MR1 matches it." "0,1"
newline
bitfld.long 0x14 3. "MR1I,Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC." "0,1"
bitfld.long 0x14 2. "MR0S,Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." "0,1"
newline
bitfld.long 0x14 1. "MR0R,Reset on MR0: the TC will be reset if MR0 matches it." "0,1"
bitfld.long 0x14 0. "MR0I,Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC." "0,1"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x18)++0x3
line.long 0x0 "MR[$1],Match Register . MR can be enabled through the MCR to reset the TC. stop both the TC and PC. and/or generate an interrupt every time MR matches the TC."
hexmask.long 0x0 0.--31. 1. "MATCH,Timer counter match value."
repeat.end
group.long 0x28++0x3
line.long 0x0 "CCR,Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."
bitfld.long 0x0 11. "CAP3I,Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt." "0,1"
bitfld.long 0x0 10. "CAP3FE,Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 9. "CAP3RE,Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 8. "CAP2I,Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 7. "CAP2FE,Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 6. "CAP2RE,Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 5. "CAP1I,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt." "0,1"
bitfld.long 0x0 4. "CAP1FE,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 3. "CAP1RE,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 2. "CAP0I,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 1. "CAP0FE,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 0. "CAP0RE,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x2C)++0x3
line.long 0x0 "CR[$1],Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input."
hexmask.long 0x0 0.--31. 1. "CAP,Timer counter capture value."
repeat.end
group.long 0x3C++0x3
line.long 0x0 "EMR,External Match Register. The EMR controls the match function and the external match pins."
bitfld.long 0x0 10.--11. "EMC3,External Match Control 3. Determines the functionality of External Match 3." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 8.--9. "EMC2,External Match Control 2. Determines the functionality of External Match 2." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 6.--7. "EMC1,External Match Control 1. Determines the functionality of External Match 1." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 4.--5. "EMC0,External Match Control 0. Determines the functionality of External Match 0." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 3. "EM3,External Match 3. This bit reflects the state of output MAT3  whether or not this output is connected to a pin. When a match occurs between the TC and MR3  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by MR[11:10]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 2. "EM2,External Match 2. This bit reflects the state of output MAT2  whether or not this output is connected to a pin. When a match occurs between the TC and MR2  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[9:8]. This bit.." "0: LOW,1: HIGH"
newline
bitfld.long 0x0 1. "EM1,External Match 1. This bit reflects the state of output MAT1  whether or not this output is connected to a pin. When a match occurs between the TC and MR1  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[7:6]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 0. "EM0,External Match 0. This bit reflects the state of output MAT0  whether or not this output is connected to a pin. When a match occurs between the TC and MR0  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[5:4]. This bit.." "0: LOW,1: HIGH"
group.long 0x70++0x7
line.long 0x0 "CTCR,Count Control Register. The CTCR selects between Timer and Counter mode. and in Counter mode selects the signal and edge(s) for counting."
bitfld.long 0x0 5.--7. "SELCC,Edge select. When bit 4 is 1  these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved." "0: Channel 0 Rising Edge. Rising edge of the signal..,1: Channel 0 Falling Edge. Falling edge of the..,2: Channel 1 Rising Edge. Rising edge of the signal..,3: Channel 1 Falling Edge. Falling edge of the..,4: Channel 2 Rising Edge. Rising edge of the signal..,5: Channel 2 Falling Edge. Falling edge of the..,?,?"
bitfld.long 0x0 4. "ENCC,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." "0,1"
newline
bitfld.long 0x0 2.--3. "CINSEL,Count Input Select When bits 1:0 in this register are not 00  these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR  the 3 bits for that input in the Capture Control.." "0: Channel 0. CAPn.0 for CTIMERn,1: 0 in this register are not 00,2: Channel 2. CAPn.2 for CTIMERn,3: Channel 3. CAPn.3 for CTIMERn"
bitfld.long 0x0 0.--1. "CTMODE,Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC)  or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale.." "0: Timer Mode. Incremented every rising APB bus..,1: Counter Mode rising edge. TC is incremented on..,2: Counter Mode falling edge. TC is incremented on..,3: Counter Mode dual edge. TC is incremented on.."
line.long 0x4 "PWMC,PWM Control Register. The PWMCON enables PWM mode for the external match pins."
bitfld.long 0x4 3. "PWMEN3,PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle." "0: Match. CTIMERn_MAT3 is controlled by EM3.,1: PWM. PWM mode is enabled for CT132Bn_MAT3."
bitfld.long 0x4 2. "PWMEN2,PWM mode enable for channel2." "0: Match. CTIMERn_MAT2 is controlled by EM2.,1: PWM. PWM mode is enabled for CTIMERn_MAT2."
newline
bitfld.long 0x4 1. "PWMEN1,PWM mode enable for channel1." "0: Match. CTIMERn_MAT01 is controlled by EM1.,1: PWM. PWM mode is enabled for CTIMERn_MAT1."
bitfld.long 0x4 0. "PWMEN0,PWM mode enable for channel0." "0: Match. CTIMERn_MAT0 is controlled by EM0.,1: PWM. PWM mode is enabled for CTIMERn_MAT0."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x78)++0x3
line.long 0x0 "MSR[$1],Match Shadow Register"
hexmask.long 0x0 0.--31. 1. "SHADOWW,Timer counter match shadow value."
repeat.end
tree.end
tree "CTIMER2"
base ad:0x40028000
group.long 0x0++0x17
line.long 0x0 "IR,Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending."
bitfld.long 0x0 7. "CR3INT,Interrupt flag for capture channel 3 event." "0,1"
bitfld.long 0x0 6. "CR2INT,Interrupt flag for capture channel 2 event." "0,1"
newline
bitfld.long 0x0 5. "CR1INT,Interrupt flag for capture channel 1 event." "0,1"
bitfld.long 0x0 4. "CR0INT,Interrupt flag for capture channel 0 event." "0,1"
newline
bitfld.long 0x0 3. "MR3INT,Interrupt flag for match channel 3." "0,1"
bitfld.long 0x0 2. "MR2INT,Interrupt flag for match channel 2." "0,1"
newline
bitfld.long 0x0 1. "MR1INT,Interrupt flag for match channel 1." "0,1"
bitfld.long 0x0 0. "MR0INT,Interrupt flag for match channel 0." "0,1"
line.long 0x4 "TCR,Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."
bitfld.long 0x4 1. "CRST,Counter reset." "0: Disabled. Do nothing.,1: Enabled. The Timer Counter and the Prescale.."
bitfld.long 0x4 0. "CEN,Counter enable." "0: Disabled.The counters are disabled.,1: Enabled. The Timer Counter and Prescale Counter.."
line.long 0x8 "TC,Timer Counter"
hexmask.long 0x8 0.--31. 1. "TCVAL,Timer counter value."
line.long 0xC "PR,Prescale Register"
hexmask.long 0xC 0.--31. 1. "PRVAL,Prescale counter value."
line.long 0x10 "PC,Prescale Counter"
hexmask.long 0x10 0.--31. 1. "PCVAL,Prescale counter value."
line.long 0x14 "MCR,Match Control Register"
bitfld.long 0x14 27. "MR3RL,Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 26. "MR2RL,Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 25. "MR1RL,Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 24. "MR0RL,Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 11. "MR3S,Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." "0,1"
bitfld.long 0x14 10. "MR3R,Reset on MR3: the TC will be reset if MR3 matches it." "0,1"
newline
bitfld.long 0x14 9. "MR3I,Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC." "0,1"
bitfld.long 0x14 8. "MR2S,Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC." "0,1"
newline
bitfld.long 0x14 7. "MR2R,Reset on MR2: the TC will be reset if MR2 matches it." "0,1"
bitfld.long 0x14 6. "MR2I,Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC." "0,1"
newline
bitfld.long 0x14 5. "MR1S,Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." "0,1"
bitfld.long 0x14 4. "MR1R,Reset on MR1: the TC will be reset if MR1 matches it." "0,1"
newline
bitfld.long 0x14 3. "MR1I,Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC." "0,1"
bitfld.long 0x14 2. "MR0S,Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." "0,1"
newline
bitfld.long 0x14 1. "MR0R,Reset on MR0: the TC will be reset if MR0 matches it." "0,1"
bitfld.long 0x14 0. "MR0I,Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC." "0,1"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x18)++0x3
line.long 0x0 "MR[$1],Match Register . MR can be enabled through the MCR to reset the TC. stop both the TC and PC. and/or generate an interrupt every time MR matches the TC."
hexmask.long 0x0 0.--31. 1. "MATCH,Timer counter match value."
repeat.end
group.long 0x28++0x3
line.long 0x0 "CCR,Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."
bitfld.long 0x0 11. "CAP3I,Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt." "0,1"
bitfld.long 0x0 10. "CAP3FE,Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 9. "CAP3RE,Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 8. "CAP2I,Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 7. "CAP2FE,Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 6. "CAP2RE,Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 5. "CAP1I,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt." "0,1"
bitfld.long 0x0 4. "CAP1FE,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 3. "CAP1RE,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 2. "CAP0I,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 1. "CAP0FE,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 0. "CAP0RE,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x2C)++0x3
line.long 0x0 "CR[$1],Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input."
hexmask.long 0x0 0.--31. 1. "CAP,Timer counter capture value."
repeat.end
group.long 0x3C++0x3
line.long 0x0 "EMR,External Match Register. The EMR controls the match function and the external match pins."
bitfld.long 0x0 10.--11. "EMC3,External Match Control 3. Determines the functionality of External Match 3." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 8.--9. "EMC2,External Match Control 2. Determines the functionality of External Match 2." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 6.--7. "EMC1,External Match Control 1. Determines the functionality of External Match 1." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 4.--5. "EMC0,External Match Control 0. Determines the functionality of External Match 0." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 3. "EM3,External Match 3. This bit reflects the state of output MAT3  whether or not this output is connected to a pin. When a match occurs between the TC and MR3  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by MR[11:10]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 2. "EM2,External Match 2. This bit reflects the state of output MAT2  whether or not this output is connected to a pin. When a match occurs between the TC and MR2  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[9:8]. This bit.." "0: LOW,1: HIGH"
newline
bitfld.long 0x0 1. "EM1,External Match 1. This bit reflects the state of output MAT1  whether or not this output is connected to a pin. When a match occurs between the TC and MR1  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[7:6]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 0. "EM0,External Match 0. This bit reflects the state of output MAT0  whether or not this output is connected to a pin. When a match occurs between the TC and MR0  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[5:4]. This bit.." "0: LOW,1: HIGH"
group.long 0x70++0x7
line.long 0x0 "CTCR,Count Control Register. The CTCR selects between Timer and Counter mode. and in Counter mode selects the signal and edge(s) for counting."
bitfld.long 0x0 5.--7. "SELCC,Edge select. When bit 4 is 1  these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved." "0: Channel 0 Rising Edge. Rising edge of the signal..,1: Channel 0 Falling Edge. Falling edge of the..,2: Channel 1 Rising Edge. Rising edge of the signal..,3: Channel 1 Falling Edge. Falling edge of the..,4: Channel 2 Rising Edge. Rising edge of the signal..,5: Channel 2 Falling Edge. Falling edge of the..,?,?"
bitfld.long 0x0 4. "ENCC,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." "0,1"
newline
bitfld.long 0x0 2.--3. "CINSEL,Count Input Select When bits 1:0 in this register are not 00  these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR  the 3 bits for that input in the Capture Control.." "0: Channel 0. CAPn.0 for CTIMERn,1: 0 in this register are not 00,2: Channel 2. CAPn.2 for CTIMERn,3: Channel 3. CAPn.3 for CTIMERn"
bitfld.long 0x0 0.--1. "CTMODE,Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC)  or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale.." "0: Timer Mode. Incremented every rising APB bus..,1: Counter Mode rising edge. TC is incremented on..,2: Counter Mode falling edge. TC is incremented on..,3: Counter Mode dual edge. TC is incremented on.."
line.long 0x4 "PWMC,PWM Control Register. The PWMCON enables PWM mode for the external match pins."
bitfld.long 0x4 3. "PWMEN3,PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle." "0: Match. CTIMERn_MAT3 is controlled by EM3.,1: PWM. PWM mode is enabled for CT132Bn_MAT3."
bitfld.long 0x4 2. "PWMEN2,PWM mode enable for channel2." "0: Match. CTIMERn_MAT2 is controlled by EM2.,1: PWM. PWM mode is enabled for CTIMERn_MAT2."
newline
bitfld.long 0x4 1. "PWMEN1,PWM mode enable for channel1." "0: Match. CTIMERn_MAT01 is controlled by EM1.,1: PWM. PWM mode is enabled for CTIMERn_MAT1."
bitfld.long 0x4 0. "PWMEN0,PWM mode enable for channel0." "0: Match. CTIMERn_MAT0 is controlled by EM0.,1: PWM. PWM mode is enabled for CTIMERn_MAT0."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x78)++0x3
line.long 0x0 "MSR[$1],Match Shadow Register"
hexmask.long 0x0 0.--31. 1. "SHADOWW,Timer counter match shadow value."
repeat.end
tree.end
tree "CTIMER3"
base ad:0x40048000
group.long 0x0++0x17
line.long 0x0 "IR,Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending."
bitfld.long 0x0 7. "CR3INT,Interrupt flag for capture channel 3 event." "0,1"
bitfld.long 0x0 6. "CR2INT,Interrupt flag for capture channel 2 event." "0,1"
newline
bitfld.long 0x0 5. "CR1INT,Interrupt flag for capture channel 1 event." "0,1"
bitfld.long 0x0 4. "CR0INT,Interrupt flag for capture channel 0 event." "0,1"
newline
bitfld.long 0x0 3. "MR3INT,Interrupt flag for match channel 3." "0,1"
bitfld.long 0x0 2. "MR2INT,Interrupt flag for match channel 2." "0,1"
newline
bitfld.long 0x0 1. "MR1INT,Interrupt flag for match channel 1." "0,1"
bitfld.long 0x0 0. "MR0INT,Interrupt flag for match channel 0." "0,1"
line.long 0x4 "TCR,Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."
bitfld.long 0x4 1. "CRST,Counter reset." "0: Disabled. Do nothing.,1: Enabled. The Timer Counter and the Prescale.."
bitfld.long 0x4 0. "CEN,Counter enable." "0: Disabled.The counters are disabled.,1: Enabled. The Timer Counter and Prescale Counter.."
line.long 0x8 "TC,Timer Counter"
hexmask.long 0x8 0.--31. 1. "TCVAL,Timer counter value."
line.long 0xC "PR,Prescale Register"
hexmask.long 0xC 0.--31. 1. "PRVAL,Prescale counter value."
line.long 0x10 "PC,Prescale Counter"
hexmask.long 0x10 0.--31. 1. "PCVAL,Prescale counter value."
line.long 0x14 "MCR,Match Control Register"
bitfld.long 0x14 27. "MR3RL,Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 26. "MR2RL,Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 25. "MR1RL,Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 24. "MR0RL,Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 11. "MR3S,Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." "0,1"
bitfld.long 0x14 10. "MR3R,Reset on MR3: the TC will be reset if MR3 matches it." "0,1"
newline
bitfld.long 0x14 9. "MR3I,Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC." "0,1"
bitfld.long 0x14 8. "MR2S,Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC." "0,1"
newline
bitfld.long 0x14 7. "MR2R,Reset on MR2: the TC will be reset if MR2 matches it." "0,1"
bitfld.long 0x14 6. "MR2I,Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC." "0,1"
newline
bitfld.long 0x14 5. "MR1S,Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." "0,1"
bitfld.long 0x14 4. "MR1R,Reset on MR1: the TC will be reset if MR1 matches it." "0,1"
newline
bitfld.long 0x14 3. "MR1I,Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC." "0,1"
bitfld.long 0x14 2. "MR0S,Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." "0,1"
newline
bitfld.long 0x14 1. "MR0R,Reset on MR0: the TC will be reset if MR0 matches it." "0,1"
bitfld.long 0x14 0. "MR0I,Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC." "0,1"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x18)++0x3
line.long 0x0 "MR[$1],Match Register . MR can be enabled through the MCR to reset the TC. stop both the TC and PC. and/or generate an interrupt every time MR matches the TC."
hexmask.long 0x0 0.--31. 1. "MATCH,Timer counter match value."
repeat.end
group.long 0x28++0x3
line.long 0x0 "CCR,Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."
bitfld.long 0x0 11. "CAP3I,Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt." "0,1"
bitfld.long 0x0 10. "CAP3FE,Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 9. "CAP3RE,Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 8. "CAP2I,Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 7. "CAP2FE,Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 6. "CAP2RE,Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 5. "CAP1I,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt." "0,1"
bitfld.long 0x0 4. "CAP1FE,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 3. "CAP1RE,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 2. "CAP0I,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 1. "CAP0FE,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 0. "CAP0RE,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x2C)++0x3
line.long 0x0 "CR[$1],Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input."
hexmask.long 0x0 0.--31. 1. "CAP,Timer counter capture value."
repeat.end
group.long 0x3C++0x3
line.long 0x0 "EMR,External Match Register. The EMR controls the match function and the external match pins."
bitfld.long 0x0 10.--11. "EMC3,External Match Control 3. Determines the functionality of External Match 3." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 8.--9. "EMC2,External Match Control 2. Determines the functionality of External Match 2." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 6.--7. "EMC1,External Match Control 1. Determines the functionality of External Match 1." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 4.--5. "EMC0,External Match Control 0. Determines the functionality of External Match 0." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 3. "EM3,External Match 3. This bit reflects the state of output MAT3  whether or not this output is connected to a pin. When a match occurs between the TC and MR3  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by MR[11:10]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 2. "EM2,External Match 2. This bit reflects the state of output MAT2  whether or not this output is connected to a pin. When a match occurs between the TC and MR2  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[9:8]. This bit.." "0: LOW,1: HIGH"
newline
bitfld.long 0x0 1. "EM1,External Match 1. This bit reflects the state of output MAT1  whether or not this output is connected to a pin. When a match occurs between the TC and MR1  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[7:6]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 0. "EM0,External Match 0. This bit reflects the state of output MAT0  whether or not this output is connected to a pin. When a match occurs between the TC and MR0  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[5:4]. This bit.." "0: LOW,1: HIGH"
group.long 0x70++0x7
line.long 0x0 "CTCR,Count Control Register. The CTCR selects between Timer and Counter mode. and in Counter mode selects the signal and edge(s) for counting."
bitfld.long 0x0 5.--7. "SELCC,Edge select. When bit 4 is 1  these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved." "0: Channel 0 Rising Edge. Rising edge of the signal..,1: Channel 0 Falling Edge. Falling edge of the..,2: Channel 1 Rising Edge. Rising edge of the signal..,3: Channel 1 Falling Edge. Falling edge of the..,4: Channel 2 Rising Edge. Rising edge of the signal..,5: Channel 2 Falling Edge. Falling edge of the..,?,?"
bitfld.long 0x0 4. "ENCC,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." "0,1"
newline
bitfld.long 0x0 2.--3. "CINSEL,Count Input Select When bits 1:0 in this register are not 00  these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR  the 3 bits for that input in the Capture Control.." "0: Channel 0. CAPn.0 for CTIMERn,1: 0 in this register are not 00,2: Channel 2. CAPn.2 for CTIMERn,3: Channel 3. CAPn.3 for CTIMERn"
bitfld.long 0x0 0.--1. "CTMODE,Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC)  or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale.." "0: Timer Mode. Incremented every rising APB bus..,1: Counter Mode rising edge. TC is incremented on..,2: Counter Mode falling edge. TC is incremented on..,3: Counter Mode dual edge. TC is incremented on.."
line.long 0x4 "PWMC,PWM Control Register. The PWMCON enables PWM mode for the external match pins."
bitfld.long 0x4 3. "PWMEN3,PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle." "0: Match. CTIMERn_MAT3 is controlled by EM3.,1: PWM. PWM mode is enabled for CT132Bn_MAT3."
bitfld.long 0x4 2. "PWMEN2,PWM mode enable for channel2." "0: Match. CTIMERn_MAT2 is controlled by EM2.,1: PWM. PWM mode is enabled for CTIMERn_MAT2."
newline
bitfld.long 0x4 1. "PWMEN1,PWM mode enable for channel1." "0: Match. CTIMERn_MAT01 is controlled by EM1.,1: PWM. PWM mode is enabled for CTIMERn_MAT1."
bitfld.long 0x4 0. "PWMEN0,PWM mode enable for channel0." "0: Match. CTIMERn_MAT0 is controlled by EM0.,1: PWM. PWM mode is enabled for CTIMERn_MAT0."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x78)++0x3
line.long 0x0 "MSR[$1],Match Shadow Register"
hexmask.long 0x0 0.--31. 1. "SHADOWW,Timer counter match shadow value."
repeat.end
tree.end
tree "CTIMER4"
base ad:0x40049000
group.long 0x0++0x17
line.long 0x0 "IR,Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending."
bitfld.long 0x0 7. "CR3INT,Interrupt flag for capture channel 3 event." "0,1"
bitfld.long 0x0 6. "CR2INT,Interrupt flag for capture channel 2 event." "0,1"
newline
bitfld.long 0x0 5. "CR1INT,Interrupt flag for capture channel 1 event." "0,1"
bitfld.long 0x0 4. "CR0INT,Interrupt flag for capture channel 0 event." "0,1"
newline
bitfld.long 0x0 3. "MR3INT,Interrupt flag for match channel 3." "0,1"
bitfld.long 0x0 2. "MR2INT,Interrupt flag for match channel 2." "0,1"
newline
bitfld.long 0x0 1. "MR1INT,Interrupt flag for match channel 1." "0,1"
bitfld.long 0x0 0. "MR0INT,Interrupt flag for match channel 0." "0,1"
line.long 0x4 "TCR,Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."
bitfld.long 0x4 1. "CRST,Counter reset." "0: Disabled. Do nothing.,1: Enabled. The Timer Counter and the Prescale.."
bitfld.long 0x4 0. "CEN,Counter enable." "0: Disabled.The counters are disabled.,1: Enabled. The Timer Counter and Prescale Counter.."
line.long 0x8 "TC,Timer Counter"
hexmask.long 0x8 0.--31. 1. "TCVAL,Timer counter value."
line.long 0xC "PR,Prescale Register"
hexmask.long 0xC 0.--31. 1. "PRVAL,Prescale counter value."
line.long 0x10 "PC,Prescale Counter"
hexmask.long 0x10 0.--31. 1. "PCVAL,Prescale counter value."
line.long 0x14 "MCR,Match Control Register"
bitfld.long 0x14 27. "MR3RL,Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 26. "MR2RL,Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 25. "MR1RL,Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 24. "MR0RL,Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 11. "MR3S,Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." "0,1"
bitfld.long 0x14 10. "MR3R,Reset on MR3: the TC will be reset if MR3 matches it." "0,1"
newline
bitfld.long 0x14 9. "MR3I,Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC." "0,1"
bitfld.long 0x14 8. "MR2S,Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC." "0,1"
newline
bitfld.long 0x14 7. "MR2R,Reset on MR2: the TC will be reset if MR2 matches it." "0,1"
bitfld.long 0x14 6. "MR2I,Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC." "0,1"
newline
bitfld.long 0x14 5. "MR1S,Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." "0,1"
bitfld.long 0x14 4. "MR1R,Reset on MR1: the TC will be reset if MR1 matches it." "0,1"
newline
bitfld.long 0x14 3. "MR1I,Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC." "0,1"
bitfld.long 0x14 2. "MR0S,Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." "0,1"
newline
bitfld.long 0x14 1. "MR0R,Reset on MR0: the TC will be reset if MR0 matches it." "0,1"
bitfld.long 0x14 0. "MR0I,Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC." "0,1"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x18)++0x3
line.long 0x0 "MR[$1],Match Register . MR can be enabled through the MCR to reset the TC. stop both the TC and PC. and/or generate an interrupt every time MR matches the TC."
hexmask.long 0x0 0.--31. 1. "MATCH,Timer counter match value."
repeat.end
group.long 0x28++0x3
line.long 0x0 "CCR,Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."
bitfld.long 0x0 11. "CAP3I,Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt." "0,1"
bitfld.long 0x0 10. "CAP3FE,Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 9. "CAP3RE,Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 8. "CAP2I,Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 7. "CAP2FE,Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 6. "CAP2RE,Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 5. "CAP1I,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt." "0,1"
bitfld.long 0x0 4. "CAP1FE,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 3. "CAP1RE,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 2. "CAP0I,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 1. "CAP0FE,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 0. "CAP0RE,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x2C)++0x3
line.long 0x0 "CR[$1],Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input."
hexmask.long 0x0 0.--31. 1. "CAP,Timer counter capture value."
repeat.end
group.long 0x3C++0x3
line.long 0x0 "EMR,External Match Register. The EMR controls the match function and the external match pins."
bitfld.long 0x0 10.--11. "EMC3,External Match Control 3. Determines the functionality of External Match 3." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 8.--9. "EMC2,External Match Control 2. Determines the functionality of External Match 2." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 6.--7. "EMC1,External Match Control 1. Determines the functionality of External Match 1." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 4.--5. "EMC0,External Match Control 0. Determines the functionality of External Match 0." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 3. "EM3,External Match 3. This bit reflects the state of output MAT3  whether or not this output is connected to a pin. When a match occurs between the TC and MR3  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by MR[11:10]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 2. "EM2,External Match 2. This bit reflects the state of output MAT2  whether or not this output is connected to a pin. When a match occurs between the TC and MR2  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[9:8]. This bit.." "0: LOW,1: HIGH"
newline
bitfld.long 0x0 1. "EM1,External Match 1. This bit reflects the state of output MAT1  whether or not this output is connected to a pin. When a match occurs between the TC and MR1  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[7:6]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 0. "EM0,External Match 0. This bit reflects the state of output MAT0  whether or not this output is connected to a pin. When a match occurs between the TC and MR0  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[5:4]. This bit.." "0: LOW,1: HIGH"
group.long 0x70++0x7
line.long 0x0 "CTCR,Count Control Register. The CTCR selects between Timer and Counter mode. and in Counter mode selects the signal and edge(s) for counting."
bitfld.long 0x0 5.--7. "SELCC,Edge select. When bit 4 is 1  these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved." "0: Channel 0 Rising Edge. Rising edge of the signal..,1: Channel 0 Falling Edge. Falling edge of the..,2: Channel 1 Rising Edge. Rising edge of the signal..,3: Channel 1 Falling Edge. Falling edge of the..,4: Channel 2 Rising Edge. Rising edge of the signal..,5: Channel 2 Falling Edge. Falling edge of the..,?,?"
bitfld.long 0x0 4. "ENCC,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." "0,1"
newline
bitfld.long 0x0 2.--3. "CINSEL,Count Input Select When bits 1:0 in this register are not 00  these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR  the 3 bits for that input in the Capture Control.." "0: Channel 0. CAPn.0 for CTIMERn,1: 0 in this register are not 00,2: Channel 2. CAPn.2 for CTIMERn,3: Channel 3. CAPn.3 for CTIMERn"
bitfld.long 0x0 0.--1. "CTMODE,Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC)  or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale.." "0: Timer Mode. Incremented every rising APB bus..,1: Counter Mode rising edge. TC is incremented on..,2: Counter Mode falling edge. TC is incremented on..,3: Counter Mode dual edge. TC is incremented on.."
line.long 0x4 "PWMC,PWM Control Register. The PWMCON enables PWM mode for the external match pins."
bitfld.long 0x4 3. "PWMEN3,PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle." "0: Match. CTIMERn_MAT3 is controlled by EM3.,1: PWM. PWM mode is enabled for CT132Bn_MAT3."
bitfld.long 0x4 2. "PWMEN2,PWM mode enable for channel2." "0: Match. CTIMERn_MAT2 is controlled by EM2.,1: PWM. PWM mode is enabled for CTIMERn_MAT2."
newline
bitfld.long 0x4 1. "PWMEN1,PWM mode enable for channel1." "0: Match. CTIMERn_MAT01 is controlled by EM1.,1: PWM. PWM mode is enabled for CTIMERn_MAT1."
bitfld.long 0x4 0. "PWMEN0,PWM mode enable for channel0." "0: Match. CTIMERn_MAT0 is controlled by EM0.,1: PWM. PWM mode is enabled for CTIMERn_MAT0."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x78)++0x3
line.long 0x0 "MSR[$1],Match Shadow Register"
hexmask.long 0x0 0.--31. 1. "SHADOWW,Timer counter match shadow value."
repeat.end
tree.end
endif
sif (cpuis("LPC54606*"))
tree "CTIMER0"
base ad:0x40008000
group.long 0x0++0x17
line.long 0x0 "IR,Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending."
bitfld.long 0x0 7. "CR3INT,Interrupt flag for capture channel 3 event." "0,1"
bitfld.long 0x0 6. "CR2INT,Interrupt flag for capture channel 2 event." "0,1"
newline
bitfld.long 0x0 5. "CR1INT,Interrupt flag for capture channel 1 event." "0,1"
bitfld.long 0x0 4. "CR0INT,Interrupt flag for capture channel 0 event." "0,1"
newline
bitfld.long 0x0 3. "MR3INT,Interrupt flag for match channel 3." "0,1"
bitfld.long 0x0 2. "MR2INT,Interrupt flag for match channel 2." "0,1"
newline
bitfld.long 0x0 1. "MR1INT,Interrupt flag for match channel 1." "0,1"
bitfld.long 0x0 0. "MR0INT,Interrupt flag for match channel 0." "0,1"
line.long 0x4 "TCR,Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."
bitfld.long 0x4 1. "CRST,Counter reset." "0: Disabled. Do nothing.,1: Enabled. The Timer Counter and the Prescale.."
bitfld.long 0x4 0. "CEN,Counter enable." "0: Disabled.The counters are disabled.,1: Enabled. The Timer Counter and Prescale Counter.."
line.long 0x8 "TC,Timer Counter"
hexmask.long 0x8 0.--31. 1. "TCVAL,Timer counter value."
line.long 0xC "PR,Prescale Register"
hexmask.long 0xC 0.--31. 1. "PRVAL,Prescale counter value."
line.long 0x10 "PC,Prescale Counter"
hexmask.long 0x10 0.--31. 1. "PCVAL,Prescale counter value."
line.long 0x14 "MCR,Match Control Register"
bitfld.long 0x14 27. "MR3RL,Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 26. "MR2RL,Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 25. "MR1RL,Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 24. "MR0RL,Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 11. "MR3S,Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." "0,1"
bitfld.long 0x14 10. "MR3R,Reset on MR3: the TC will be reset if MR3 matches it." "0,1"
newline
bitfld.long 0x14 9. "MR3I,Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC." "0,1"
bitfld.long 0x14 8. "MR2S,Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC." "0,1"
newline
bitfld.long 0x14 7. "MR2R,Reset on MR2: the TC will be reset if MR2 matches it." "0,1"
bitfld.long 0x14 6. "MR2I,Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC." "0,1"
newline
bitfld.long 0x14 5. "MR1S,Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." "0,1"
bitfld.long 0x14 4. "MR1R,Reset on MR1: the TC will be reset if MR1 matches it." "0,1"
newline
bitfld.long 0x14 3. "MR1I,Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC." "0,1"
bitfld.long 0x14 2. "MR0S,Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." "0,1"
newline
bitfld.long 0x14 1. "MR0R,Reset on MR0: the TC will be reset if MR0 matches it." "0,1"
bitfld.long 0x14 0. "MR0I,Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC." "0,1"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x18)++0x3
line.long 0x0 "MR[$1],Match Register . MR can be enabled through the MCR to reset the TC. stop both the TC and PC. and/or generate an interrupt every time MR matches the TC."
hexmask.long 0x0 0.--31. 1. "MATCH,Timer counter match value."
repeat.end
group.long 0x28++0x3
line.long 0x0 "CCR,Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."
bitfld.long 0x0 11. "CAP3I,Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt." "0,1"
bitfld.long 0x0 10. "CAP3FE,Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 9. "CAP3RE,Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 8. "CAP2I,Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 7. "CAP2FE,Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 6. "CAP2RE,Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 5. "CAP1I,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt." "0,1"
bitfld.long 0x0 4. "CAP1FE,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 3. "CAP1RE,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 2. "CAP0I,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 1. "CAP0FE,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 0. "CAP0RE,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x2C)++0x3
line.long 0x0 "CR[$1],Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input."
hexmask.long 0x0 0.--31. 1. "CAP,Timer counter capture value."
repeat.end
group.long 0x3C++0x3
line.long 0x0 "EMR,External Match Register. The EMR controls the match function and the external match pins."
bitfld.long 0x0 10.--11. "EMC3,External Match Control 3. Determines the functionality of External Match 3." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 8.--9. "EMC2,External Match Control 2. Determines the functionality of External Match 2." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 6.--7. "EMC1,External Match Control 1. Determines the functionality of External Match 1." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 4.--5. "EMC0,External Match Control 0. Determines the functionality of External Match 0." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 3. "EM3,External Match 3. This bit reflects the state of output MAT3  whether or not this output is connected to a pin. When a match occurs between the TC and MR3  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by MR[11:10]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 2. "EM2,External Match 2. This bit reflects the state of output MAT2  whether or not this output is connected to a pin. When a match occurs between the TC and MR2  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[9:8]. This bit.." "0: LOW,1: HIGH"
newline
bitfld.long 0x0 1. "EM1,External Match 1. This bit reflects the state of output MAT1  whether or not this output is connected to a pin. When a match occurs between the TC and MR1  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[7:6]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 0. "EM0,External Match 0. This bit reflects the state of output MAT0  whether or not this output is connected to a pin. When a match occurs between the TC and MR0  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[5:4]. This bit.." "0: LOW,1: HIGH"
group.long 0x70++0x7
line.long 0x0 "CTCR,Count Control Register. The CTCR selects between Timer and Counter mode. and in Counter mode selects the signal and edge(s) for counting."
bitfld.long 0x0 5.--7. "SELCC,Edge select. When bit 4 is 1  these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved." "0: Channel 0 Rising Edge. Rising edge of the signal..,1: Channel 0 Falling Edge. Falling edge of the..,2: Channel 1 Rising Edge. Rising edge of the signal..,3: Channel 1 Falling Edge. Falling edge of the..,4: Channel 2 Rising Edge. Rising edge of the signal..,5: Channel 2 Falling Edge. Falling edge of the..,?,?"
bitfld.long 0x0 4. "ENCC,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." "0,1"
newline
bitfld.long 0x0 2.--3. "CINSEL,Count Input Select When bits 1:0 in this register are not 00  these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR  the 3 bits for that input in the Capture Control.." "0: Channel 0. CAPn.0 for CTIMERn,1: 0 in this register are not 00,2: Channel 2. CAPn.2 for CTIMERn,3: Channel 3. CAPn.3 for CTIMERn"
bitfld.long 0x0 0.--1. "CTMODE,Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC)  or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale.." "0: Timer Mode. Incremented every rising APB bus..,1: Counter Mode rising edge. TC is incremented on..,2: Counter Mode falling edge. TC is incremented on..,3: Counter Mode dual edge. TC is incremented on.."
line.long 0x4 "PWMC,PWM Control Register. The PWMCON enables PWM mode for the external match pins."
bitfld.long 0x4 3. "PWMEN3,PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle." "0: Match. CTIMERn_MAT3 is controlled by EM3.,1: PWM. PWM mode is enabled for CT132Bn_MAT3."
bitfld.long 0x4 2. "PWMEN2,PWM mode enable for channel2." "0: Match. CTIMERn_MAT2 is controlled by EM2.,1: PWM. PWM mode is enabled for CTIMERn_MAT2."
newline
bitfld.long 0x4 1. "PWMEN1,PWM mode enable for channel1." "0: Match. CTIMERn_MAT01 is controlled by EM1.,1: PWM. PWM mode is enabled for CTIMERn_MAT1."
bitfld.long 0x4 0. "PWMEN0,PWM mode enable for channel0." "0: Match. CTIMERn_MAT0 is controlled by EM0.,1: PWM. PWM mode is enabled for CTIMERn_MAT0."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x78)++0x3
line.long 0x0 "MSR[$1],Match Shadow Register"
hexmask.long 0x0 0.--31. 1. "SHADOWW,Timer counter match shadow value."
repeat.end
tree.end
tree "CTIMER1"
base ad:0x40009000
group.long 0x0++0x17
line.long 0x0 "IR,Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending."
bitfld.long 0x0 7. "CR3INT,Interrupt flag for capture channel 3 event." "0,1"
bitfld.long 0x0 6. "CR2INT,Interrupt flag for capture channel 2 event." "0,1"
newline
bitfld.long 0x0 5. "CR1INT,Interrupt flag for capture channel 1 event." "0,1"
bitfld.long 0x0 4. "CR0INT,Interrupt flag for capture channel 0 event." "0,1"
newline
bitfld.long 0x0 3. "MR3INT,Interrupt flag for match channel 3." "0,1"
bitfld.long 0x0 2. "MR2INT,Interrupt flag for match channel 2." "0,1"
newline
bitfld.long 0x0 1. "MR1INT,Interrupt flag for match channel 1." "0,1"
bitfld.long 0x0 0. "MR0INT,Interrupt flag for match channel 0." "0,1"
line.long 0x4 "TCR,Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."
bitfld.long 0x4 1. "CRST,Counter reset." "0: Disabled. Do nothing.,1: Enabled. The Timer Counter and the Prescale.."
bitfld.long 0x4 0. "CEN,Counter enable." "0: Disabled.The counters are disabled.,1: Enabled. The Timer Counter and Prescale Counter.."
line.long 0x8 "TC,Timer Counter"
hexmask.long 0x8 0.--31. 1. "TCVAL,Timer counter value."
line.long 0xC "PR,Prescale Register"
hexmask.long 0xC 0.--31. 1. "PRVAL,Prescale counter value."
line.long 0x10 "PC,Prescale Counter"
hexmask.long 0x10 0.--31. 1. "PCVAL,Prescale counter value."
line.long 0x14 "MCR,Match Control Register"
bitfld.long 0x14 27. "MR3RL,Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 26. "MR2RL,Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 25. "MR1RL,Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 24. "MR0RL,Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 11. "MR3S,Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." "0,1"
bitfld.long 0x14 10. "MR3R,Reset on MR3: the TC will be reset if MR3 matches it." "0,1"
newline
bitfld.long 0x14 9. "MR3I,Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC." "0,1"
bitfld.long 0x14 8. "MR2S,Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC." "0,1"
newline
bitfld.long 0x14 7. "MR2R,Reset on MR2: the TC will be reset if MR2 matches it." "0,1"
bitfld.long 0x14 6. "MR2I,Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC." "0,1"
newline
bitfld.long 0x14 5. "MR1S,Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." "0,1"
bitfld.long 0x14 4. "MR1R,Reset on MR1: the TC will be reset if MR1 matches it." "0,1"
newline
bitfld.long 0x14 3. "MR1I,Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC." "0,1"
bitfld.long 0x14 2. "MR0S,Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." "0,1"
newline
bitfld.long 0x14 1. "MR0R,Reset on MR0: the TC will be reset if MR0 matches it." "0,1"
bitfld.long 0x14 0. "MR0I,Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC." "0,1"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x18)++0x3
line.long 0x0 "MR[$1],Match Register . MR can be enabled through the MCR to reset the TC. stop both the TC and PC. and/or generate an interrupt every time MR matches the TC."
hexmask.long 0x0 0.--31. 1. "MATCH,Timer counter match value."
repeat.end
group.long 0x28++0x3
line.long 0x0 "CCR,Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."
bitfld.long 0x0 11. "CAP3I,Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt." "0,1"
bitfld.long 0x0 10. "CAP3FE,Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 9. "CAP3RE,Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 8. "CAP2I,Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 7. "CAP2FE,Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 6. "CAP2RE,Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 5. "CAP1I,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt." "0,1"
bitfld.long 0x0 4. "CAP1FE,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 3. "CAP1RE,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 2. "CAP0I,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 1. "CAP0FE,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 0. "CAP0RE,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x2C)++0x3
line.long 0x0 "CR[$1],Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input."
hexmask.long 0x0 0.--31. 1. "CAP,Timer counter capture value."
repeat.end
group.long 0x3C++0x3
line.long 0x0 "EMR,External Match Register. The EMR controls the match function and the external match pins."
bitfld.long 0x0 10.--11. "EMC3,External Match Control 3. Determines the functionality of External Match 3." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 8.--9. "EMC2,External Match Control 2. Determines the functionality of External Match 2." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 6.--7. "EMC1,External Match Control 1. Determines the functionality of External Match 1." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 4.--5. "EMC0,External Match Control 0. Determines the functionality of External Match 0." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 3. "EM3,External Match 3. This bit reflects the state of output MAT3  whether or not this output is connected to a pin. When a match occurs between the TC and MR3  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by MR[11:10]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 2. "EM2,External Match 2. This bit reflects the state of output MAT2  whether or not this output is connected to a pin. When a match occurs between the TC and MR2  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[9:8]. This bit.." "0: LOW,1: HIGH"
newline
bitfld.long 0x0 1. "EM1,External Match 1. This bit reflects the state of output MAT1  whether or not this output is connected to a pin. When a match occurs between the TC and MR1  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[7:6]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 0. "EM0,External Match 0. This bit reflects the state of output MAT0  whether or not this output is connected to a pin. When a match occurs between the TC and MR0  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[5:4]. This bit.." "0: LOW,1: HIGH"
group.long 0x70++0x7
line.long 0x0 "CTCR,Count Control Register. The CTCR selects between Timer and Counter mode. and in Counter mode selects the signal and edge(s) for counting."
bitfld.long 0x0 5.--7. "SELCC,Edge select. When bit 4 is 1  these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved." "0: Channel 0 Rising Edge. Rising edge of the signal..,1: Channel 0 Falling Edge. Falling edge of the..,2: Channel 1 Rising Edge. Rising edge of the signal..,3: Channel 1 Falling Edge. Falling edge of the..,4: Channel 2 Rising Edge. Rising edge of the signal..,5: Channel 2 Falling Edge. Falling edge of the..,?,?"
bitfld.long 0x0 4. "ENCC,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." "0,1"
newline
bitfld.long 0x0 2.--3. "CINSEL,Count Input Select When bits 1:0 in this register are not 00  these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR  the 3 bits for that input in the Capture Control.." "0: Channel 0. CAPn.0 for CTIMERn,1: 0 in this register are not 00,2: Channel 2. CAPn.2 for CTIMERn,3: Channel 3. CAPn.3 for CTIMERn"
bitfld.long 0x0 0.--1. "CTMODE,Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC)  or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale.." "0: Timer Mode. Incremented every rising APB bus..,1: Counter Mode rising edge. TC is incremented on..,2: Counter Mode falling edge. TC is incremented on..,3: Counter Mode dual edge. TC is incremented on.."
line.long 0x4 "PWMC,PWM Control Register. The PWMCON enables PWM mode for the external match pins."
bitfld.long 0x4 3. "PWMEN3,PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle." "0: Match. CTIMERn_MAT3 is controlled by EM3.,1: PWM. PWM mode is enabled for CT132Bn_MAT3."
bitfld.long 0x4 2. "PWMEN2,PWM mode enable for channel2." "0: Match. CTIMERn_MAT2 is controlled by EM2.,1: PWM. PWM mode is enabled for CTIMERn_MAT2."
newline
bitfld.long 0x4 1. "PWMEN1,PWM mode enable for channel1." "0: Match. CTIMERn_MAT01 is controlled by EM1.,1: PWM. PWM mode is enabled for CTIMERn_MAT1."
bitfld.long 0x4 0. "PWMEN0,PWM mode enable for channel0." "0: Match. CTIMERn_MAT0 is controlled by EM0.,1: PWM. PWM mode is enabled for CTIMERn_MAT0."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x78)++0x3
line.long 0x0 "MSR[$1],Match Shadow Register"
hexmask.long 0x0 0.--31. 1. "SHADOWW,Timer counter match shadow value."
repeat.end
tree.end
tree "CTIMER2"
base ad:0x40028000
group.long 0x0++0x17
line.long 0x0 "IR,Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending."
bitfld.long 0x0 7. "CR3INT,Interrupt flag for capture channel 3 event." "0,1"
bitfld.long 0x0 6. "CR2INT,Interrupt flag for capture channel 2 event." "0,1"
newline
bitfld.long 0x0 5. "CR1INT,Interrupt flag for capture channel 1 event." "0,1"
bitfld.long 0x0 4. "CR0INT,Interrupt flag for capture channel 0 event." "0,1"
newline
bitfld.long 0x0 3. "MR3INT,Interrupt flag for match channel 3." "0,1"
bitfld.long 0x0 2. "MR2INT,Interrupt flag for match channel 2." "0,1"
newline
bitfld.long 0x0 1. "MR1INT,Interrupt flag for match channel 1." "0,1"
bitfld.long 0x0 0. "MR0INT,Interrupt flag for match channel 0." "0,1"
line.long 0x4 "TCR,Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."
bitfld.long 0x4 1. "CRST,Counter reset." "0: Disabled. Do nothing.,1: Enabled. The Timer Counter and the Prescale.."
bitfld.long 0x4 0. "CEN,Counter enable." "0: Disabled.The counters are disabled.,1: Enabled. The Timer Counter and Prescale Counter.."
line.long 0x8 "TC,Timer Counter"
hexmask.long 0x8 0.--31. 1. "TCVAL,Timer counter value."
line.long 0xC "PR,Prescale Register"
hexmask.long 0xC 0.--31. 1. "PRVAL,Prescale counter value."
line.long 0x10 "PC,Prescale Counter"
hexmask.long 0x10 0.--31. 1. "PCVAL,Prescale counter value."
line.long 0x14 "MCR,Match Control Register"
bitfld.long 0x14 27. "MR3RL,Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 26. "MR2RL,Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
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bitfld.long 0x14 25. "MR1RL,Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 24. "MR0RL,Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 11. "MR3S,Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." "0,1"
bitfld.long 0x14 10. "MR3R,Reset on MR3: the TC will be reset if MR3 matches it." "0,1"
newline
bitfld.long 0x14 9. "MR3I,Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC." "0,1"
bitfld.long 0x14 8. "MR2S,Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC." "0,1"
newline
bitfld.long 0x14 7. "MR2R,Reset on MR2: the TC will be reset if MR2 matches it." "0,1"
bitfld.long 0x14 6. "MR2I,Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC." "0,1"
newline
bitfld.long 0x14 5. "MR1S,Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." "0,1"
bitfld.long 0x14 4. "MR1R,Reset on MR1: the TC will be reset if MR1 matches it." "0,1"
newline
bitfld.long 0x14 3. "MR1I,Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC." "0,1"
bitfld.long 0x14 2. "MR0S,Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." "0,1"
newline
bitfld.long 0x14 1. "MR0R,Reset on MR0: the TC will be reset if MR0 matches it." "0,1"
bitfld.long 0x14 0. "MR0I,Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC." "0,1"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x18)++0x3
line.long 0x0 "MR[$1],Match Register . MR can be enabled through the MCR to reset the TC. stop both the TC and PC. and/or generate an interrupt every time MR matches the TC."
hexmask.long 0x0 0.--31. 1. "MATCH,Timer counter match value."
repeat.end
group.long 0x28++0x3
line.long 0x0 "CCR,Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."
bitfld.long 0x0 11. "CAP3I,Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt." "0,1"
bitfld.long 0x0 10. "CAP3FE,Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 9. "CAP3RE,Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 8. "CAP2I,Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 7. "CAP2FE,Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 6. "CAP2RE,Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 5. "CAP1I,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt." "0,1"
bitfld.long 0x0 4. "CAP1FE,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 3. "CAP1RE,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 2. "CAP0I,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 1. "CAP0FE,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 0. "CAP0RE,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x2C)++0x3
line.long 0x0 "CR[$1],Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input."
hexmask.long 0x0 0.--31. 1. "CAP,Timer counter capture value."
repeat.end
group.long 0x3C++0x3
line.long 0x0 "EMR,External Match Register. The EMR controls the match function and the external match pins."
bitfld.long 0x0 10.--11. "EMC3,External Match Control 3. Determines the functionality of External Match 3." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 8.--9. "EMC2,External Match Control 2. Determines the functionality of External Match 2." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 6.--7. "EMC1,External Match Control 1. Determines the functionality of External Match 1." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 4.--5. "EMC0,External Match Control 0. Determines the functionality of External Match 0." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 3. "EM3,External Match 3. This bit reflects the state of output MAT3  whether or not this output is connected to a pin. When a match occurs between the TC and MR3  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by MR[11:10]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 2. "EM2,External Match 2. This bit reflects the state of output MAT2  whether or not this output is connected to a pin. When a match occurs between the TC and MR2  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[9:8]. This bit.." "0: LOW,1: HIGH"
newline
bitfld.long 0x0 1. "EM1,External Match 1. This bit reflects the state of output MAT1  whether or not this output is connected to a pin. When a match occurs between the TC and MR1  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[7:6]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 0. "EM0,External Match 0. This bit reflects the state of output MAT0  whether or not this output is connected to a pin. When a match occurs between the TC and MR0  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[5:4]. This bit.." "0: LOW,1: HIGH"
group.long 0x70++0x7
line.long 0x0 "CTCR,Count Control Register. The CTCR selects between Timer and Counter mode. and in Counter mode selects the signal and edge(s) for counting."
bitfld.long 0x0 5.--7. "SELCC,Edge select. When bit 4 is 1  these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved." "0: Channel 0 Rising Edge. Rising edge of the signal..,1: Channel 0 Falling Edge. Falling edge of the..,2: Channel 1 Rising Edge. Rising edge of the signal..,3: Channel 1 Falling Edge. Falling edge of the..,4: Channel 2 Rising Edge. Rising edge of the signal..,5: Channel 2 Falling Edge. Falling edge of the..,?,?"
bitfld.long 0x0 4. "ENCC,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." "0,1"
newline
bitfld.long 0x0 2.--3. "CINSEL,Count Input Select When bits 1:0 in this register are not 00  these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR  the 3 bits for that input in the Capture Control.." "0: Channel 0. CAPn.0 for CTIMERn,1: 0 in this register are not 00,2: Channel 2. CAPn.2 for CTIMERn,3: Channel 3. CAPn.3 for CTIMERn"
bitfld.long 0x0 0.--1. "CTMODE,Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC)  or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale.." "0: Timer Mode. Incremented every rising APB bus..,1: Counter Mode rising edge. TC is incremented on..,2: Counter Mode falling edge. TC is incremented on..,3: Counter Mode dual edge. TC is incremented on.."
line.long 0x4 "PWMC,PWM Control Register. The PWMCON enables PWM mode for the external match pins."
bitfld.long 0x4 3. "PWMEN3,PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle." "0: Match. CTIMERn_MAT3 is controlled by EM3.,1: PWM. PWM mode is enabled for CT132Bn_MAT3."
bitfld.long 0x4 2. "PWMEN2,PWM mode enable for channel2." "0: Match. CTIMERn_MAT2 is controlled by EM2.,1: PWM. PWM mode is enabled for CTIMERn_MAT2."
newline
bitfld.long 0x4 1. "PWMEN1,PWM mode enable for channel1." "0: Match. CTIMERn_MAT01 is controlled by EM1.,1: PWM. PWM mode is enabled for CTIMERn_MAT1."
bitfld.long 0x4 0. "PWMEN0,PWM mode enable for channel0." "0: Match. CTIMERn_MAT0 is controlled by EM0.,1: PWM. PWM mode is enabled for CTIMERn_MAT0."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x78)++0x3
line.long 0x0 "MSR[$1],Match Shadow Register"
hexmask.long 0x0 0.--31. 1. "SHADOWW,Timer counter match shadow value."
repeat.end
tree.end
tree "CTIMER3"
base ad:0x40048000
group.long 0x0++0x17
line.long 0x0 "IR,Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending."
bitfld.long 0x0 7. "CR3INT,Interrupt flag for capture channel 3 event." "0,1"
bitfld.long 0x0 6. "CR2INT,Interrupt flag for capture channel 2 event." "0,1"
newline
bitfld.long 0x0 5. "CR1INT,Interrupt flag for capture channel 1 event." "0,1"
bitfld.long 0x0 4. "CR0INT,Interrupt flag for capture channel 0 event." "0,1"
newline
bitfld.long 0x0 3. "MR3INT,Interrupt flag for match channel 3." "0,1"
bitfld.long 0x0 2. "MR2INT,Interrupt flag for match channel 2." "0,1"
newline
bitfld.long 0x0 1. "MR1INT,Interrupt flag for match channel 1." "0,1"
bitfld.long 0x0 0. "MR0INT,Interrupt flag for match channel 0." "0,1"
line.long 0x4 "TCR,Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."
bitfld.long 0x4 1. "CRST,Counter reset." "0: Disabled. Do nothing.,1: Enabled. The Timer Counter and the Prescale.."
bitfld.long 0x4 0. "CEN,Counter enable." "0: Disabled.The counters are disabled.,1: Enabled. The Timer Counter and Prescale Counter.."
line.long 0x8 "TC,Timer Counter"
hexmask.long 0x8 0.--31. 1. "TCVAL,Timer counter value."
line.long 0xC "PR,Prescale Register"
hexmask.long 0xC 0.--31. 1. "PRVAL,Prescale counter value."
line.long 0x10 "PC,Prescale Counter"
hexmask.long 0x10 0.--31. 1. "PCVAL,Prescale counter value."
line.long 0x14 "MCR,Match Control Register"
bitfld.long 0x14 27. "MR3RL,Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 26. "MR2RL,Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 25. "MR1RL,Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 24. "MR0RL,Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 11. "MR3S,Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." "0,1"
bitfld.long 0x14 10. "MR3R,Reset on MR3: the TC will be reset if MR3 matches it." "0,1"
newline
bitfld.long 0x14 9. "MR3I,Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC." "0,1"
bitfld.long 0x14 8. "MR2S,Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC." "0,1"
newline
bitfld.long 0x14 7. "MR2R,Reset on MR2: the TC will be reset if MR2 matches it." "0,1"
bitfld.long 0x14 6. "MR2I,Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC." "0,1"
newline
bitfld.long 0x14 5. "MR1S,Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." "0,1"
bitfld.long 0x14 4. "MR1R,Reset on MR1: the TC will be reset if MR1 matches it." "0,1"
newline
bitfld.long 0x14 3. "MR1I,Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC." "0,1"
bitfld.long 0x14 2. "MR0S,Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." "0,1"
newline
bitfld.long 0x14 1. "MR0R,Reset on MR0: the TC will be reset if MR0 matches it." "0,1"
bitfld.long 0x14 0. "MR0I,Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC." "0,1"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x18)++0x3
line.long 0x0 "MR[$1],Match Register . MR can be enabled through the MCR to reset the TC. stop both the TC and PC. and/or generate an interrupt every time MR matches the TC."
hexmask.long 0x0 0.--31. 1. "MATCH,Timer counter match value."
repeat.end
group.long 0x28++0x3
line.long 0x0 "CCR,Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."
bitfld.long 0x0 11. "CAP3I,Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt." "0,1"
bitfld.long 0x0 10. "CAP3FE,Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 9. "CAP3RE,Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 8. "CAP2I,Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 7. "CAP2FE,Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 6. "CAP2RE,Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 5. "CAP1I,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt." "0,1"
bitfld.long 0x0 4. "CAP1FE,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 3. "CAP1RE,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 2. "CAP0I,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 1. "CAP0FE,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 0. "CAP0RE,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x2C)++0x3
line.long 0x0 "CR[$1],Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input."
hexmask.long 0x0 0.--31. 1. "CAP,Timer counter capture value."
repeat.end
group.long 0x3C++0x3
line.long 0x0 "EMR,External Match Register. The EMR controls the match function and the external match pins."
bitfld.long 0x0 10.--11. "EMC3,External Match Control 3. Determines the functionality of External Match 3." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 8.--9. "EMC2,External Match Control 2. Determines the functionality of External Match 2." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 6.--7. "EMC1,External Match Control 1. Determines the functionality of External Match 1." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 4.--5. "EMC0,External Match Control 0. Determines the functionality of External Match 0." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 3. "EM3,External Match 3. This bit reflects the state of output MAT3  whether or not this output is connected to a pin. When a match occurs between the TC and MR3  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by MR[11:10]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 2. "EM2,External Match 2. This bit reflects the state of output MAT2  whether or not this output is connected to a pin. When a match occurs between the TC and MR2  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[9:8]. This bit.." "0: LOW,1: HIGH"
newline
bitfld.long 0x0 1. "EM1,External Match 1. This bit reflects the state of output MAT1  whether or not this output is connected to a pin. When a match occurs between the TC and MR1  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[7:6]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 0. "EM0,External Match 0. This bit reflects the state of output MAT0  whether or not this output is connected to a pin. When a match occurs between the TC and MR0  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[5:4]. This bit.." "0: LOW,1: HIGH"
group.long 0x70++0x7
line.long 0x0 "CTCR,Count Control Register. The CTCR selects between Timer and Counter mode. and in Counter mode selects the signal and edge(s) for counting."
bitfld.long 0x0 5.--7. "SELCC,Edge select. When bit 4 is 1  these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved." "0: Channel 0 Rising Edge. Rising edge of the signal..,1: Channel 0 Falling Edge. Falling edge of the..,2: Channel 1 Rising Edge. Rising edge of the signal..,3: Channel 1 Falling Edge. Falling edge of the..,4: Channel 2 Rising Edge. Rising edge of the signal..,5: Channel 2 Falling Edge. Falling edge of the..,?,?"
bitfld.long 0x0 4. "ENCC,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." "0,1"
newline
bitfld.long 0x0 2.--3. "CINSEL,Count Input Select When bits 1:0 in this register are not 00  these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR  the 3 bits for that input in the Capture Control.." "0: Channel 0. CAPn.0 for CTIMERn,1: 0 in this register are not 00,2: Channel 2. CAPn.2 for CTIMERn,3: Channel 3. CAPn.3 for CTIMERn"
bitfld.long 0x0 0.--1. "CTMODE,Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC)  or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale.." "0: Timer Mode. Incremented every rising APB bus..,1: Counter Mode rising edge. TC is incremented on..,2: Counter Mode falling edge. TC is incremented on..,3: Counter Mode dual edge. TC is incremented on.."
line.long 0x4 "PWMC,PWM Control Register. The PWMCON enables PWM mode for the external match pins."
bitfld.long 0x4 3. "PWMEN3,PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle." "0: Match. CTIMERn_MAT3 is controlled by EM3.,1: PWM. PWM mode is enabled for CT132Bn_MAT3."
bitfld.long 0x4 2. "PWMEN2,PWM mode enable for channel2." "0: Match. CTIMERn_MAT2 is controlled by EM2.,1: PWM. PWM mode is enabled for CTIMERn_MAT2."
newline
bitfld.long 0x4 1. "PWMEN1,PWM mode enable for channel1." "0: Match. CTIMERn_MAT01 is controlled by EM1.,1: PWM. PWM mode is enabled for CTIMERn_MAT1."
bitfld.long 0x4 0. "PWMEN0,PWM mode enable for channel0." "0: Match. CTIMERn_MAT0 is controlled by EM0.,1: PWM. PWM mode is enabled for CTIMERn_MAT0."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x78)++0x3
line.long 0x0 "MSR[$1],Match Shadow Register"
hexmask.long 0x0 0.--31. 1. "SHADOWW,Timer counter match shadow value."
repeat.end
tree.end
tree "CTIMER4"
base ad:0x40049000
group.long 0x0++0x17
line.long 0x0 "IR,Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending."
bitfld.long 0x0 7. "CR3INT,Interrupt flag for capture channel 3 event." "0,1"
bitfld.long 0x0 6. "CR2INT,Interrupt flag for capture channel 2 event." "0,1"
newline
bitfld.long 0x0 5. "CR1INT,Interrupt flag for capture channel 1 event." "0,1"
bitfld.long 0x0 4. "CR0INT,Interrupt flag for capture channel 0 event." "0,1"
newline
bitfld.long 0x0 3. "MR3INT,Interrupt flag for match channel 3." "0,1"
bitfld.long 0x0 2. "MR2INT,Interrupt flag for match channel 2." "0,1"
newline
bitfld.long 0x0 1. "MR1INT,Interrupt flag for match channel 1." "0,1"
bitfld.long 0x0 0. "MR0INT,Interrupt flag for match channel 0." "0,1"
line.long 0x4 "TCR,Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."
bitfld.long 0x4 1. "CRST,Counter reset." "0: Disabled. Do nothing.,1: Enabled. The Timer Counter and the Prescale.."
bitfld.long 0x4 0. "CEN,Counter enable." "0: Disabled.The counters are disabled.,1: Enabled. The Timer Counter and Prescale Counter.."
line.long 0x8 "TC,Timer Counter"
hexmask.long 0x8 0.--31. 1. "TCVAL,Timer counter value."
line.long 0xC "PR,Prescale Register"
hexmask.long 0xC 0.--31. 1. "PRVAL,Prescale counter value."
line.long 0x10 "PC,Prescale Counter"
hexmask.long 0x10 0.--31. 1. "PCVAL,Prescale counter value."
line.long 0x14 "MCR,Match Control Register"
bitfld.long 0x14 27. "MR3RL,Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 26. "MR2RL,Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 25. "MR1RL,Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 24. "MR0RL,Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 11. "MR3S,Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." "0,1"
bitfld.long 0x14 10. "MR3R,Reset on MR3: the TC will be reset if MR3 matches it." "0,1"
newline
bitfld.long 0x14 9. "MR3I,Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC." "0,1"
bitfld.long 0x14 8. "MR2S,Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC." "0,1"
newline
bitfld.long 0x14 7. "MR2R,Reset on MR2: the TC will be reset if MR2 matches it." "0,1"
bitfld.long 0x14 6. "MR2I,Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC." "0,1"
newline
bitfld.long 0x14 5. "MR1S,Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." "0,1"
bitfld.long 0x14 4. "MR1R,Reset on MR1: the TC will be reset if MR1 matches it." "0,1"
newline
bitfld.long 0x14 3. "MR1I,Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC." "0,1"
bitfld.long 0x14 2. "MR0S,Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." "0,1"
newline
bitfld.long 0x14 1. "MR0R,Reset on MR0: the TC will be reset if MR0 matches it." "0,1"
bitfld.long 0x14 0. "MR0I,Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC." "0,1"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x18)++0x3
line.long 0x0 "MR[$1],Match Register . MR can be enabled through the MCR to reset the TC. stop both the TC and PC. and/or generate an interrupt every time MR matches the TC."
hexmask.long 0x0 0.--31. 1. "MATCH,Timer counter match value."
repeat.end
group.long 0x28++0x3
line.long 0x0 "CCR,Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."
bitfld.long 0x0 11. "CAP3I,Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt." "0,1"
bitfld.long 0x0 10. "CAP3FE,Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 9. "CAP3RE,Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 8. "CAP2I,Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 7. "CAP2FE,Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 6. "CAP2RE,Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 5. "CAP1I,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt." "0,1"
bitfld.long 0x0 4. "CAP1FE,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 3. "CAP1RE,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 2. "CAP0I,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 1. "CAP0FE,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 0. "CAP0RE,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x2C)++0x3
line.long 0x0 "CR[$1],Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input."
hexmask.long 0x0 0.--31. 1. "CAP,Timer counter capture value."
repeat.end
group.long 0x3C++0x3
line.long 0x0 "EMR,External Match Register. The EMR controls the match function and the external match pins."
bitfld.long 0x0 10.--11. "EMC3,External Match Control 3. Determines the functionality of External Match 3." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 8.--9. "EMC2,External Match Control 2. Determines the functionality of External Match 2." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 6.--7. "EMC1,External Match Control 1. Determines the functionality of External Match 1." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 4.--5. "EMC0,External Match Control 0. Determines the functionality of External Match 0." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 3. "EM3,External Match 3. This bit reflects the state of output MAT3  whether or not this output is connected to a pin. When a match occurs between the TC and MR3  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by MR[11:10]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 2. "EM2,External Match 2. This bit reflects the state of output MAT2  whether or not this output is connected to a pin. When a match occurs between the TC and MR2  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[9:8]. This bit.." "0: LOW,1: HIGH"
newline
bitfld.long 0x0 1. "EM1,External Match 1. This bit reflects the state of output MAT1  whether or not this output is connected to a pin. When a match occurs between the TC and MR1  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[7:6]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 0. "EM0,External Match 0. This bit reflects the state of output MAT0  whether or not this output is connected to a pin. When a match occurs between the TC and MR0  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[5:4]. This bit.." "0: LOW,1: HIGH"
group.long 0x70++0x7
line.long 0x0 "CTCR,Count Control Register. The CTCR selects between Timer and Counter mode. and in Counter mode selects the signal and edge(s) for counting."
bitfld.long 0x0 5.--7. "SELCC,Edge select. When bit 4 is 1  these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved." "0: Channel 0 Rising Edge. Rising edge of the signal..,1: Channel 0 Falling Edge. Falling edge of the..,2: Channel 1 Rising Edge. Rising edge of the signal..,3: Channel 1 Falling Edge. Falling edge of the..,4: Channel 2 Rising Edge. Rising edge of the signal..,5: Channel 2 Falling Edge. Falling edge of the..,?,?"
bitfld.long 0x0 4. "ENCC,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." "0,1"
newline
bitfld.long 0x0 2.--3. "CINSEL,Count Input Select When bits 1:0 in this register are not 00  these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR  the 3 bits for that input in the Capture Control.." "0: Channel 0. CAPn.0 for CTIMERn,1: 0 in this register are not 00,2: Channel 2. CAPn.2 for CTIMERn,3: Channel 3. CAPn.3 for CTIMERn"
bitfld.long 0x0 0.--1. "CTMODE,Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC)  or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale.." "0: Timer Mode. Incremented every rising APB bus..,1: Counter Mode rising edge. TC is incremented on..,2: Counter Mode falling edge. TC is incremented on..,3: Counter Mode dual edge. TC is incremented on.."
line.long 0x4 "PWMC,PWM Control Register. The PWMCON enables PWM mode for the external match pins."
bitfld.long 0x4 3. "PWMEN3,PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle." "0: Match. CTIMERn_MAT3 is controlled by EM3.,1: PWM. PWM mode is enabled for CT132Bn_MAT3."
bitfld.long 0x4 2. "PWMEN2,PWM mode enable for channel2." "0: Match. CTIMERn_MAT2 is controlled by EM2.,1: PWM. PWM mode is enabled for CTIMERn_MAT2."
newline
bitfld.long 0x4 1. "PWMEN1,PWM mode enable for channel1." "0: Match. CTIMERn_MAT01 is controlled by EM1.,1: PWM. PWM mode is enabled for CTIMERn_MAT1."
bitfld.long 0x4 0. "PWMEN0,PWM mode enable for channel0." "0: Match. CTIMERn_MAT0 is controlled by EM0.,1: PWM. PWM mode is enabled for CTIMERn_MAT0."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x78)++0x3
line.long 0x0 "MSR[$1],Match Shadow Register"
hexmask.long 0x0 0.--31. 1. "SHADOWW,Timer counter match shadow value."
repeat.end
tree.end
endif
sif (cpuis("LPC54607*"))
tree "CTIMER0"
base ad:0x40008000
group.long 0x0++0x17
line.long 0x0 "IR,Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending."
bitfld.long 0x0 7. "CR3INT,Interrupt flag for capture channel 3 event." "0,1"
bitfld.long 0x0 6. "CR2INT,Interrupt flag for capture channel 2 event." "0,1"
newline
bitfld.long 0x0 5. "CR1INT,Interrupt flag for capture channel 1 event." "0,1"
bitfld.long 0x0 4. "CR0INT,Interrupt flag for capture channel 0 event." "0,1"
newline
bitfld.long 0x0 3. "MR3INT,Interrupt flag for match channel 3." "0,1"
bitfld.long 0x0 2. "MR2INT,Interrupt flag for match channel 2." "0,1"
newline
bitfld.long 0x0 1. "MR1INT,Interrupt flag for match channel 1." "0,1"
bitfld.long 0x0 0. "MR0INT,Interrupt flag for match channel 0." "0,1"
line.long 0x4 "TCR,Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."
bitfld.long 0x4 1. "CRST,Counter reset." "0: Disabled. Do nothing.,1: Enabled. The Timer Counter and the Prescale.."
bitfld.long 0x4 0. "CEN,Counter enable." "0: Disabled.The counters are disabled.,1: Enabled. The Timer Counter and Prescale Counter.."
line.long 0x8 "TC,Timer Counter"
hexmask.long 0x8 0.--31. 1. "TCVAL,Timer counter value."
line.long 0xC "PR,Prescale Register"
hexmask.long 0xC 0.--31. 1. "PRVAL,Prescale counter value."
line.long 0x10 "PC,Prescale Counter"
hexmask.long 0x10 0.--31. 1. "PCVAL,Prescale counter value."
line.long 0x14 "MCR,Match Control Register"
bitfld.long 0x14 27. "MR3RL,Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 26. "MR2RL,Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 25. "MR1RL,Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 24. "MR0RL,Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 11. "MR3S,Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." "0,1"
bitfld.long 0x14 10. "MR3R,Reset on MR3: the TC will be reset if MR3 matches it." "0,1"
newline
bitfld.long 0x14 9. "MR3I,Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC." "0,1"
bitfld.long 0x14 8. "MR2S,Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC." "0,1"
newline
bitfld.long 0x14 7. "MR2R,Reset on MR2: the TC will be reset if MR2 matches it." "0,1"
bitfld.long 0x14 6. "MR2I,Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC." "0,1"
newline
bitfld.long 0x14 5. "MR1S,Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." "0,1"
bitfld.long 0x14 4. "MR1R,Reset on MR1: the TC will be reset if MR1 matches it." "0,1"
newline
bitfld.long 0x14 3. "MR1I,Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC." "0,1"
bitfld.long 0x14 2. "MR0S,Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." "0,1"
newline
bitfld.long 0x14 1. "MR0R,Reset on MR0: the TC will be reset if MR0 matches it." "0,1"
bitfld.long 0x14 0. "MR0I,Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC." "0,1"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x18)++0x3
line.long 0x0 "MR[$1],Match Register . MR can be enabled through the MCR to reset the TC. stop both the TC and PC. and/or generate an interrupt every time MR matches the TC."
hexmask.long 0x0 0.--31. 1. "MATCH,Timer counter match value."
repeat.end
group.long 0x28++0x3
line.long 0x0 "CCR,Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."
bitfld.long 0x0 11. "CAP3I,Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt." "0,1"
bitfld.long 0x0 10. "CAP3FE,Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 9. "CAP3RE,Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 8. "CAP2I,Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 7. "CAP2FE,Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 6. "CAP2RE,Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 5. "CAP1I,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt." "0,1"
bitfld.long 0x0 4. "CAP1FE,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 3. "CAP1RE,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 2. "CAP0I,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 1. "CAP0FE,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 0. "CAP0RE,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x2C)++0x3
line.long 0x0 "CR[$1],Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input."
hexmask.long 0x0 0.--31. 1. "CAP,Timer counter capture value."
repeat.end
group.long 0x3C++0x3
line.long 0x0 "EMR,External Match Register. The EMR controls the match function and the external match pins."
bitfld.long 0x0 10.--11. "EMC3,External Match Control 3. Determines the functionality of External Match 3." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 8.--9. "EMC2,External Match Control 2. Determines the functionality of External Match 2." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 6.--7. "EMC1,External Match Control 1. Determines the functionality of External Match 1." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 4.--5. "EMC0,External Match Control 0. Determines the functionality of External Match 0." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 3. "EM3,External Match 3. This bit reflects the state of output MAT3  whether or not this output is connected to a pin. When a match occurs between the TC and MR3  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by MR[11:10]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 2. "EM2,External Match 2. This bit reflects the state of output MAT2  whether or not this output is connected to a pin. When a match occurs between the TC and MR2  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[9:8]. This bit.." "0: LOW,1: HIGH"
newline
bitfld.long 0x0 1. "EM1,External Match 1. This bit reflects the state of output MAT1  whether or not this output is connected to a pin. When a match occurs between the TC and MR1  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[7:6]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 0. "EM0,External Match 0. This bit reflects the state of output MAT0  whether or not this output is connected to a pin. When a match occurs between the TC and MR0  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[5:4]. This bit.." "0: LOW,1: HIGH"
group.long 0x70++0x7
line.long 0x0 "CTCR,Count Control Register. The CTCR selects between Timer and Counter mode. and in Counter mode selects the signal and edge(s) for counting."
bitfld.long 0x0 5.--7. "SELCC,Edge select. When bit 4 is 1  these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved." "0: Channel 0 Rising Edge. Rising edge of the signal..,1: Channel 0 Falling Edge. Falling edge of the..,2: Channel 1 Rising Edge. Rising edge of the signal..,3: Channel 1 Falling Edge. Falling edge of the..,4: Channel 2 Rising Edge. Rising edge of the signal..,5: Channel 2 Falling Edge. Falling edge of the..,?,?"
bitfld.long 0x0 4. "ENCC,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." "0,1"
newline
bitfld.long 0x0 2.--3. "CINSEL,Count Input Select When bits 1:0 in this register are not 00  these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR  the 3 bits for that input in the Capture Control.." "0: Channel 0. CAPn.0 for CTIMERn,1: 0 in this register are not 00,2: Channel 2. CAPn.2 for CTIMERn,3: Channel 3. CAPn.3 for CTIMERn"
bitfld.long 0x0 0.--1. "CTMODE,Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC)  or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale.." "0: Timer Mode. Incremented every rising APB bus..,1: Counter Mode rising edge. TC is incremented on..,2: Counter Mode falling edge. TC is incremented on..,3: Counter Mode dual edge. TC is incremented on.."
line.long 0x4 "PWMC,PWM Control Register. The PWMCON enables PWM mode for the external match pins."
bitfld.long 0x4 3. "PWMEN3,PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle." "0: Match. CTIMERn_MAT3 is controlled by EM3.,1: PWM. PWM mode is enabled for CT132Bn_MAT3."
bitfld.long 0x4 2. "PWMEN2,PWM mode enable for channel2." "0: Match. CTIMERn_MAT2 is controlled by EM2.,1: PWM. PWM mode is enabled for CTIMERn_MAT2."
newline
bitfld.long 0x4 1. "PWMEN1,PWM mode enable for channel1." "0: Match. CTIMERn_MAT01 is controlled by EM1.,1: PWM. PWM mode is enabled for CTIMERn_MAT1."
bitfld.long 0x4 0. "PWMEN0,PWM mode enable for channel0." "0: Match. CTIMERn_MAT0 is controlled by EM0.,1: PWM. PWM mode is enabled for CTIMERn_MAT0."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x78)++0x3
line.long 0x0 "MSR[$1],Match Shadow Register"
hexmask.long 0x0 0.--31. 1. "SHADOWW,Timer counter match shadow value."
repeat.end
tree.end
tree "CTIMER1"
base ad:0x40009000
group.long 0x0++0x17
line.long 0x0 "IR,Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending."
bitfld.long 0x0 7. "CR3INT,Interrupt flag for capture channel 3 event." "0,1"
bitfld.long 0x0 6. "CR2INT,Interrupt flag for capture channel 2 event." "0,1"
newline
bitfld.long 0x0 5. "CR1INT,Interrupt flag for capture channel 1 event." "0,1"
bitfld.long 0x0 4. "CR0INT,Interrupt flag for capture channel 0 event." "0,1"
newline
bitfld.long 0x0 3. "MR3INT,Interrupt flag for match channel 3." "0,1"
bitfld.long 0x0 2. "MR2INT,Interrupt flag for match channel 2." "0,1"
newline
bitfld.long 0x0 1. "MR1INT,Interrupt flag for match channel 1." "0,1"
bitfld.long 0x0 0. "MR0INT,Interrupt flag for match channel 0." "0,1"
line.long 0x4 "TCR,Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."
bitfld.long 0x4 1. "CRST,Counter reset." "0: Disabled. Do nothing.,1: Enabled. The Timer Counter and the Prescale.."
bitfld.long 0x4 0. "CEN,Counter enable." "0: Disabled.The counters are disabled.,1: Enabled. The Timer Counter and Prescale Counter.."
line.long 0x8 "TC,Timer Counter"
hexmask.long 0x8 0.--31. 1. "TCVAL,Timer counter value."
line.long 0xC "PR,Prescale Register"
hexmask.long 0xC 0.--31. 1. "PRVAL,Prescale counter value."
line.long 0x10 "PC,Prescale Counter"
hexmask.long 0x10 0.--31. 1. "PCVAL,Prescale counter value."
line.long 0x14 "MCR,Match Control Register"
bitfld.long 0x14 27. "MR3RL,Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 26. "MR2RL,Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 25. "MR1RL,Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 24. "MR0RL,Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 11. "MR3S,Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." "0,1"
bitfld.long 0x14 10. "MR3R,Reset on MR3: the TC will be reset if MR3 matches it." "0,1"
newline
bitfld.long 0x14 9. "MR3I,Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC." "0,1"
bitfld.long 0x14 8. "MR2S,Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC." "0,1"
newline
bitfld.long 0x14 7. "MR2R,Reset on MR2: the TC will be reset if MR2 matches it." "0,1"
bitfld.long 0x14 6. "MR2I,Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC." "0,1"
newline
bitfld.long 0x14 5. "MR1S,Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." "0,1"
bitfld.long 0x14 4. "MR1R,Reset on MR1: the TC will be reset if MR1 matches it." "0,1"
newline
bitfld.long 0x14 3. "MR1I,Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC." "0,1"
bitfld.long 0x14 2. "MR0S,Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." "0,1"
newline
bitfld.long 0x14 1. "MR0R,Reset on MR0: the TC will be reset if MR0 matches it." "0,1"
bitfld.long 0x14 0. "MR0I,Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC." "0,1"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x18)++0x3
line.long 0x0 "MR[$1],Match Register . MR can be enabled through the MCR to reset the TC. stop both the TC and PC. and/or generate an interrupt every time MR matches the TC."
hexmask.long 0x0 0.--31. 1. "MATCH,Timer counter match value."
repeat.end
group.long 0x28++0x3
line.long 0x0 "CCR,Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."
bitfld.long 0x0 11. "CAP3I,Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt." "0,1"
bitfld.long 0x0 10. "CAP3FE,Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 9. "CAP3RE,Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 8. "CAP2I,Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 7. "CAP2FE,Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 6. "CAP2RE,Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 5. "CAP1I,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt." "0,1"
bitfld.long 0x0 4. "CAP1FE,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 3. "CAP1RE,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 2. "CAP0I,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 1. "CAP0FE,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 0. "CAP0RE,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x2C)++0x3
line.long 0x0 "CR[$1],Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input."
hexmask.long 0x0 0.--31. 1. "CAP,Timer counter capture value."
repeat.end
group.long 0x3C++0x3
line.long 0x0 "EMR,External Match Register. The EMR controls the match function and the external match pins."
bitfld.long 0x0 10.--11. "EMC3,External Match Control 3. Determines the functionality of External Match 3." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 8.--9. "EMC2,External Match Control 2. Determines the functionality of External Match 2." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 6.--7. "EMC1,External Match Control 1. Determines the functionality of External Match 1." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 4.--5. "EMC0,External Match Control 0. Determines the functionality of External Match 0." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 3. "EM3,External Match 3. This bit reflects the state of output MAT3  whether or not this output is connected to a pin. When a match occurs between the TC and MR3  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by MR[11:10]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 2. "EM2,External Match 2. This bit reflects the state of output MAT2  whether or not this output is connected to a pin. When a match occurs between the TC and MR2  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[9:8]. This bit.." "0: LOW,1: HIGH"
newline
bitfld.long 0x0 1. "EM1,External Match 1. This bit reflects the state of output MAT1  whether or not this output is connected to a pin. When a match occurs between the TC and MR1  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[7:6]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 0. "EM0,External Match 0. This bit reflects the state of output MAT0  whether or not this output is connected to a pin. When a match occurs between the TC and MR0  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[5:4]. This bit.." "0: LOW,1: HIGH"
group.long 0x70++0x7
line.long 0x0 "CTCR,Count Control Register. The CTCR selects between Timer and Counter mode. and in Counter mode selects the signal and edge(s) for counting."
bitfld.long 0x0 5.--7. "SELCC,Edge select. When bit 4 is 1  these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved." "0: Channel 0 Rising Edge. Rising edge of the signal..,1: Channel 0 Falling Edge. Falling edge of the..,2: Channel 1 Rising Edge. Rising edge of the signal..,3: Channel 1 Falling Edge. Falling edge of the..,4: Channel 2 Rising Edge. Rising edge of the signal..,5: Channel 2 Falling Edge. Falling edge of the..,?,?"
bitfld.long 0x0 4. "ENCC,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." "0,1"
newline
bitfld.long 0x0 2.--3. "CINSEL,Count Input Select When bits 1:0 in this register are not 00  these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR  the 3 bits for that input in the Capture Control.." "0: Channel 0. CAPn.0 for CTIMERn,1: 0 in this register are not 00,2: Channel 2. CAPn.2 for CTIMERn,3: Channel 3. CAPn.3 for CTIMERn"
bitfld.long 0x0 0.--1. "CTMODE,Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC)  or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale.." "0: Timer Mode. Incremented every rising APB bus..,1: Counter Mode rising edge. TC is incremented on..,2: Counter Mode falling edge. TC is incremented on..,3: Counter Mode dual edge. TC is incremented on.."
line.long 0x4 "PWMC,PWM Control Register. The PWMCON enables PWM mode for the external match pins."
bitfld.long 0x4 3. "PWMEN3,PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle." "0: Match. CTIMERn_MAT3 is controlled by EM3.,1: PWM. PWM mode is enabled for CT132Bn_MAT3."
bitfld.long 0x4 2. "PWMEN2,PWM mode enable for channel2." "0: Match. CTIMERn_MAT2 is controlled by EM2.,1: PWM. PWM mode is enabled for CTIMERn_MAT2."
newline
bitfld.long 0x4 1. "PWMEN1,PWM mode enable for channel1." "0: Match. CTIMERn_MAT01 is controlled by EM1.,1: PWM. PWM mode is enabled for CTIMERn_MAT1."
bitfld.long 0x4 0. "PWMEN0,PWM mode enable for channel0." "0: Match. CTIMERn_MAT0 is controlled by EM0.,1: PWM. PWM mode is enabled for CTIMERn_MAT0."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x78)++0x3
line.long 0x0 "MSR[$1],Match Shadow Register"
hexmask.long 0x0 0.--31. 1. "SHADOWW,Timer counter match shadow value."
repeat.end
tree.end
tree "CTIMER2"
base ad:0x40028000
group.long 0x0++0x17
line.long 0x0 "IR,Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending."
bitfld.long 0x0 7. "CR3INT,Interrupt flag for capture channel 3 event." "0,1"
bitfld.long 0x0 6. "CR2INT,Interrupt flag for capture channel 2 event." "0,1"
newline
bitfld.long 0x0 5. "CR1INT,Interrupt flag for capture channel 1 event." "0,1"
bitfld.long 0x0 4. "CR0INT,Interrupt flag for capture channel 0 event." "0,1"
newline
bitfld.long 0x0 3. "MR3INT,Interrupt flag for match channel 3." "0,1"
bitfld.long 0x0 2. "MR2INT,Interrupt flag for match channel 2." "0,1"
newline
bitfld.long 0x0 1. "MR1INT,Interrupt flag for match channel 1." "0,1"
bitfld.long 0x0 0. "MR0INT,Interrupt flag for match channel 0." "0,1"
line.long 0x4 "TCR,Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."
bitfld.long 0x4 1. "CRST,Counter reset." "0: Disabled. Do nothing.,1: Enabled. The Timer Counter and the Prescale.."
bitfld.long 0x4 0. "CEN,Counter enable." "0: Disabled.The counters are disabled.,1: Enabled. The Timer Counter and Prescale Counter.."
line.long 0x8 "TC,Timer Counter"
hexmask.long 0x8 0.--31. 1. "TCVAL,Timer counter value."
line.long 0xC "PR,Prescale Register"
hexmask.long 0xC 0.--31. 1. "PRVAL,Prescale counter value."
line.long 0x10 "PC,Prescale Counter"
hexmask.long 0x10 0.--31. 1. "PCVAL,Prescale counter value."
line.long 0x14 "MCR,Match Control Register"
bitfld.long 0x14 27. "MR3RL,Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 26. "MR2RL,Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 25. "MR1RL,Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 24. "MR0RL,Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 11. "MR3S,Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." "0,1"
bitfld.long 0x14 10. "MR3R,Reset on MR3: the TC will be reset if MR3 matches it." "0,1"
newline
bitfld.long 0x14 9. "MR3I,Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC." "0,1"
bitfld.long 0x14 8. "MR2S,Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC." "0,1"
newline
bitfld.long 0x14 7. "MR2R,Reset on MR2: the TC will be reset if MR2 matches it." "0,1"
bitfld.long 0x14 6. "MR2I,Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC." "0,1"
newline
bitfld.long 0x14 5. "MR1S,Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." "0,1"
bitfld.long 0x14 4. "MR1R,Reset on MR1: the TC will be reset if MR1 matches it." "0,1"
newline
bitfld.long 0x14 3. "MR1I,Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC." "0,1"
bitfld.long 0x14 2. "MR0S,Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." "0,1"
newline
bitfld.long 0x14 1. "MR0R,Reset on MR0: the TC will be reset if MR0 matches it." "0,1"
bitfld.long 0x14 0. "MR0I,Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC." "0,1"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x18)++0x3
line.long 0x0 "MR[$1],Match Register . MR can be enabled through the MCR to reset the TC. stop both the TC and PC. and/or generate an interrupt every time MR matches the TC."
hexmask.long 0x0 0.--31. 1. "MATCH,Timer counter match value."
repeat.end
group.long 0x28++0x3
line.long 0x0 "CCR,Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."
bitfld.long 0x0 11. "CAP3I,Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt." "0,1"
bitfld.long 0x0 10. "CAP3FE,Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 9. "CAP3RE,Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 8. "CAP2I,Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 7. "CAP2FE,Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 6. "CAP2RE,Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 5. "CAP1I,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt." "0,1"
bitfld.long 0x0 4. "CAP1FE,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 3. "CAP1RE,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 2. "CAP0I,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 1. "CAP0FE,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 0. "CAP0RE,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x2C)++0x3
line.long 0x0 "CR[$1],Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input."
hexmask.long 0x0 0.--31. 1. "CAP,Timer counter capture value."
repeat.end
group.long 0x3C++0x3
line.long 0x0 "EMR,External Match Register. The EMR controls the match function and the external match pins."
bitfld.long 0x0 10.--11. "EMC3,External Match Control 3. Determines the functionality of External Match 3." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 8.--9. "EMC2,External Match Control 2. Determines the functionality of External Match 2." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 6.--7. "EMC1,External Match Control 1. Determines the functionality of External Match 1." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 4.--5. "EMC0,External Match Control 0. Determines the functionality of External Match 0." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 3. "EM3,External Match 3. This bit reflects the state of output MAT3  whether or not this output is connected to a pin. When a match occurs between the TC and MR3  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by MR[11:10]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 2. "EM2,External Match 2. This bit reflects the state of output MAT2  whether or not this output is connected to a pin. When a match occurs between the TC and MR2  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[9:8]. This bit.." "0: LOW,1: HIGH"
newline
bitfld.long 0x0 1. "EM1,External Match 1. This bit reflects the state of output MAT1  whether or not this output is connected to a pin. When a match occurs between the TC and MR1  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[7:6]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 0. "EM0,External Match 0. This bit reflects the state of output MAT0  whether or not this output is connected to a pin. When a match occurs between the TC and MR0  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[5:4]. This bit.." "0: LOW,1: HIGH"
group.long 0x70++0x7
line.long 0x0 "CTCR,Count Control Register. The CTCR selects between Timer and Counter mode. and in Counter mode selects the signal and edge(s) for counting."
bitfld.long 0x0 5.--7. "SELCC,Edge select. When bit 4 is 1  these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved." "0: Channel 0 Rising Edge. Rising edge of the signal..,1: Channel 0 Falling Edge. Falling edge of the..,2: Channel 1 Rising Edge. Rising edge of the signal..,3: Channel 1 Falling Edge. Falling edge of the..,4: Channel 2 Rising Edge. Rising edge of the signal..,5: Channel 2 Falling Edge. Falling edge of the..,?,?"
bitfld.long 0x0 4. "ENCC,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." "0,1"
newline
bitfld.long 0x0 2.--3. "CINSEL,Count Input Select When bits 1:0 in this register are not 00  these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR  the 3 bits for that input in the Capture Control.." "0: Channel 0. CAPn.0 for CTIMERn,1: 0 in this register are not 00,2: Channel 2. CAPn.2 for CTIMERn,3: Channel 3. CAPn.3 for CTIMERn"
bitfld.long 0x0 0.--1. "CTMODE,Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC)  or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale.." "0: Timer Mode. Incremented every rising APB bus..,1: Counter Mode rising edge. TC is incremented on..,2: Counter Mode falling edge. TC is incremented on..,3: Counter Mode dual edge. TC is incremented on.."
line.long 0x4 "PWMC,PWM Control Register. The PWMCON enables PWM mode for the external match pins."
bitfld.long 0x4 3. "PWMEN3,PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle." "0: Match. CTIMERn_MAT3 is controlled by EM3.,1: PWM. PWM mode is enabled for CT132Bn_MAT3."
bitfld.long 0x4 2. "PWMEN2,PWM mode enable for channel2." "0: Match. CTIMERn_MAT2 is controlled by EM2.,1: PWM. PWM mode is enabled for CTIMERn_MAT2."
newline
bitfld.long 0x4 1. "PWMEN1,PWM mode enable for channel1." "0: Match. CTIMERn_MAT01 is controlled by EM1.,1: PWM. PWM mode is enabled for CTIMERn_MAT1."
bitfld.long 0x4 0. "PWMEN0,PWM mode enable for channel0." "0: Match. CTIMERn_MAT0 is controlled by EM0.,1: PWM. PWM mode is enabled for CTIMERn_MAT0."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x78)++0x3
line.long 0x0 "MSR[$1],Match Shadow Register"
hexmask.long 0x0 0.--31. 1. "SHADOWW,Timer counter match shadow value."
repeat.end
tree.end
tree "CTIMER3"
base ad:0x40048000
group.long 0x0++0x17
line.long 0x0 "IR,Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending."
bitfld.long 0x0 7. "CR3INT,Interrupt flag for capture channel 3 event." "0,1"
bitfld.long 0x0 6. "CR2INT,Interrupt flag for capture channel 2 event." "0,1"
newline
bitfld.long 0x0 5. "CR1INT,Interrupt flag for capture channel 1 event." "0,1"
bitfld.long 0x0 4. "CR0INT,Interrupt flag for capture channel 0 event." "0,1"
newline
bitfld.long 0x0 3. "MR3INT,Interrupt flag for match channel 3." "0,1"
bitfld.long 0x0 2. "MR2INT,Interrupt flag for match channel 2." "0,1"
newline
bitfld.long 0x0 1. "MR1INT,Interrupt flag for match channel 1." "0,1"
bitfld.long 0x0 0. "MR0INT,Interrupt flag for match channel 0." "0,1"
line.long 0x4 "TCR,Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."
bitfld.long 0x4 1. "CRST,Counter reset." "0: Disabled. Do nothing.,1: Enabled. The Timer Counter and the Prescale.."
bitfld.long 0x4 0. "CEN,Counter enable." "0: Disabled.The counters are disabled.,1: Enabled. The Timer Counter and Prescale Counter.."
line.long 0x8 "TC,Timer Counter"
hexmask.long 0x8 0.--31. 1. "TCVAL,Timer counter value."
line.long 0xC "PR,Prescale Register"
hexmask.long 0xC 0.--31. 1. "PRVAL,Prescale counter value."
line.long 0x10 "PC,Prescale Counter"
hexmask.long 0x10 0.--31. 1. "PCVAL,Prescale counter value."
line.long 0x14 "MCR,Match Control Register"
bitfld.long 0x14 27. "MR3RL,Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 26. "MR2RL,Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 25. "MR1RL,Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 24. "MR0RL,Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 11. "MR3S,Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." "0,1"
bitfld.long 0x14 10. "MR3R,Reset on MR3: the TC will be reset if MR3 matches it." "0,1"
newline
bitfld.long 0x14 9. "MR3I,Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC." "0,1"
bitfld.long 0x14 8. "MR2S,Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC." "0,1"
newline
bitfld.long 0x14 7. "MR2R,Reset on MR2: the TC will be reset if MR2 matches it." "0,1"
bitfld.long 0x14 6. "MR2I,Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC." "0,1"
newline
bitfld.long 0x14 5. "MR1S,Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." "0,1"
bitfld.long 0x14 4. "MR1R,Reset on MR1: the TC will be reset if MR1 matches it." "0,1"
newline
bitfld.long 0x14 3. "MR1I,Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC." "0,1"
bitfld.long 0x14 2. "MR0S,Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." "0,1"
newline
bitfld.long 0x14 1. "MR0R,Reset on MR0: the TC will be reset if MR0 matches it." "0,1"
bitfld.long 0x14 0. "MR0I,Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC." "0,1"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x18)++0x3
line.long 0x0 "MR[$1],Match Register . MR can be enabled through the MCR to reset the TC. stop both the TC and PC. and/or generate an interrupt every time MR matches the TC."
hexmask.long 0x0 0.--31. 1. "MATCH,Timer counter match value."
repeat.end
group.long 0x28++0x3
line.long 0x0 "CCR,Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."
bitfld.long 0x0 11. "CAP3I,Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt." "0,1"
bitfld.long 0x0 10. "CAP3FE,Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 9. "CAP3RE,Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 8. "CAP2I,Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 7. "CAP2FE,Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 6. "CAP2RE,Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 5. "CAP1I,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt." "0,1"
bitfld.long 0x0 4. "CAP1FE,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 3. "CAP1RE,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 2. "CAP0I,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 1. "CAP0FE,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 0. "CAP0RE,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x2C)++0x3
line.long 0x0 "CR[$1],Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input."
hexmask.long 0x0 0.--31. 1. "CAP,Timer counter capture value."
repeat.end
group.long 0x3C++0x3
line.long 0x0 "EMR,External Match Register. The EMR controls the match function and the external match pins."
bitfld.long 0x0 10.--11. "EMC3,External Match Control 3. Determines the functionality of External Match 3." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 8.--9. "EMC2,External Match Control 2. Determines the functionality of External Match 2." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 6.--7. "EMC1,External Match Control 1. Determines the functionality of External Match 1." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 4.--5. "EMC0,External Match Control 0. Determines the functionality of External Match 0." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 3. "EM3,External Match 3. This bit reflects the state of output MAT3  whether or not this output is connected to a pin. When a match occurs between the TC and MR3  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by MR[11:10]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 2. "EM2,External Match 2. This bit reflects the state of output MAT2  whether or not this output is connected to a pin. When a match occurs between the TC and MR2  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[9:8]. This bit.." "0: LOW,1: HIGH"
newline
bitfld.long 0x0 1. "EM1,External Match 1. This bit reflects the state of output MAT1  whether or not this output is connected to a pin. When a match occurs between the TC and MR1  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[7:6]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 0. "EM0,External Match 0. This bit reflects the state of output MAT0  whether or not this output is connected to a pin. When a match occurs between the TC and MR0  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[5:4]. This bit.." "0: LOW,1: HIGH"
group.long 0x70++0x7
line.long 0x0 "CTCR,Count Control Register. The CTCR selects between Timer and Counter mode. and in Counter mode selects the signal and edge(s) for counting."
bitfld.long 0x0 5.--7. "SELCC,Edge select. When bit 4 is 1  these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved." "0: Channel 0 Rising Edge. Rising edge of the signal..,1: Channel 0 Falling Edge. Falling edge of the..,2: Channel 1 Rising Edge. Rising edge of the signal..,3: Channel 1 Falling Edge. Falling edge of the..,4: Channel 2 Rising Edge. Rising edge of the signal..,5: Channel 2 Falling Edge. Falling edge of the..,?,?"
bitfld.long 0x0 4. "ENCC,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." "0,1"
newline
bitfld.long 0x0 2.--3. "CINSEL,Count Input Select When bits 1:0 in this register are not 00  these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR  the 3 bits for that input in the Capture Control.." "0: Channel 0. CAPn.0 for CTIMERn,1: 0 in this register are not 00,2: Channel 2. CAPn.2 for CTIMERn,3: Channel 3. CAPn.3 for CTIMERn"
bitfld.long 0x0 0.--1. "CTMODE,Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC)  or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale.." "0: Timer Mode. Incremented every rising APB bus..,1: Counter Mode rising edge. TC is incremented on..,2: Counter Mode falling edge. TC is incremented on..,3: Counter Mode dual edge. TC is incremented on.."
line.long 0x4 "PWMC,PWM Control Register. The PWMCON enables PWM mode for the external match pins."
bitfld.long 0x4 3. "PWMEN3,PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle." "0: Match. CTIMERn_MAT3 is controlled by EM3.,1: PWM. PWM mode is enabled for CT132Bn_MAT3."
bitfld.long 0x4 2. "PWMEN2,PWM mode enable for channel2." "0: Match. CTIMERn_MAT2 is controlled by EM2.,1: PWM. PWM mode is enabled for CTIMERn_MAT2."
newline
bitfld.long 0x4 1. "PWMEN1,PWM mode enable for channel1." "0: Match. CTIMERn_MAT01 is controlled by EM1.,1: PWM. PWM mode is enabled for CTIMERn_MAT1."
bitfld.long 0x4 0. "PWMEN0,PWM mode enable for channel0." "0: Match. CTIMERn_MAT0 is controlled by EM0.,1: PWM. PWM mode is enabled for CTIMERn_MAT0."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x78)++0x3
line.long 0x0 "MSR[$1],Match Shadow Register"
hexmask.long 0x0 0.--31. 1. "SHADOWW,Timer counter match shadow value."
repeat.end
tree.end
tree "CTIMER4"
base ad:0x40049000
group.long 0x0++0x17
line.long 0x0 "IR,Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending."
bitfld.long 0x0 7. "CR3INT,Interrupt flag for capture channel 3 event." "0,1"
bitfld.long 0x0 6. "CR2INT,Interrupt flag for capture channel 2 event." "0,1"
newline
bitfld.long 0x0 5. "CR1INT,Interrupt flag for capture channel 1 event." "0,1"
bitfld.long 0x0 4. "CR0INT,Interrupt flag for capture channel 0 event." "0,1"
newline
bitfld.long 0x0 3. "MR3INT,Interrupt flag for match channel 3." "0,1"
bitfld.long 0x0 2. "MR2INT,Interrupt flag for match channel 2." "0,1"
newline
bitfld.long 0x0 1. "MR1INT,Interrupt flag for match channel 1." "0,1"
bitfld.long 0x0 0. "MR0INT,Interrupt flag for match channel 0." "0,1"
line.long 0x4 "TCR,Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."
bitfld.long 0x4 1. "CRST,Counter reset." "0: Disabled. Do nothing.,1: Enabled. The Timer Counter and the Prescale.."
bitfld.long 0x4 0. "CEN,Counter enable." "0: Disabled.The counters are disabled.,1: Enabled. The Timer Counter and Prescale Counter.."
line.long 0x8 "TC,Timer Counter"
hexmask.long 0x8 0.--31. 1. "TCVAL,Timer counter value."
line.long 0xC "PR,Prescale Register"
hexmask.long 0xC 0.--31. 1. "PRVAL,Prescale counter value."
line.long 0x10 "PC,Prescale Counter"
hexmask.long 0x10 0.--31. 1. "PCVAL,Prescale counter value."
line.long 0x14 "MCR,Match Control Register"
bitfld.long 0x14 27. "MR3RL,Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 26. "MR2RL,Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 25. "MR1RL,Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 24. "MR0RL,Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 11. "MR3S,Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." "0,1"
bitfld.long 0x14 10. "MR3R,Reset on MR3: the TC will be reset if MR3 matches it." "0,1"
newline
bitfld.long 0x14 9. "MR3I,Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC." "0,1"
bitfld.long 0x14 8. "MR2S,Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC." "0,1"
newline
bitfld.long 0x14 7. "MR2R,Reset on MR2: the TC will be reset if MR2 matches it." "0,1"
bitfld.long 0x14 6. "MR2I,Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC." "0,1"
newline
bitfld.long 0x14 5. "MR1S,Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." "0,1"
bitfld.long 0x14 4. "MR1R,Reset on MR1: the TC will be reset if MR1 matches it." "0,1"
newline
bitfld.long 0x14 3. "MR1I,Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC." "0,1"
bitfld.long 0x14 2. "MR0S,Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." "0,1"
newline
bitfld.long 0x14 1. "MR0R,Reset on MR0: the TC will be reset if MR0 matches it." "0,1"
bitfld.long 0x14 0. "MR0I,Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC." "0,1"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x18)++0x3
line.long 0x0 "MR[$1],Match Register . MR can be enabled through the MCR to reset the TC. stop both the TC and PC. and/or generate an interrupt every time MR matches the TC."
hexmask.long 0x0 0.--31. 1. "MATCH,Timer counter match value."
repeat.end
group.long 0x28++0x3
line.long 0x0 "CCR,Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."
bitfld.long 0x0 11. "CAP3I,Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt." "0,1"
bitfld.long 0x0 10. "CAP3FE,Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 9. "CAP3RE,Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 8. "CAP2I,Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 7. "CAP2FE,Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 6. "CAP2RE,Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 5. "CAP1I,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt." "0,1"
bitfld.long 0x0 4. "CAP1FE,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 3. "CAP1RE,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 2. "CAP0I,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 1. "CAP0FE,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 0. "CAP0RE,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x2C)++0x3
line.long 0x0 "CR[$1],Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input."
hexmask.long 0x0 0.--31. 1. "CAP,Timer counter capture value."
repeat.end
group.long 0x3C++0x3
line.long 0x0 "EMR,External Match Register. The EMR controls the match function and the external match pins."
bitfld.long 0x0 10.--11. "EMC3,External Match Control 3. Determines the functionality of External Match 3." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 8.--9. "EMC2,External Match Control 2. Determines the functionality of External Match 2." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 6.--7. "EMC1,External Match Control 1. Determines the functionality of External Match 1." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 4.--5. "EMC0,External Match Control 0. Determines the functionality of External Match 0." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 3. "EM3,External Match 3. This bit reflects the state of output MAT3  whether or not this output is connected to a pin. When a match occurs between the TC and MR3  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by MR[11:10]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 2. "EM2,External Match 2. This bit reflects the state of output MAT2  whether or not this output is connected to a pin. When a match occurs between the TC and MR2  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[9:8]. This bit.." "0: LOW,1: HIGH"
newline
bitfld.long 0x0 1. "EM1,External Match 1. This bit reflects the state of output MAT1  whether or not this output is connected to a pin. When a match occurs between the TC and MR1  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[7:6]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 0. "EM0,External Match 0. This bit reflects the state of output MAT0  whether or not this output is connected to a pin. When a match occurs between the TC and MR0  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[5:4]. This bit.." "0: LOW,1: HIGH"
group.long 0x70++0x7
line.long 0x0 "CTCR,Count Control Register. The CTCR selects between Timer and Counter mode. and in Counter mode selects the signal and edge(s) for counting."
bitfld.long 0x0 5.--7. "SELCC,Edge select. When bit 4 is 1  these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved." "0: Channel 0 Rising Edge. Rising edge of the signal..,1: Channel 0 Falling Edge. Falling edge of the..,2: Channel 1 Rising Edge. Rising edge of the signal..,3: Channel 1 Falling Edge. Falling edge of the..,4: Channel 2 Rising Edge. Rising edge of the signal..,5: Channel 2 Falling Edge. Falling edge of the..,?,?"
bitfld.long 0x0 4. "ENCC,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." "0,1"
newline
bitfld.long 0x0 2.--3. "CINSEL,Count Input Select When bits 1:0 in this register are not 00  these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR  the 3 bits for that input in the Capture Control.." "0: Channel 0. CAPn.0 for CTIMERn,1: 0 in this register are not 00,2: Channel 2. CAPn.2 for CTIMERn,3: Channel 3. CAPn.3 for CTIMERn"
bitfld.long 0x0 0.--1. "CTMODE,Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC)  or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale.." "0: Timer Mode. Incremented every rising APB bus..,1: Counter Mode rising edge. TC is incremented on..,2: Counter Mode falling edge. TC is incremented on..,3: Counter Mode dual edge. TC is incremented on.."
line.long 0x4 "PWMC,PWM Control Register. The PWMCON enables PWM mode for the external match pins."
bitfld.long 0x4 3. "PWMEN3,PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle." "0: Match. CTIMERn_MAT3 is controlled by EM3.,1: PWM. PWM mode is enabled for CT132Bn_MAT3."
bitfld.long 0x4 2. "PWMEN2,PWM mode enable for channel2." "0: Match. CTIMERn_MAT2 is controlled by EM2.,1: PWM. PWM mode is enabled for CTIMERn_MAT2."
newline
bitfld.long 0x4 1. "PWMEN1,PWM mode enable for channel1." "0: Match. CTIMERn_MAT01 is controlled by EM1.,1: PWM. PWM mode is enabled for CTIMERn_MAT1."
bitfld.long 0x4 0. "PWMEN0,PWM mode enable for channel0." "0: Match. CTIMERn_MAT0 is controlled by EM0.,1: PWM. PWM mode is enabled for CTIMERn_MAT0."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x78)++0x3
line.long 0x0 "MSR[$1],Match Shadow Register"
hexmask.long 0x0 0.--31. 1. "SHADOWW,Timer counter match shadow value."
repeat.end
tree.end
endif
sif (cpuis("LPC54608*"))
tree "CTIMER0"
base ad:0x40008000
group.long 0x0++0x17
line.long 0x0 "IR,Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending."
bitfld.long 0x0 7. "CR3INT,Interrupt flag for capture channel 3 event." "0,1"
bitfld.long 0x0 6. "CR2INT,Interrupt flag for capture channel 2 event." "0,1"
newline
bitfld.long 0x0 5. "CR1INT,Interrupt flag for capture channel 1 event." "0,1"
bitfld.long 0x0 4. "CR0INT,Interrupt flag for capture channel 0 event." "0,1"
newline
bitfld.long 0x0 3. "MR3INT,Interrupt flag for match channel 3." "0,1"
bitfld.long 0x0 2. "MR2INT,Interrupt flag for match channel 2." "0,1"
newline
bitfld.long 0x0 1. "MR1INT,Interrupt flag for match channel 1." "0,1"
bitfld.long 0x0 0. "MR0INT,Interrupt flag for match channel 0." "0,1"
line.long 0x4 "TCR,Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."
bitfld.long 0x4 1. "CRST,Counter reset." "0: Disabled. Do nothing.,1: Enabled. The Timer Counter and the Prescale.."
bitfld.long 0x4 0. "CEN,Counter enable." "0: Disabled.The counters are disabled.,1: Enabled. The Timer Counter and Prescale Counter.."
line.long 0x8 "TC,Timer Counter"
hexmask.long 0x8 0.--31. 1. "TCVAL,Timer counter value."
line.long 0xC "PR,Prescale Register"
hexmask.long 0xC 0.--31. 1. "PRVAL,Prescale counter value."
line.long 0x10 "PC,Prescale Counter"
hexmask.long 0x10 0.--31. 1. "PCVAL,Prescale counter value."
line.long 0x14 "MCR,Match Control Register"
bitfld.long 0x14 27. "MR3RL,Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 26. "MR2RL,Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 25. "MR1RL,Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 24. "MR0RL,Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 11. "MR3S,Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." "0,1"
bitfld.long 0x14 10. "MR3R,Reset on MR3: the TC will be reset if MR3 matches it." "0,1"
newline
bitfld.long 0x14 9. "MR3I,Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC." "0,1"
bitfld.long 0x14 8. "MR2S,Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC." "0,1"
newline
bitfld.long 0x14 7. "MR2R,Reset on MR2: the TC will be reset if MR2 matches it." "0,1"
bitfld.long 0x14 6. "MR2I,Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC." "0,1"
newline
bitfld.long 0x14 5. "MR1S,Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." "0,1"
bitfld.long 0x14 4. "MR1R,Reset on MR1: the TC will be reset if MR1 matches it." "0,1"
newline
bitfld.long 0x14 3. "MR1I,Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC." "0,1"
bitfld.long 0x14 2. "MR0S,Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." "0,1"
newline
bitfld.long 0x14 1. "MR0R,Reset on MR0: the TC will be reset if MR0 matches it." "0,1"
bitfld.long 0x14 0. "MR0I,Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC." "0,1"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x18)++0x3
line.long 0x0 "MR[$1],Match Register . MR can be enabled through the MCR to reset the TC. stop both the TC and PC. and/or generate an interrupt every time MR matches the TC."
hexmask.long 0x0 0.--31. 1. "MATCH,Timer counter match value."
repeat.end
group.long 0x28++0x3
line.long 0x0 "CCR,Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."
bitfld.long 0x0 11. "CAP3I,Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt." "0,1"
bitfld.long 0x0 10. "CAP3FE,Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 9. "CAP3RE,Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 8. "CAP2I,Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 7. "CAP2FE,Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 6. "CAP2RE,Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 5. "CAP1I,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt." "0,1"
bitfld.long 0x0 4. "CAP1FE,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 3. "CAP1RE,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 2. "CAP0I,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 1. "CAP0FE,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 0. "CAP0RE,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x2C)++0x3
line.long 0x0 "CR[$1],Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input."
hexmask.long 0x0 0.--31. 1. "CAP,Timer counter capture value."
repeat.end
group.long 0x3C++0x3
line.long 0x0 "EMR,External Match Register. The EMR controls the match function and the external match pins."
bitfld.long 0x0 10.--11. "EMC3,External Match Control 3. Determines the functionality of External Match 3." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 8.--9. "EMC2,External Match Control 2. Determines the functionality of External Match 2." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 6.--7. "EMC1,External Match Control 1. Determines the functionality of External Match 1." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 4.--5. "EMC0,External Match Control 0. Determines the functionality of External Match 0." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 3. "EM3,External Match 3. This bit reflects the state of output MAT3  whether or not this output is connected to a pin. When a match occurs between the TC and MR3  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by MR[11:10]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 2. "EM2,External Match 2. This bit reflects the state of output MAT2  whether or not this output is connected to a pin. When a match occurs between the TC and MR2  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[9:8]. This bit.." "0: LOW,1: HIGH"
newline
bitfld.long 0x0 1. "EM1,External Match 1. This bit reflects the state of output MAT1  whether or not this output is connected to a pin. When a match occurs between the TC and MR1  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[7:6]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 0. "EM0,External Match 0. This bit reflects the state of output MAT0  whether or not this output is connected to a pin. When a match occurs between the TC and MR0  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[5:4]. This bit.." "0: LOW,1: HIGH"
group.long 0x70++0x7
line.long 0x0 "CTCR,Count Control Register. The CTCR selects between Timer and Counter mode. and in Counter mode selects the signal and edge(s) for counting."
bitfld.long 0x0 5.--7. "SELCC,Edge select. When bit 4 is 1  these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved." "0: Channel 0 Rising Edge. Rising edge of the signal..,1: Channel 0 Falling Edge. Falling edge of the..,2: Channel 1 Rising Edge. Rising edge of the signal..,3: Channel 1 Falling Edge. Falling edge of the..,4: Channel 2 Rising Edge. Rising edge of the signal..,5: Channel 2 Falling Edge. Falling edge of the..,?,?"
bitfld.long 0x0 4. "ENCC,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." "0,1"
newline
bitfld.long 0x0 2.--3. "CINSEL,Count Input Select When bits 1:0 in this register are not 00  these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR  the 3 bits for that input in the Capture Control.." "0: Channel 0. CAPn.0 for CTIMERn,1: 0 in this register are not 00,2: Channel 2. CAPn.2 for CTIMERn,3: Channel 3. CAPn.3 for CTIMERn"
bitfld.long 0x0 0.--1. "CTMODE,Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC)  or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale.." "0: Timer Mode. Incremented every rising APB bus..,1: Counter Mode rising edge. TC is incremented on..,2: Counter Mode falling edge. TC is incremented on..,3: Counter Mode dual edge. TC is incremented on.."
line.long 0x4 "PWMC,PWM Control Register. The PWMCON enables PWM mode for the external match pins."
bitfld.long 0x4 3. "PWMEN3,PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle." "0: Match. CTIMERn_MAT3 is controlled by EM3.,1: PWM. PWM mode is enabled for CT132Bn_MAT3."
bitfld.long 0x4 2. "PWMEN2,PWM mode enable for channel2." "0: Match. CTIMERn_MAT2 is controlled by EM2.,1: PWM. PWM mode is enabled for CTIMERn_MAT2."
newline
bitfld.long 0x4 1. "PWMEN1,PWM mode enable for channel1." "0: Match. CTIMERn_MAT01 is controlled by EM1.,1: PWM. PWM mode is enabled for CTIMERn_MAT1."
bitfld.long 0x4 0. "PWMEN0,PWM mode enable for channel0." "0: Match. CTIMERn_MAT0 is controlled by EM0.,1: PWM. PWM mode is enabled for CTIMERn_MAT0."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x78)++0x3
line.long 0x0 "MSR[$1],Match Shadow Register"
hexmask.long 0x0 0.--31. 1. "SHADOWW,Timer counter match shadow value."
repeat.end
tree.end
tree "CTIMER1"
base ad:0x40009000
group.long 0x0++0x17
line.long 0x0 "IR,Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending."
bitfld.long 0x0 7. "CR3INT,Interrupt flag for capture channel 3 event." "0,1"
bitfld.long 0x0 6. "CR2INT,Interrupt flag for capture channel 2 event." "0,1"
newline
bitfld.long 0x0 5. "CR1INT,Interrupt flag for capture channel 1 event." "0,1"
bitfld.long 0x0 4. "CR0INT,Interrupt flag for capture channel 0 event." "0,1"
newline
bitfld.long 0x0 3. "MR3INT,Interrupt flag for match channel 3." "0,1"
bitfld.long 0x0 2. "MR2INT,Interrupt flag for match channel 2." "0,1"
newline
bitfld.long 0x0 1. "MR1INT,Interrupt flag for match channel 1." "0,1"
bitfld.long 0x0 0. "MR0INT,Interrupt flag for match channel 0." "0,1"
line.long 0x4 "TCR,Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."
bitfld.long 0x4 1. "CRST,Counter reset." "0: Disabled. Do nothing.,1: Enabled. The Timer Counter and the Prescale.."
bitfld.long 0x4 0. "CEN,Counter enable." "0: Disabled.The counters are disabled.,1: Enabled. The Timer Counter and Prescale Counter.."
line.long 0x8 "TC,Timer Counter"
hexmask.long 0x8 0.--31. 1. "TCVAL,Timer counter value."
line.long 0xC "PR,Prescale Register"
hexmask.long 0xC 0.--31. 1. "PRVAL,Prescale counter value."
line.long 0x10 "PC,Prescale Counter"
hexmask.long 0x10 0.--31. 1. "PCVAL,Prescale counter value."
line.long 0x14 "MCR,Match Control Register"
bitfld.long 0x14 27. "MR3RL,Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 26. "MR2RL,Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 25. "MR1RL,Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 24. "MR0RL,Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 11. "MR3S,Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." "0,1"
bitfld.long 0x14 10. "MR3R,Reset on MR3: the TC will be reset if MR3 matches it." "0,1"
newline
bitfld.long 0x14 9. "MR3I,Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC." "0,1"
bitfld.long 0x14 8. "MR2S,Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC." "0,1"
newline
bitfld.long 0x14 7. "MR2R,Reset on MR2: the TC will be reset if MR2 matches it." "0,1"
bitfld.long 0x14 6. "MR2I,Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC." "0,1"
newline
bitfld.long 0x14 5. "MR1S,Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." "0,1"
bitfld.long 0x14 4. "MR1R,Reset on MR1: the TC will be reset if MR1 matches it." "0,1"
newline
bitfld.long 0x14 3. "MR1I,Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC." "0,1"
bitfld.long 0x14 2. "MR0S,Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." "0,1"
newline
bitfld.long 0x14 1. "MR0R,Reset on MR0: the TC will be reset if MR0 matches it." "0,1"
bitfld.long 0x14 0. "MR0I,Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC." "0,1"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x18)++0x3
line.long 0x0 "MR[$1],Match Register . MR can be enabled through the MCR to reset the TC. stop both the TC and PC. and/or generate an interrupt every time MR matches the TC."
hexmask.long 0x0 0.--31. 1. "MATCH,Timer counter match value."
repeat.end
group.long 0x28++0x3
line.long 0x0 "CCR,Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."
bitfld.long 0x0 11. "CAP3I,Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt." "0,1"
bitfld.long 0x0 10. "CAP3FE,Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 9. "CAP3RE,Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 8. "CAP2I,Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 7. "CAP2FE,Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 6. "CAP2RE,Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 5. "CAP1I,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt." "0,1"
bitfld.long 0x0 4. "CAP1FE,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 3. "CAP1RE,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 2. "CAP0I,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 1. "CAP0FE,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 0. "CAP0RE,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x2C)++0x3
line.long 0x0 "CR[$1],Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input."
hexmask.long 0x0 0.--31. 1. "CAP,Timer counter capture value."
repeat.end
group.long 0x3C++0x3
line.long 0x0 "EMR,External Match Register. The EMR controls the match function and the external match pins."
bitfld.long 0x0 10.--11. "EMC3,External Match Control 3. Determines the functionality of External Match 3." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 8.--9. "EMC2,External Match Control 2. Determines the functionality of External Match 2." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 6.--7. "EMC1,External Match Control 1. Determines the functionality of External Match 1." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 4.--5. "EMC0,External Match Control 0. Determines the functionality of External Match 0." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 3. "EM3,External Match 3. This bit reflects the state of output MAT3  whether or not this output is connected to a pin. When a match occurs between the TC and MR3  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by MR[11:10]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 2. "EM2,External Match 2. This bit reflects the state of output MAT2  whether or not this output is connected to a pin. When a match occurs between the TC and MR2  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[9:8]. This bit.." "0: LOW,1: HIGH"
newline
bitfld.long 0x0 1. "EM1,External Match 1. This bit reflects the state of output MAT1  whether or not this output is connected to a pin. When a match occurs between the TC and MR1  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[7:6]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 0. "EM0,External Match 0. This bit reflects the state of output MAT0  whether or not this output is connected to a pin. When a match occurs between the TC and MR0  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[5:4]. This bit.." "0: LOW,1: HIGH"
group.long 0x70++0x7
line.long 0x0 "CTCR,Count Control Register. The CTCR selects between Timer and Counter mode. and in Counter mode selects the signal and edge(s) for counting."
bitfld.long 0x0 5.--7. "SELCC,Edge select. When bit 4 is 1  these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved." "0: Channel 0 Rising Edge. Rising edge of the signal..,1: Channel 0 Falling Edge. Falling edge of the..,2: Channel 1 Rising Edge. Rising edge of the signal..,3: Channel 1 Falling Edge. Falling edge of the..,4: Channel 2 Rising Edge. Rising edge of the signal..,5: Channel 2 Falling Edge. Falling edge of the..,?,?"
bitfld.long 0x0 4. "ENCC,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." "0,1"
newline
bitfld.long 0x0 2.--3. "CINSEL,Count Input Select When bits 1:0 in this register are not 00  these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR  the 3 bits for that input in the Capture Control.." "0: Channel 0. CAPn.0 for CTIMERn,1: 0 in this register are not 00,2: Channel 2. CAPn.2 for CTIMERn,3: Channel 3. CAPn.3 for CTIMERn"
bitfld.long 0x0 0.--1. "CTMODE,Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC)  or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale.." "0: Timer Mode. Incremented every rising APB bus..,1: Counter Mode rising edge. TC is incremented on..,2: Counter Mode falling edge. TC is incremented on..,3: Counter Mode dual edge. TC is incremented on.."
line.long 0x4 "PWMC,PWM Control Register. The PWMCON enables PWM mode for the external match pins."
bitfld.long 0x4 3. "PWMEN3,PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle." "0: Match. CTIMERn_MAT3 is controlled by EM3.,1: PWM. PWM mode is enabled for CT132Bn_MAT3."
bitfld.long 0x4 2. "PWMEN2,PWM mode enable for channel2." "0: Match. CTIMERn_MAT2 is controlled by EM2.,1: PWM. PWM mode is enabled for CTIMERn_MAT2."
newline
bitfld.long 0x4 1. "PWMEN1,PWM mode enable for channel1." "0: Match. CTIMERn_MAT01 is controlled by EM1.,1: PWM. PWM mode is enabled for CTIMERn_MAT1."
bitfld.long 0x4 0. "PWMEN0,PWM mode enable for channel0." "0: Match. CTIMERn_MAT0 is controlled by EM0.,1: PWM. PWM mode is enabled for CTIMERn_MAT0."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x78)++0x3
line.long 0x0 "MSR[$1],Match Shadow Register"
hexmask.long 0x0 0.--31. 1. "SHADOWW,Timer counter match shadow value."
repeat.end
tree.end
tree "CTIMER2"
base ad:0x40028000
group.long 0x0++0x17
line.long 0x0 "IR,Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending."
bitfld.long 0x0 7. "CR3INT,Interrupt flag for capture channel 3 event." "0,1"
bitfld.long 0x0 6. "CR2INT,Interrupt flag for capture channel 2 event." "0,1"
newline
bitfld.long 0x0 5. "CR1INT,Interrupt flag for capture channel 1 event." "0,1"
bitfld.long 0x0 4. "CR0INT,Interrupt flag for capture channel 0 event." "0,1"
newline
bitfld.long 0x0 3. "MR3INT,Interrupt flag for match channel 3." "0,1"
bitfld.long 0x0 2. "MR2INT,Interrupt flag for match channel 2." "0,1"
newline
bitfld.long 0x0 1. "MR1INT,Interrupt flag for match channel 1." "0,1"
bitfld.long 0x0 0. "MR0INT,Interrupt flag for match channel 0." "0,1"
line.long 0x4 "TCR,Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."
bitfld.long 0x4 1. "CRST,Counter reset." "0: Disabled. Do nothing.,1: Enabled. The Timer Counter and the Prescale.."
bitfld.long 0x4 0. "CEN,Counter enable." "0: Disabled.The counters are disabled.,1: Enabled. The Timer Counter and Prescale Counter.."
line.long 0x8 "TC,Timer Counter"
hexmask.long 0x8 0.--31. 1. "TCVAL,Timer counter value."
line.long 0xC "PR,Prescale Register"
hexmask.long 0xC 0.--31. 1. "PRVAL,Prescale counter value."
line.long 0x10 "PC,Prescale Counter"
hexmask.long 0x10 0.--31. 1. "PCVAL,Prescale counter value."
line.long 0x14 "MCR,Match Control Register"
bitfld.long 0x14 27. "MR3RL,Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 26. "MR2RL,Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 25. "MR1RL,Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 24. "MR0RL,Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 11. "MR3S,Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." "0,1"
bitfld.long 0x14 10. "MR3R,Reset on MR3: the TC will be reset if MR3 matches it." "0,1"
newline
bitfld.long 0x14 9. "MR3I,Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC." "0,1"
bitfld.long 0x14 8. "MR2S,Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC." "0,1"
newline
bitfld.long 0x14 7. "MR2R,Reset on MR2: the TC will be reset if MR2 matches it." "0,1"
bitfld.long 0x14 6. "MR2I,Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC." "0,1"
newline
bitfld.long 0x14 5. "MR1S,Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." "0,1"
bitfld.long 0x14 4. "MR1R,Reset on MR1: the TC will be reset if MR1 matches it." "0,1"
newline
bitfld.long 0x14 3. "MR1I,Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC." "0,1"
bitfld.long 0x14 2. "MR0S,Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." "0,1"
newline
bitfld.long 0x14 1. "MR0R,Reset on MR0: the TC will be reset if MR0 matches it." "0,1"
bitfld.long 0x14 0. "MR0I,Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC." "0,1"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x18)++0x3
line.long 0x0 "MR[$1],Match Register . MR can be enabled through the MCR to reset the TC. stop both the TC and PC. and/or generate an interrupt every time MR matches the TC."
hexmask.long 0x0 0.--31. 1. "MATCH,Timer counter match value."
repeat.end
group.long 0x28++0x3
line.long 0x0 "CCR,Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."
bitfld.long 0x0 11. "CAP3I,Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt." "0,1"
bitfld.long 0x0 10. "CAP3FE,Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 9. "CAP3RE,Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 8. "CAP2I,Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 7. "CAP2FE,Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 6. "CAP2RE,Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 5. "CAP1I,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt." "0,1"
bitfld.long 0x0 4. "CAP1FE,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 3. "CAP1RE,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 2. "CAP0I,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 1. "CAP0FE,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 0. "CAP0RE,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x2C)++0x3
line.long 0x0 "CR[$1],Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input."
hexmask.long 0x0 0.--31. 1. "CAP,Timer counter capture value."
repeat.end
group.long 0x3C++0x3
line.long 0x0 "EMR,External Match Register. The EMR controls the match function and the external match pins."
bitfld.long 0x0 10.--11. "EMC3,External Match Control 3. Determines the functionality of External Match 3." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 8.--9. "EMC2,External Match Control 2. Determines the functionality of External Match 2." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 6.--7. "EMC1,External Match Control 1. Determines the functionality of External Match 1." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 4.--5. "EMC0,External Match Control 0. Determines the functionality of External Match 0." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 3. "EM3,External Match 3. This bit reflects the state of output MAT3  whether or not this output is connected to a pin. When a match occurs between the TC and MR3  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by MR[11:10]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 2. "EM2,External Match 2. This bit reflects the state of output MAT2  whether or not this output is connected to a pin. When a match occurs between the TC and MR2  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[9:8]. This bit.." "0: LOW,1: HIGH"
newline
bitfld.long 0x0 1. "EM1,External Match 1. This bit reflects the state of output MAT1  whether or not this output is connected to a pin. When a match occurs between the TC and MR1  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[7:6]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 0. "EM0,External Match 0. This bit reflects the state of output MAT0  whether or not this output is connected to a pin. When a match occurs between the TC and MR0  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[5:4]. This bit.." "0: LOW,1: HIGH"
group.long 0x70++0x7
line.long 0x0 "CTCR,Count Control Register. The CTCR selects between Timer and Counter mode. and in Counter mode selects the signal and edge(s) for counting."
bitfld.long 0x0 5.--7. "SELCC,Edge select. When bit 4 is 1  these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved." "0: Channel 0 Rising Edge. Rising edge of the signal..,1: Channel 0 Falling Edge. Falling edge of the..,2: Channel 1 Rising Edge. Rising edge of the signal..,3: Channel 1 Falling Edge. Falling edge of the..,4: Channel 2 Rising Edge. Rising edge of the signal..,5: Channel 2 Falling Edge. Falling edge of the..,?,?"
bitfld.long 0x0 4. "ENCC,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." "0,1"
newline
bitfld.long 0x0 2.--3. "CINSEL,Count Input Select When bits 1:0 in this register are not 00  these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR  the 3 bits for that input in the Capture Control.." "0: Channel 0. CAPn.0 for CTIMERn,1: 0 in this register are not 00,2: Channel 2. CAPn.2 for CTIMERn,3: Channel 3. CAPn.3 for CTIMERn"
bitfld.long 0x0 0.--1. "CTMODE,Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC)  or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale.." "0: Timer Mode. Incremented every rising APB bus..,1: Counter Mode rising edge. TC is incremented on..,2: Counter Mode falling edge. TC is incremented on..,3: Counter Mode dual edge. TC is incremented on.."
line.long 0x4 "PWMC,PWM Control Register. The PWMCON enables PWM mode for the external match pins."
bitfld.long 0x4 3. "PWMEN3,PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle." "0: Match. CTIMERn_MAT3 is controlled by EM3.,1: PWM. PWM mode is enabled for CT132Bn_MAT3."
bitfld.long 0x4 2. "PWMEN2,PWM mode enable for channel2." "0: Match. CTIMERn_MAT2 is controlled by EM2.,1: PWM. PWM mode is enabled for CTIMERn_MAT2."
newline
bitfld.long 0x4 1. "PWMEN1,PWM mode enable for channel1." "0: Match. CTIMERn_MAT01 is controlled by EM1.,1: PWM. PWM mode is enabled for CTIMERn_MAT1."
bitfld.long 0x4 0. "PWMEN0,PWM mode enable for channel0." "0: Match. CTIMERn_MAT0 is controlled by EM0.,1: PWM. PWM mode is enabled for CTIMERn_MAT0."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x78)++0x3
line.long 0x0 "MSR[$1],Match Shadow Register"
hexmask.long 0x0 0.--31. 1. "SHADOWW,Timer counter match shadow value."
repeat.end
tree.end
tree "CTIMER3"
base ad:0x40048000
group.long 0x0++0x17
line.long 0x0 "IR,Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending."
bitfld.long 0x0 7. "CR3INT,Interrupt flag for capture channel 3 event." "0,1"
bitfld.long 0x0 6. "CR2INT,Interrupt flag for capture channel 2 event." "0,1"
newline
bitfld.long 0x0 5. "CR1INT,Interrupt flag for capture channel 1 event." "0,1"
bitfld.long 0x0 4. "CR0INT,Interrupt flag for capture channel 0 event." "0,1"
newline
bitfld.long 0x0 3. "MR3INT,Interrupt flag for match channel 3." "0,1"
bitfld.long 0x0 2. "MR2INT,Interrupt flag for match channel 2." "0,1"
newline
bitfld.long 0x0 1. "MR1INT,Interrupt flag for match channel 1." "0,1"
bitfld.long 0x0 0. "MR0INT,Interrupt flag for match channel 0." "0,1"
line.long 0x4 "TCR,Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."
bitfld.long 0x4 1. "CRST,Counter reset." "0: Disabled. Do nothing.,1: Enabled. The Timer Counter and the Prescale.."
bitfld.long 0x4 0. "CEN,Counter enable." "0: Disabled.The counters are disabled.,1: Enabled. The Timer Counter and Prescale Counter.."
line.long 0x8 "TC,Timer Counter"
hexmask.long 0x8 0.--31. 1. "TCVAL,Timer counter value."
line.long 0xC "PR,Prescale Register"
hexmask.long 0xC 0.--31. 1. "PRVAL,Prescale counter value."
line.long 0x10 "PC,Prescale Counter"
hexmask.long 0x10 0.--31. 1. "PCVAL,Prescale counter value."
line.long 0x14 "MCR,Match Control Register"
bitfld.long 0x14 27. "MR3RL,Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 26. "MR2RL,Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 25. "MR1RL,Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 24. "MR0RL,Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 11. "MR3S,Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." "0,1"
bitfld.long 0x14 10. "MR3R,Reset on MR3: the TC will be reset if MR3 matches it." "0,1"
newline
bitfld.long 0x14 9. "MR3I,Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC." "0,1"
bitfld.long 0x14 8. "MR2S,Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC." "0,1"
newline
bitfld.long 0x14 7. "MR2R,Reset on MR2: the TC will be reset if MR2 matches it." "0,1"
bitfld.long 0x14 6. "MR2I,Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC." "0,1"
newline
bitfld.long 0x14 5. "MR1S,Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." "0,1"
bitfld.long 0x14 4. "MR1R,Reset on MR1: the TC will be reset if MR1 matches it." "0,1"
newline
bitfld.long 0x14 3. "MR1I,Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC." "0,1"
bitfld.long 0x14 2. "MR0S,Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." "0,1"
newline
bitfld.long 0x14 1. "MR0R,Reset on MR0: the TC will be reset if MR0 matches it." "0,1"
bitfld.long 0x14 0. "MR0I,Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC." "0,1"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x18)++0x3
line.long 0x0 "MR[$1],Match Register . MR can be enabled through the MCR to reset the TC. stop both the TC and PC. and/or generate an interrupt every time MR matches the TC."
hexmask.long 0x0 0.--31. 1. "MATCH,Timer counter match value."
repeat.end
group.long 0x28++0x3
line.long 0x0 "CCR,Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."
bitfld.long 0x0 11. "CAP3I,Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt." "0,1"
bitfld.long 0x0 10. "CAP3FE,Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 9. "CAP3RE,Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 8. "CAP2I,Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 7. "CAP2FE,Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 6. "CAP2RE,Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 5. "CAP1I,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt." "0,1"
bitfld.long 0x0 4. "CAP1FE,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 3. "CAP1RE,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 2. "CAP0I,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 1. "CAP0FE,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 0. "CAP0RE,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x2C)++0x3
line.long 0x0 "CR[$1],Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input."
hexmask.long 0x0 0.--31. 1. "CAP,Timer counter capture value."
repeat.end
group.long 0x3C++0x3
line.long 0x0 "EMR,External Match Register. The EMR controls the match function and the external match pins."
bitfld.long 0x0 10.--11. "EMC3,External Match Control 3. Determines the functionality of External Match 3." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 8.--9. "EMC2,External Match Control 2. Determines the functionality of External Match 2." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 6.--7. "EMC1,External Match Control 1. Determines the functionality of External Match 1." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 4.--5. "EMC0,External Match Control 0. Determines the functionality of External Match 0." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 3. "EM3,External Match 3. This bit reflects the state of output MAT3  whether or not this output is connected to a pin. When a match occurs between the TC and MR3  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by MR[11:10]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 2. "EM2,External Match 2. This bit reflects the state of output MAT2  whether or not this output is connected to a pin. When a match occurs between the TC and MR2  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[9:8]. This bit.." "0: LOW,1: HIGH"
newline
bitfld.long 0x0 1. "EM1,External Match 1. This bit reflects the state of output MAT1  whether or not this output is connected to a pin. When a match occurs between the TC and MR1  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[7:6]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 0. "EM0,External Match 0. This bit reflects the state of output MAT0  whether or not this output is connected to a pin. When a match occurs between the TC and MR0  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[5:4]. This bit.." "0: LOW,1: HIGH"
group.long 0x70++0x7
line.long 0x0 "CTCR,Count Control Register. The CTCR selects between Timer and Counter mode. and in Counter mode selects the signal and edge(s) for counting."
bitfld.long 0x0 5.--7. "SELCC,Edge select. When bit 4 is 1  these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved." "0: Channel 0 Rising Edge. Rising edge of the signal..,1: Channel 0 Falling Edge. Falling edge of the..,2: Channel 1 Rising Edge. Rising edge of the signal..,3: Channel 1 Falling Edge. Falling edge of the..,4: Channel 2 Rising Edge. Rising edge of the signal..,5: Channel 2 Falling Edge. Falling edge of the..,?,?"
bitfld.long 0x0 4. "ENCC,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." "0,1"
newline
bitfld.long 0x0 2.--3. "CINSEL,Count Input Select When bits 1:0 in this register are not 00  these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR  the 3 bits for that input in the Capture Control.." "0: Channel 0. CAPn.0 for CTIMERn,1: 0 in this register are not 00,2: Channel 2. CAPn.2 for CTIMERn,3: Channel 3. CAPn.3 for CTIMERn"
bitfld.long 0x0 0.--1. "CTMODE,Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC)  or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale.." "0: Timer Mode. Incremented every rising APB bus..,1: Counter Mode rising edge. TC is incremented on..,2: Counter Mode falling edge. TC is incremented on..,3: Counter Mode dual edge. TC is incremented on.."
line.long 0x4 "PWMC,PWM Control Register. The PWMCON enables PWM mode for the external match pins."
bitfld.long 0x4 3. "PWMEN3,PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle." "0: Match. CTIMERn_MAT3 is controlled by EM3.,1: PWM. PWM mode is enabled for CT132Bn_MAT3."
bitfld.long 0x4 2. "PWMEN2,PWM mode enable for channel2." "0: Match. CTIMERn_MAT2 is controlled by EM2.,1: PWM. PWM mode is enabled for CTIMERn_MAT2."
newline
bitfld.long 0x4 1. "PWMEN1,PWM mode enable for channel1." "0: Match. CTIMERn_MAT01 is controlled by EM1.,1: PWM. PWM mode is enabled for CTIMERn_MAT1."
bitfld.long 0x4 0. "PWMEN0,PWM mode enable for channel0." "0: Match. CTIMERn_MAT0 is controlled by EM0.,1: PWM. PWM mode is enabled for CTIMERn_MAT0."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x78)++0x3
line.long 0x0 "MSR[$1],Match Shadow Register"
hexmask.long 0x0 0.--31. 1. "SHADOWW,Timer counter match shadow value."
repeat.end
tree.end
tree "CTIMER4"
base ad:0x40049000
group.long 0x0++0x17
line.long 0x0 "IR,Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending."
bitfld.long 0x0 7. "CR3INT,Interrupt flag for capture channel 3 event." "0,1"
bitfld.long 0x0 6. "CR2INT,Interrupt flag for capture channel 2 event." "0,1"
newline
bitfld.long 0x0 5. "CR1INT,Interrupt flag for capture channel 1 event." "0,1"
bitfld.long 0x0 4. "CR0INT,Interrupt flag for capture channel 0 event." "0,1"
newline
bitfld.long 0x0 3. "MR3INT,Interrupt flag for match channel 3." "0,1"
bitfld.long 0x0 2. "MR2INT,Interrupt flag for match channel 2." "0,1"
newline
bitfld.long 0x0 1. "MR1INT,Interrupt flag for match channel 1." "0,1"
bitfld.long 0x0 0. "MR0INT,Interrupt flag for match channel 0." "0,1"
line.long 0x4 "TCR,Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."
bitfld.long 0x4 1. "CRST,Counter reset." "0: Disabled. Do nothing.,1: Enabled. The Timer Counter and the Prescale.."
bitfld.long 0x4 0. "CEN,Counter enable." "0: Disabled.The counters are disabled.,1: Enabled. The Timer Counter and Prescale Counter.."
line.long 0x8 "TC,Timer Counter"
hexmask.long 0x8 0.--31. 1. "TCVAL,Timer counter value."
line.long 0xC "PR,Prescale Register"
hexmask.long 0xC 0.--31. 1. "PRVAL,Prescale counter value."
line.long 0x10 "PC,Prescale Counter"
hexmask.long 0x10 0.--31. 1. "PCVAL,Prescale counter value."
line.long 0x14 "MCR,Match Control Register"
bitfld.long 0x14 27. "MR3RL,Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 26. "MR2RL,Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 25. "MR1RL,Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 24. "MR0RL,Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 11. "MR3S,Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." "0,1"
bitfld.long 0x14 10. "MR3R,Reset on MR3: the TC will be reset if MR3 matches it." "0,1"
newline
bitfld.long 0x14 9. "MR3I,Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC." "0,1"
bitfld.long 0x14 8. "MR2S,Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC." "0,1"
newline
bitfld.long 0x14 7. "MR2R,Reset on MR2: the TC will be reset if MR2 matches it." "0,1"
bitfld.long 0x14 6. "MR2I,Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC." "0,1"
newline
bitfld.long 0x14 5. "MR1S,Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." "0,1"
bitfld.long 0x14 4. "MR1R,Reset on MR1: the TC will be reset if MR1 matches it." "0,1"
newline
bitfld.long 0x14 3. "MR1I,Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC." "0,1"
bitfld.long 0x14 2. "MR0S,Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." "0,1"
newline
bitfld.long 0x14 1. "MR0R,Reset on MR0: the TC will be reset if MR0 matches it." "0,1"
bitfld.long 0x14 0. "MR0I,Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC." "0,1"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x18)++0x3
line.long 0x0 "MR[$1],Match Register . MR can be enabled through the MCR to reset the TC. stop both the TC and PC. and/or generate an interrupt every time MR matches the TC."
hexmask.long 0x0 0.--31. 1. "MATCH,Timer counter match value."
repeat.end
group.long 0x28++0x3
line.long 0x0 "CCR,Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."
bitfld.long 0x0 11. "CAP3I,Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt." "0,1"
bitfld.long 0x0 10. "CAP3FE,Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 9. "CAP3RE,Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 8. "CAP2I,Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 7. "CAP2FE,Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 6. "CAP2RE,Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 5. "CAP1I,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt." "0,1"
bitfld.long 0x0 4. "CAP1FE,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 3. "CAP1RE,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 2. "CAP0I,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 1. "CAP0FE,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 0. "CAP0RE,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x2C)++0x3
line.long 0x0 "CR[$1],Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input."
hexmask.long 0x0 0.--31. 1. "CAP,Timer counter capture value."
repeat.end
group.long 0x3C++0x3
line.long 0x0 "EMR,External Match Register. The EMR controls the match function and the external match pins."
bitfld.long 0x0 10.--11. "EMC3,External Match Control 3. Determines the functionality of External Match 3." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 8.--9. "EMC2,External Match Control 2. Determines the functionality of External Match 2." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 6.--7. "EMC1,External Match Control 1. Determines the functionality of External Match 1." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 4.--5. "EMC0,External Match Control 0. Determines the functionality of External Match 0." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 3. "EM3,External Match 3. This bit reflects the state of output MAT3  whether or not this output is connected to a pin. When a match occurs between the TC and MR3  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by MR[11:10]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 2. "EM2,External Match 2. This bit reflects the state of output MAT2  whether or not this output is connected to a pin. When a match occurs between the TC and MR2  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[9:8]. This bit.." "0: LOW,1: HIGH"
newline
bitfld.long 0x0 1. "EM1,External Match 1. This bit reflects the state of output MAT1  whether or not this output is connected to a pin. When a match occurs between the TC and MR1  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[7:6]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 0. "EM0,External Match 0. This bit reflects the state of output MAT0  whether or not this output is connected to a pin. When a match occurs between the TC and MR0  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[5:4]. This bit.." "0: LOW,1: HIGH"
group.long 0x70++0x7
line.long 0x0 "CTCR,Count Control Register. The CTCR selects between Timer and Counter mode. and in Counter mode selects the signal and edge(s) for counting."
bitfld.long 0x0 5.--7. "SELCC,Edge select. When bit 4 is 1  these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved." "0: Channel 0 Rising Edge. Rising edge of the signal..,1: Channel 0 Falling Edge. Falling edge of the..,2: Channel 1 Rising Edge. Rising edge of the signal..,3: Channel 1 Falling Edge. Falling edge of the..,4: Channel 2 Rising Edge. Rising edge of the signal..,5: Channel 2 Falling Edge. Falling edge of the..,?,?"
bitfld.long 0x0 4. "ENCC,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." "0,1"
newline
bitfld.long 0x0 2.--3. "CINSEL,Count Input Select When bits 1:0 in this register are not 00  these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR  the 3 bits for that input in the Capture Control.." "0: Channel 0. CAPn.0 for CTIMERn,1: 0 in this register are not 00,2: Channel 2. CAPn.2 for CTIMERn,3: Channel 3. CAPn.3 for CTIMERn"
bitfld.long 0x0 0.--1. "CTMODE,Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC)  or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale.." "0: Timer Mode. Incremented every rising APB bus..,1: Counter Mode rising edge. TC is incremented on..,2: Counter Mode falling edge. TC is incremented on..,3: Counter Mode dual edge. TC is incremented on.."
line.long 0x4 "PWMC,PWM Control Register. The PWMCON enables PWM mode for the external match pins."
bitfld.long 0x4 3. "PWMEN3,PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle." "0: Match. CTIMERn_MAT3 is controlled by EM3.,1: PWM. PWM mode is enabled for CT132Bn_MAT3."
bitfld.long 0x4 2. "PWMEN2,PWM mode enable for channel2." "0: Match. CTIMERn_MAT2 is controlled by EM2.,1: PWM. PWM mode is enabled for CTIMERn_MAT2."
newline
bitfld.long 0x4 1. "PWMEN1,PWM mode enable for channel1." "0: Match. CTIMERn_MAT01 is controlled by EM1.,1: PWM. PWM mode is enabled for CTIMERn_MAT1."
bitfld.long 0x4 0. "PWMEN0,PWM mode enable for channel0." "0: Match. CTIMERn_MAT0 is controlled by EM0.,1: PWM. PWM mode is enabled for CTIMERn_MAT0."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x78)++0x3
line.long 0x0 "MSR[$1],Match Shadow Register"
hexmask.long 0x0 0.--31. 1. "SHADOWW,Timer counter match shadow value."
repeat.end
tree.end
endif
sif (cpuis("LPC54616*"))
tree "CTIMER0"
base ad:0x40008000
group.long 0x0++0x17
line.long 0x0 "IR,Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending."
bitfld.long 0x0 7. "CR3INT,Interrupt flag for capture channel 3 event." "0,1"
bitfld.long 0x0 6. "CR2INT,Interrupt flag for capture channel 2 event." "0,1"
newline
bitfld.long 0x0 5. "CR1INT,Interrupt flag for capture channel 1 event." "0,1"
bitfld.long 0x0 4. "CR0INT,Interrupt flag for capture channel 0 event." "0,1"
newline
bitfld.long 0x0 3. "MR3INT,Interrupt flag for match channel 3." "0,1"
bitfld.long 0x0 2. "MR2INT,Interrupt flag for match channel 2." "0,1"
newline
bitfld.long 0x0 1. "MR1INT,Interrupt flag for match channel 1." "0,1"
bitfld.long 0x0 0. "MR0INT,Interrupt flag for match channel 0." "0,1"
line.long 0x4 "TCR,Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."
bitfld.long 0x4 1. "CRST,Counter reset." "0: Disabled. Do nothing.,1: Enabled. The Timer Counter and the Prescale.."
bitfld.long 0x4 0. "CEN,Counter enable." "0: Disabled.The counters are disabled.,1: Enabled. The Timer Counter and Prescale Counter.."
line.long 0x8 "TC,Timer Counter"
hexmask.long 0x8 0.--31. 1. "TCVAL,Timer counter value."
line.long 0xC "PR,Prescale Register"
hexmask.long 0xC 0.--31. 1. "PRVAL,Prescale counter value."
line.long 0x10 "PC,Prescale Counter"
hexmask.long 0x10 0.--31. 1. "PCVAL,Prescale counter value."
line.long 0x14 "MCR,Match Control Register"
bitfld.long 0x14 27. "MR3RL,Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 26. "MR2RL,Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 25. "MR1RL,Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 24. "MR0RL,Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 11. "MR3S,Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." "0,1"
bitfld.long 0x14 10. "MR3R,Reset on MR3: the TC will be reset if MR3 matches it." "0,1"
newline
bitfld.long 0x14 9. "MR3I,Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC." "0,1"
bitfld.long 0x14 8. "MR2S,Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC." "0,1"
newline
bitfld.long 0x14 7. "MR2R,Reset on MR2: the TC will be reset if MR2 matches it." "0,1"
bitfld.long 0x14 6. "MR2I,Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC." "0,1"
newline
bitfld.long 0x14 5. "MR1S,Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." "0,1"
bitfld.long 0x14 4. "MR1R,Reset on MR1: the TC will be reset if MR1 matches it." "0,1"
newline
bitfld.long 0x14 3. "MR1I,Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC." "0,1"
bitfld.long 0x14 2. "MR0S,Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." "0,1"
newline
bitfld.long 0x14 1. "MR0R,Reset on MR0: the TC will be reset if MR0 matches it." "0,1"
bitfld.long 0x14 0. "MR0I,Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC." "0,1"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x18)++0x3
line.long 0x0 "MR[$1],Match Register . MR can be enabled through the MCR to reset the TC. stop both the TC and PC. and/or generate an interrupt every time MR matches the TC."
hexmask.long 0x0 0.--31. 1. "MATCH,Timer counter match value."
repeat.end
group.long 0x28++0x3
line.long 0x0 "CCR,Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."
bitfld.long 0x0 11. "CAP3I,Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt." "0,1"
bitfld.long 0x0 10. "CAP3FE,Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 9. "CAP3RE,Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 8. "CAP2I,Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 7. "CAP2FE,Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 6. "CAP2RE,Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 5. "CAP1I,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt." "0,1"
bitfld.long 0x0 4. "CAP1FE,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 3. "CAP1RE,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 2. "CAP0I,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 1. "CAP0FE,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 0. "CAP0RE,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x2C)++0x3
line.long 0x0 "CR[$1],Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input."
hexmask.long 0x0 0.--31. 1. "CAP,Timer counter capture value."
repeat.end
group.long 0x3C++0x3
line.long 0x0 "EMR,External Match Register. The EMR controls the match function and the external match pins."
bitfld.long 0x0 10.--11. "EMC3,External Match Control 3. Determines the functionality of External Match 3." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 8.--9. "EMC2,External Match Control 2. Determines the functionality of External Match 2." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 6.--7. "EMC1,External Match Control 1. Determines the functionality of External Match 1." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 4.--5. "EMC0,External Match Control 0. Determines the functionality of External Match 0." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 3. "EM3,External Match 3. This bit reflects the state of output MAT3  whether or not this output is connected to a pin. When a match occurs between the TC and MR3  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by MR[11:10]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 2. "EM2,External Match 2. This bit reflects the state of output MAT2  whether or not this output is connected to a pin. When a match occurs between the TC and MR2  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[9:8]. This bit.." "0: LOW,1: HIGH"
newline
bitfld.long 0x0 1. "EM1,External Match 1. This bit reflects the state of output MAT1  whether or not this output is connected to a pin. When a match occurs between the TC and MR1  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[7:6]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 0. "EM0,External Match 0. This bit reflects the state of output MAT0  whether or not this output is connected to a pin. When a match occurs between the TC and MR0  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[5:4]. This bit.." "0: LOW,1: HIGH"
group.long 0x70++0x7
line.long 0x0 "CTCR,Count Control Register. The CTCR selects between Timer and Counter mode. and in Counter mode selects the signal and edge(s) for counting."
bitfld.long 0x0 5.--7. "SELCC,Edge select. When bit 4 is 1  these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved." "0: Channel 0 Rising Edge. Rising edge of the signal..,1: Channel 0 Falling Edge. Falling edge of the..,2: Channel 1 Rising Edge. Rising edge of the signal..,3: Channel 1 Falling Edge. Falling edge of the..,4: Channel 2 Rising Edge. Rising edge of the signal..,5: Channel 2 Falling Edge. Falling edge of the..,?,?"
bitfld.long 0x0 4. "ENCC,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." "0,1"
newline
bitfld.long 0x0 2.--3. "CINSEL,Count Input Select When bits 1:0 in this register are not 00  these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR  the 3 bits for that input in the Capture Control.." "0: Channel 0. CAPn.0 for CTIMERn,1: 0 in this register are not 00,2: Channel 2. CAPn.2 for CTIMERn,3: Channel 3. CAPn.3 for CTIMERn"
bitfld.long 0x0 0.--1. "CTMODE,Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC)  or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale.." "0: Timer Mode. Incremented every rising APB bus..,1: Counter Mode rising edge. TC is incremented on..,2: Counter Mode falling edge. TC is incremented on..,3: Counter Mode dual edge. TC is incremented on.."
line.long 0x4 "PWMC,PWM Control Register. The PWMCON enables PWM mode for the external match pins."
bitfld.long 0x4 3. "PWMEN3,PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle." "0: Match. CTIMERn_MAT3 is controlled by EM3.,1: PWM. PWM mode is enabled for CT132Bn_MAT3."
bitfld.long 0x4 2. "PWMEN2,PWM mode enable for channel2." "0: Match. CTIMERn_MAT2 is controlled by EM2.,1: PWM. PWM mode is enabled for CTIMERn_MAT2."
newline
bitfld.long 0x4 1. "PWMEN1,PWM mode enable for channel1." "0: Match. CTIMERn_MAT01 is controlled by EM1.,1: PWM. PWM mode is enabled for CTIMERn_MAT1."
bitfld.long 0x4 0. "PWMEN0,PWM mode enable for channel0." "0: Match. CTIMERn_MAT0 is controlled by EM0.,1: PWM. PWM mode is enabled for CTIMERn_MAT0."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x78)++0x3
line.long 0x0 "MSR[$1],Match Shadow Register"
hexmask.long 0x0 0.--31. 1. "SHADOWW,Timer counter match shadow value."
repeat.end
tree.end
tree "CTIMER1"
base ad:0x40009000
group.long 0x0++0x17
line.long 0x0 "IR,Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending."
bitfld.long 0x0 7. "CR3INT,Interrupt flag for capture channel 3 event." "0,1"
bitfld.long 0x0 6. "CR2INT,Interrupt flag for capture channel 2 event." "0,1"
newline
bitfld.long 0x0 5. "CR1INT,Interrupt flag for capture channel 1 event." "0,1"
bitfld.long 0x0 4. "CR0INT,Interrupt flag for capture channel 0 event." "0,1"
newline
bitfld.long 0x0 3. "MR3INT,Interrupt flag for match channel 3." "0,1"
bitfld.long 0x0 2. "MR2INT,Interrupt flag for match channel 2." "0,1"
newline
bitfld.long 0x0 1. "MR1INT,Interrupt flag for match channel 1." "0,1"
bitfld.long 0x0 0. "MR0INT,Interrupt flag for match channel 0." "0,1"
line.long 0x4 "TCR,Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."
bitfld.long 0x4 1. "CRST,Counter reset." "0: Disabled. Do nothing.,1: Enabled. The Timer Counter and the Prescale.."
bitfld.long 0x4 0. "CEN,Counter enable." "0: Disabled.The counters are disabled.,1: Enabled. The Timer Counter and Prescale Counter.."
line.long 0x8 "TC,Timer Counter"
hexmask.long 0x8 0.--31. 1. "TCVAL,Timer counter value."
line.long 0xC "PR,Prescale Register"
hexmask.long 0xC 0.--31. 1. "PRVAL,Prescale counter value."
line.long 0x10 "PC,Prescale Counter"
hexmask.long 0x10 0.--31. 1. "PCVAL,Prescale counter value."
line.long 0x14 "MCR,Match Control Register"
bitfld.long 0x14 27. "MR3RL,Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 26. "MR2RL,Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 25. "MR1RL,Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 24. "MR0RL,Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 11. "MR3S,Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." "0,1"
bitfld.long 0x14 10. "MR3R,Reset on MR3: the TC will be reset if MR3 matches it." "0,1"
newline
bitfld.long 0x14 9. "MR3I,Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC." "0,1"
bitfld.long 0x14 8. "MR2S,Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC." "0,1"
newline
bitfld.long 0x14 7. "MR2R,Reset on MR2: the TC will be reset if MR2 matches it." "0,1"
bitfld.long 0x14 6. "MR2I,Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC." "0,1"
newline
bitfld.long 0x14 5. "MR1S,Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." "0,1"
bitfld.long 0x14 4. "MR1R,Reset on MR1: the TC will be reset if MR1 matches it." "0,1"
newline
bitfld.long 0x14 3. "MR1I,Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC." "0,1"
bitfld.long 0x14 2. "MR0S,Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." "0,1"
newline
bitfld.long 0x14 1. "MR0R,Reset on MR0: the TC will be reset if MR0 matches it." "0,1"
bitfld.long 0x14 0. "MR0I,Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC." "0,1"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x18)++0x3
line.long 0x0 "MR[$1],Match Register . MR can be enabled through the MCR to reset the TC. stop both the TC and PC. and/or generate an interrupt every time MR matches the TC."
hexmask.long 0x0 0.--31. 1. "MATCH,Timer counter match value."
repeat.end
group.long 0x28++0x3
line.long 0x0 "CCR,Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."
bitfld.long 0x0 11. "CAP3I,Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt." "0,1"
bitfld.long 0x0 10. "CAP3FE,Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 9. "CAP3RE,Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 8. "CAP2I,Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 7. "CAP2FE,Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 6. "CAP2RE,Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 5. "CAP1I,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt." "0,1"
bitfld.long 0x0 4. "CAP1FE,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 3. "CAP1RE,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 2. "CAP0I,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 1. "CAP0FE,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 0. "CAP0RE,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x2C)++0x3
line.long 0x0 "CR[$1],Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input."
hexmask.long 0x0 0.--31. 1. "CAP,Timer counter capture value."
repeat.end
group.long 0x3C++0x3
line.long 0x0 "EMR,External Match Register. The EMR controls the match function and the external match pins."
bitfld.long 0x0 10.--11. "EMC3,External Match Control 3. Determines the functionality of External Match 3." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 8.--9. "EMC2,External Match Control 2. Determines the functionality of External Match 2." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 6.--7. "EMC1,External Match Control 1. Determines the functionality of External Match 1." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 4.--5. "EMC0,External Match Control 0. Determines the functionality of External Match 0." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 3. "EM3,External Match 3. This bit reflects the state of output MAT3  whether or not this output is connected to a pin. When a match occurs between the TC and MR3  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by MR[11:10]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 2. "EM2,External Match 2. This bit reflects the state of output MAT2  whether or not this output is connected to a pin. When a match occurs between the TC and MR2  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[9:8]. This bit.." "0: LOW,1: HIGH"
newline
bitfld.long 0x0 1. "EM1,External Match 1. This bit reflects the state of output MAT1  whether or not this output is connected to a pin. When a match occurs between the TC and MR1  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[7:6]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 0. "EM0,External Match 0. This bit reflects the state of output MAT0  whether or not this output is connected to a pin. When a match occurs between the TC and MR0  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[5:4]. This bit.." "0: LOW,1: HIGH"
group.long 0x70++0x7
line.long 0x0 "CTCR,Count Control Register. The CTCR selects between Timer and Counter mode. and in Counter mode selects the signal and edge(s) for counting."
bitfld.long 0x0 5.--7. "SELCC,Edge select. When bit 4 is 1  these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved." "0: Channel 0 Rising Edge. Rising edge of the signal..,1: Channel 0 Falling Edge. Falling edge of the..,2: Channel 1 Rising Edge. Rising edge of the signal..,3: Channel 1 Falling Edge. Falling edge of the..,4: Channel 2 Rising Edge. Rising edge of the signal..,5: Channel 2 Falling Edge. Falling edge of the..,?,?"
bitfld.long 0x0 4. "ENCC,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." "0,1"
newline
bitfld.long 0x0 2.--3. "CINSEL,Count Input Select When bits 1:0 in this register are not 00  these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR  the 3 bits for that input in the Capture Control.." "0: Channel 0. CAPn.0 for CTIMERn,1: 0 in this register are not 00,2: Channel 2. CAPn.2 for CTIMERn,3: Channel 3. CAPn.3 for CTIMERn"
bitfld.long 0x0 0.--1. "CTMODE,Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC)  or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale.." "0: Timer Mode. Incremented every rising APB bus..,1: Counter Mode rising edge. TC is incremented on..,2: Counter Mode falling edge. TC is incremented on..,3: Counter Mode dual edge. TC is incremented on.."
line.long 0x4 "PWMC,PWM Control Register. The PWMCON enables PWM mode for the external match pins."
bitfld.long 0x4 3. "PWMEN3,PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle." "0: Match. CTIMERn_MAT3 is controlled by EM3.,1: PWM. PWM mode is enabled for CT132Bn_MAT3."
bitfld.long 0x4 2. "PWMEN2,PWM mode enable for channel2." "0: Match. CTIMERn_MAT2 is controlled by EM2.,1: PWM. PWM mode is enabled for CTIMERn_MAT2."
newline
bitfld.long 0x4 1. "PWMEN1,PWM mode enable for channel1." "0: Match. CTIMERn_MAT01 is controlled by EM1.,1: PWM. PWM mode is enabled for CTIMERn_MAT1."
bitfld.long 0x4 0. "PWMEN0,PWM mode enable for channel0." "0: Match. CTIMERn_MAT0 is controlled by EM0.,1: PWM. PWM mode is enabled for CTIMERn_MAT0."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x78)++0x3
line.long 0x0 "MSR[$1],Match Shadow Register"
hexmask.long 0x0 0.--31. 1. "SHADOWW,Timer counter match shadow value."
repeat.end
tree.end
tree "CTIMER2"
base ad:0x40028000
group.long 0x0++0x17
line.long 0x0 "IR,Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending."
bitfld.long 0x0 7. "CR3INT,Interrupt flag for capture channel 3 event." "0,1"
bitfld.long 0x0 6. "CR2INT,Interrupt flag for capture channel 2 event." "0,1"
newline
bitfld.long 0x0 5. "CR1INT,Interrupt flag for capture channel 1 event." "0,1"
bitfld.long 0x0 4. "CR0INT,Interrupt flag for capture channel 0 event." "0,1"
newline
bitfld.long 0x0 3. "MR3INT,Interrupt flag for match channel 3." "0,1"
bitfld.long 0x0 2. "MR2INT,Interrupt flag for match channel 2." "0,1"
newline
bitfld.long 0x0 1. "MR1INT,Interrupt flag for match channel 1." "0,1"
bitfld.long 0x0 0. "MR0INT,Interrupt flag for match channel 0." "0,1"
line.long 0x4 "TCR,Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."
bitfld.long 0x4 1. "CRST,Counter reset." "0: Disabled. Do nothing.,1: Enabled. The Timer Counter and the Prescale.."
bitfld.long 0x4 0. "CEN,Counter enable." "0: Disabled.The counters are disabled.,1: Enabled. The Timer Counter and Prescale Counter.."
line.long 0x8 "TC,Timer Counter"
hexmask.long 0x8 0.--31. 1. "TCVAL,Timer counter value."
line.long 0xC "PR,Prescale Register"
hexmask.long 0xC 0.--31. 1. "PRVAL,Prescale counter value."
line.long 0x10 "PC,Prescale Counter"
hexmask.long 0x10 0.--31. 1. "PCVAL,Prescale counter value."
line.long 0x14 "MCR,Match Control Register"
bitfld.long 0x14 27. "MR3RL,Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 26. "MR2RL,Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 25. "MR1RL,Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 24. "MR0RL,Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 11. "MR3S,Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." "0,1"
bitfld.long 0x14 10. "MR3R,Reset on MR3: the TC will be reset if MR3 matches it." "0,1"
newline
bitfld.long 0x14 9. "MR3I,Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC." "0,1"
bitfld.long 0x14 8. "MR2S,Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC." "0,1"
newline
bitfld.long 0x14 7. "MR2R,Reset on MR2: the TC will be reset if MR2 matches it." "0,1"
bitfld.long 0x14 6. "MR2I,Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC." "0,1"
newline
bitfld.long 0x14 5. "MR1S,Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." "0,1"
bitfld.long 0x14 4. "MR1R,Reset on MR1: the TC will be reset if MR1 matches it." "0,1"
newline
bitfld.long 0x14 3. "MR1I,Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC." "0,1"
bitfld.long 0x14 2. "MR0S,Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." "0,1"
newline
bitfld.long 0x14 1. "MR0R,Reset on MR0: the TC will be reset if MR0 matches it." "0,1"
bitfld.long 0x14 0. "MR0I,Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC." "0,1"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x18)++0x3
line.long 0x0 "MR[$1],Match Register . MR can be enabled through the MCR to reset the TC. stop both the TC and PC. and/or generate an interrupt every time MR matches the TC."
hexmask.long 0x0 0.--31. 1. "MATCH,Timer counter match value."
repeat.end
group.long 0x28++0x3
line.long 0x0 "CCR,Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."
bitfld.long 0x0 11. "CAP3I,Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt." "0,1"
bitfld.long 0x0 10. "CAP3FE,Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 9. "CAP3RE,Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 8. "CAP2I,Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 7. "CAP2FE,Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 6. "CAP2RE,Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 5. "CAP1I,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt." "0,1"
bitfld.long 0x0 4. "CAP1FE,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 3. "CAP1RE,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 2. "CAP0I,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 1. "CAP0FE,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 0. "CAP0RE,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x2C)++0x3
line.long 0x0 "CR[$1],Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input."
hexmask.long 0x0 0.--31. 1. "CAP,Timer counter capture value."
repeat.end
group.long 0x3C++0x3
line.long 0x0 "EMR,External Match Register. The EMR controls the match function and the external match pins."
bitfld.long 0x0 10.--11. "EMC3,External Match Control 3. Determines the functionality of External Match 3." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 8.--9. "EMC2,External Match Control 2. Determines the functionality of External Match 2." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 6.--7. "EMC1,External Match Control 1. Determines the functionality of External Match 1." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 4.--5. "EMC0,External Match Control 0. Determines the functionality of External Match 0." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 3. "EM3,External Match 3. This bit reflects the state of output MAT3  whether or not this output is connected to a pin. When a match occurs between the TC and MR3  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by MR[11:10]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 2. "EM2,External Match 2. This bit reflects the state of output MAT2  whether or not this output is connected to a pin. When a match occurs between the TC and MR2  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[9:8]. This bit.." "0: LOW,1: HIGH"
newline
bitfld.long 0x0 1. "EM1,External Match 1. This bit reflects the state of output MAT1  whether or not this output is connected to a pin. When a match occurs between the TC and MR1  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[7:6]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 0. "EM0,External Match 0. This bit reflects the state of output MAT0  whether or not this output is connected to a pin. When a match occurs between the TC and MR0  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[5:4]. This bit.." "0: LOW,1: HIGH"
group.long 0x70++0x7
line.long 0x0 "CTCR,Count Control Register. The CTCR selects between Timer and Counter mode. and in Counter mode selects the signal and edge(s) for counting."
bitfld.long 0x0 5.--7. "SELCC,Edge select. When bit 4 is 1  these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved." "0: Channel 0 Rising Edge. Rising edge of the signal..,1: Channel 0 Falling Edge. Falling edge of the..,2: Channel 1 Rising Edge. Rising edge of the signal..,3: Channel 1 Falling Edge. Falling edge of the..,4: Channel 2 Rising Edge. Rising edge of the signal..,5: Channel 2 Falling Edge. Falling edge of the..,?,?"
bitfld.long 0x0 4. "ENCC,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." "0,1"
newline
bitfld.long 0x0 2.--3. "CINSEL,Count Input Select When bits 1:0 in this register are not 00  these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR  the 3 bits for that input in the Capture Control.." "0: Channel 0. CAPn.0 for CTIMERn,1: 0 in this register are not 00,2: Channel 2. CAPn.2 for CTIMERn,3: Channel 3. CAPn.3 for CTIMERn"
bitfld.long 0x0 0.--1. "CTMODE,Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC)  or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale.." "0: Timer Mode. Incremented every rising APB bus..,1: Counter Mode rising edge. TC is incremented on..,2: Counter Mode falling edge. TC is incremented on..,3: Counter Mode dual edge. TC is incremented on.."
line.long 0x4 "PWMC,PWM Control Register. The PWMCON enables PWM mode for the external match pins."
bitfld.long 0x4 3. "PWMEN3,PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle." "0: Match. CTIMERn_MAT3 is controlled by EM3.,1: PWM. PWM mode is enabled for CT132Bn_MAT3."
bitfld.long 0x4 2. "PWMEN2,PWM mode enable for channel2." "0: Match. CTIMERn_MAT2 is controlled by EM2.,1: PWM. PWM mode is enabled for CTIMERn_MAT2."
newline
bitfld.long 0x4 1. "PWMEN1,PWM mode enable for channel1." "0: Match. CTIMERn_MAT01 is controlled by EM1.,1: PWM. PWM mode is enabled for CTIMERn_MAT1."
bitfld.long 0x4 0. "PWMEN0,PWM mode enable for channel0." "0: Match. CTIMERn_MAT0 is controlled by EM0.,1: PWM. PWM mode is enabled for CTIMERn_MAT0."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x78)++0x3
line.long 0x0 "MSR[$1],Match Shadow Register"
hexmask.long 0x0 0.--31. 1. "SHADOWW,Timer counter match shadow value."
repeat.end
tree.end
tree "CTIMER3"
base ad:0x40048000
group.long 0x0++0x17
line.long 0x0 "IR,Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending."
bitfld.long 0x0 7. "CR3INT,Interrupt flag for capture channel 3 event." "0,1"
bitfld.long 0x0 6. "CR2INT,Interrupt flag for capture channel 2 event." "0,1"
newline
bitfld.long 0x0 5. "CR1INT,Interrupt flag for capture channel 1 event." "0,1"
bitfld.long 0x0 4. "CR0INT,Interrupt flag for capture channel 0 event." "0,1"
newline
bitfld.long 0x0 3. "MR3INT,Interrupt flag for match channel 3." "0,1"
bitfld.long 0x0 2. "MR2INT,Interrupt flag for match channel 2." "0,1"
newline
bitfld.long 0x0 1. "MR1INT,Interrupt flag for match channel 1." "0,1"
bitfld.long 0x0 0. "MR0INT,Interrupt flag for match channel 0." "0,1"
line.long 0x4 "TCR,Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."
bitfld.long 0x4 1. "CRST,Counter reset." "0: Disabled. Do nothing.,1: Enabled. The Timer Counter and the Prescale.."
bitfld.long 0x4 0. "CEN,Counter enable." "0: Disabled.The counters are disabled.,1: Enabled. The Timer Counter and Prescale Counter.."
line.long 0x8 "TC,Timer Counter"
hexmask.long 0x8 0.--31. 1. "TCVAL,Timer counter value."
line.long 0xC "PR,Prescale Register"
hexmask.long 0xC 0.--31. 1. "PRVAL,Prescale counter value."
line.long 0x10 "PC,Prescale Counter"
hexmask.long 0x10 0.--31. 1. "PCVAL,Prescale counter value."
line.long 0x14 "MCR,Match Control Register"
bitfld.long 0x14 27. "MR3RL,Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 26. "MR2RL,Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 25. "MR1RL,Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 24. "MR0RL,Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 11. "MR3S,Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." "0,1"
bitfld.long 0x14 10. "MR3R,Reset on MR3: the TC will be reset if MR3 matches it." "0,1"
newline
bitfld.long 0x14 9. "MR3I,Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC." "0,1"
bitfld.long 0x14 8. "MR2S,Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC." "0,1"
newline
bitfld.long 0x14 7. "MR2R,Reset on MR2: the TC will be reset if MR2 matches it." "0,1"
bitfld.long 0x14 6. "MR2I,Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC." "0,1"
newline
bitfld.long 0x14 5. "MR1S,Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." "0,1"
bitfld.long 0x14 4. "MR1R,Reset on MR1: the TC will be reset if MR1 matches it." "0,1"
newline
bitfld.long 0x14 3. "MR1I,Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC." "0,1"
bitfld.long 0x14 2. "MR0S,Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." "0,1"
newline
bitfld.long 0x14 1. "MR0R,Reset on MR0: the TC will be reset if MR0 matches it." "0,1"
bitfld.long 0x14 0. "MR0I,Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC." "0,1"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x18)++0x3
line.long 0x0 "MR[$1],Match Register . MR can be enabled through the MCR to reset the TC. stop both the TC and PC. and/or generate an interrupt every time MR matches the TC."
hexmask.long 0x0 0.--31. 1. "MATCH,Timer counter match value."
repeat.end
group.long 0x28++0x3
line.long 0x0 "CCR,Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."
bitfld.long 0x0 11. "CAP3I,Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt." "0,1"
bitfld.long 0x0 10. "CAP3FE,Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 9. "CAP3RE,Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 8. "CAP2I,Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 7. "CAP2FE,Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 6. "CAP2RE,Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 5. "CAP1I,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt." "0,1"
bitfld.long 0x0 4. "CAP1FE,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 3. "CAP1RE,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 2. "CAP0I,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 1. "CAP0FE,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 0. "CAP0RE,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x2C)++0x3
line.long 0x0 "CR[$1],Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input."
hexmask.long 0x0 0.--31. 1. "CAP,Timer counter capture value."
repeat.end
group.long 0x3C++0x3
line.long 0x0 "EMR,External Match Register. The EMR controls the match function and the external match pins."
bitfld.long 0x0 10.--11. "EMC3,External Match Control 3. Determines the functionality of External Match 3." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 8.--9. "EMC2,External Match Control 2. Determines the functionality of External Match 2." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 6.--7. "EMC1,External Match Control 1. Determines the functionality of External Match 1." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 4.--5. "EMC0,External Match Control 0. Determines the functionality of External Match 0." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 3. "EM3,External Match 3. This bit reflects the state of output MAT3  whether or not this output is connected to a pin. When a match occurs between the TC and MR3  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by MR[11:10]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 2. "EM2,External Match 2. This bit reflects the state of output MAT2  whether or not this output is connected to a pin. When a match occurs between the TC and MR2  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[9:8]. This bit.." "0: LOW,1: HIGH"
newline
bitfld.long 0x0 1. "EM1,External Match 1. This bit reflects the state of output MAT1  whether or not this output is connected to a pin. When a match occurs between the TC and MR1  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[7:6]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 0. "EM0,External Match 0. This bit reflects the state of output MAT0  whether or not this output is connected to a pin. When a match occurs between the TC and MR0  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[5:4]. This bit.." "0: LOW,1: HIGH"
group.long 0x70++0x7
line.long 0x0 "CTCR,Count Control Register. The CTCR selects between Timer and Counter mode. and in Counter mode selects the signal and edge(s) for counting."
bitfld.long 0x0 5.--7. "SELCC,Edge select. When bit 4 is 1  these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved." "0: Channel 0 Rising Edge. Rising edge of the signal..,1: Channel 0 Falling Edge. Falling edge of the..,2: Channel 1 Rising Edge. Rising edge of the signal..,3: Channel 1 Falling Edge. Falling edge of the..,4: Channel 2 Rising Edge. Rising edge of the signal..,5: Channel 2 Falling Edge. Falling edge of the..,?,?"
bitfld.long 0x0 4. "ENCC,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." "0,1"
newline
bitfld.long 0x0 2.--3. "CINSEL,Count Input Select When bits 1:0 in this register are not 00  these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR  the 3 bits for that input in the Capture Control.." "0: Channel 0. CAPn.0 for CTIMERn,1: 0 in this register are not 00,2: Channel 2. CAPn.2 for CTIMERn,3: Channel 3. CAPn.3 for CTIMERn"
bitfld.long 0x0 0.--1. "CTMODE,Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC)  or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale.." "0: Timer Mode. Incremented every rising APB bus..,1: Counter Mode rising edge. TC is incremented on..,2: Counter Mode falling edge. TC is incremented on..,3: Counter Mode dual edge. TC is incremented on.."
line.long 0x4 "PWMC,PWM Control Register. The PWMCON enables PWM mode for the external match pins."
bitfld.long 0x4 3. "PWMEN3,PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle." "0: Match. CTIMERn_MAT3 is controlled by EM3.,1: PWM. PWM mode is enabled for CT132Bn_MAT3."
bitfld.long 0x4 2. "PWMEN2,PWM mode enable for channel2." "0: Match. CTIMERn_MAT2 is controlled by EM2.,1: PWM. PWM mode is enabled for CTIMERn_MAT2."
newline
bitfld.long 0x4 1. "PWMEN1,PWM mode enable for channel1." "0: Match. CTIMERn_MAT01 is controlled by EM1.,1: PWM. PWM mode is enabled for CTIMERn_MAT1."
bitfld.long 0x4 0. "PWMEN0,PWM mode enable for channel0." "0: Match. CTIMERn_MAT0 is controlled by EM0.,1: PWM. PWM mode is enabled for CTIMERn_MAT0."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x78)++0x3
line.long 0x0 "MSR[$1],Match Shadow Register"
hexmask.long 0x0 0.--31. 1. "SHADOWW,Timer counter match shadow value."
repeat.end
tree.end
tree "CTIMER4"
base ad:0x40049000
group.long 0x0++0x17
line.long 0x0 "IR,Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending."
bitfld.long 0x0 7. "CR3INT,Interrupt flag for capture channel 3 event." "0,1"
bitfld.long 0x0 6. "CR2INT,Interrupt flag for capture channel 2 event." "0,1"
newline
bitfld.long 0x0 5. "CR1INT,Interrupt flag for capture channel 1 event." "0,1"
bitfld.long 0x0 4. "CR0INT,Interrupt flag for capture channel 0 event." "0,1"
newline
bitfld.long 0x0 3. "MR3INT,Interrupt flag for match channel 3." "0,1"
bitfld.long 0x0 2. "MR2INT,Interrupt flag for match channel 2." "0,1"
newline
bitfld.long 0x0 1. "MR1INT,Interrupt flag for match channel 1." "0,1"
bitfld.long 0x0 0. "MR0INT,Interrupt flag for match channel 0." "0,1"
line.long 0x4 "TCR,Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."
bitfld.long 0x4 1. "CRST,Counter reset." "0: Disabled. Do nothing.,1: Enabled. The Timer Counter and the Prescale.."
bitfld.long 0x4 0. "CEN,Counter enable." "0: Disabled.The counters are disabled.,1: Enabled. The Timer Counter and Prescale Counter.."
line.long 0x8 "TC,Timer Counter"
hexmask.long 0x8 0.--31. 1. "TCVAL,Timer counter value."
line.long 0xC "PR,Prescale Register"
hexmask.long 0xC 0.--31. 1. "PRVAL,Prescale counter value."
line.long 0x10 "PC,Prescale Counter"
hexmask.long 0x10 0.--31. 1. "PCVAL,Prescale counter value."
line.long 0x14 "MCR,Match Control Register"
bitfld.long 0x14 27. "MR3RL,Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 26. "MR2RL,Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 25. "MR1RL,Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 24. "MR0RL,Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 11. "MR3S,Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." "0,1"
bitfld.long 0x14 10. "MR3R,Reset on MR3: the TC will be reset if MR3 matches it." "0,1"
newline
bitfld.long 0x14 9. "MR3I,Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC." "0,1"
bitfld.long 0x14 8. "MR2S,Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC." "0,1"
newline
bitfld.long 0x14 7. "MR2R,Reset on MR2: the TC will be reset if MR2 matches it." "0,1"
bitfld.long 0x14 6. "MR2I,Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC." "0,1"
newline
bitfld.long 0x14 5. "MR1S,Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." "0,1"
bitfld.long 0x14 4. "MR1R,Reset on MR1: the TC will be reset if MR1 matches it." "0,1"
newline
bitfld.long 0x14 3. "MR1I,Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC." "0,1"
bitfld.long 0x14 2. "MR0S,Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." "0,1"
newline
bitfld.long 0x14 1. "MR0R,Reset on MR0: the TC will be reset if MR0 matches it." "0,1"
bitfld.long 0x14 0. "MR0I,Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC." "0,1"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x18)++0x3
line.long 0x0 "MR[$1],Match Register . MR can be enabled through the MCR to reset the TC. stop both the TC and PC. and/or generate an interrupt every time MR matches the TC."
hexmask.long 0x0 0.--31. 1. "MATCH,Timer counter match value."
repeat.end
group.long 0x28++0x3
line.long 0x0 "CCR,Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."
bitfld.long 0x0 11. "CAP3I,Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt." "0,1"
bitfld.long 0x0 10. "CAP3FE,Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 9. "CAP3RE,Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 8. "CAP2I,Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 7. "CAP2FE,Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 6. "CAP2RE,Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 5. "CAP1I,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt." "0,1"
bitfld.long 0x0 4. "CAP1FE,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 3. "CAP1RE,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 2. "CAP0I,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 1. "CAP0FE,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 0. "CAP0RE,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x2C)++0x3
line.long 0x0 "CR[$1],Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input."
hexmask.long 0x0 0.--31. 1. "CAP,Timer counter capture value."
repeat.end
group.long 0x3C++0x3
line.long 0x0 "EMR,External Match Register. The EMR controls the match function and the external match pins."
bitfld.long 0x0 10.--11. "EMC3,External Match Control 3. Determines the functionality of External Match 3." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 8.--9. "EMC2,External Match Control 2. Determines the functionality of External Match 2." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 6.--7. "EMC1,External Match Control 1. Determines the functionality of External Match 1." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 4.--5. "EMC0,External Match Control 0. Determines the functionality of External Match 0." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 3. "EM3,External Match 3. This bit reflects the state of output MAT3  whether or not this output is connected to a pin. When a match occurs between the TC and MR3  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by MR[11:10]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 2. "EM2,External Match 2. This bit reflects the state of output MAT2  whether or not this output is connected to a pin. When a match occurs between the TC and MR2  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[9:8]. This bit.." "0: LOW,1: HIGH"
newline
bitfld.long 0x0 1. "EM1,External Match 1. This bit reflects the state of output MAT1  whether or not this output is connected to a pin. When a match occurs between the TC and MR1  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[7:6]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 0. "EM0,External Match 0. This bit reflects the state of output MAT0  whether or not this output is connected to a pin. When a match occurs between the TC and MR0  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[5:4]. This bit.." "0: LOW,1: HIGH"
group.long 0x70++0x7
line.long 0x0 "CTCR,Count Control Register. The CTCR selects between Timer and Counter mode. and in Counter mode selects the signal and edge(s) for counting."
bitfld.long 0x0 5.--7. "SELCC,Edge select. When bit 4 is 1  these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved." "0: Channel 0 Rising Edge. Rising edge of the signal..,1: Channel 0 Falling Edge. Falling edge of the..,2: Channel 1 Rising Edge. Rising edge of the signal..,3: Channel 1 Falling Edge. Falling edge of the..,4: Channel 2 Rising Edge. Rising edge of the signal..,5: Channel 2 Falling Edge. Falling edge of the..,?,?"
bitfld.long 0x0 4. "ENCC,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." "0,1"
newline
bitfld.long 0x0 2.--3. "CINSEL,Count Input Select When bits 1:0 in this register are not 00  these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR  the 3 bits for that input in the Capture Control.." "0: Channel 0. CAPn.0 for CTIMERn,1: 0 in this register are not 00,2: Channel 2. CAPn.2 for CTIMERn,3: Channel 3. CAPn.3 for CTIMERn"
bitfld.long 0x0 0.--1. "CTMODE,Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC)  or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale.." "0: Timer Mode. Incremented every rising APB bus..,1: Counter Mode rising edge. TC is incremented on..,2: Counter Mode falling edge. TC is incremented on..,3: Counter Mode dual edge. TC is incremented on.."
line.long 0x4 "PWMC,PWM Control Register. The PWMCON enables PWM mode for the external match pins."
bitfld.long 0x4 3. "PWMEN3,PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle." "0: Match. CTIMERn_MAT3 is controlled by EM3.,1: PWM. PWM mode is enabled for CT132Bn_MAT3."
bitfld.long 0x4 2. "PWMEN2,PWM mode enable for channel2." "0: Match. CTIMERn_MAT2 is controlled by EM2.,1: PWM. PWM mode is enabled for CTIMERn_MAT2."
newline
bitfld.long 0x4 1. "PWMEN1,PWM mode enable for channel1." "0: Match. CTIMERn_MAT01 is controlled by EM1.,1: PWM. PWM mode is enabled for CTIMERn_MAT1."
bitfld.long 0x4 0. "PWMEN0,PWM mode enable for channel0." "0: Match. CTIMERn_MAT0 is controlled by EM0.,1: PWM. PWM mode is enabled for CTIMERn_MAT0."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x78)++0x3
line.long 0x0 "MSR[$1],Match Shadow Register"
hexmask.long 0x0 0.--31. 1. "SHADOWW,Timer counter match shadow value."
repeat.end
tree.end
endif
sif (cpuis("LPC54618*"))
tree "CTIMER0"
base ad:0x40008000
group.long 0x0++0x17
line.long 0x0 "IR,Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending."
bitfld.long 0x0 7. "CR3INT,Interrupt flag for capture channel 3 event." "0,1"
bitfld.long 0x0 6. "CR2INT,Interrupt flag for capture channel 2 event." "0,1"
newline
bitfld.long 0x0 5. "CR1INT,Interrupt flag for capture channel 1 event." "0,1"
bitfld.long 0x0 4. "CR0INT,Interrupt flag for capture channel 0 event." "0,1"
newline
bitfld.long 0x0 3. "MR3INT,Interrupt flag for match channel 3." "0,1"
bitfld.long 0x0 2. "MR2INT,Interrupt flag for match channel 2." "0,1"
newline
bitfld.long 0x0 1. "MR1INT,Interrupt flag for match channel 1." "0,1"
bitfld.long 0x0 0. "MR0INT,Interrupt flag for match channel 0." "0,1"
line.long 0x4 "TCR,Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."
bitfld.long 0x4 1. "CRST,Counter reset." "0: Disabled. Do nothing.,1: Enabled. The Timer Counter and the Prescale.."
bitfld.long 0x4 0. "CEN,Counter enable." "0: Disabled.The counters are disabled.,1: Enabled. The Timer Counter and Prescale Counter.."
line.long 0x8 "TC,Timer Counter"
hexmask.long 0x8 0.--31. 1. "TCVAL,Timer counter value."
line.long 0xC "PR,Prescale Register"
hexmask.long 0xC 0.--31. 1. "PRVAL,Prescale counter value."
line.long 0x10 "PC,Prescale Counter"
hexmask.long 0x10 0.--31. 1. "PCVAL,Prescale counter value."
line.long 0x14 "MCR,Match Control Register"
bitfld.long 0x14 27. "MR3RL,Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 26. "MR2RL,Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 25. "MR1RL,Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 24. "MR0RL,Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 11. "MR3S,Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." "0,1"
bitfld.long 0x14 10. "MR3R,Reset on MR3: the TC will be reset if MR3 matches it." "0,1"
newline
bitfld.long 0x14 9. "MR3I,Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC." "0,1"
bitfld.long 0x14 8. "MR2S,Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC." "0,1"
newline
bitfld.long 0x14 7. "MR2R,Reset on MR2: the TC will be reset if MR2 matches it." "0,1"
bitfld.long 0x14 6. "MR2I,Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC." "0,1"
newline
bitfld.long 0x14 5. "MR1S,Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." "0,1"
bitfld.long 0x14 4. "MR1R,Reset on MR1: the TC will be reset if MR1 matches it." "0,1"
newline
bitfld.long 0x14 3. "MR1I,Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC." "0,1"
bitfld.long 0x14 2. "MR0S,Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." "0,1"
newline
bitfld.long 0x14 1. "MR0R,Reset on MR0: the TC will be reset if MR0 matches it." "0,1"
bitfld.long 0x14 0. "MR0I,Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC." "0,1"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x18)++0x3
line.long 0x0 "MR[$1],Match Register . MR can be enabled through the MCR to reset the TC. stop both the TC and PC. and/or generate an interrupt every time MR matches the TC."
hexmask.long 0x0 0.--31. 1. "MATCH,Timer counter match value."
repeat.end
group.long 0x28++0x3
line.long 0x0 "CCR,Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."
bitfld.long 0x0 11. "CAP3I,Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt." "0,1"
bitfld.long 0x0 10. "CAP3FE,Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 9. "CAP3RE,Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 8. "CAP2I,Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 7. "CAP2FE,Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 6. "CAP2RE,Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 5. "CAP1I,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt." "0,1"
bitfld.long 0x0 4. "CAP1FE,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 3. "CAP1RE,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 2. "CAP0I,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 1. "CAP0FE,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 0. "CAP0RE,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x2C)++0x3
line.long 0x0 "CR[$1],Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input."
hexmask.long 0x0 0.--31. 1. "CAP,Timer counter capture value."
repeat.end
group.long 0x3C++0x3
line.long 0x0 "EMR,External Match Register. The EMR controls the match function and the external match pins."
bitfld.long 0x0 10.--11. "EMC3,External Match Control 3. Determines the functionality of External Match 3." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 8.--9. "EMC2,External Match Control 2. Determines the functionality of External Match 2." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 6.--7. "EMC1,External Match Control 1. Determines the functionality of External Match 1." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 4.--5. "EMC0,External Match Control 0. Determines the functionality of External Match 0." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 3. "EM3,External Match 3. This bit reflects the state of output MAT3  whether or not this output is connected to a pin. When a match occurs between the TC and MR3  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by MR[11:10]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 2. "EM2,External Match 2. This bit reflects the state of output MAT2  whether or not this output is connected to a pin. When a match occurs between the TC and MR2  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[9:8]. This bit.." "0: LOW,1: HIGH"
newline
bitfld.long 0x0 1. "EM1,External Match 1. This bit reflects the state of output MAT1  whether or not this output is connected to a pin. When a match occurs between the TC and MR1  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[7:6]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 0. "EM0,External Match 0. This bit reflects the state of output MAT0  whether or not this output is connected to a pin. When a match occurs between the TC and MR0  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[5:4]. This bit.." "0: LOW,1: HIGH"
group.long 0x70++0x7
line.long 0x0 "CTCR,Count Control Register. The CTCR selects between Timer and Counter mode. and in Counter mode selects the signal and edge(s) for counting."
bitfld.long 0x0 5.--7. "SELCC,Edge select. When bit 4 is 1  these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved." "0: Channel 0 Rising Edge. Rising edge of the signal..,1: Channel 0 Falling Edge. Falling edge of the..,2: Channel 1 Rising Edge. Rising edge of the signal..,3: Channel 1 Falling Edge. Falling edge of the..,4: Channel 2 Rising Edge. Rising edge of the signal..,5: Channel 2 Falling Edge. Falling edge of the..,?,?"
bitfld.long 0x0 4. "ENCC,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." "0,1"
newline
bitfld.long 0x0 2.--3. "CINSEL,Count Input Select When bits 1:0 in this register are not 00  these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR  the 3 bits for that input in the Capture Control.." "0: Channel 0. CAPn.0 for CTIMERn,1: 0 in this register are not 00,2: Channel 2. CAPn.2 for CTIMERn,3: Channel 3. CAPn.3 for CTIMERn"
bitfld.long 0x0 0.--1. "CTMODE,Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC)  or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale.." "0: Timer Mode. Incremented every rising APB bus..,1: Counter Mode rising edge. TC is incremented on..,2: Counter Mode falling edge. TC is incremented on..,3: Counter Mode dual edge. TC is incremented on.."
line.long 0x4 "PWMC,PWM Control Register. The PWMCON enables PWM mode for the external match pins."
bitfld.long 0x4 3. "PWMEN3,PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle." "0: Match. CTIMERn_MAT3 is controlled by EM3.,1: PWM. PWM mode is enabled for CT132Bn_MAT3."
bitfld.long 0x4 2. "PWMEN2,PWM mode enable for channel2." "0: Match. CTIMERn_MAT2 is controlled by EM2.,1: PWM. PWM mode is enabled for CTIMERn_MAT2."
newline
bitfld.long 0x4 1. "PWMEN1,PWM mode enable for channel1." "0: Match. CTIMERn_MAT01 is controlled by EM1.,1: PWM. PWM mode is enabled for CTIMERn_MAT1."
bitfld.long 0x4 0. "PWMEN0,PWM mode enable for channel0." "0: Match. CTIMERn_MAT0 is controlled by EM0.,1: PWM. PWM mode is enabled for CTIMERn_MAT0."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x78)++0x3
line.long 0x0 "MSR[$1],Match Shadow Register"
hexmask.long 0x0 0.--31. 1. "SHADOWW,Timer counter match shadow value."
repeat.end
tree.end
tree "CTIMER1"
base ad:0x40009000
group.long 0x0++0x17
line.long 0x0 "IR,Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending."
bitfld.long 0x0 7. "CR3INT,Interrupt flag for capture channel 3 event." "0,1"
bitfld.long 0x0 6. "CR2INT,Interrupt flag for capture channel 2 event." "0,1"
newline
bitfld.long 0x0 5. "CR1INT,Interrupt flag for capture channel 1 event." "0,1"
bitfld.long 0x0 4. "CR0INT,Interrupt flag for capture channel 0 event." "0,1"
newline
bitfld.long 0x0 3. "MR3INT,Interrupt flag for match channel 3." "0,1"
bitfld.long 0x0 2. "MR2INT,Interrupt flag for match channel 2." "0,1"
newline
bitfld.long 0x0 1. "MR1INT,Interrupt flag for match channel 1." "0,1"
bitfld.long 0x0 0. "MR0INT,Interrupt flag for match channel 0." "0,1"
line.long 0x4 "TCR,Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."
bitfld.long 0x4 1. "CRST,Counter reset." "0: Disabled. Do nothing.,1: Enabled. The Timer Counter and the Prescale.."
bitfld.long 0x4 0. "CEN,Counter enable." "0: Disabled.The counters are disabled.,1: Enabled. The Timer Counter and Prescale Counter.."
line.long 0x8 "TC,Timer Counter"
hexmask.long 0x8 0.--31. 1. "TCVAL,Timer counter value."
line.long 0xC "PR,Prescale Register"
hexmask.long 0xC 0.--31. 1. "PRVAL,Prescale counter value."
line.long 0x10 "PC,Prescale Counter"
hexmask.long 0x10 0.--31. 1. "PCVAL,Prescale counter value."
line.long 0x14 "MCR,Match Control Register"
bitfld.long 0x14 27. "MR3RL,Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 26. "MR2RL,Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 25. "MR1RL,Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 24. "MR0RL,Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 11. "MR3S,Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." "0,1"
bitfld.long 0x14 10. "MR3R,Reset on MR3: the TC will be reset if MR3 matches it." "0,1"
newline
bitfld.long 0x14 9. "MR3I,Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC." "0,1"
bitfld.long 0x14 8. "MR2S,Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC." "0,1"
newline
bitfld.long 0x14 7. "MR2R,Reset on MR2: the TC will be reset if MR2 matches it." "0,1"
bitfld.long 0x14 6. "MR2I,Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC." "0,1"
newline
bitfld.long 0x14 5. "MR1S,Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." "0,1"
bitfld.long 0x14 4. "MR1R,Reset on MR1: the TC will be reset if MR1 matches it." "0,1"
newline
bitfld.long 0x14 3. "MR1I,Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC." "0,1"
bitfld.long 0x14 2. "MR0S,Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." "0,1"
newline
bitfld.long 0x14 1. "MR0R,Reset on MR0: the TC will be reset if MR0 matches it." "0,1"
bitfld.long 0x14 0. "MR0I,Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC." "0,1"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x18)++0x3
line.long 0x0 "MR[$1],Match Register . MR can be enabled through the MCR to reset the TC. stop both the TC and PC. and/or generate an interrupt every time MR matches the TC."
hexmask.long 0x0 0.--31. 1. "MATCH,Timer counter match value."
repeat.end
group.long 0x28++0x3
line.long 0x0 "CCR,Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."
bitfld.long 0x0 11. "CAP3I,Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt." "0,1"
bitfld.long 0x0 10. "CAP3FE,Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 9. "CAP3RE,Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 8. "CAP2I,Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 7. "CAP2FE,Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 6. "CAP2RE,Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 5. "CAP1I,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt." "0,1"
bitfld.long 0x0 4. "CAP1FE,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 3. "CAP1RE,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 2. "CAP0I,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 1. "CAP0FE,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 0. "CAP0RE,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x2C)++0x3
line.long 0x0 "CR[$1],Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input."
hexmask.long 0x0 0.--31. 1. "CAP,Timer counter capture value."
repeat.end
group.long 0x3C++0x3
line.long 0x0 "EMR,External Match Register. The EMR controls the match function and the external match pins."
bitfld.long 0x0 10.--11. "EMC3,External Match Control 3. Determines the functionality of External Match 3." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 8.--9. "EMC2,External Match Control 2. Determines the functionality of External Match 2." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 6.--7. "EMC1,External Match Control 1. Determines the functionality of External Match 1." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 4.--5. "EMC0,External Match Control 0. Determines the functionality of External Match 0." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 3. "EM3,External Match 3. This bit reflects the state of output MAT3  whether or not this output is connected to a pin. When a match occurs between the TC and MR3  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by MR[11:10]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 2. "EM2,External Match 2. This bit reflects the state of output MAT2  whether or not this output is connected to a pin. When a match occurs between the TC and MR2  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[9:8]. This bit.." "0: LOW,1: HIGH"
newline
bitfld.long 0x0 1. "EM1,External Match 1. This bit reflects the state of output MAT1  whether or not this output is connected to a pin. When a match occurs between the TC and MR1  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[7:6]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 0. "EM0,External Match 0. This bit reflects the state of output MAT0  whether or not this output is connected to a pin. When a match occurs between the TC and MR0  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[5:4]. This bit.." "0: LOW,1: HIGH"
group.long 0x70++0x7
line.long 0x0 "CTCR,Count Control Register. The CTCR selects between Timer and Counter mode. and in Counter mode selects the signal and edge(s) for counting."
bitfld.long 0x0 5.--7. "SELCC,Edge select. When bit 4 is 1  these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved." "0: Channel 0 Rising Edge. Rising edge of the signal..,1: Channel 0 Falling Edge. Falling edge of the..,2: Channel 1 Rising Edge. Rising edge of the signal..,3: Channel 1 Falling Edge. Falling edge of the..,4: Channel 2 Rising Edge. Rising edge of the signal..,5: Channel 2 Falling Edge. Falling edge of the..,?,?"
bitfld.long 0x0 4. "ENCC,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." "0,1"
newline
bitfld.long 0x0 2.--3. "CINSEL,Count Input Select When bits 1:0 in this register are not 00  these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR  the 3 bits for that input in the Capture Control.." "0: Channel 0. CAPn.0 for CTIMERn,1: 0 in this register are not 00,2: Channel 2. CAPn.2 for CTIMERn,3: Channel 3. CAPn.3 for CTIMERn"
bitfld.long 0x0 0.--1. "CTMODE,Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC)  or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale.." "0: Timer Mode. Incremented every rising APB bus..,1: Counter Mode rising edge. TC is incremented on..,2: Counter Mode falling edge. TC is incremented on..,3: Counter Mode dual edge. TC is incremented on.."
line.long 0x4 "PWMC,PWM Control Register. The PWMCON enables PWM mode for the external match pins."
bitfld.long 0x4 3. "PWMEN3,PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle." "0: Match. CTIMERn_MAT3 is controlled by EM3.,1: PWM. PWM mode is enabled for CT132Bn_MAT3."
bitfld.long 0x4 2. "PWMEN2,PWM mode enable for channel2." "0: Match. CTIMERn_MAT2 is controlled by EM2.,1: PWM. PWM mode is enabled for CTIMERn_MAT2."
newline
bitfld.long 0x4 1. "PWMEN1,PWM mode enable for channel1." "0: Match. CTIMERn_MAT01 is controlled by EM1.,1: PWM. PWM mode is enabled for CTIMERn_MAT1."
bitfld.long 0x4 0. "PWMEN0,PWM mode enable for channel0." "0: Match. CTIMERn_MAT0 is controlled by EM0.,1: PWM. PWM mode is enabled for CTIMERn_MAT0."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x78)++0x3
line.long 0x0 "MSR[$1],Match Shadow Register"
hexmask.long 0x0 0.--31. 1. "SHADOWW,Timer counter match shadow value."
repeat.end
tree.end
tree "CTIMER2"
base ad:0x40028000
group.long 0x0++0x17
line.long 0x0 "IR,Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending."
bitfld.long 0x0 7. "CR3INT,Interrupt flag for capture channel 3 event." "0,1"
bitfld.long 0x0 6. "CR2INT,Interrupt flag for capture channel 2 event." "0,1"
newline
bitfld.long 0x0 5. "CR1INT,Interrupt flag for capture channel 1 event." "0,1"
bitfld.long 0x0 4. "CR0INT,Interrupt flag for capture channel 0 event." "0,1"
newline
bitfld.long 0x0 3. "MR3INT,Interrupt flag for match channel 3." "0,1"
bitfld.long 0x0 2. "MR2INT,Interrupt flag for match channel 2." "0,1"
newline
bitfld.long 0x0 1. "MR1INT,Interrupt flag for match channel 1." "0,1"
bitfld.long 0x0 0. "MR0INT,Interrupt flag for match channel 0." "0,1"
line.long 0x4 "TCR,Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."
bitfld.long 0x4 1. "CRST,Counter reset." "0: Disabled. Do nothing.,1: Enabled. The Timer Counter and the Prescale.."
bitfld.long 0x4 0. "CEN,Counter enable." "0: Disabled.The counters are disabled.,1: Enabled. The Timer Counter and Prescale Counter.."
line.long 0x8 "TC,Timer Counter"
hexmask.long 0x8 0.--31. 1. "TCVAL,Timer counter value."
line.long 0xC "PR,Prescale Register"
hexmask.long 0xC 0.--31. 1. "PRVAL,Prescale counter value."
line.long 0x10 "PC,Prescale Counter"
hexmask.long 0x10 0.--31. 1. "PCVAL,Prescale counter value."
line.long 0x14 "MCR,Match Control Register"
bitfld.long 0x14 27. "MR3RL,Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 26. "MR2RL,Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 25. "MR1RL,Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 24. "MR0RL,Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 11. "MR3S,Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." "0,1"
bitfld.long 0x14 10. "MR3R,Reset on MR3: the TC will be reset if MR3 matches it." "0,1"
newline
bitfld.long 0x14 9. "MR3I,Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC." "0,1"
bitfld.long 0x14 8. "MR2S,Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC." "0,1"
newline
bitfld.long 0x14 7. "MR2R,Reset on MR2: the TC will be reset if MR2 matches it." "0,1"
bitfld.long 0x14 6. "MR2I,Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC." "0,1"
newline
bitfld.long 0x14 5. "MR1S,Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." "0,1"
bitfld.long 0x14 4. "MR1R,Reset on MR1: the TC will be reset if MR1 matches it." "0,1"
newline
bitfld.long 0x14 3. "MR1I,Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC." "0,1"
bitfld.long 0x14 2. "MR0S,Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." "0,1"
newline
bitfld.long 0x14 1. "MR0R,Reset on MR0: the TC will be reset if MR0 matches it." "0,1"
bitfld.long 0x14 0. "MR0I,Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC." "0,1"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x18)++0x3
line.long 0x0 "MR[$1],Match Register . MR can be enabled through the MCR to reset the TC. stop both the TC and PC. and/or generate an interrupt every time MR matches the TC."
hexmask.long 0x0 0.--31. 1. "MATCH,Timer counter match value."
repeat.end
group.long 0x28++0x3
line.long 0x0 "CCR,Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."
bitfld.long 0x0 11. "CAP3I,Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt." "0,1"
bitfld.long 0x0 10. "CAP3FE,Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 9. "CAP3RE,Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 8. "CAP2I,Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 7. "CAP2FE,Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 6. "CAP2RE,Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 5. "CAP1I,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt." "0,1"
bitfld.long 0x0 4. "CAP1FE,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 3. "CAP1RE,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 2. "CAP0I,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 1. "CAP0FE,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 0. "CAP0RE,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x2C)++0x3
line.long 0x0 "CR[$1],Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input."
hexmask.long 0x0 0.--31. 1. "CAP,Timer counter capture value."
repeat.end
group.long 0x3C++0x3
line.long 0x0 "EMR,External Match Register. The EMR controls the match function and the external match pins."
bitfld.long 0x0 10.--11. "EMC3,External Match Control 3. Determines the functionality of External Match 3." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 8.--9. "EMC2,External Match Control 2. Determines the functionality of External Match 2." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 6.--7. "EMC1,External Match Control 1. Determines the functionality of External Match 1." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 4.--5. "EMC0,External Match Control 0. Determines the functionality of External Match 0." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 3. "EM3,External Match 3. This bit reflects the state of output MAT3  whether or not this output is connected to a pin. When a match occurs between the TC and MR3  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by MR[11:10]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 2. "EM2,External Match 2. This bit reflects the state of output MAT2  whether or not this output is connected to a pin. When a match occurs between the TC and MR2  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[9:8]. This bit.." "0: LOW,1: HIGH"
newline
bitfld.long 0x0 1. "EM1,External Match 1. This bit reflects the state of output MAT1  whether or not this output is connected to a pin. When a match occurs between the TC and MR1  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[7:6]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 0. "EM0,External Match 0. This bit reflects the state of output MAT0  whether or not this output is connected to a pin. When a match occurs between the TC and MR0  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[5:4]. This bit.." "0: LOW,1: HIGH"
group.long 0x70++0x7
line.long 0x0 "CTCR,Count Control Register. The CTCR selects between Timer and Counter mode. and in Counter mode selects the signal and edge(s) for counting."
bitfld.long 0x0 5.--7. "SELCC,Edge select. When bit 4 is 1  these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved." "0: Channel 0 Rising Edge. Rising edge of the signal..,1: Channel 0 Falling Edge. Falling edge of the..,2: Channel 1 Rising Edge. Rising edge of the signal..,3: Channel 1 Falling Edge. Falling edge of the..,4: Channel 2 Rising Edge. Rising edge of the signal..,5: Channel 2 Falling Edge. Falling edge of the..,?,?"
bitfld.long 0x0 4. "ENCC,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." "0,1"
newline
bitfld.long 0x0 2.--3. "CINSEL,Count Input Select When bits 1:0 in this register are not 00  these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR  the 3 bits for that input in the Capture Control.." "0: Channel 0. CAPn.0 for CTIMERn,1: 0 in this register are not 00,2: Channel 2. CAPn.2 for CTIMERn,3: Channel 3. CAPn.3 for CTIMERn"
bitfld.long 0x0 0.--1. "CTMODE,Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC)  or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale.." "0: Timer Mode. Incremented every rising APB bus..,1: Counter Mode rising edge. TC is incremented on..,2: Counter Mode falling edge. TC is incremented on..,3: Counter Mode dual edge. TC is incremented on.."
line.long 0x4 "PWMC,PWM Control Register. The PWMCON enables PWM mode for the external match pins."
bitfld.long 0x4 3. "PWMEN3,PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle." "0: Match. CTIMERn_MAT3 is controlled by EM3.,1: PWM. PWM mode is enabled for CT132Bn_MAT3."
bitfld.long 0x4 2. "PWMEN2,PWM mode enable for channel2." "0: Match. CTIMERn_MAT2 is controlled by EM2.,1: PWM. PWM mode is enabled for CTIMERn_MAT2."
newline
bitfld.long 0x4 1. "PWMEN1,PWM mode enable for channel1." "0: Match. CTIMERn_MAT01 is controlled by EM1.,1: PWM. PWM mode is enabled for CTIMERn_MAT1."
bitfld.long 0x4 0. "PWMEN0,PWM mode enable for channel0." "0: Match. CTIMERn_MAT0 is controlled by EM0.,1: PWM. PWM mode is enabled for CTIMERn_MAT0."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x78)++0x3
line.long 0x0 "MSR[$1],Match Shadow Register"
hexmask.long 0x0 0.--31. 1. "SHADOWW,Timer counter match shadow value."
repeat.end
tree.end
tree "CTIMER3"
base ad:0x40048000
group.long 0x0++0x17
line.long 0x0 "IR,Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending."
bitfld.long 0x0 7. "CR3INT,Interrupt flag for capture channel 3 event." "0,1"
bitfld.long 0x0 6. "CR2INT,Interrupt flag for capture channel 2 event." "0,1"
newline
bitfld.long 0x0 5. "CR1INT,Interrupt flag for capture channel 1 event." "0,1"
bitfld.long 0x0 4. "CR0INT,Interrupt flag for capture channel 0 event." "0,1"
newline
bitfld.long 0x0 3. "MR3INT,Interrupt flag for match channel 3." "0,1"
bitfld.long 0x0 2. "MR2INT,Interrupt flag for match channel 2." "0,1"
newline
bitfld.long 0x0 1. "MR1INT,Interrupt flag for match channel 1." "0,1"
bitfld.long 0x0 0. "MR0INT,Interrupt flag for match channel 0." "0,1"
line.long 0x4 "TCR,Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."
bitfld.long 0x4 1. "CRST,Counter reset." "0: Disabled. Do nothing.,1: Enabled. The Timer Counter and the Prescale.."
bitfld.long 0x4 0. "CEN,Counter enable." "0: Disabled.The counters are disabled.,1: Enabled. The Timer Counter and Prescale Counter.."
line.long 0x8 "TC,Timer Counter"
hexmask.long 0x8 0.--31. 1. "TCVAL,Timer counter value."
line.long 0xC "PR,Prescale Register"
hexmask.long 0xC 0.--31. 1. "PRVAL,Prescale counter value."
line.long 0x10 "PC,Prescale Counter"
hexmask.long 0x10 0.--31. 1. "PCVAL,Prescale counter value."
line.long 0x14 "MCR,Match Control Register"
bitfld.long 0x14 27. "MR3RL,Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 26. "MR2RL,Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 25. "MR1RL,Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 24. "MR0RL,Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 11. "MR3S,Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." "0,1"
bitfld.long 0x14 10. "MR3R,Reset on MR3: the TC will be reset if MR3 matches it." "0,1"
newline
bitfld.long 0x14 9. "MR3I,Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC." "0,1"
bitfld.long 0x14 8. "MR2S,Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC." "0,1"
newline
bitfld.long 0x14 7. "MR2R,Reset on MR2: the TC will be reset if MR2 matches it." "0,1"
bitfld.long 0x14 6. "MR2I,Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC." "0,1"
newline
bitfld.long 0x14 5. "MR1S,Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." "0,1"
bitfld.long 0x14 4. "MR1R,Reset on MR1: the TC will be reset if MR1 matches it." "0,1"
newline
bitfld.long 0x14 3. "MR1I,Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC." "0,1"
bitfld.long 0x14 2. "MR0S,Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." "0,1"
newline
bitfld.long 0x14 1. "MR0R,Reset on MR0: the TC will be reset if MR0 matches it." "0,1"
bitfld.long 0x14 0. "MR0I,Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC." "0,1"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x18)++0x3
line.long 0x0 "MR[$1],Match Register . MR can be enabled through the MCR to reset the TC. stop both the TC and PC. and/or generate an interrupt every time MR matches the TC."
hexmask.long 0x0 0.--31. 1. "MATCH,Timer counter match value."
repeat.end
group.long 0x28++0x3
line.long 0x0 "CCR,Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."
bitfld.long 0x0 11. "CAP3I,Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt." "0,1"
bitfld.long 0x0 10. "CAP3FE,Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 9. "CAP3RE,Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 8. "CAP2I,Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 7. "CAP2FE,Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 6. "CAP2RE,Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 5. "CAP1I,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt." "0,1"
bitfld.long 0x0 4. "CAP1FE,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 3. "CAP1RE,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 2. "CAP0I,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 1. "CAP0FE,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 0. "CAP0RE,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x2C)++0x3
line.long 0x0 "CR[$1],Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input."
hexmask.long 0x0 0.--31. 1. "CAP,Timer counter capture value."
repeat.end
group.long 0x3C++0x3
line.long 0x0 "EMR,External Match Register. The EMR controls the match function and the external match pins."
bitfld.long 0x0 10.--11. "EMC3,External Match Control 3. Determines the functionality of External Match 3." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 8.--9. "EMC2,External Match Control 2. Determines the functionality of External Match 2." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 6.--7. "EMC1,External Match Control 1. Determines the functionality of External Match 1." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 4.--5. "EMC0,External Match Control 0. Determines the functionality of External Match 0." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 3. "EM3,External Match 3. This bit reflects the state of output MAT3  whether or not this output is connected to a pin. When a match occurs between the TC and MR3  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by MR[11:10]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 2. "EM2,External Match 2. This bit reflects the state of output MAT2  whether or not this output is connected to a pin. When a match occurs between the TC and MR2  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[9:8]. This bit.." "0: LOW,1: HIGH"
newline
bitfld.long 0x0 1. "EM1,External Match 1. This bit reflects the state of output MAT1  whether or not this output is connected to a pin. When a match occurs between the TC and MR1  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[7:6]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 0. "EM0,External Match 0. This bit reflects the state of output MAT0  whether or not this output is connected to a pin. When a match occurs between the TC and MR0  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[5:4]. This bit.." "0: LOW,1: HIGH"
group.long 0x70++0x7
line.long 0x0 "CTCR,Count Control Register. The CTCR selects between Timer and Counter mode. and in Counter mode selects the signal and edge(s) for counting."
bitfld.long 0x0 5.--7. "SELCC,Edge select. When bit 4 is 1  these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved." "0: Channel 0 Rising Edge. Rising edge of the signal..,1: Channel 0 Falling Edge. Falling edge of the..,2: Channel 1 Rising Edge. Rising edge of the signal..,3: Channel 1 Falling Edge. Falling edge of the..,4: Channel 2 Rising Edge. Rising edge of the signal..,5: Channel 2 Falling Edge. Falling edge of the..,?,?"
bitfld.long 0x0 4. "ENCC,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." "0,1"
newline
bitfld.long 0x0 2.--3. "CINSEL,Count Input Select When bits 1:0 in this register are not 00  these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR  the 3 bits for that input in the Capture Control.." "0: Channel 0. CAPn.0 for CTIMERn,1: 0 in this register are not 00,2: Channel 2. CAPn.2 for CTIMERn,3: Channel 3. CAPn.3 for CTIMERn"
bitfld.long 0x0 0.--1. "CTMODE,Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC)  or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale.." "0: Timer Mode. Incremented every rising APB bus..,1: Counter Mode rising edge. TC is incremented on..,2: Counter Mode falling edge. TC is incremented on..,3: Counter Mode dual edge. TC is incremented on.."
line.long 0x4 "PWMC,PWM Control Register. The PWMCON enables PWM mode for the external match pins."
bitfld.long 0x4 3. "PWMEN3,PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle." "0: Match. CTIMERn_MAT3 is controlled by EM3.,1: PWM. PWM mode is enabled for CT132Bn_MAT3."
bitfld.long 0x4 2. "PWMEN2,PWM mode enable for channel2." "0: Match. CTIMERn_MAT2 is controlled by EM2.,1: PWM. PWM mode is enabled for CTIMERn_MAT2."
newline
bitfld.long 0x4 1. "PWMEN1,PWM mode enable for channel1." "0: Match. CTIMERn_MAT01 is controlled by EM1.,1: PWM. PWM mode is enabled for CTIMERn_MAT1."
bitfld.long 0x4 0. "PWMEN0,PWM mode enable for channel0." "0: Match. CTIMERn_MAT0 is controlled by EM0.,1: PWM. PWM mode is enabled for CTIMERn_MAT0."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x78)++0x3
line.long 0x0 "MSR[$1],Match Shadow Register"
hexmask.long 0x0 0.--31. 1. "SHADOWW,Timer counter match shadow value."
repeat.end
tree.end
tree "CTIMER4"
base ad:0x40049000
group.long 0x0++0x17
line.long 0x0 "IR,Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending."
bitfld.long 0x0 7. "CR3INT,Interrupt flag for capture channel 3 event." "0,1"
bitfld.long 0x0 6. "CR2INT,Interrupt flag for capture channel 2 event." "0,1"
newline
bitfld.long 0x0 5. "CR1INT,Interrupt flag for capture channel 1 event." "0,1"
bitfld.long 0x0 4. "CR0INT,Interrupt flag for capture channel 0 event." "0,1"
newline
bitfld.long 0x0 3. "MR3INT,Interrupt flag for match channel 3." "0,1"
bitfld.long 0x0 2. "MR2INT,Interrupt flag for match channel 2." "0,1"
newline
bitfld.long 0x0 1. "MR1INT,Interrupt flag for match channel 1." "0,1"
bitfld.long 0x0 0. "MR0INT,Interrupt flag for match channel 0." "0,1"
line.long 0x4 "TCR,Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."
bitfld.long 0x4 1. "CRST,Counter reset." "0: Disabled. Do nothing.,1: Enabled. The Timer Counter and the Prescale.."
bitfld.long 0x4 0. "CEN,Counter enable." "0: Disabled.The counters are disabled.,1: Enabled. The Timer Counter and Prescale Counter.."
line.long 0x8 "TC,Timer Counter"
hexmask.long 0x8 0.--31. 1. "TCVAL,Timer counter value."
line.long 0xC "PR,Prescale Register"
hexmask.long 0xC 0.--31. 1. "PRVAL,Prescale counter value."
line.long 0x10 "PC,Prescale Counter"
hexmask.long 0x10 0.--31. 1. "PCVAL,Prescale counter value."
line.long 0x14 "MCR,Match Control Register"
bitfld.long 0x14 27. "MR3RL,Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 26. "MR2RL,Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 25. "MR1RL,Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 24. "MR0RL,Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 11. "MR3S,Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." "0,1"
bitfld.long 0x14 10. "MR3R,Reset on MR3: the TC will be reset if MR3 matches it." "0,1"
newline
bitfld.long 0x14 9. "MR3I,Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC." "0,1"
bitfld.long 0x14 8. "MR2S,Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC." "0,1"
newline
bitfld.long 0x14 7. "MR2R,Reset on MR2: the TC will be reset if MR2 matches it." "0,1"
bitfld.long 0x14 6. "MR2I,Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC." "0,1"
newline
bitfld.long 0x14 5. "MR1S,Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." "0,1"
bitfld.long 0x14 4. "MR1R,Reset on MR1: the TC will be reset if MR1 matches it." "0,1"
newline
bitfld.long 0x14 3. "MR1I,Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC." "0,1"
bitfld.long 0x14 2. "MR0S,Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." "0,1"
newline
bitfld.long 0x14 1. "MR0R,Reset on MR0: the TC will be reset if MR0 matches it." "0,1"
bitfld.long 0x14 0. "MR0I,Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC." "0,1"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x18)++0x3
line.long 0x0 "MR[$1],Match Register . MR can be enabled through the MCR to reset the TC. stop both the TC and PC. and/or generate an interrupt every time MR matches the TC."
hexmask.long 0x0 0.--31. 1. "MATCH,Timer counter match value."
repeat.end
group.long 0x28++0x3
line.long 0x0 "CCR,Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."
bitfld.long 0x0 11. "CAP3I,Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt." "0,1"
bitfld.long 0x0 10. "CAP3FE,Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 9. "CAP3RE,Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 8. "CAP2I,Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 7. "CAP2FE,Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 6. "CAP2RE,Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 5. "CAP1I,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt." "0,1"
bitfld.long 0x0 4. "CAP1FE,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 3. "CAP1RE,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 2. "CAP0I,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 1. "CAP0FE,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 0. "CAP0RE,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x2C)++0x3
line.long 0x0 "CR[$1],Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input."
hexmask.long 0x0 0.--31. 1. "CAP,Timer counter capture value."
repeat.end
group.long 0x3C++0x3
line.long 0x0 "EMR,External Match Register. The EMR controls the match function and the external match pins."
bitfld.long 0x0 10.--11. "EMC3,External Match Control 3. Determines the functionality of External Match 3." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 8.--9. "EMC2,External Match Control 2. Determines the functionality of External Match 2." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 6.--7. "EMC1,External Match Control 1. Determines the functionality of External Match 1." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 4.--5. "EMC0,External Match Control 0. Determines the functionality of External Match 0." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 3. "EM3,External Match 3. This bit reflects the state of output MAT3  whether or not this output is connected to a pin. When a match occurs between the TC and MR3  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by MR[11:10]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 2. "EM2,External Match 2. This bit reflects the state of output MAT2  whether or not this output is connected to a pin. When a match occurs between the TC and MR2  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[9:8]. This bit.." "0: LOW,1: HIGH"
newline
bitfld.long 0x0 1. "EM1,External Match 1. This bit reflects the state of output MAT1  whether or not this output is connected to a pin. When a match occurs between the TC and MR1  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[7:6]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 0. "EM0,External Match 0. This bit reflects the state of output MAT0  whether or not this output is connected to a pin. When a match occurs between the TC and MR0  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[5:4]. This bit.." "0: LOW,1: HIGH"
group.long 0x70++0x7
line.long 0x0 "CTCR,Count Control Register. The CTCR selects between Timer and Counter mode. and in Counter mode selects the signal and edge(s) for counting."
bitfld.long 0x0 5.--7. "SELCC,Edge select. When bit 4 is 1  these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved." "0: Channel 0 Rising Edge. Rising edge of the signal..,1: Channel 0 Falling Edge. Falling edge of the..,2: Channel 1 Rising Edge. Rising edge of the signal..,3: Channel 1 Falling Edge. Falling edge of the..,4: Channel 2 Rising Edge. Rising edge of the signal..,5: Channel 2 Falling Edge. Falling edge of the..,?,?"
bitfld.long 0x0 4. "ENCC,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." "0,1"
newline
bitfld.long 0x0 2.--3. "CINSEL,Count Input Select When bits 1:0 in this register are not 00  these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR  the 3 bits for that input in the Capture Control.." "0: Channel 0. CAPn.0 for CTIMERn,1: 0 in this register are not 00,2: Channel 2. CAPn.2 for CTIMERn,3: Channel 3. CAPn.3 for CTIMERn"
bitfld.long 0x0 0.--1. "CTMODE,Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC)  or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale.." "0: Timer Mode. Incremented every rising APB bus..,1: Counter Mode rising edge. TC is incremented on..,2: Counter Mode falling edge. TC is incremented on..,3: Counter Mode dual edge. TC is incremented on.."
line.long 0x4 "PWMC,PWM Control Register. The PWMCON enables PWM mode for the external match pins."
bitfld.long 0x4 3. "PWMEN3,PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle." "0: Match. CTIMERn_MAT3 is controlled by EM3.,1: PWM. PWM mode is enabled for CT132Bn_MAT3."
bitfld.long 0x4 2. "PWMEN2,PWM mode enable for channel2." "0: Match. CTIMERn_MAT2 is controlled by EM2.,1: PWM. PWM mode is enabled for CTIMERn_MAT2."
newline
bitfld.long 0x4 1. "PWMEN1,PWM mode enable for channel1." "0: Match. CTIMERn_MAT01 is controlled by EM1.,1: PWM. PWM mode is enabled for CTIMERn_MAT1."
bitfld.long 0x4 0. "PWMEN0,PWM mode enable for channel0." "0: Match. CTIMERn_MAT0 is controlled by EM0.,1: PWM. PWM mode is enabled for CTIMERn_MAT0."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x78)++0x3
line.long 0x0 "MSR[$1],Match Shadow Register"
hexmask.long 0x0 0.--31. 1. "SHADOWW,Timer counter match shadow value."
repeat.end
tree.end
endif
sif (cpuis("LPC54628*"))
tree "CTIMER0"
base ad:0x40008000
group.long 0x0++0x17
line.long 0x0 "IR,Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending."
bitfld.long 0x0 7. "CR3INT,Interrupt flag for capture channel 3 event." "0,1"
bitfld.long 0x0 6. "CR2INT,Interrupt flag for capture channel 2 event." "0,1"
newline
bitfld.long 0x0 5. "CR1INT,Interrupt flag for capture channel 1 event." "0,1"
bitfld.long 0x0 4. "CR0INT,Interrupt flag for capture channel 0 event." "0,1"
newline
bitfld.long 0x0 3. "MR3INT,Interrupt flag for match channel 3." "0,1"
bitfld.long 0x0 2. "MR2INT,Interrupt flag for match channel 2." "0,1"
newline
bitfld.long 0x0 1. "MR1INT,Interrupt flag for match channel 1." "0,1"
bitfld.long 0x0 0. "MR0INT,Interrupt flag for match channel 0." "0,1"
line.long 0x4 "TCR,Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."
bitfld.long 0x4 1. "CRST,Counter reset." "0: Disabled. Do nothing.,1: Enabled. The Timer Counter and the Prescale.."
bitfld.long 0x4 0. "CEN,Counter enable." "0: Disabled.The counters are disabled.,1: Enabled. The Timer Counter and Prescale Counter.."
line.long 0x8 "TC,Timer Counter"
hexmask.long 0x8 0.--31. 1. "TCVAL,Timer counter value."
line.long 0xC "PR,Prescale Register"
hexmask.long 0xC 0.--31. 1. "PRVAL,Prescale counter value."
line.long 0x10 "PC,Prescale Counter"
hexmask.long 0x10 0.--31. 1. "PCVAL,Prescale counter value."
line.long 0x14 "MCR,Match Control Register"
bitfld.long 0x14 27. "MR3RL,Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 26. "MR2RL,Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 25. "MR1RL,Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 24. "MR0RL,Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 11. "MR3S,Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." "0,1"
bitfld.long 0x14 10. "MR3R,Reset on MR3: the TC will be reset if MR3 matches it." "0,1"
newline
bitfld.long 0x14 9. "MR3I,Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC." "0,1"
bitfld.long 0x14 8. "MR2S,Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC." "0,1"
newline
bitfld.long 0x14 7. "MR2R,Reset on MR2: the TC will be reset if MR2 matches it." "0,1"
bitfld.long 0x14 6. "MR2I,Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC." "0,1"
newline
bitfld.long 0x14 5. "MR1S,Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." "0,1"
bitfld.long 0x14 4. "MR1R,Reset on MR1: the TC will be reset if MR1 matches it." "0,1"
newline
bitfld.long 0x14 3. "MR1I,Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC." "0,1"
bitfld.long 0x14 2. "MR0S,Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." "0,1"
newline
bitfld.long 0x14 1. "MR0R,Reset on MR0: the TC will be reset if MR0 matches it." "0,1"
bitfld.long 0x14 0. "MR0I,Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC." "0,1"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x18)++0x3
line.long 0x0 "MR[$1],Match Register . MR can be enabled through the MCR to reset the TC. stop both the TC and PC. and/or generate an interrupt every time MR matches the TC."
hexmask.long 0x0 0.--31. 1. "MATCH,Timer counter match value."
repeat.end
group.long 0x28++0x3
line.long 0x0 "CCR,Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."
bitfld.long 0x0 11. "CAP3I,Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt." "0,1"
bitfld.long 0x0 10. "CAP3FE,Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 9. "CAP3RE,Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 8. "CAP2I,Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 7. "CAP2FE,Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 6. "CAP2RE,Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 5. "CAP1I,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt." "0,1"
bitfld.long 0x0 4. "CAP1FE,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 3. "CAP1RE,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 2. "CAP0I,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 1. "CAP0FE,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 0. "CAP0RE,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x2C)++0x3
line.long 0x0 "CR[$1],Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input."
hexmask.long 0x0 0.--31. 1. "CAP,Timer counter capture value."
repeat.end
group.long 0x3C++0x3
line.long 0x0 "EMR,External Match Register. The EMR controls the match function and the external match pins."
bitfld.long 0x0 10.--11. "EMC3,External Match Control 3. Determines the functionality of External Match 3." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 8.--9. "EMC2,External Match Control 2. Determines the functionality of External Match 2." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 6.--7. "EMC1,External Match Control 1. Determines the functionality of External Match 1." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 4.--5. "EMC0,External Match Control 0. Determines the functionality of External Match 0." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 3. "EM3,External Match 3. This bit reflects the state of output MAT3  whether or not this output is connected to a pin. When a match occurs between the TC and MR3  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by MR[11:10]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 2. "EM2,External Match 2. This bit reflects the state of output MAT2  whether or not this output is connected to a pin. When a match occurs between the TC and MR2  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[9:8]. This bit.." "0: LOW,1: HIGH"
newline
bitfld.long 0x0 1. "EM1,External Match 1. This bit reflects the state of output MAT1  whether or not this output is connected to a pin. When a match occurs between the TC and MR1  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[7:6]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 0. "EM0,External Match 0. This bit reflects the state of output MAT0  whether or not this output is connected to a pin. When a match occurs between the TC and MR0  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[5:4]. This bit.." "0: LOW,1: HIGH"
group.long 0x70++0x7
line.long 0x0 "CTCR,Count Control Register. The CTCR selects between Timer and Counter mode. and in Counter mode selects the signal and edge(s) for counting."
bitfld.long 0x0 5.--7. "SELCC,Edge select. When bit 4 is 1  these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved." "0: Channel 0 Rising Edge. Rising edge of the signal..,1: Channel 0 Falling Edge. Falling edge of the..,2: Channel 1 Rising Edge. Rising edge of the signal..,3: Channel 1 Falling Edge. Falling edge of the..,4: Channel 2 Rising Edge. Rising edge of the signal..,5: Channel 2 Falling Edge. Falling edge of the..,?,?"
bitfld.long 0x0 4. "ENCC,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." "0,1"
newline
bitfld.long 0x0 2.--3. "CINSEL,Count Input Select When bits 1:0 in this register are not 00  these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR  the 3 bits for that input in the Capture Control.." "0: Channel 0. CAPn.0 for CTIMERn,1: 0 in this register are not 00,2: Channel 2. CAPn.2 for CTIMERn,3: Channel 3. CAPn.3 for CTIMERn"
bitfld.long 0x0 0.--1. "CTMODE,Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC)  or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale.." "0: Timer Mode. Incremented every rising APB bus..,1: Counter Mode rising edge. TC is incremented on..,2: Counter Mode falling edge. TC is incremented on..,3: Counter Mode dual edge. TC is incremented on.."
line.long 0x4 "PWMC,PWM Control Register. The PWMCON enables PWM mode for the external match pins."
bitfld.long 0x4 3. "PWMEN3,PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle." "0: Match. CTIMERn_MAT3 is controlled by EM3.,1: PWM. PWM mode is enabled for CT132Bn_MAT3."
bitfld.long 0x4 2. "PWMEN2,PWM mode enable for channel2." "0: Match. CTIMERn_MAT2 is controlled by EM2.,1: PWM. PWM mode is enabled for CTIMERn_MAT2."
newline
bitfld.long 0x4 1. "PWMEN1,PWM mode enable for channel1." "0: Match. CTIMERn_MAT01 is controlled by EM1.,1: PWM. PWM mode is enabled for CTIMERn_MAT1."
bitfld.long 0x4 0. "PWMEN0,PWM mode enable for channel0." "0: Match. CTIMERn_MAT0 is controlled by EM0.,1: PWM. PWM mode is enabled for CTIMERn_MAT0."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x78)++0x3
line.long 0x0 "MSR[$1],Match Shadow Register"
hexmask.long 0x0 0.--31. 1. "SHADOWW,Timer counter match shadow value."
repeat.end
tree.end
tree "CTIMER1"
base ad:0x40009000
group.long 0x0++0x17
line.long 0x0 "IR,Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending."
bitfld.long 0x0 7. "CR3INT,Interrupt flag for capture channel 3 event." "0,1"
bitfld.long 0x0 6. "CR2INT,Interrupt flag for capture channel 2 event." "0,1"
newline
bitfld.long 0x0 5. "CR1INT,Interrupt flag for capture channel 1 event." "0,1"
bitfld.long 0x0 4. "CR0INT,Interrupt flag for capture channel 0 event." "0,1"
newline
bitfld.long 0x0 3. "MR3INT,Interrupt flag for match channel 3." "0,1"
bitfld.long 0x0 2. "MR2INT,Interrupt flag for match channel 2." "0,1"
newline
bitfld.long 0x0 1. "MR1INT,Interrupt flag for match channel 1." "0,1"
bitfld.long 0x0 0. "MR0INT,Interrupt flag for match channel 0." "0,1"
line.long 0x4 "TCR,Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."
bitfld.long 0x4 1. "CRST,Counter reset." "0: Disabled. Do nothing.,1: Enabled. The Timer Counter and the Prescale.."
bitfld.long 0x4 0. "CEN,Counter enable." "0: Disabled.The counters are disabled.,1: Enabled. The Timer Counter and Prescale Counter.."
line.long 0x8 "TC,Timer Counter"
hexmask.long 0x8 0.--31. 1. "TCVAL,Timer counter value."
line.long 0xC "PR,Prescale Register"
hexmask.long 0xC 0.--31. 1. "PRVAL,Prescale counter value."
line.long 0x10 "PC,Prescale Counter"
hexmask.long 0x10 0.--31. 1. "PCVAL,Prescale counter value."
line.long 0x14 "MCR,Match Control Register"
bitfld.long 0x14 27. "MR3RL,Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 26. "MR2RL,Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 25. "MR1RL,Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 24. "MR0RL,Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 11. "MR3S,Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." "0,1"
bitfld.long 0x14 10. "MR3R,Reset on MR3: the TC will be reset if MR3 matches it." "0,1"
newline
bitfld.long 0x14 9. "MR3I,Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC." "0,1"
bitfld.long 0x14 8. "MR2S,Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC." "0,1"
newline
bitfld.long 0x14 7. "MR2R,Reset on MR2: the TC will be reset if MR2 matches it." "0,1"
bitfld.long 0x14 6. "MR2I,Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC." "0,1"
newline
bitfld.long 0x14 5. "MR1S,Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." "0,1"
bitfld.long 0x14 4. "MR1R,Reset on MR1: the TC will be reset if MR1 matches it." "0,1"
newline
bitfld.long 0x14 3. "MR1I,Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC." "0,1"
bitfld.long 0x14 2. "MR0S,Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." "0,1"
newline
bitfld.long 0x14 1. "MR0R,Reset on MR0: the TC will be reset if MR0 matches it." "0,1"
bitfld.long 0x14 0. "MR0I,Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC." "0,1"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x18)++0x3
line.long 0x0 "MR[$1],Match Register . MR can be enabled through the MCR to reset the TC. stop both the TC and PC. and/or generate an interrupt every time MR matches the TC."
hexmask.long 0x0 0.--31. 1. "MATCH,Timer counter match value."
repeat.end
group.long 0x28++0x3
line.long 0x0 "CCR,Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."
bitfld.long 0x0 11. "CAP3I,Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt." "0,1"
bitfld.long 0x0 10. "CAP3FE,Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 9. "CAP3RE,Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 8. "CAP2I,Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 7. "CAP2FE,Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 6. "CAP2RE,Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 5. "CAP1I,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt." "0,1"
bitfld.long 0x0 4. "CAP1FE,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 3. "CAP1RE,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 2. "CAP0I,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 1. "CAP0FE,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 0. "CAP0RE,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x2C)++0x3
line.long 0x0 "CR[$1],Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input."
hexmask.long 0x0 0.--31. 1. "CAP,Timer counter capture value."
repeat.end
group.long 0x3C++0x3
line.long 0x0 "EMR,External Match Register. The EMR controls the match function and the external match pins."
bitfld.long 0x0 10.--11. "EMC3,External Match Control 3. Determines the functionality of External Match 3." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 8.--9. "EMC2,External Match Control 2. Determines the functionality of External Match 2." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 6.--7. "EMC1,External Match Control 1. Determines the functionality of External Match 1." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 4.--5. "EMC0,External Match Control 0. Determines the functionality of External Match 0." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 3. "EM3,External Match 3. This bit reflects the state of output MAT3  whether or not this output is connected to a pin. When a match occurs between the TC and MR3  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by MR[11:10]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 2. "EM2,External Match 2. This bit reflects the state of output MAT2  whether or not this output is connected to a pin. When a match occurs between the TC and MR2  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[9:8]. This bit.." "0: LOW,1: HIGH"
newline
bitfld.long 0x0 1. "EM1,External Match 1. This bit reflects the state of output MAT1  whether or not this output is connected to a pin. When a match occurs between the TC and MR1  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[7:6]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 0. "EM0,External Match 0. This bit reflects the state of output MAT0  whether or not this output is connected to a pin. When a match occurs between the TC and MR0  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[5:4]. This bit.." "0: LOW,1: HIGH"
group.long 0x70++0x7
line.long 0x0 "CTCR,Count Control Register. The CTCR selects between Timer and Counter mode. and in Counter mode selects the signal and edge(s) for counting."
bitfld.long 0x0 5.--7. "SELCC,Edge select. When bit 4 is 1  these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved." "0: Channel 0 Rising Edge. Rising edge of the signal..,1: Channel 0 Falling Edge. Falling edge of the..,2: Channel 1 Rising Edge. Rising edge of the signal..,3: Channel 1 Falling Edge. Falling edge of the..,4: Channel 2 Rising Edge. Rising edge of the signal..,5: Channel 2 Falling Edge. Falling edge of the..,?,?"
bitfld.long 0x0 4. "ENCC,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." "0,1"
newline
bitfld.long 0x0 2.--3. "CINSEL,Count Input Select When bits 1:0 in this register are not 00  these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR  the 3 bits for that input in the Capture Control.." "0: Channel 0. CAPn.0 for CTIMERn,1: 0 in this register are not 00,2: Channel 2. CAPn.2 for CTIMERn,3: Channel 3. CAPn.3 for CTIMERn"
bitfld.long 0x0 0.--1. "CTMODE,Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC)  or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale.." "0: Timer Mode. Incremented every rising APB bus..,1: Counter Mode rising edge. TC is incremented on..,2: Counter Mode falling edge. TC is incremented on..,3: Counter Mode dual edge. TC is incremented on.."
line.long 0x4 "PWMC,PWM Control Register. The PWMCON enables PWM mode for the external match pins."
bitfld.long 0x4 3. "PWMEN3,PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle." "0: Match. CTIMERn_MAT3 is controlled by EM3.,1: PWM. PWM mode is enabled for CT132Bn_MAT3."
bitfld.long 0x4 2. "PWMEN2,PWM mode enable for channel2." "0: Match. CTIMERn_MAT2 is controlled by EM2.,1: PWM. PWM mode is enabled for CTIMERn_MAT2."
newline
bitfld.long 0x4 1. "PWMEN1,PWM mode enable for channel1." "0: Match. CTIMERn_MAT01 is controlled by EM1.,1: PWM. PWM mode is enabled for CTIMERn_MAT1."
bitfld.long 0x4 0. "PWMEN0,PWM mode enable for channel0." "0: Match. CTIMERn_MAT0 is controlled by EM0.,1: PWM. PWM mode is enabled for CTIMERn_MAT0."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x78)++0x3
line.long 0x0 "MSR[$1],Match Shadow Register"
hexmask.long 0x0 0.--31. 1. "SHADOWW,Timer counter match shadow value."
repeat.end
tree.end
tree "CTIMER2"
base ad:0x40028000
group.long 0x0++0x17
line.long 0x0 "IR,Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending."
bitfld.long 0x0 7. "CR3INT,Interrupt flag for capture channel 3 event." "0,1"
bitfld.long 0x0 6. "CR2INT,Interrupt flag for capture channel 2 event." "0,1"
newline
bitfld.long 0x0 5. "CR1INT,Interrupt flag for capture channel 1 event." "0,1"
bitfld.long 0x0 4. "CR0INT,Interrupt flag for capture channel 0 event." "0,1"
newline
bitfld.long 0x0 3. "MR3INT,Interrupt flag for match channel 3." "0,1"
bitfld.long 0x0 2. "MR2INT,Interrupt flag for match channel 2." "0,1"
newline
bitfld.long 0x0 1. "MR1INT,Interrupt flag for match channel 1." "0,1"
bitfld.long 0x0 0. "MR0INT,Interrupt flag for match channel 0." "0,1"
line.long 0x4 "TCR,Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."
bitfld.long 0x4 1. "CRST,Counter reset." "0: Disabled. Do nothing.,1: Enabled. The Timer Counter and the Prescale.."
bitfld.long 0x4 0. "CEN,Counter enable." "0: Disabled.The counters are disabled.,1: Enabled. The Timer Counter and Prescale Counter.."
line.long 0x8 "TC,Timer Counter"
hexmask.long 0x8 0.--31. 1. "TCVAL,Timer counter value."
line.long 0xC "PR,Prescale Register"
hexmask.long 0xC 0.--31. 1. "PRVAL,Prescale counter value."
line.long 0x10 "PC,Prescale Counter"
hexmask.long 0x10 0.--31. 1. "PCVAL,Prescale counter value."
line.long 0x14 "MCR,Match Control Register"
bitfld.long 0x14 27. "MR3RL,Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 26. "MR2RL,Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 25. "MR1RL,Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 24. "MR0RL,Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 11. "MR3S,Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." "0,1"
bitfld.long 0x14 10. "MR3R,Reset on MR3: the TC will be reset if MR3 matches it." "0,1"
newline
bitfld.long 0x14 9. "MR3I,Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC." "0,1"
bitfld.long 0x14 8. "MR2S,Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC." "0,1"
newline
bitfld.long 0x14 7. "MR2R,Reset on MR2: the TC will be reset if MR2 matches it." "0,1"
bitfld.long 0x14 6. "MR2I,Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC." "0,1"
newline
bitfld.long 0x14 5. "MR1S,Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." "0,1"
bitfld.long 0x14 4. "MR1R,Reset on MR1: the TC will be reset if MR1 matches it." "0,1"
newline
bitfld.long 0x14 3. "MR1I,Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC." "0,1"
bitfld.long 0x14 2. "MR0S,Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." "0,1"
newline
bitfld.long 0x14 1. "MR0R,Reset on MR0: the TC will be reset if MR0 matches it." "0,1"
bitfld.long 0x14 0. "MR0I,Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC." "0,1"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x18)++0x3
line.long 0x0 "MR[$1],Match Register . MR can be enabled through the MCR to reset the TC. stop both the TC and PC. and/or generate an interrupt every time MR matches the TC."
hexmask.long 0x0 0.--31. 1. "MATCH,Timer counter match value."
repeat.end
group.long 0x28++0x3
line.long 0x0 "CCR,Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."
bitfld.long 0x0 11. "CAP3I,Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt." "0,1"
bitfld.long 0x0 10. "CAP3FE,Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 9. "CAP3RE,Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 8. "CAP2I,Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 7. "CAP2FE,Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 6. "CAP2RE,Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 5. "CAP1I,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt." "0,1"
bitfld.long 0x0 4. "CAP1FE,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 3. "CAP1RE,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 2. "CAP0I,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 1. "CAP0FE,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 0. "CAP0RE,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x2C)++0x3
line.long 0x0 "CR[$1],Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input."
hexmask.long 0x0 0.--31. 1. "CAP,Timer counter capture value."
repeat.end
group.long 0x3C++0x3
line.long 0x0 "EMR,External Match Register. The EMR controls the match function and the external match pins."
bitfld.long 0x0 10.--11. "EMC3,External Match Control 3. Determines the functionality of External Match 3." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 8.--9. "EMC2,External Match Control 2. Determines the functionality of External Match 2." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 6.--7. "EMC1,External Match Control 1. Determines the functionality of External Match 1." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 4.--5. "EMC0,External Match Control 0. Determines the functionality of External Match 0." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 3. "EM3,External Match 3. This bit reflects the state of output MAT3  whether or not this output is connected to a pin. When a match occurs between the TC and MR3  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by MR[11:10]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 2. "EM2,External Match 2. This bit reflects the state of output MAT2  whether or not this output is connected to a pin. When a match occurs between the TC and MR2  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[9:8]. This bit.." "0: LOW,1: HIGH"
newline
bitfld.long 0x0 1. "EM1,External Match 1. This bit reflects the state of output MAT1  whether or not this output is connected to a pin. When a match occurs between the TC and MR1  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[7:6]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 0. "EM0,External Match 0. This bit reflects the state of output MAT0  whether or not this output is connected to a pin. When a match occurs between the TC and MR0  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[5:4]. This bit.." "0: LOW,1: HIGH"
group.long 0x70++0x7
line.long 0x0 "CTCR,Count Control Register. The CTCR selects between Timer and Counter mode. and in Counter mode selects the signal and edge(s) for counting."
bitfld.long 0x0 5.--7. "SELCC,Edge select. When bit 4 is 1  these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved." "0: Channel 0 Rising Edge. Rising edge of the signal..,1: Channel 0 Falling Edge. Falling edge of the..,2: Channel 1 Rising Edge. Rising edge of the signal..,3: Channel 1 Falling Edge. Falling edge of the..,4: Channel 2 Rising Edge. Rising edge of the signal..,5: Channel 2 Falling Edge. Falling edge of the..,?,?"
bitfld.long 0x0 4. "ENCC,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." "0,1"
newline
bitfld.long 0x0 2.--3. "CINSEL,Count Input Select When bits 1:0 in this register are not 00  these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR  the 3 bits for that input in the Capture Control.." "0: Channel 0. CAPn.0 for CTIMERn,1: 0 in this register are not 00,2: Channel 2. CAPn.2 for CTIMERn,3: Channel 3. CAPn.3 for CTIMERn"
bitfld.long 0x0 0.--1. "CTMODE,Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC)  or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale.." "0: Timer Mode. Incremented every rising APB bus..,1: Counter Mode rising edge. TC is incremented on..,2: Counter Mode falling edge. TC is incremented on..,3: Counter Mode dual edge. TC is incremented on.."
line.long 0x4 "PWMC,PWM Control Register. The PWMCON enables PWM mode for the external match pins."
bitfld.long 0x4 3. "PWMEN3,PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle." "0: Match. CTIMERn_MAT3 is controlled by EM3.,1: PWM. PWM mode is enabled for CT132Bn_MAT3."
bitfld.long 0x4 2. "PWMEN2,PWM mode enable for channel2." "0: Match. CTIMERn_MAT2 is controlled by EM2.,1: PWM. PWM mode is enabled for CTIMERn_MAT2."
newline
bitfld.long 0x4 1. "PWMEN1,PWM mode enable for channel1." "0: Match. CTIMERn_MAT01 is controlled by EM1.,1: PWM. PWM mode is enabled for CTIMERn_MAT1."
bitfld.long 0x4 0. "PWMEN0,PWM mode enable for channel0." "0: Match. CTIMERn_MAT0 is controlled by EM0.,1: PWM. PWM mode is enabled for CTIMERn_MAT0."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x78)++0x3
line.long 0x0 "MSR[$1],Match Shadow Register"
hexmask.long 0x0 0.--31. 1. "SHADOWW,Timer counter match shadow value."
repeat.end
tree.end
tree "CTIMER3"
base ad:0x40048000
group.long 0x0++0x17
line.long 0x0 "IR,Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending."
bitfld.long 0x0 7. "CR3INT,Interrupt flag for capture channel 3 event." "0,1"
bitfld.long 0x0 6. "CR2INT,Interrupt flag for capture channel 2 event." "0,1"
newline
bitfld.long 0x0 5. "CR1INT,Interrupt flag for capture channel 1 event." "0,1"
bitfld.long 0x0 4. "CR0INT,Interrupt flag for capture channel 0 event." "0,1"
newline
bitfld.long 0x0 3. "MR3INT,Interrupt flag for match channel 3." "0,1"
bitfld.long 0x0 2. "MR2INT,Interrupt flag for match channel 2." "0,1"
newline
bitfld.long 0x0 1. "MR1INT,Interrupt flag for match channel 1." "0,1"
bitfld.long 0x0 0. "MR0INT,Interrupt flag for match channel 0." "0,1"
line.long 0x4 "TCR,Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."
bitfld.long 0x4 1. "CRST,Counter reset." "0: Disabled. Do nothing.,1: Enabled. The Timer Counter and the Prescale.."
bitfld.long 0x4 0. "CEN,Counter enable." "0: Disabled.The counters are disabled.,1: Enabled. The Timer Counter and Prescale Counter.."
line.long 0x8 "TC,Timer Counter"
hexmask.long 0x8 0.--31. 1. "TCVAL,Timer counter value."
line.long 0xC "PR,Prescale Register"
hexmask.long 0xC 0.--31. 1. "PRVAL,Prescale counter value."
line.long 0x10 "PC,Prescale Counter"
hexmask.long 0x10 0.--31. 1. "PCVAL,Prescale counter value."
line.long 0x14 "MCR,Match Control Register"
bitfld.long 0x14 27. "MR3RL,Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 26. "MR2RL,Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 25. "MR1RL,Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 24. "MR0RL,Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 11. "MR3S,Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." "0,1"
bitfld.long 0x14 10. "MR3R,Reset on MR3: the TC will be reset if MR3 matches it." "0,1"
newline
bitfld.long 0x14 9. "MR3I,Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC." "0,1"
bitfld.long 0x14 8. "MR2S,Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC." "0,1"
newline
bitfld.long 0x14 7. "MR2R,Reset on MR2: the TC will be reset if MR2 matches it." "0,1"
bitfld.long 0x14 6. "MR2I,Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC." "0,1"
newline
bitfld.long 0x14 5. "MR1S,Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." "0,1"
bitfld.long 0x14 4. "MR1R,Reset on MR1: the TC will be reset if MR1 matches it." "0,1"
newline
bitfld.long 0x14 3. "MR1I,Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC." "0,1"
bitfld.long 0x14 2. "MR0S,Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." "0,1"
newline
bitfld.long 0x14 1. "MR0R,Reset on MR0: the TC will be reset if MR0 matches it." "0,1"
bitfld.long 0x14 0. "MR0I,Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC." "0,1"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x18)++0x3
line.long 0x0 "MR[$1],Match Register . MR can be enabled through the MCR to reset the TC. stop both the TC and PC. and/or generate an interrupt every time MR matches the TC."
hexmask.long 0x0 0.--31. 1. "MATCH,Timer counter match value."
repeat.end
group.long 0x28++0x3
line.long 0x0 "CCR,Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."
bitfld.long 0x0 11. "CAP3I,Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt." "0,1"
bitfld.long 0x0 10. "CAP3FE,Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 9. "CAP3RE,Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 8. "CAP2I,Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 7. "CAP2FE,Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 6. "CAP2RE,Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 5. "CAP1I,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt." "0,1"
bitfld.long 0x0 4. "CAP1FE,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 3. "CAP1RE,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 2. "CAP0I,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 1. "CAP0FE,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 0. "CAP0RE,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x2C)++0x3
line.long 0x0 "CR[$1],Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input."
hexmask.long 0x0 0.--31. 1. "CAP,Timer counter capture value."
repeat.end
group.long 0x3C++0x3
line.long 0x0 "EMR,External Match Register. The EMR controls the match function and the external match pins."
bitfld.long 0x0 10.--11. "EMC3,External Match Control 3. Determines the functionality of External Match 3." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 8.--9. "EMC2,External Match Control 2. Determines the functionality of External Match 2." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 6.--7. "EMC1,External Match Control 1. Determines the functionality of External Match 1." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 4.--5. "EMC0,External Match Control 0. Determines the functionality of External Match 0." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 3. "EM3,External Match 3. This bit reflects the state of output MAT3  whether or not this output is connected to a pin. When a match occurs between the TC and MR3  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by MR[11:10]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 2. "EM2,External Match 2. This bit reflects the state of output MAT2  whether or not this output is connected to a pin. When a match occurs between the TC and MR2  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[9:8]. This bit.." "0: LOW,1: HIGH"
newline
bitfld.long 0x0 1. "EM1,External Match 1. This bit reflects the state of output MAT1  whether or not this output is connected to a pin. When a match occurs between the TC and MR1  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[7:6]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 0. "EM0,External Match 0. This bit reflects the state of output MAT0  whether or not this output is connected to a pin. When a match occurs between the TC and MR0  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[5:4]. This bit.." "0: LOW,1: HIGH"
group.long 0x70++0x7
line.long 0x0 "CTCR,Count Control Register. The CTCR selects between Timer and Counter mode. and in Counter mode selects the signal and edge(s) for counting."
bitfld.long 0x0 5.--7. "SELCC,Edge select. When bit 4 is 1  these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved." "0: Channel 0 Rising Edge. Rising edge of the signal..,1: Channel 0 Falling Edge. Falling edge of the..,2: Channel 1 Rising Edge. Rising edge of the signal..,3: Channel 1 Falling Edge. Falling edge of the..,4: Channel 2 Rising Edge. Rising edge of the signal..,5: Channel 2 Falling Edge. Falling edge of the..,?,?"
bitfld.long 0x0 4. "ENCC,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." "0,1"
newline
bitfld.long 0x0 2.--3. "CINSEL,Count Input Select When bits 1:0 in this register are not 00  these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR  the 3 bits for that input in the Capture Control.." "0: Channel 0. CAPn.0 for CTIMERn,1: 0 in this register are not 00,2: Channel 2. CAPn.2 for CTIMERn,3: Channel 3. CAPn.3 for CTIMERn"
bitfld.long 0x0 0.--1. "CTMODE,Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC)  or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale.." "0: Timer Mode. Incremented every rising APB bus..,1: Counter Mode rising edge. TC is incremented on..,2: Counter Mode falling edge. TC is incremented on..,3: Counter Mode dual edge. TC is incremented on.."
line.long 0x4 "PWMC,PWM Control Register. The PWMCON enables PWM mode for the external match pins."
bitfld.long 0x4 3. "PWMEN3,PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle." "0: Match. CTIMERn_MAT3 is controlled by EM3.,1: PWM. PWM mode is enabled for CT132Bn_MAT3."
bitfld.long 0x4 2. "PWMEN2,PWM mode enable for channel2." "0: Match. CTIMERn_MAT2 is controlled by EM2.,1: PWM. PWM mode is enabled for CTIMERn_MAT2."
newline
bitfld.long 0x4 1. "PWMEN1,PWM mode enable for channel1." "0: Match. CTIMERn_MAT01 is controlled by EM1.,1: PWM. PWM mode is enabled for CTIMERn_MAT1."
bitfld.long 0x4 0. "PWMEN0,PWM mode enable for channel0." "0: Match. CTIMERn_MAT0 is controlled by EM0.,1: PWM. PWM mode is enabled for CTIMERn_MAT0."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x78)++0x3
line.long 0x0 "MSR[$1],Match Shadow Register"
hexmask.long 0x0 0.--31. 1. "SHADOWW,Timer counter match shadow value."
repeat.end
tree.end
tree "CTIMER4"
base ad:0x40049000
group.long 0x0++0x17
line.long 0x0 "IR,Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending."
bitfld.long 0x0 7. "CR3INT,Interrupt flag for capture channel 3 event." "0,1"
bitfld.long 0x0 6. "CR2INT,Interrupt flag for capture channel 2 event." "0,1"
newline
bitfld.long 0x0 5. "CR1INT,Interrupt flag for capture channel 1 event." "0,1"
bitfld.long 0x0 4. "CR0INT,Interrupt flag for capture channel 0 event." "0,1"
newline
bitfld.long 0x0 3. "MR3INT,Interrupt flag for match channel 3." "0,1"
bitfld.long 0x0 2. "MR2INT,Interrupt flag for match channel 2." "0,1"
newline
bitfld.long 0x0 1. "MR1INT,Interrupt flag for match channel 1." "0,1"
bitfld.long 0x0 0. "MR0INT,Interrupt flag for match channel 0." "0,1"
line.long 0x4 "TCR,Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."
bitfld.long 0x4 1. "CRST,Counter reset." "0: Disabled. Do nothing.,1: Enabled. The Timer Counter and the Prescale.."
bitfld.long 0x4 0. "CEN,Counter enable." "0: Disabled.The counters are disabled.,1: Enabled. The Timer Counter and Prescale Counter.."
line.long 0x8 "TC,Timer Counter"
hexmask.long 0x8 0.--31. 1. "TCVAL,Timer counter value."
line.long 0xC "PR,Prescale Register"
hexmask.long 0xC 0.--31. 1. "PRVAL,Prescale counter value."
line.long 0x10 "PC,Prescale Counter"
hexmask.long 0x10 0.--31. 1. "PCVAL,Prescale counter value."
line.long 0x14 "MCR,Match Control Register"
bitfld.long 0x14 27. "MR3RL,Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 26. "MR2RL,Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 25. "MR1RL,Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
bitfld.long 0x14 24. "MR0RL,Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)." "0,1"
newline
bitfld.long 0x14 11. "MR3S,Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." "0,1"
bitfld.long 0x14 10. "MR3R,Reset on MR3: the TC will be reset if MR3 matches it." "0,1"
newline
bitfld.long 0x14 9. "MR3I,Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC." "0,1"
bitfld.long 0x14 8. "MR2S,Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC." "0,1"
newline
bitfld.long 0x14 7. "MR2R,Reset on MR2: the TC will be reset if MR2 matches it." "0,1"
bitfld.long 0x14 6. "MR2I,Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC." "0,1"
newline
bitfld.long 0x14 5. "MR1S,Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." "0,1"
bitfld.long 0x14 4. "MR1R,Reset on MR1: the TC will be reset if MR1 matches it." "0,1"
newline
bitfld.long 0x14 3. "MR1I,Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC." "0,1"
bitfld.long 0x14 2. "MR0S,Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." "0,1"
newline
bitfld.long 0x14 1. "MR0R,Reset on MR0: the TC will be reset if MR0 matches it." "0,1"
bitfld.long 0x14 0. "MR0I,Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC." "0,1"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x18)++0x3
line.long 0x0 "MR[$1],Match Register . MR can be enabled through the MCR to reset the TC. stop both the TC and PC. and/or generate an interrupt every time MR matches the TC."
hexmask.long 0x0 0.--31. 1. "MATCH,Timer counter match value."
repeat.end
group.long 0x28++0x3
line.long 0x0 "CCR,Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."
bitfld.long 0x0 11. "CAP3I,Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt." "0,1"
bitfld.long 0x0 10. "CAP3FE,Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 9. "CAP3RE,Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 8. "CAP2I,Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 7. "CAP2FE,Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 6. "CAP2RE,Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 5. "CAP1I,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt." "0,1"
bitfld.long 0x0 4. "CAP1FE,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
newline
bitfld.long 0x0 3. "CAP1RE,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 2. "CAP0I,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt." "0,1"
newline
bitfld.long 0x0 1. "CAP0FE,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
bitfld.long 0x0 0. "CAP0RE,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled." "0: disabled,1: enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x2C)++0x3
line.long 0x0 "CR[$1],Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input."
hexmask.long 0x0 0.--31. 1. "CAP,Timer counter capture value."
repeat.end
group.long 0x3C++0x3
line.long 0x0 "EMR,External Match Register. The EMR controls the match function and the external match pins."
bitfld.long 0x0 10.--11. "EMC3,External Match Control 3. Determines the functionality of External Match 3." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 8.--9. "EMC2,External Match Control 2. Determines the functionality of External Match 2." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 6.--7. "EMC1,External Match Control 1. Determines the functionality of External Match 1." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 4.--5. "EMC0,External Match Control 0. Determines the functionality of External Match 0." "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 3. "EM3,External Match 3. This bit reflects the state of output MAT3  whether or not this output is connected to a pin. When a match occurs between the TC and MR3  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by MR[11:10]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 2. "EM2,External Match 2. This bit reflects the state of output MAT2  whether or not this output is connected to a pin. When a match occurs between the TC and MR2  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[9:8]. This bit.." "0: LOW,1: HIGH"
newline
bitfld.long 0x0 1. "EM1,External Match 1. This bit reflects the state of output MAT1  whether or not this output is connected to a pin. When a match occurs between the TC and MR1  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[7:6]. This bit.." "0: LOW,1: HIGH"
bitfld.long 0x0 0. "EM0,External Match 0. This bit reflects the state of output MAT0  whether or not this output is connected to a pin. When a match occurs between the TC and MR0  this bit can either toggle  go LOW  go HIGH  or do nothing  as selected by EMR[5:4]. This bit.." "0: LOW,1: HIGH"
group.long 0x70++0x7
line.long 0x0 "CTCR,Count Control Register. The CTCR selects between Timer and Counter mode. and in Counter mode selects the signal and edge(s) for counting."
bitfld.long 0x0 5.--7. "SELCC,Edge select. When bit 4 is 1  these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved." "0: Channel 0 Rising Edge. Rising edge of the signal..,1: Channel 0 Falling Edge. Falling edge of the..,2: Channel 1 Rising Edge. Rising edge of the signal..,3: Channel 1 Falling Edge. Falling edge of the..,4: Channel 2 Rising Edge. Rising edge of the signal..,5: Channel 2 Falling Edge. Falling edge of the..,?,?"
bitfld.long 0x0 4. "ENCC,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." "0,1"
newline
bitfld.long 0x0 2.--3. "CINSEL,Count Input Select When bits 1:0 in this register are not 00  these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR  the 3 bits for that input in the Capture Control.." "0: Channel 0. CAPn.0 for CTIMERn,1: 0 in this register are not 00,2: Channel 2. CAPn.2 for CTIMERn,3: Channel 3. CAPn.3 for CTIMERn"
bitfld.long 0x0 0.--1. "CTMODE,Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC)  or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale.." "0: Timer Mode. Incremented every rising APB bus..,1: Counter Mode rising edge. TC is incremented on..,2: Counter Mode falling edge. TC is incremented on..,3: Counter Mode dual edge. TC is incremented on.."
line.long 0x4 "PWMC,PWM Control Register. The PWMCON enables PWM mode for the external match pins."
bitfld.long 0x4 3. "PWMEN3,PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle." "0: Match. CTIMERn_MAT3 is controlled by EM3.,1: PWM. PWM mode is enabled for CT132Bn_MAT3."
bitfld.long 0x4 2. "PWMEN2,PWM mode enable for channel2." "0: Match. CTIMERn_MAT2 is controlled by EM2.,1: PWM. PWM mode is enabled for CTIMERn_MAT2."
newline
bitfld.long 0x4 1. "PWMEN1,PWM mode enable for channel1." "0: Match. CTIMERn_MAT01 is controlled by EM1.,1: PWM. PWM mode is enabled for CTIMERn_MAT1."
bitfld.long 0x4 0. "PWMEN0,PWM mode enable for channel0." "0: Match. CTIMERn_MAT0 is controlled by EM0.,1: PWM. PWM mode is enabled for CTIMERn_MAT0."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x78)++0x3
line.long 0x0 "MSR[$1],Match Shadow Register"
hexmask.long 0x0 0.--31. 1. "SHADOWW,Timer counter match shadow value."
repeat.end
tree.end
endif
tree.end
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54113*")||cpuis("LPC54114*")||cpuis("LPC54605*")||cpuis("LPC54606*")||cpuis("LPC54607*")||cpuis("LPC54608*")||cpuis("LPC54616*")||cpuis("LPC54618*")||cpuis("LPC54628*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
base ad:0x40082000
elif (cpuis("LPC54101*")||cpuis("LPC54102*"))
base ad:0x1C004000
endif
tree "DMA (DMA Controller)"
group.long 0x0++0x3
line.long 0x0 "CTRL,DMA control."
bitfld.long 0x0 0. "ENABLE,DMA controller master enable." "0: Disabled. The DMA controller is disabled. This..,1: Enabled. The DMA controller is enabled."
rgroup.long 0x4++0x3
line.long 0x0 "INTSTAT,Interrupt status."
bitfld.long 0x0 2. "ACTIVEERRINT,Summarizes whether any error interrupts are pending." "0: Not pending. No error interrupts are pending.,1: Pending. At least one error interrupt is pending."
bitfld.long 0x0 1. "ACTIVEINT,Summarizes whether any enabled interrupts (other than error interrupts) are pending." "0: Not pending. No enabled interrupts are pending.,1: Pending. At least one enabled interrupt is.."
group.long 0x8++0x3
line.long 0x0 "SRAMBASE,SRAM address of the channel configuration table."
hexmask.long.tbyte 0x0 9.--31. 1. "OFFSET,Address bits 31:9 of the beginning of the DMA descriptor table. For 18 channels  the table must begin on a 512 byte boundary."
group.long 0x20++0x3
line.long 0x0 "ENABLESET0,Channel Enable read and Set for all DMA channels."
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
hexmask.long 0x0 0.--31. 1. "ENA,Enable for DMA channels. Bit n enables or disables DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = disabled. 1 = enabled."
endif
sif (cpuis("LPC54101*"))
hexmask.long.tbyte 0x0 0.--21. 1. "ENA,Enable for DMA channels. Bit n enables or disables DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = disabled. 1 = enabled."
newline
endif
sif (cpuis("LPC54102*"))
hexmask.long.tbyte 0x0 0.--21. 1. "ENA,Enable for DMA channels. Bit n enables or disables DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = disabled. 1 = enabled."
endif
sif (cpuis("LPC54113*"))
hexmask.long 0x0 0.--31. 1. "ENA,Enable for DMA channels. Bit n enables or disables DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = disabled. 1 = enabled."
newline
endif
sif (cpuis("LPC54114*"))
hexmask.long 0x0 0.--31. 1. "ENA,Enable for DMA channels. Bit n enables or disables DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = disabled. 1 = enabled."
endif
sif (cpuis("LPC54605*"))
hexmask.long 0x0 0.--31. 1. "ENA,Enable for DMA channels. Bit n enables or disables DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = disabled. 1 = enabled."
newline
endif
sif (cpuis("LPC54606*"))
hexmask.long 0x0 0.--31. 1. "ENA,Enable for DMA channels. Bit n enables or disables DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = disabled. 1 = enabled."
endif
sif (cpuis("LPC54607*"))
hexmask.long 0x0 0.--31. 1. "ENA,Enable for DMA channels. Bit n enables or disables DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = disabled. 1 = enabled."
newline
endif
sif (cpuis("LPC54608*"))
hexmask.long 0x0 0.--31. 1. "ENA,Enable for DMA channels. Bit n enables or disables DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = disabled. 1 = enabled."
endif
sif (cpuis("LPC54616*"))
hexmask.long 0x0 0.--31. 1. "ENA,Enable for DMA channels. Bit n enables or disables DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = disabled. 1 = enabled."
newline
endif
sif (cpuis("LPC54618*"))
hexmask.long 0x0 0.--31. 1. "ENA,Enable for DMA channels. Bit n enables or disables DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = disabled. 1 = enabled."
endif
sif (cpuis("LPC54628*"))
hexmask.long 0x0 0.--31. 1. "ENA,Enable for DMA channels. Bit n enables or disables DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = disabled. 1 = enabled."
endif
wgroup.long 0x28++0x3
line.long 0x0 "ENABLECLR0,Channel Enable Clear for all DMA channels."
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
hexmask.long 0x0 0.--31. 1. "CLR,Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n. The number of bits = number of DMA channels in this device. Other bits are reserved."
endif
sif (cpuis("LPC54101*"))
hexmask.long.tbyte 0x0 0.--21. 1. "CLR,Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n. The number of bits = number of DMA channels in this device. Other bits are reserved."
newline
endif
sif (cpuis("LPC54102*"))
hexmask.long.tbyte 0x0 0.--21. 1. "CLR,Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n. The number of bits = number of DMA channels in this device. Other bits are reserved."
endif
sif (cpuis("LPC54113*"))
hexmask.long 0x0 0.--31. 1. "CLR,Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n. The number of bits = number of DMA channels in this device. Other bits are reserved."
newline
endif
sif (cpuis("LPC54114*"))
hexmask.long 0x0 0.--31. 1. "CLR,Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n. The number of bits = number of DMA channels in this device. Other bits are reserved."
endif
sif (cpuis("LPC54605*"))
hexmask.long 0x0 0.--31. 1. "CLR,Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n. The number of bits = number of DMA channels in this device. Other bits are reserved."
newline
endif
sif (cpuis("LPC54606*"))
hexmask.long 0x0 0.--31. 1. "CLR,Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n. The number of bits = number of DMA channels in this device. Other bits are reserved."
endif
sif (cpuis("LPC54607*"))
hexmask.long 0x0 0.--31. 1. "CLR,Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n. The number of bits = number of DMA channels in this device. Other bits are reserved."
newline
endif
sif (cpuis("LPC54608*"))
hexmask.long 0x0 0.--31. 1. "CLR,Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n. The number of bits = number of DMA channels in this device. Other bits are reserved."
endif
sif (cpuis("LPC54616*"))
hexmask.long 0x0 0.--31. 1. "CLR,Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n. The number of bits = number of DMA channels in this device. Other bits are reserved."
newline
endif
sif (cpuis("LPC54618*"))
hexmask.long 0x0 0.--31. 1. "CLR,Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n. The number of bits = number of DMA channels in this device. Other bits are reserved."
endif
sif (cpuis("LPC54628*"))
hexmask.long 0x0 0.--31. 1. "CLR,Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n. The number of bits = number of DMA channels in this device. Other bits are reserved."
endif
rgroup.long 0x30++0x3
line.long 0x0 "ACTIVE0,Channel Active status for all DMA channels."
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
hexmask.long 0x0 0.--31. 1. "ACT,Active flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = not active. 1 = active."
endif
sif (cpuis("LPC54101*"))
hexmask.long.tbyte 0x0 0.--21. 1. "ACT,Active flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = not active. 1 = active."
newline
endif
sif (cpuis("LPC54102*"))
hexmask.long.tbyte 0x0 0.--21. 1. "ACT,Active flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = not active. 1 = active."
endif
sif (cpuis("LPC54113*"))
hexmask.long 0x0 0.--31. 1. "ACT,Active flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = not active. 1 = active."
newline
endif
sif (cpuis("LPC54114*"))
hexmask.long 0x0 0.--31. 1. "ACT,Active flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = not active. 1 = active."
endif
sif (cpuis("LPC54605*"))
hexmask.long 0x0 0.--31. 1. "ACT,Active flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = not active. 1 = active."
newline
endif
sif (cpuis("LPC54606*"))
hexmask.long 0x0 0.--31. 1. "ACT,Active flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = not active. 1 = active."
endif
sif (cpuis("LPC54607*"))
hexmask.long 0x0 0.--31. 1. "ACT,Active flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = not active. 1 = active."
newline
endif
sif (cpuis("LPC54608*"))
hexmask.long 0x0 0.--31. 1. "ACT,Active flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = not active. 1 = active."
endif
sif (cpuis("LPC54616*"))
hexmask.long 0x0 0.--31. 1. "ACT,Active flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = not active. 1 = active."
newline
endif
sif (cpuis("LPC54618*"))
hexmask.long 0x0 0.--31. 1. "ACT,Active flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = not active. 1 = active."
endif
sif (cpuis("LPC54628*"))
hexmask.long 0x0 0.--31. 1. "ACT,Active flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = not active. 1 = active."
endif
rgroup.long 0x38++0x3
line.long 0x0 "BUSY0,Channel Busy status for all DMA channels."
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
hexmask.long 0x0 0.--31. 1. "BSY,Busy flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = not busy. 1 = busy."
endif
sif (cpuis("LPC54101*"))
hexmask.long.tbyte 0x0 0.--21. 1. "BSY,Busy flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = not busy. 1 = busy."
newline
endif
sif (cpuis("LPC54102*"))
hexmask.long.tbyte 0x0 0.--21. 1. "BSY,Busy flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = not busy. 1 = busy."
endif
sif (cpuis("LPC54113*"))
hexmask.long 0x0 0.--31. 1. "BSY,Busy flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = not busy. 1 = busy."
newline
endif
sif (cpuis("LPC54114*"))
hexmask.long 0x0 0.--31. 1. "BSY,Busy flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = not busy. 1 = busy."
endif
sif (cpuis("LPC54605*"))
hexmask.long 0x0 0.--31. 1. "BSY,Busy flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = not busy. 1 = busy."
newline
endif
sif (cpuis("LPC54606*"))
hexmask.long 0x0 0.--31. 1. "BSY,Busy flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = not busy. 1 = busy."
endif
sif (cpuis("LPC54607*"))
hexmask.long 0x0 0.--31. 1. "BSY,Busy flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = not busy. 1 = busy."
newline
endif
sif (cpuis("LPC54608*"))
hexmask.long 0x0 0.--31. 1. "BSY,Busy flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = not busy. 1 = busy."
endif
sif (cpuis("LPC54616*"))
hexmask.long 0x0 0.--31. 1. "BSY,Busy flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = not busy. 1 = busy."
newline
endif
sif (cpuis("LPC54618*"))
hexmask.long 0x0 0.--31. 1. "BSY,Busy flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = not busy. 1 = busy."
endif
sif (cpuis("LPC54628*"))
hexmask.long 0x0 0.--31. 1. "BSY,Busy flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = not busy. 1 = busy."
endif
group.long 0x40++0x3
line.long 0x0 "ERRINT0,Error Interrupt status for all DMA channels."
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
hexmask.long 0x0 0.--31. 1. "ERR,Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = error interrupt is not active. 1 = error interrupt is active."
endif
sif (cpuis("LPC54101*"))
hexmask.long.tbyte 0x0 0.--21. 1. "ERR,Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = error interrupt is not active. 1 = error interrupt is active."
newline
endif
sif (cpuis("LPC54102*"))
hexmask.long.tbyte 0x0 0.--21. 1. "ERR,Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = error interrupt is not active. 1 = error interrupt is active."
endif
sif (cpuis("LPC54113*"))
hexmask.long 0x0 0.--31. 1. "ERR,Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = error interrupt is not active. 1 = error interrupt is active."
newline
endif
sif (cpuis("LPC54114*"))
hexmask.long 0x0 0.--31. 1. "ERR,Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = error interrupt is not active. 1 = error interrupt is active."
endif
sif (cpuis("LPC54605*"))
hexmask.long 0x0 0.--31. 1. "ERR,Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = error interrupt is not active. 1 = error interrupt is active."
newline
endif
sif (cpuis("LPC54606*"))
hexmask.long 0x0 0.--31. 1. "ERR,Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = error interrupt is not active. 1 = error interrupt is active."
endif
sif (cpuis("LPC54607*"))
hexmask.long 0x0 0.--31. 1. "ERR,Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = error interrupt is not active. 1 = error interrupt is active."
newline
endif
sif (cpuis("LPC54608*"))
hexmask.long 0x0 0.--31. 1. "ERR,Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = error interrupt is not active. 1 = error interrupt is active."
endif
sif (cpuis("LPC54616*"))
hexmask.long 0x0 0.--31. 1. "ERR,Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = error interrupt is not active. 1 = error interrupt is active."
newline
endif
sif (cpuis("LPC54618*"))
hexmask.long 0x0 0.--31. 1. "ERR,Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = error interrupt is not active. 1 = error interrupt is active."
endif
sif (cpuis("LPC54628*"))
hexmask.long 0x0 0.--31. 1. "ERR,Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = error interrupt is not active. 1 = error interrupt is active."
endif
group.long 0x48++0x3
line.long 0x0 "INTENSET0,Interrupt Enable read and Set for all DMA channels."
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
hexmask.long 0x0 0.--31. 1. "INTEN,Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is.."
endif
sif (cpuis("LPC54101*"))
hexmask.long.tbyte 0x0 0.--21. 1. "INTEN,Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is.."
newline
endif
sif (cpuis("LPC54102*"))
hexmask.long.tbyte 0x0 0.--21. 1. "INTEN,Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is.."
endif
sif (cpuis("LPC54113*"))
hexmask.long 0x0 0.--31. 1. "INTEN,Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is.."
newline
endif
sif (cpuis("LPC54114*"))
hexmask.long 0x0 0.--31. 1. "INTEN,Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is.."
endif
sif (cpuis("LPC54605*"))
hexmask.long 0x0 0.--31. 1. "INTEN,Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is.."
newline
endif
sif (cpuis("LPC54606*"))
hexmask.long 0x0 0.--31. 1. "INTEN,Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is.."
endif
sif (cpuis("LPC54607*"))
hexmask.long 0x0 0.--31. 1. "INTEN,Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is.."
newline
endif
sif (cpuis("LPC54608*"))
hexmask.long 0x0 0.--31. 1. "INTEN,Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is.."
endif
sif (cpuis("LPC54616*"))
hexmask.long 0x0 0.--31. 1. "INTEN,Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is.."
newline
endif
sif (cpuis("LPC54618*"))
hexmask.long 0x0 0.--31. 1. "INTEN,Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is.."
endif
sif (cpuis("LPC54628*"))
hexmask.long 0x0 0.--31. 1. "INTEN,Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is.."
endif
wgroup.long 0x50++0x3
line.long 0x0 "INTENCLR0,Interrupt Enable Clear for all DMA channels."
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
hexmask.long 0x0 0.--31. 1. "CLR,Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved."
endif
sif (cpuis("LPC54101*"))
hexmask.long.tbyte 0x0 0.--21. 1. "CLR,Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved."
newline
endif
sif (cpuis("LPC54102*"))
hexmask.long.tbyte 0x0 0.--21. 1. "CLR,Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved."
endif
sif (cpuis("LPC54113*"))
hexmask.long 0x0 0.--31. 1. "CLR,Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved."
newline
endif
sif (cpuis("LPC54114*"))
hexmask.long 0x0 0.--31. 1. "CLR,Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved."
endif
sif (cpuis("LPC54605*"))
hexmask.long 0x0 0.--31. 1. "CLR,Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved."
newline
endif
sif (cpuis("LPC54606*"))
hexmask.long 0x0 0.--31. 1. "CLR,Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved."
endif
sif (cpuis("LPC54607*"))
hexmask.long 0x0 0.--31. 1. "CLR,Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved."
newline
endif
sif (cpuis("LPC54608*"))
hexmask.long 0x0 0.--31. 1. "CLR,Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved."
endif
sif (cpuis("LPC54616*"))
hexmask.long 0x0 0.--31. 1. "CLR,Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved."
newline
endif
sif (cpuis("LPC54618*"))
hexmask.long 0x0 0.--31. 1. "CLR,Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved."
endif
sif (cpuis("LPC54628*"))
hexmask.long 0x0 0.--31. 1. "CLR,Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved."
endif
group.long 0x58++0x3
line.long 0x0 "INTA0,Interrupt A status for all DMA channels."
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
hexmask.long 0x0 0.--31. 1. "IA,Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel interrupt A is not active. 1 = the DMA channel interrupt A is active."
endif
sif (cpuis("LPC54101*"))
hexmask.long.tbyte 0x0 0.--21. 1. "IA,Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel interrupt A is not active. 1 = the DMA channel interrupt A is active."
newline
endif
sif (cpuis("LPC54102*"))
hexmask.long.tbyte 0x0 0.--21. 1. "IA,Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel interrupt A is not active. 1 = the DMA channel interrupt A is active."
endif
sif (cpuis("LPC54113*"))
hexmask.long 0x0 0.--31. 1. "IA,Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel interrupt A is not active. 1 = the DMA channel interrupt A is active."
newline
endif
sif (cpuis("LPC54114*"))
hexmask.long 0x0 0.--31. 1. "IA,Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel interrupt A is not active. 1 = the DMA channel interrupt A is active."
endif
sif (cpuis("LPC54605*"))
hexmask.long 0x0 0.--31. 1. "IA,Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel interrupt A is not active. 1 = the DMA channel interrupt A is active."
newline
endif
sif (cpuis("LPC54606*"))
hexmask.long 0x0 0.--31. 1. "IA,Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel interrupt A is not active. 1 = the DMA channel interrupt A is active."
endif
sif (cpuis("LPC54607*"))
hexmask.long 0x0 0.--31. 1. "IA,Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel interrupt A is not active. 1 = the DMA channel interrupt A is active."
newline
endif
sif (cpuis("LPC54608*"))
hexmask.long 0x0 0.--31. 1. "IA,Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel interrupt A is not active. 1 = the DMA channel interrupt A is active."
endif
sif (cpuis("LPC54616*"))
hexmask.long 0x0 0.--31. 1. "IA,Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel interrupt A is not active. 1 = the DMA channel interrupt A is active."
newline
endif
sif (cpuis("LPC54618*"))
hexmask.long 0x0 0.--31. 1. "IA,Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel interrupt A is not active. 1 = the DMA channel interrupt A is active."
endif
sif (cpuis("LPC54628*"))
hexmask.long 0x0 0.--31. 1. "IA,Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel interrupt A is not active. 1 = the DMA channel interrupt A is active."
endif
group.long 0x60++0x3
line.long 0x0 "INTB0,Interrupt B status for all DMA channels."
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
hexmask.long 0x0 0.--31. 1. "IB,Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel interrupt B is not active. 1 = the DMA channel interrupt B is active."
endif
sif (cpuis("LPC54101*"))
hexmask.long.tbyte 0x0 0.--21. 1. "IB,Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel interrupt B is not active. 1 = the DMA channel interrupt B is active."
newline
endif
sif (cpuis("LPC54102*"))
hexmask.long.tbyte 0x0 0.--21. 1. "IB,Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel interrupt B is not active. 1 = the DMA channel interrupt B is active."
endif
sif (cpuis("LPC54113*"))
hexmask.long 0x0 0.--31. 1. "IB,Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel interrupt B is not active. 1 = the DMA channel interrupt B is active."
newline
endif
sif (cpuis("LPC54114*"))
hexmask.long 0x0 0.--31. 1. "IB,Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel interrupt B is not active. 1 = the DMA channel interrupt B is active."
endif
sif (cpuis("LPC54605*"))
hexmask.long 0x0 0.--31. 1. "IB,Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel interrupt B is not active. 1 = the DMA channel interrupt B is active."
newline
endif
sif (cpuis("LPC54606*"))
hexmask.long 0x0 0.--31. 1. "IB,Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel interrupt B is not active. 1 = the DMA channel interrupt B is active."
endif
sif (cpuis("LPC54607*"))
hexmask.long 0x0 0.--31. 1. "IB,Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel interrupt B is not active. 1 = the DMA channel interrupt B is active."
newline
endif
sif (cpuis("LPC54608*"))
hexmask.long 0x0 0.--31. 1. "IB,Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel interrupt B is not active. 1 = the DMA channel interrupt B is active."
endif
sif (cpuis("LPC54616*"))
hexmask.long 0x0 0.--31. 1. "IB,Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel interrupt B is not active. 1 = the DMA channel interrupt B is active."
newline
endif
sif (cpuis("LPC54618*"))
hexmask.long 0x0 0.--31. 1. "IB,Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel interrupt B is not active. 1 = the DMA channel interrupt B is active."
endif
sif (cpuis("LPC54628*"))
hexmask.long 0x0 0.--31. 1. "IB,Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel interrupt B is not active. 1 = the DMA channel interrupt B is active."
endif
wgroup.long 0x68++0x3
line.long 0x0 "SETVALID0,Set ValidPending control bits for all DMA channels."
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
hexmask.long 0x0 0.--31. 1. "SV,SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the VALIDPENDING control bit for DMA channel n"
endif
sif (cpuis("LPC54101*"))
hexmask.long.tbyte 0x0 0.--21. 1. "SV,SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the VALIDPENDING control bit for DMA channel n"
newline
endif
sif (cpuis("LPC54102*"))
hexmask.long.tbyte 0x0 0.--21. 1. "SV,SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the VALIDPENDING control bit for DMA channel n"
endif
sif (cpuis("LPC54113*"))
hexmask.long 0x0 0.--31. 1. "SV,SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the VALIDPENDING control bit for DMA channel n"
newline
endif
sif (cpuis("LPC54114*"))
hexmask.long 0x0 0.--31. 1. "SV,SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the VALIDPENDING control bit for DMA channel n"
endif
sif (cpuis("LPC54605*"))
hexmask.long 0x0 0.--31. 1. "SV,SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the VALIDPENDING control bit for DMA channel n"
newline
endif
sif (cpuis("LPC54606*"))
hexmask.long 0x0 0.--31. 1. "SV,SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the VALIDPENDING control bit for DMA channel n"
endif
sif (cpuis("LPC54607*"))
hexmask.long 0x0 0.--31. 1. "SV,SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the VALIDPENDING control bit for DMA channel n"
newline
endif
sif (cpuis("LPC54608*"))
hexmask.long 0x0 0.--31. 1. "SV,SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the VALIDPENDING control bit for DMA channel n"
endif
sif (cpuis("LPC54616*"))
hexmask.long 0x0 0.--31. 1. "SV,SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the VALIDPENDING control bit for DMA channel n"
newline
endif
sif (cpuis("LPC54618*"))
hexmask.long 0x0 0.--31. 1. "SV,SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the VALIDPENDING control bit for DMA channel n"
endif
sif (cpuis("LPC54628*"))
hexmask.long 0x0 0.--31. 1. "SV,SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the VALIDPENDING control bit for DMA channel n"
endif
wgroup.long 0x70++0x3
line.long 0x0 "SETTRIG0,Set Trigger control bits for all DMA channels."
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
hexmask.long 0x0 0.--31. 1. "TRIG,Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the TRIG bit for DMA channel n."
endif
sif (cpuis("LPC54101*"))
hexmask.long.tbyte 0x0 0.--21. 1. "TRIG,Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the TRIG bit for DMA channel n."
newline
endif
sif (cpuis("LPC54102*"))
hexmask.long.tbyte 0x0 0.--21. 1. "TRIG,Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the TRIG bit for DMA channel n."
endif
sif (cpuis("LPC54113*"))
hexmask.long 0x0 0.--31. 1. "TRIG,Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the TRIG bit for DMA channel n."
newline
endif
sif (cpuis("LPC54114*"))
hexmask.long 0x0 0.--31. 1. "TRIG,Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the TRIG bit for DMA channel n."
endif
sif (cpuis("LPC54605*"))
hexmask.long 0x0 0.--31. 1. "TRIG,Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the TRIG bit for DMA channel n."
newline
endif
sif (cpuis("LPC54606*"))
hexmask.long 0x0 0.--31. 1. "TRIG,Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the TRIG bit for DMA channel n."
endif
sif (cpuis("LPC54607*"))
hexmask.long 0x0 0.--31. 1. "TRIG,Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the TRIG bit for DMA channel n."
newline
endif
sif (cpuis("LPC54608*"))
hexmask.long 0x0 0.--31. 1. "TRIG,Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the TRIG bit for DMA channel n."
endif
sif (cpuis("LPC54616*"))
hexmask.long 0x0 0.--31. 1. "TRIG,Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the TRIG bit for DMA channel n."
newline
endif
sif (cpuis("LPC54618*"))
hexmask.long 0x0 0.--31. 1. "TRIG,Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the TRIG bit for DMA channel n."
endif
sif (cpuis("LPC54628*"))
hexmask.long 0x0 0.--31. 1. "TRIG,Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the TRIG bit for DMA channel n."
endif
wgroup.long 0x78++0x3
line.long 0x0 "ABORT0,Channel Abort control for all DMA channels."
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
hexmask.long 0x0 0.--31. 1. "ABORTCTRL,Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = aborts DMA operations on channel n."
endif
sif (cpuis("LPC54101*"))
hexmask.long.tbyte 0x0 0.--21. 1. "ABORTCTRL,Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = aborts DMA operations on channel n."
newline
endif
sif (cpuis("LPC54102*"))
hexmask.long.tbyte 0x0 0.--21. 1. "ABORTCTRL,Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = aborts DMA operations on channel n."
endif
sif (cpuis("LPC54113*"))
hexmask.long 0x0 0.--31. 1. "ABORTCTRL,Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = aborts DMA operations on channel n."
newline
endif
sif (cpuis("LPC54114*"))
hexmask.long 0x0 0.--31. 1. "ABORTCTRL,Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = aborts DMA operations on channel n."
endif
sif (cpuis("LPC54605*"))
hexmask.long 0x0 0.--31. 1. "ABORTCTRL,Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = aborts DMA operations on channel n."
newline
endif
sif (cpuis("LPC54606*"))
hexmask.long 0x0 0.--31. 1. "ABORTCTRL,Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = aborts DMA operations on channel n."
endif
sif (cpuis("LPC54607*"))
hexmask.long 0x0 0.--31. 1. "ABORTCTRL,Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = aborts DMA operations on channel n."
newline
endif
sif (cpuis("LPC54608*"))
hexmask.long 0x0 0.--31. 1. "ABORTCTRL,Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = aborts DMA operations on channel n."
endif
sif (cpuis("LPC54616*"))
hexmask.long 0x0 0.--31. 1. "ABORTCTRL,Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = aborts DMA operations on channel n."
newline
endif
sif (cpuis("LPC54618*"))
hexmask.long 0x0 0.--31. 1. "ABORTCTRL,Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = aborts DMA operations on channel n."
endif
sif (cpuis("LPC54628*"))
hexmask.long 0x0 0.--31. 1. "ABORTCTRL,Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = aborts DMA operations on channel n."
endif
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40082400 ad:0x40082410 ad:0x40082420 ad:0x40082430 ad:0x40082440 ad:0x40082450 ad:0x40082460 ad:0x40082470 ad:0x40082480 ad:0x40082490 ad:0x400824A0 ad:0x400824B0 ad:0x400824C0 ad:0x400824D0 ad:0x400824E0 ad:0x400824F0)
tree "CHANNEL[$1]"
base $2
group.long ($2)++0x3
line.long 0x0 "CFG,Configuration register for DMA channel ."
bitfld.long 0x0 16.--18. "CHPRIORITY,Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported: 0x0 = highest priority. 0x7 = lowest priority." "0: highest priority,?,?,?,?,?,?,7: lowest priority"
bitfld.long 0x0 15. "DSTBURSTWRAP,Destination Burst Wrap. When enabled  the destination data address for the DMA is 'wrapped'  meaning that the destination address range for each burst will be the same. As an example  this could be used to write several sequential registers.." "0: Disabled. Destination burst wrapping is not..,1: Enabled. Destination burst wrapping is enabled.."
newline
bitfld.long 0x0 14. "SRCBURSTWRAP,Source Burst Wrap. When enabled  the source data address for the DMA is 'wrapped'  meaning that the source address range for each burst will be the same. As an example  this could be used to read several sequential registers from a.." "0: Disabled. Source burst wrapping is not enabled..,1: Enabled. Source burst wrapping is enabled for.."
hexmask.long.byte 0x0 8.--11. 1. "BURSTPOWER,Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1  Burst.."
newline
bitfld.long 0x0 6. "TRIGBURST,Trigger Burst. Selects whether hardware triggers cause a single or burst transfer." "0: Single transfer. Hardware trigger causes a..,1: Burst transfer. When the trigger for this.."
bitfld.long 0x0 5. "TRIGTYPE,Trigger Type. Selects hardware trigger as edge triggered or level triggered." "0: Edge. Hardware trigger is edge triggered.,1: Level. Hardware trigger is level triggered. Note.."
newline
bitfld.long 0x0 4. "TRIGPOL,Trigger Polarity. Selects the polarity of a hardware trigger for this channel." "0: Active low - falling edge. Hardware trigger is..,1: Active high - rising edge. Hardware trigger is.."
bitfld.long 0x0 1. "HWTRIGEN,Hardware Triggering Enable for this channel." "0: Disabled. Hardware triggering is not used.,1: Enabled. Use hardware triggering."
newline
bitfld.long 0x0 0. "PERIPHREQEN,Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move  any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller." "0: Disabled. Peripheral DMA requests are disabled.,1: Enabled. Peripheral DMA requests are enabled."
rgroup.long ($2+0x4)++0x3
line.long 0x0 "CTLSTAT,Control and status register for DMA channel ."
bitfld.long 0x0 2. "TRIG,Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1." "0: Not triggered. The trigger for this DMA channel..,1: Triggered. The trigger for this DMA channel is.."
bitfld.long 0x0 0. "VALIDPENDING,Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel." "0: No effect. No effect on DMA operation.,1: Valid pending."
group.long ($2+0x8)++0x3
line.long 0x0 "XFERCFG,Transfer configuration register for DMA channel ."
hexmask.long.word 0x0 16.--25. 1. "XFERCOUNT,Total number of transfers to be performed  minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence  it cannot.."
bitfld.long 0x0 14.--15. "DSTINC,Determines whether the destination address is incremented for each DMA transfer." "0: No increment. The destination address is not..,1: 1 x width. The destination address is..,2: 2 x width. The destination address is..,3: 4 x width. The destination address is.."
newline
bitfld.long 0x0 12.--13. "SRCINC,Determines whether the source address is incremented for each DMA transfer." "0: No increment. The source address is not..,1: 1 x width. The source address is incremented by..,2: 2 x width. The source address is incremented by..,3: 4 x width. The source address is incremented by.."
bitfld.long 0x0 8.--9. "WIDTH,Transfer width used for this DMA channel." "0: 8-bit. 8-bit transfers are performed (8-bit..,1: 16-bit. 6-bit transfers are performed (16-bit..,2: 32-bit. 32-bit transfers are performed (32-bit..,?"
newline
bitfld.long 0x0 5. "SETINTB,Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention  interrupt A may be used when only one interrupt flag is.." "0: No effect.,1: Set. The INTB flag for this channel will be set.."
bitfld.long 0x0 4. "SETINTA,Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention  interrupt A may be used when only one interrupt flag is.." "0: No effect.,1: Set. The INTA flag for this channel will be set.."
newline
bitfld.long 0x0 3. "CLRTRIG,Clear Trigger." "0: Not cleared. The trigger is not cleared when..,1: Cleared. The trigger is cleared when this.."
bitfld.long 0x0 2. "SWTRIG,Software Trigger." "0: Not set. When written by software the trigger..,1: Set. When written by software the trigger for.."
newline
bitfld.long 0x0 1. "RELOAD,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers." "0: Disabled. Do not reload the channels' control..,1: Enabled. Reload the channels' control structure.."
bitfld.long 0x0 0. "CFGVALID,Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon  if all other activation criteria are fulfilled." "0: Not valid. The channel descriptor is not..,1: Valid. The current channel descriptor is.."
tree.end
repeat.end
base ad:0x40082000
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F)(list ad:0x40082500 ad:0x40082510 ad:0x40082520 ad:0x40082530 ad:0x40082540 ad:0x40082550 ad:0x40082560 ad:0x40082570 ad:0x40082580 ad:0x40082590 ad:0x400825A0 ad:0x400825B0 ad:0x400825C0 ad:0x400825D0 ad:0x400825E0 ad:0x400825F0)
tree "CHANNEL[$1]"
base $2
group.long ($2)++0x3
line.long 0x0 "CFG,Configuration register for DMA channel ."
bitfld.long 0x0 16.--18. "CHPRIORITY,Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported: 0x0 = highest priority. 0x7 = lowest priority." "0: highest priority,?,?,?,?,?,?,7: lowest priority"
bitfld.long 0x0 15. "DSTBURSTWRAP,Destination Burst Wrap. When enabled  the destination data address for the DMA is 'wrapped'  meaning that the destination address range for each burst will be the same. As an example  this could be used to write several sequential registers.." "0: Disabled. Destination burst wrapping is not..,1: Enabled. Destination burst wrapping is enabled.."
newline
bitfld.long 0x0 14. "SRCBURSTWRAP,Source Burst Wrap. When enabled  the source data address for the DMA is 'wrapped'  meaning that the source address range for each burst will be the same. As an example  this could be used to read several sequential registers from a.." "0: Disabled. Source burst wrapping is not enabled..,1: Enabled. Source burst wrapping is enabled for.."
hexmask.long.byte 0x0 8.--11. 1. "BURSTPOWER,Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1  Burst.."
newline
bitfld.long 0x0 6. "TRIGBURST,Trigger Burst. Selects whether hardware triggers cause a single or burst transfer." "0: Single transfer. Hardware trigger causes a..,1: Burst transfer. When the trigger for this.."
bitfld.long 0x0 5. "TRIGTYPE,Trigger Type. Selects hardware trigger as edge triggered or level triggered." "0: Edge. Hardware trigger is edge triggered.,1: Level. Hardware trigger is level triggered. Note.."
newline
bitfld.long 0x0 4. "TRIGPOL,Trigger Polarity. Selects the polarity of a hardware trigger for this channel." "0: Active low - falling edge. Hardware trigger is..,1: Active high - rising edge. Hardware trigger is.."
bitfld.long 0x0 1. "HWTRIGEN,Hardware Triggering Enable for this channel." "0: Disabled. Hardware triggering is not used.,1: Enabled. Use hardware triggering."
newline
bitfld.long 0x0 0. "PERIPHREQEN,Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move  any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller." "0: Disabled. Peripheral DMA requests are disabled.,1: Enabled. Peripheral DMA requests are enabled."
rgroup.long ($2+0x4)++0x3
line.long 0x0 "CTLSTAT,Control and status register for DMA channel ."
bitfld.long 0x0 2. "TRIG,Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1." "0: Not triggered. The trigger for this DMA channel..,1: Triggered. The trigger for this DMA channel is.."
bitfld.long 0x0 0. "VALIDPENDING,Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel." "0: No effect. No effect on DMA operation.,1: Valid pending."
group.long ($2+0x8)++0x3
line.long 0x0 "XFERCFG,Transfer configuration register for DMA channel ."
hexmask.long.word 0x0 16.--25. 1. "XFERCOUNT,Total number of transfers to be performed  minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence  it cannot.."
bitfld.long 0x0 14.--15. "DSTINC,Determines whether the destination address is incremented for each DMA transfer." "0: No increment. The destination address is not..,1: 1 x width. The destination address is..,2: 2 x width. The destination address is..,3: 4 x width. The destination address is.."
newline
bitfld.long 0x0 12.--13. "SRCINC,Determines whether the source address is incremented for each DMA transfer." "0: No increment. The source address is not..,1: 1 x width. The source address is incremented by..,2: 2 x width. The source address is incremented by..,3: 4 x width. The source address is incremented by.."
bitfld.long 0x0 8.--9. "WIDTH,Transfer width used for this DMA channel." "0: 8-bit. 8-bit transfers are performed (8-bit..,1: 16-bit. 6-bit transfers are performed (16-bit..,2: 32-bit. 32-bit transfers are performed (32-bit..,?"
newline
bitfld.long 0x0 5. "SETINTB,Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention  interrupt A may be used when only one interrupt flag is.." "0: No effect.,1: Set. The INTB flag for this channel will be set.."
bitfld.long 0x0 4. "SETINTA,Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention  interrupt A may be used when only one interrupt flag is.." "0: No effect.,1: Set. The INTA flag for this channel will be set.."
newline
bitfld.long 0x0 3. "CLRTRIG,Clear Trigger." "0: Not cleared. The trigger is not cleared when..,1: Cleared. The trigger is cleared when this.."
bitfld.long 0x0 2. "SWTRIG,Software Trigger." "0: Not set. When written by software the trigger..,1: Set. When written by software the trigger for.."
newline
bitfld.long 0x0 1. "RELOAD,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers." "0: Disabled. Do not reload the channels' control..,1: Enabled. Reload the channels' control structure.."
bitfld.long 0x0 0. "CFGVALID,Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon  if all other activation criteria are fulfilled." "0: Not valid. The channel descriptor is not..,1: Valid. The current channel descriptor is.."
tree.end
repeat.end
endif
sif (cpuis("LPC54101*"))
group.long 0x30++0x3
line.long 0x0 "ACTIVE0,Channel Active status for all DMA channels."
endif
sif (cpuis("LPC54101*"))
group.long 0x38++0x3
line.long 0x0 "BUSY0,Channel Busy status for all DMA channels."
endif
sif (cpuis("LPC54101*"))
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x1C004400 ad:0x1C004410 ad:0x1C004420 ad:0x1C004430 ad:0x1C004440 ad:0x1C004450 ad:0x1C004460 ad:0x1C004470 ad:0x1C004480 ad:0x1C004490 ad:0x1C0044A0 ad:0x1C0044B0 ad:0x1C0044C0 ad:0x1C0044D0 ad:0x1C0044E0 ad:0x1C0044F0)
tree "CHANNEL[$1]"
base $2
group.long ($2)++0x3
line.long 0x0 "CFG,Configuration register for DMA channel ."
bitfld.long 0x0 16.--18. "CHPRIORITY,Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported: 0x0 = highest priority. 0x7 = lowest priority." "0: highest priority,?,?,?,?,?,?,7: lowest priority"
bitfld.long 0x0 15. "DSTBURSTWRAP,Destination Burst Wrap. When enabled  the destination data address for the DMA is 'wrapped'  meaning that the destination address range for each burst will be the same. As an example  this could be used to write several sequential registers.." "0: Disabled. Destination burst wrapping is not..,1: Enabled. Destination burst wrapping is enabled.."
newline
bitfld.long 0x0 14. "SRCBURSTWRAP,Source Burst Wrap. When enabled  the source data address for the DMA is 'wrapped'  meaning that the source address range for each burst will be the same. As an example  this could be used to read several sequential registers from a.." "0: Disabled. Source burst wrapping is not enabled..,1: Enabled. Source burst wrapping is enabled for.."
hexmask.long.byte 0x0 8.--11. 1. "BURSTPOWER,Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1  Burst.."
newline
bitfld.long 0x0 6. "TRIGBURST,Trigger Burst. Selects whether hardware triggers cause a single or burst transfer." "0: Single transfer. Hardware trigger causes a..,1: Burst transfer. When the trigger for this.."
bitfld.long 0x0 5. "TRIGTYPE,Trigger Type. Selects hardware trigger as edge triggered or level triggered." "0: Edge. Hardware trigger is edge triggered.,1: Level. Hardware trigger is level triggered. Note.."
newline
bitfld.long 0x0 4. "TRIGPOL,Trigger Polarity. Selects the polarity of a hardware trigger for this channel." "0: Active low - falling edge. Hardware trigger is..,1: Active high - rising edge. Hardware trigger is.."
bitfld.long 0x0 1. "HWTRIGEN,Hardware Triggering Enable for this channel." "0: Disabled. Hardware triggering is not used.,1: Enabled. Use hardware triggering."
newline
bitfld.long 0x0 0. "PERIPHREQEN,Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move  any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller." "0: Disabled. Peripheral DMA requests are disabled.,1: Enabled. Peripheral DMA requests are enabled."
rgroup.long ($2+0x4)++0x3
line.long 0x0 "CTLSTAT,Control and status register for DMA channel ."
bitfld.long 0x0 2. "TRIG,Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1." "0: Not triggered. The trigger for this DMA channel..,1: Triggered. The trigger for this DMA channel is.."
bitfld.long 0x0 0. "VALIDPENDING,Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel." "0: No effect. No effect on DMA operation.,1: Valid pending."
group.long ($2+0x8)++0x3
line.long 0x0 "XFERCFG,Transfer configuration register for DMA channel ."
hexmask.long.word 0x0 16.--25. 1. "XFERCOUNT,Total number of transfers to be performed  minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence  it cannot.."
bitfld.long 0x0 14.--15. "DSTINC,Determines whether the destination address is incremented for each DMA transfer." "0: No increment. The destination address is not..,1: 1 x width. The destination address is..,2: 2 x width. The destination address is..,3: 4 x width. The destination address is.."
newline
bitfld.long 0x0 12.--13. "SRCINC,Determines whether the source address is incremented for each DMA transfer." "0: No increment. The source address is not..,1: 1 x width. The source address is incremented by..,2: 2 x width. The source address is incremented by..,3: 4 x width. The source address is incremented by.."
bitfld.long 0x0 8.--9. "WIDTH,Transfer width used for this DMA channel." "0: 8-bit. 8-bit transfers are performed (8-bit..,1: 16-bit. 6-bit transfers are performed (16-bit..,2: 32-bit. 32-bit transfers are performed (32-bit..,?"
newline
bitfld.long 0x0 5. "SETINTB,Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention  interrupt A may be used when only one interrupt flag is.." "0: No effect.,1: Set. The INTB flag for this channel will be set.."
bitfld.long 0x0 4. "SETINTA,Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention  interrupt A may be used when only one interrupt flag is.." "0: No effect.,1: Set. The INTA flag for this channel will be set.."
newline
bitfld.long 0x0 3. "CLRTRIG,Clear Trigger." "0: Not cleared. The trigger is not cleared when..,1: Cleared. The trigger is cleared when this.."
bitfld.long 0x0 2. "SWTRIG,Software Trigger." "0: Not set. When written by software the trigger..,1: Set. When written by software the trigger for.."
newline
bitfld.long 0x0 1. "RELOAD,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers." "0: Disabled. Do not reload the channels' control..,1: Enabled. Reload the channels' control structure.."
bitfld.long 0x0 0. "CFGVALID,Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon  if all other activation criteria are fulfilled." "0: Not valid. The channel descriptor is not..,1: Valid. The current channel descriptor is.."
tree.end
repeat.end
endif
sif (cpuis("LPC54101*"))
repeat 6. (list 0x10 0x11 0x12 0x13 0x14 0x15)(list ad:0x1C004500 ad:0x1C004510 ad:0x1C004520 ad:0x1C004530 ad:0x1C004540 ad:0x1C004550)
tree "CHANNEL[$1]"
base $2
group.long ($2)++0x3
line.long 0x0 "CFG,Configuration register for DMA channel ."
bitfld.long 0x0 16.--18. "CHPRIORITY,Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported: 0x0 = highest priority. 0x7 = lowest priority." "0: highest priority,?,?,?,?,?,?,7: lowest priority"
bitfld.long 0x0 15. "DSTBURSTWRAP,Destination Burst Wrap. When enabled  the destination data address for the DMA is 'wrapped'  meaning that the destination address range for each burst will be the same. As an example  this could be used to write several sequential registers.." "0: Disabled. Destination burst wrapping is not..,1: Enabled. Destination burst wrapping is enabled.."
newline
bitfld.long 0x0 14. "SRCBURSTWRAP,Source Burst Wrap. When enabled  the source data address for the DMA is 'wrapped'  meaning that the source address range for each burst will be the same. As an example  this could be used to read several sequential registers from a.." "0: Disabled. Source burst wrapping is not enabled..,1: Enabled. Source burst wrapping is enabled for.."
hexmask.long.byte 0x0 8.--11. 1. "BURSTPOWER,Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1  Burst.."
newline
bitfld.long 0x0 6. "TRIGBURST,Trigger Burst. Selects whether hardware triggers cause a single or burst transfer." "0: Single transfer. Hardware trigger causes a..,1: Burst transfer. When the trigger for this.."
bitfld.long 0x0 5. "TRIGTYPE,Trigger Type. Selects hardware trigger as edge triggered or level triggered." "0: Edge. Hardware trigger is edge triggered.,1: Level. Hardware trigger is level triggered. Note.."
newline
bitfld.long 0x0 4. "TRIGPOL,Trigger Polarity. Selects the polarity of a hardware trigger for this channel." "0: Active low - falling edge. Hardware trigger is..,1: Active high - rising edge. Hardware trigger is.."
bitfld.long 0x0 1. "HWTRIGEN,Hardware Triggering Enable for this channel." "0: Disabled. Hardware triggering is not used.,1: Enabled. Use hardware triggering."
newline
bitfld.long 0x0 0. "PERIPHREQEN,Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move  any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller." "0: Disabled. Peripheral DMA requests are disabled.,1: Enabled. Peripheral DMA requests are enabled."
rgroup.long ($2+0x4)++0x3
line.long 0x0 "CTLSTAT,Control and status register for DMA channel ."
bitfld.long 0x0 2. "TRIG,Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1." "0: Not triggered. The trigger for this DMA channel..,1: Triggered. The trigger for this DMA channel is.."
bitfld.long 0x0 0. "VALIDPENDING,Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel." "0: No effect. No effect on DMA operation.,1: Valid pending."
group.long ($2+0x8)++0x3
line.long 0x0 "XFERCFG,Transfer configuration register for DMA channel ."
hexmask.long.word 0x0 16.--25. 1. "XFERCOUNT,Total number of transfers to be performed  minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence  it cannot.."
bitfld.long 0x0 14.--15. "DSTINC,Determines whether the destination address is incremented for each DMA transfer." "0: No increment. The destination address is not..,1: 1 x width. The destination address is..,2: 2 x width. The destination address is..,3: 4 x width. The destination address is.."
newline
bitfld.long 0x0 12.--13. "SRCINC,Determines whether the source address is incremented for each DMA transfer." "0: No increment. The source address is not..,1: 1 x width. The source address is incremented by..,2: 2 x width. The source address is incremented by..,3: 4 x width. The source address is incremented by.."
bitfld.long 0x0 8.--9. "WIDTH,Transfer width used for this DMA channel." "0: 8-bit. 8-bit transfers are performed (8-bit..,1: 16-bit. 6-bit transfers are performed (16-bit..,2: 32-bit. 32-bit transfers are performed (32-bit..,?"
newline
bitfld.long 0x0 5. "SETINTB,Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention  interrupt A may be used when only one interrupt flag is.." "0: No effect.,1: Set. The INTB flag for this channel will be set.."
bitfld.long 0x0 4. "SETINTA,Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention  interrupt A may be used when only one interrupt flag is.." "0: No effect.,1: Set. The INTA flag for this channel will be set.."
newline
bitfld.long 0x0 3. "CLRTRIG,Clear Trigger." "0: Not cleared. The trigger is not cleared when..,1: Cleared. The trigger is cleared when this.."
bitfld.long 0x0 2. "SWTRIG,Software Trigger." "0: Not set. When written by software the trigger..,1: Set. When written by software the trigger for.."
newline
bitfld.long 0x0 1. "RELOAD,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers." "0: Disabled. Do not reload the channels' control..,1: Enabled. Reload the channels' control structure.."
bitfld.long 0x0 0. "CFGVALID,Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon  if all other activation criteria are fulfilled." "0: Not valid. The channel descriptor is not..,1: Valid. The current channel descriptor is.."
tree.end
repeat.end
endif
sif (cpuis("LPC54102*"))
group.long 0x30++0x3
line.long 0x0 "ACTIVE0,Channel Active status for all DMA channels."
endif
sif (cpuis("LPC54102*"))
group.long 0x38++0x3
line.long 0x0 "BUSY0,Channel Busy status for all DMA channels."
endif
sif (cpuis("LPC54102*"))
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x1C004400 ad:0x1C004410 ad:0x1C004420 ad:0x1C004430 ad:0x1C004440 ad:0x1C004450 ad:0x1C004460 ad:0x1C004470 ad:0x1C004480 ad:0x1C004490 ad:0x1C0044A0 ad:0x1C0044B0 ad:0x1C0044C0 ad:0x1C0044D0 ad:0x1C0044E0 ad:0x1C0044F0)
tree "CHANNEL[$1]"
base $2
group.long ($2)++0x3
line.long 0x0 "CFG,Configuration register for DMA channel ."
bitfld.long 0x0 16.--18. "CHPRIORITY,Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported: 0x0 = highest priority. 0x7 = lowest priority." "0: highest priority,?,?,?,?,?,?,7: lowest priority"
bitfld.long 0x0 15. "DSTBURSTWRAP,Destination Burst Wrap. When enabled  the destination data address for the DMA is 'wrapped'  meaning that the destination address range for each burst will be the same. As an example  this could be used to write several sequential registers.." "0: Disabled. Destination burst wrapping is not..,1: Enabled. Destination burst wrapping is enabled.."
newline
bitfld.long 0x0 14. "SRCBURSTWRAP,Source Burst Wrap. When enabled  the source data address for the DMA is 'wrapped'  meaning that the source address range for each burst will be the same. As an example  this could be used to read several sequential registers from a.." "0: Disabled. Source burst wrapping is not enabled..,1: Enabled. Source burst wrapping is enabled for.."
hexmask.long.byte 0x0 8.--11. 1. "BURSTPOWER,Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1  Burst.."
newline
bitfld.long 0x0 6. "TRIGBURST,Trigger Burst. Selects whether hardware triggers cause a single or burst transfer." "0: Single transfer. Hardware trigger causes a..,1: Burst transfer. When the trigger for this.."
bitfld.long 0x0 5. "TRIGTYPE,Trigger Type. Selects hardware trigger as edge triggered or level triggered." "0: Edge. Hardware trigger is edge triggered.,1: Level. Hardware trigger is level triggered. Note.."
newline
bitfld.long 0x0 4. "TRIGPOL,Trigger Polarity. Selects the polarity of a hardware trigger for this channel." "0: Active low - falling edge. Hardware trigger is..,1: Active high - rising edge. Hardware trigger is.."
bitfld.long 0x0 1. "HWTRIGEN,Hardware Triggering Enable for this channel." "0: Disabled. Hardware triggering is not used.,1: Enabled. Use hardware triggering."
newline
bitfld.long 0x0 0. "PERIPHREQEN,Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move  any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller." "0: Disabled. Peripheral DMA requests are disabled.,1: Enabled. Peripheral DMA requests are enabled."
rgroup.long ($2+0x4)++0x3
line.long 0x0 "CTLSTAT,Control and status register for DMA channel ."
bitfld.long 0x0 2. "TRIG,Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1." "0: Not triggered. The trigger for this DMA channel..,1: Triggered. The trigger for this DMA channel is.."
bitfld.long 0x0 0. "VALIDPENDING,Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel." "0: No effect. No effect on DMA operation.,1: Valid pending."
group.long ($2+0x8)++0x3
line.long 0x0 "XFERCFG,Transfer configuration register for DMA channel ."
hexmask.long.word 0x0 16.--25. 1. "XFERCOUNT,Total number of transfers to be performed  minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence  it cannot.."
bitfld.long 0x0 14.--15. "DSTINC,Determines whether the destination address is incremented for each DMA transfer." "0: No increment. The destination address is not..,1: 1 x width. The destination address is..,2: 2 x width. The destination address is..,3: 4 x width. The destination address is.."
newline
bitfld.long 0x0 12.--13. "SRCINC,Determines whether the source address is incremented for each DMA transfer." "0: No increment. The source address is not..,1: 1 x width. The source address is incremented by..,2: 2 x width. The source address is incremented by..,3: 4 x width. The source address is incremented by.."
bitfld.long 0x0 8.--9. "WIDTH,Transfer width used for this DMA channel." "0: 8-bit. 8-bit transfers are performed (8-bit..,1: 16-bit. 6-bit transfers are performed (16-bit..,2: 32-bit. 32-bit transfers are performed (32-bit..,?"
newline
bitfld.long 0x0 5. "SETINTB,Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention  interrupt A may be used when only one interrupt flag is.." "0: No effect.,1: Set. The INTB flag for this channel will be set.."
bitfld.long 0x0 4. "SETINTA,Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention  interrupt A may be used when only one interrupt flag is.." "0: No effect.,1: Set. The INTA flag for this channel will be set.."
newline
bitfld.long 0x0 3. "CLRTRIG,Clear Trigger." "0: Not cleared. The trigger is not cleared when..,1: Cleared. The trigger is cleared when this.."
bitfld.long 0x0 2. "SWTRIG,Software Trigger." "0: Not set. When written by software the trigger..,1: Set. When written by software the trigger for.."
newline
bitfld.long 0x0 1. "RELOAD,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers." "0: Disabled. Do not reload the channels' control..,1: Enabled. Reload the channels' control structure.."
bitfld.long 0x0 0. "CFGVALID,Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon  if all other activation criteria are fulfilled." "0: Not valid. The channel descriptor is not..,1: Valid. The current channel descriptor is.."
tree.end
repeat.end
endif
sif (cpuis("LPC54102*"))
repeat 6. (list 0x10 0x11 0x12 0x13 0x14 0x15)(list ad:0x1C004500 ad:0x1C004510 ad:0x1C004520 ad:0x1C004530 ad:0x1C004540 ad:0x1C004550)
tree "CHANNEL[$1]"
base $2
group.long ($2)++0x3
line.long 0x0 "CFG,Configuration register for DMA channel ."
bitfld.long 0x0 16.--18. "CHPRIORITY,Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported: 0x0 = highest priority. 0x7 = lowest priority." "0: highest priority,?,?,?,?,?,?,7: lowest priority"
bitfld.long 0x0 15. "DSTBURSTWRAP,Destination Burst Wrap. When enabled  the destination data address for the DMA is 'wrapped'  meaning that the destination address range for each burst will be the same. As an example  this could be used to write several sequential registers.." "0: Disabled. Destination burst wrapping is not..,1: Enabled. Destination burst wrapping is enabled.."
newline
bitfld.long 0x0 14. "SRCBURSTWRAP,Source Burst Wrap. When enabled  the source data address for the DMA is 'wrapped'  meaning that the source address range for each burst will be the same. As an example  this could be used to read several sequential registers from a.." "0: Disabled. Source burst wrapping is not enabled..,1: Enabled. Source burst wrapping is enabled for.."
hexmask.long.byte 0x0 8.--11. 1. "BURSTPOWER,Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1  Burst.."
newline
bitfld.long 0x0 6. "TRIGBURST,Trigger Burst. Selects whether hardware triggers cause a single or burst transfer." "0: Single transfer. Hardware trigger causes a..,1: Burst transfer. When the trigger for this.."
bitfld.long 0x0 5. "TRIGTYPE,Trigger Type. Selects hardware trigger as edge triggered or level triggered." "0: Edge. Hardware trigger is edge triggered.,1: Level. Hardware trigger is level triggered. Note.."
newline
bitfld.long 0x0 4. "TRIGPOL,Trigger Polarity. Selects the polarity of a hardware trigger for this channel." "0: Active low - falling edge. Hardware trigger is..,1: Active high - rising edge. Hardware trigger is.."
bitfld.long 0x0 1. "HWTRIGEN,Hardware Triggering Enable for this channel." "0: Disabled. Hardware triggering is not used.,1: Enabled. Use hardware triggering."
newline
bitfld.long 0x0 0. "PERIPHREQEN,Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move  any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller." "0: Disabled. Peripheral DMA requests are disabled.,1: Enabled. Peripheral DMA requests are enabled."
rgroup.long ($2+0x4)++0x3
line.long 0x0 "CTLSTAT,Control and status register for DMA channel ."
bitfld.long 0x0 2. "TRIG,Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1." "0: Not triggered. The trigger for this DMA channel..,1: Triggered. The trigger for this DMA channel is.."
bitfld.long 0x0 0. "VALIDPENDING,Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel." "0: No effect. No effect on DMA operation.,1: Valid pending."
group.long ($2+0x8)++0x3
line.long 0x0 "XFERCFG,Transfer configuration register for DMA channel ."
hexmask.long.word 0x0 16.--25. 1. "XFERCOUNT,Total number of transfers to be performed  minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence  it cannot.."
bitfld.long 0x0 14.--15. "DSTINC,Determines whether the destination address is incremented for each DMA transfer." "0: No increment. The destination address is not..,1: 1 x width. The destination address is..,2: 2 x width. The destination address is..,3: 4 x width. The destination address is.."
newline
bitfld.long 0x0 12.--13. "SRCINC,Determines whether the source address is incremented for each DMA transfer." "0: No increment. The source address is not..,1: 1 x width. The source address is incremented by..,2: 2 x width. The source address is incremented by..,3: 4 x width. The source address is incremented by.."
bitfld.long 0x0 8.--9. "WIDTH,Transfer width used for this DMA channel." "0: 8-bit. 8-bit transfers are performed (8-bit..,1: 16-bit. 6-bit transfers are performed (16-bit..,2: 32-bit. 32-bit transfers are performed (32-bit..,?"
newline
bitfld.long 0x0 5. "SETINTB,Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention  interrupt A may be used when only one interrupt flag is.." "0: No effect.,1: Set. The INTB flag for this channel will be set.."
bitfld.long 0x0 4. "SETINTA,Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention  interrupt A may be used when only one interrupt flag is.." "0: No effect.,1: Set. The INTA flag for this channel will be set.."
newline
bitfld.long 0x0 3. "CLRTRIG,Clear Trigger." "0: Not cleared. The trigger is not cleared when..,1: Cleared. The trigger is cleared when this.."
bitfld.long 0x0 2. "SWTRIG,Software Trigger." "0: Not set. When written by software the trigger..,1: Set. When written by software the trigger for.."
newline
bitfld.long 0x0 1. "RELOAD,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers." "0: Disabled. Do not reload the channels' control..,1: Enabled. Reload the channels' control structure.."
bitfld.long 0x0 0. "CFGVALID,Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon  if all other activation criteria are fulfilled." "0: Not valid. The channel descriptor is not..,1: Valid. The current channel descriptor is.."
tree.end
repeat.end
endif
sif (cpuis("LPC54113*"))
repeat 4. (list 0x10 0x11 0x12 0x13)(list ad:0x40082500 ad:0x40082510 ad:0x40082520 ad:0x40082530)
tree "CHANNEL[$1]"
base $2
group.long ($2)++0x3
line.long 0x0 "CFG,Configuration register for DMA channel ."
bitfld.long 0x0 16.--18. "CHPRIORITY,Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported: 0x0 = highest priority. 0x7 = lowest priority." "0: highest priority,?,?,?,?,?,?,7: lowest priority"
bitfld.long 0x0 15. "DSTBURSTWRAP,Destination Burst Wrap. When enabled  the destination data address for the DMA is 'wrapped'  meaning that the destination address range for each burst will be the same. As an example  this could be used to write several sequential registers.." "0: Disabled. Destination burst wrapping is not..,1: Enabled. Destination burst wrapping is enabled.."
newline
bitfld.long 0x0 14. "SRCBURSTWRAP,Source Burst Wrap. When enabled  the source data address for the DMA is 'wrapped'  meaning that the source address range for each burst will be the same. As an example  this could be used to read several sequential registers from a.." "0: Disabled. Source burst wrapping is not enabled..,1: Enabled. Source burst wrapping is enabled for.."
hexmask.long.byte 0x0 8.--11. 1. "BURSTPOWER,Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1  Burst.."
newline
bitfld.long 0x0 6. "TRIGBURST,Trigger Burst. Selects whether hardware triggers cause a single or burst transfer." "0: Single transfer. Hardware trigger causes a..,1: Burst transfer. When the trigger for this.."
bitfld.long 0x0 5. "TRIGTYPE,Trigger Type. Selects hardware trigger as edge triggered or level triggered." "0: Edge. Hardware trigger is edge triggered.,1: Level. Hardware trigger is level triggered. Note.."
newline
bitfld.long 0x0 4. "TRIGPOL,Trigger Polarity. Selects the polarity of a hardware trigger for this channel." "0: Active low - falling edge. Hardware trigger is..,1: Active high - rising edge. Hardware trigger is.."
bitfld.long 0x0 1. "HWTRIGEN,Hardware Triggering Enable for this channel." "0: Disabled. Hardware triggering is not used.,1: Enabled. Use hardware triggering."
newline
bitfld.long 0x0 0. "PERIPHREQEN,Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move  any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller." "0: Disabled. Peripheral DMA requests are disabled.,1: Enabled. Peripheral DMA requests are enabled."
rgroup.long ($2+0x4)++0x3
line.long 0x0 "CTLSTAT,Control and status register for DMA channel ."
bitfld.long 0x0 2. "TRIG,Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1." "0: Not triggered. The trigger for this DMA channel..,1: Triggered. The trigger for this DMA channel is.."
bitfld.long 0x0 0. "VALIDPENDING,Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel." "0: No effect. No effect on DMA operation.,1: Valid pending."
group.long ($2+0x8)++0x3
line.long 0x0 "XFERCFG,Transfer configuration register for DMA channel ."
hexmask.long.word 0x0 16.--25. 1. "XFERCOUNT,Total number of transfers to be performed  minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence  it cannot.."
bitfld.long 0x0 14.--15. "DSTINC,Determines whether the destination address is incremented for each DMA transfer." "0: No increment. The destination address is not..,1: 1 x width. The destination address is..,2: 2 x width. The destination address is..,3: 4 x width. The destination address is.."
newline
bitfld.long 0x0 12.--13. "SRCINC,Determines whether the source address is incremented for each DMA transfer." "0: No increment. The source address is not..,1: 1 x width. The source address is incremented by..,2: 2 x width. The source address is incremented by..,3: 4 x width. The source address is incremented by.."
bitfld.long 0x0 8.--9. "WIDTH,Transfer width used for this DMA channel." "0: 8-bit. 8-bit transfers are performed (8-bit..,1: 16-bit. 6-bit transfers are performed (16-bit..,2: 32-bit. 32-bit transfers are performed (32-bit..,?"
newline
bitfld.long 0x0 5. "SETINTB,Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention  interrupt A may be used when only one interrupt flag is.." "0: No effect.,1: Set. The INTB flag for this channel will be set.."
bitfld.long 0x0 4. "SETINTA,Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention  interrupt A may be used when only one interrupt flag is.." "0: No effect.,1: Set. The INTA flag for this channel will be set.."
newline
bitfld.long 0x0 3. "CLRTRIG,Clear Trigger." "0: Not cleared. The trigger is not cleared when..,1: Cleared. The trigger is cleared when this.."
bitfld.long 0x0 2. "SWTRIG,Software Trigger." "0: Not set. When written by software the trigger..,1: Set. When written by software the trigger for.."
newline
bitfld.long 0x0 1. "RELOAD,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers." "0: Disabled. Do not reload the channels' control..,1: Enabled. Reload the channels' control structure.."
bitfld.long 0x0 0. "CFGVALID,Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon  if all other activation criteria are fulfilled." "0: Not valid. The channel descriptor is not..,1: Valid. The current channel descriptor is.."
tree.end
repeat.end
endif
sif (cpuis("LPC54114*"))
repeat 4. (list 0x10 0x11 0x12 0x13)(list ad:0x40082500 ad:0x40082510 ad:0x40082520 ad:0x40082530)
tree "CHANNEL[$1]"
base $2
group.long ($2)++0x3
line.long 0x0 "CFG,Configuration register for DMA channel ."
bitfld.long 0x0 16.--18. "CHPRIORITY,Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported: 0x0 = highest priority. 0x7 = lowest priority." "0: highest priority,?,?,?,?,?,?,7: lowest priority"
bitfld.long 0x0 15. "DSTBURSTWRAP,Destination Burst Wrap. When enabled  the destination data address for the DMA is 'wrapped'  meaning that the destination address range for each burst will be the same. As an example  this could be used to write several sequential registers.." "0: Disabled. Destination burst wrapping is not..,1: Enabled. Destination burst wrapping is enabled.."
newline
bitfld.long 0x0 14. "SRCBURSTWRAP,Source Burst Wrap. When enabled  the source data address for the DMA is 'wrapped'  meaning that the source address range for each burst will be the same. As an example  this could be used to read several sequential registers from a.." "0: Disabled. Source burst wrapping is not enabled..,1: Enabled. Source burst wrapping is enabled for.."
hexmask.long.byte 0x0 8.--11. 1. "BURSTPOWER,Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1  Burst.."
newline
bitfld.long 0x0 6. "TRIGBURST,Trigger Burst. Selects whether hardware triggers cause a single or burst transfer." "0: Single transfer. Hardware trigger causes a..,1: Burst transfer. When the trigger for this.."
bitfld.long 0x0 5. "TRIGTYPE,Trigger Type. Selects hardware trigger as edge triggered or level triggered." "0: Edge. Hardware trigger is edge triggered.,1: Level. Hardware trigger is level triggered. Note.."
newline
bitfld.long 0x0 4. "TRIGPOL,Trigger Polarity. Selects the polarity of a hardware trigger for this channel." "0: Active low - falling edge. Hardware trigger is..,1: Active high - rising edge. Hardware trigger is.."
bitfld.long 0x0 1. "HWTRIGEN,Hardware Triggering Enable for this channel." "0: Disabled. Hardware triggering is not used.,1: Enabled. Use hardware triggering."
newline
bitfld.long 0x0 0. "PERIPHREQEN,Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move  any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller." "0: Disabled. Peripheral DMA requests are disabled.,1: Enabled. Peripheral DMA requests are enabled."
rgroup.long ($2+0x4)++0x3
line.long 0x0 "CTLSTAT,Control and status register for DMA channel ."
bitfld.long 0x0 2. "TRIG,Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1." "0: Not triggered. The trigger for this DMA channel..,1: Triggered. The trigger for this DMA channel is.."
bitfld.long 0x0 0. "VALIDPENDING,Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel." "0: No effect. No effect on DMA operation.,1: Valid pending."
group.long ($2+0x8)++0x3
line.long 0x0 "XFERCFG,Transfer configuration register for DMA channel ."
hexmask.long.word 0x0 16.--25. 1. "XFERCOUNT,Total number of transfers to be performed  minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence  it cannot.."
bitfld.long 0x0 14.--15. "DSTINC,Determines whether the destination address is incremented for each DMA transfer." "0: No increment. The destination address is not..,1: 1 x width. The destination address is..,2: 2 x width. The destination address is..,3: 4 x width. The destination address is.."
newline
bitfld.long 0x0 12.--13. "SRCINC,Determines whether the source address is incremented for each DMA transfer." "0: No increment. The source address is not..,1: 1 x width. The source address is incremented by..,2: 2 x width. The source address is incremented by..,3: 4 x width. The source address is incremented by.."
bitfld.long 0x0 8.--9. "WIDTH,Transfer width used for this DMA channel." "0: 8-bit. 8-bit transfers are performed (8-bit..,1: 16-bit. 6-bit transfers are performed (16-bit..,2: 32-bit. 32-bit transfers are performed (32-bit..,?"
newline
bitfld.long 0x0 5. "SETINTB,Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention  interrupt A may be used when only one interrupt flag is.." "0: No effect.,1: Set. The INTB flag for this channel will be set.."
bitfld.long 0x0 4. "SETINTA,Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention  interrupt A may be used when only one interrupt flag is.." "0: No effect.,1: Set. The INTA flag for this channel will be set.."
newline
bitfld.long 0x0 3. "CLRTRIG,Clear Trigger." "0: Not cleared. The trigger is not cleared when..,1: Cleared. The trigger is cleared when this.."
bitfld.long 0x0 2. "SWTRIG,Software Trigger." "0: Not set. When written by software the trigger..,1: Set. When written by software the trigger for.."
newline
bitfld.long 0x0 1. "RELOAD,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers." "0: Disabled. Do not reload the channels' control..,1: Enabled. Reload the channels' control structure.."
bitfld.long 0x0 0. "CFGVALID,Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon  if all other activation criteria are fulfilled." "0: Not valid. The channel descriptor is not..,1: Valid. The current channel descriptor is.."
tree.end
repeat.end
endif
sif (cpuis("LPC54605*"))
repeat 14. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D)(list ad:0x40082500 ad:0x40082510 ad:0x40082520 ad:0x40082530 ad:0x40082540 ad:0x40082550 ad:0x40082560 ad:0x40082570 ad:0x40082580 ad:0x40082590 ad:0x400825A0 ad:0x400825B0 ad:0x400825C0 ad:0x400825D0)
tree "CHANNEL[$1]"
base $2
group.long ($2)++0x3
line.long 0x0 "CFG,Configuration register for DMA channel ."
bitfld.long 0x0 16.--18. "CHPRIORITY,Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported: 0x0 = highest priority. 0x7 = lowest priority." "0: highest priority,?,?,?,?,?,?,7: lowest priority"
bitfld.long 0x0 15. "DSTBURSTWRAP,Destination Burst Wrap. When enabled  the destination data address for the DMA is 'wrapped'  meaning that the destination address range for each burst will be the same. As an example  this could be used to write several sequential registers.." "0: Disabled. Destination burst wrapping is not..,1: Enabled. Destination burst wrapping is enabled.."
newline
bitfld.long 0x0 14. "SRCBURSTWRAP,Source Burst Wrap. When enabled  the source data address for the DMA is 'wrapped'  meaning that the source address range for each burst will be the same. As an example  this could be used to read several sequential registers from a.." "0: Disabled. Source burst wrapping is not enabled..,1: Enabled. Source burst wrapping is enabled for.."
hexmask.long.byte 0x0 8.--11. 1. "BURSTPOWER,Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1  Burst.."
newline
bitfld.long 0x0 6. "TRIGBURST,Trigger Burst. Selects whether hardware triggers cause a single or burst transfer." "0: Single transfer. Hardware trigger causes a..,1: Burst transfer. When the trigger for this.."
bitfld.long 0x0 5. "TRIGTYPE,Trigger Type. Selects hardware trigger as edge triggered or level triggered." "0: Edge. Hardware trigger is edge triggered.,1: Level. Hardware trigger is level triggered. Note.."
newline
bitfld.long 0x0 4. "TRIGPOL,Trigger Polarity. Selects the polarity of a hardware trigger for this channel." "0: Active low - falling edge. Hardware trigger is..,1: Active high - rising edge. Hardware trigger is.."
bitfld.long 0x0 1. "HWTRIGEN,Hardware Triggering Enable for this channel." "0: Disabled. Hardware triggering is not used.,1: Enabled. Use hardware triggering."
newline
bitfld.long 0x0 0. "PERIPHREQEN,Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move  any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller." "0: Disabled. Peripheral DMA requests are disabled.,1: Enabled. Peripheral DMA requests are enabled."
rgroup.long ($2+0x4)++0x3
line.long 0x0 "CTLSTAT,Control and status register for DMA channel ."
bitfld.long 0x0 2. "TRIG,Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1." "0: Not triggered. The trigger for this DMA channel..,1: Triggered. The trigger for this DMA channel is.."
bitfld.long 0x0 0. "VALIDPENDING,Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel." "0: No effect. No effect on DMA operation.,1: Valid pending."
group.long ($2+0x8)++0x3
line.long 0x0 "XFERCFG,Transfer configuration register for DMA channel ."
hexmask.long.word 0x0 16.--25. 1. "XFERCOUNT,Total number of transfers to be performed  minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence  it cannot.."
bitfld.long 0x0 14.--15. "DSTINC,Determines whether the destination address is incremented for each DMA transfer." "0: No increment. The destination address is not..,1: 1 x width. The destination address is..,2: 2 x width. The destination address is..,3: 4 x width. The destination address is.."
newline
bitfld.long 0x0 12.--13. "SRCINC,Determines whether the source address is incremented for each DMA transfer." "0: No increment. The source address is not..,1: 1 x width. The source address is incremented by..,2: 2 x width. The source address is incremented by..,3: 4 x width. The source address is incremented by.."
bitfld.long 0x0 8.--9. "WIDTH,Transfer width used for this DMA channel." "0: 8-bit. 8-bit transfers are performed (8-bit..,1: 16-bit. 6-bit transfers are performed (16-bit..,2: 32-bit. 32-bit transfers are performed (32-bit..,?"
newline
bitfld.long 0x0 5. "SETINTB,Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention  interrupt A may be used when only one interrupt flag is.." "0: No effect.,1: Set. The INTB flag for this channel will be set.."
bitfld.long 0x0 4. "SETINTA,Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention  interrupt A may be used when only one interrupt flag is.." "0: No effect.,1: Set. The INTA flag for this channel will be set.."
newline
bitfld.long 0x0 3. "CLRTRIG,Clear Trigger." "0: Not cleared. The trigger is not cleared when..,1: Cleared. The trigger is cleared when this.."
bitfld.long 0x0 2. "SWTRIG,Software Trigger." "0: Not set. When written by software the trigger..,1: Set. When written by software the trigger for.."
newline
bitfld.long 0x0 1. "RELOAD,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers." "0: Disabled. Do not reload the channels' control..,1: Enabled. Reload the channels' control structure.."
bitfld.long 0x0 0. "CFGVALID,Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon  if all other activation criteria are fulfilled." "0: Not valid. The channel descriptor is not..,1: Valid. The current channel descriptor is.."
tree.end
repeat.end
endif
sif (cpuis("LPC54606*"))
repeat 14. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D)(list ad:0x40082500 ad:0x40082510 ad:0x40082520 ad:0x40082530 ad:0x40082540 ad:0x40082550 ad:0x40082560 ad:0x40082570 ad:0x40082580 ad:0x40082590 ad:0x400825A0 ad:0x400825B0 ad:0x400825C0 ad:0x400825D0)
tree "CHANNEL[$1]"
base $2
group.long ($2)++0x3
line.long 0x0 "CFG,Configuration register for DMA channel ."
bitfld.long 0x0 16.--18. "CHPRIORITY,Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported: 0x0 = highest priority. 0x7 = lowest priority." "0: highest priority,?,?,?,?,?,?,7: lowest priority"
bitfld.long 0x0 15. "DSTBURSTWRAP,Destination Burst Wrap. When enabled  the destination data address for the DMA is 'wrapped'  meaning that the destination address range for each burst will be the same. As an example  this could be used to write several sequential registers.." "0: Disabled. Destination burst wrapping is not..,1: Enabled. Destination burst wrapping is enabled.."
newline
bitfld.long 0x0 14. "SRCBURSTWRAP,Source Burst Wrap. When enabled  the source data address for the DMA is 'wrapped'  meaning that the source address range for each burst will be the same. As an example  this could be used to read several sequential registers from a.." "0: Disabled. Source burst wrapping is not enabled..,1: Enabled. Source burst wrapping is enabled for.."
hexmask.long.byte 0x0 8.--11. 1. "BURSTPOWER,Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1  Burst.."
newline
bitfld.long 0x0 6. "TRIGBURST,Trigger Burst. Selects whether hardware triggers cause a single or burst transfer." "0: Single transfer. Hardware trigger causes a..,1: Burst transfer. When the trigger for this.."
bitfld.long 0x0 5. "TRIGTYPE,Trigger Type. Selects hardware trigger as edge triggered or level triggered." "0: Edge. Hardware trigger is edge triggered.,1: Level. Hardware trigger is level triggered. Note.."
newline
bitfld.long 0x0 4. "TRIGPOL,Trigger Polarity. Selects the polarity of a hardware trigger for this channel." "0: Active low - falling edge. Hardware trigger is..,1: Active high - rising edge. Hardware trigger is.."
bitfld.long 0x0 1. "HWTRIGEN,Hardware Triggering Enable for this channel." "0: Disabled. Hardware triggering is not used.,1: Enabled. Use hardware triggering."
newline
bitfld.long 0x0 0. "PERIPHREQEN,Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move  any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller." "0: Disabled. Peripheral DMA requests are disabled.,1: Enabled. Peripheral DMA requests are enabled."
rgroup.long ($2+0x4)++0x3
line.long 0x0 "CTLSTAT,Control and status register for DMA channel ."
bitfld.long 0x0 2. "TRIG,Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1." "0: Not triggered. The trigger for this DMA channel..,1: Triggered. The trigger for this DMA channel is.."
bitfld.long 0x0 0. "VALIDPENDING,Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel." "0: No effect. No effect on DMA operation.,1: Valid pending."
group.long ($2+0x8)++0x3
line.long 0x0 "XFERCFG,Transfer configuration register for DMA channel ."
hexmask.long.word 0x0 16.--25. 1. "XFERCOUNT,Total number of transfers to be performed  minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence  it cannot.."
bitfld.long 0x0 14.--15. "DSTINC,Determines whether the destination address is incremented for each DMA transfer." "0: No increment. The destination address is not..,1: 1 x width. The destination address is..,2: 2 x width. The destination address is..,3: 4 x width. The destination address is.."
newline
bitfld.long 0x0 12.--13. "SRCINC,Determines whether the source address is incremented for each DMA transfer." "0: No increment. The source address is not..,1: 1 x width. The source address is incremented by..,2: 2 x width. The source address is incremented by..,3: 4 x width. The source address is incremented by.."
bitfld.long 0x0 8.--9. "WIDTH,Transfer width used for this DMA channel." "0: 8-bit. 8-bit transfers are performed (8-bit..,1: 16-bit. 6-bit transfers are performed (16-bit..,2: 32-bit. 32-bit transfers are performed (32-bit..,?"
newline
bitfld.long 0x0 5. "SETINTB,Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention  interrupt A may be used when only one interrupt flag is.." "0: No effect.,1: Set. The INTB flag for this channel will be set.."
bitfld.long 0x0 4. "SETINTA,Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention  interrupt A may be used when only one interrupt flag is.." "0: No effect.,1: Set. The INTA flag for this channel will be set.."
newline
bitfld.long 0x0 3. "CLRTRIG,Clear Trigger." "0: Not cleared. The trigger is not cleared when..,1: Cleared. The trigger is cleared when this.."
bitfld.long 0x0 2. "SWTRIG,Software Trigger." "0: Not set. When written by software the trigger..,1: Set. When written by software the trigger for.."
newline
bitfld.long 0x0 1. "RELOAD,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers." "0: Disabled. Do not reload the channels' control..,1: Enabled. Reload the channels' control structure.."
bitfld.long 0x0 0. "CFGVALID,Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon  if all other activation criteria are fulfilled." "0: Not valid. The channel descriptor is not..,1: Valid. The current channel descriptor is.."
tree.end
repeat.end
endif
sif (cpuis("LPC54607*"))
repeat 14. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D)(list ad:0x40082500 ad:0x40082510 ad:0x40082520 ad:0x40082530 ad:0x40082540 ad:0x40082550 ad:0x40082560 ad:0x40082570 ad:0x40082580 ad:0x40082590 ad:0x400825A0 ad:0x400825B0 ad:0x400825C0 ad:0x400825D0)
tree "CHANNEL[$1]"
base $2
group.long ($2)++0x3
line.long 0x0 "CFG,Configuration register for DMA channel ."
bitfld.long 0x0 16.--18. "CHPRIORITY,Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported: 0x0 = highest priority. 0x7 = lowest priority." "0: highest priority,?,?,?,?,?,?,7: lowest priority"
bitfld.long 0x0 15. "DSTBURSTWRAP,Destination Burst Wrap. When enabled  the destination data address for the DMA is 'wrapped'  meaning that the destination address range for each burst will be the same. As an example  this could be used to write several sequential registers.." "0: Disabled. Destination burst wrapping is not..,1: Enabled. Destination burst wrapping is enabled.."
newline
bitfld.long 0x0 14. "SRCBURSTWRAP,Source Burst Wrap. When enabled  the source data address for the DMA is 'wrapped'  meaning that the source address range for each burst will be the same. As an example  this could be used to read several sequential registers from a.." "0: Disabled. Source burst wrapping is not enabled..,1: Enabled. Source burst wrapping is enabled for.."
hexmask.long.byte 0x0 8.--11. 1. "BURSTPOWER,Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1  Burst.."
newline
bitfld.long 0x0 6. "TRIGBURST,Trigger Burst. Selects whether hardware triggers cause a single or burst transfer." "0: Single transfer. Hardware trigger causes a..,1: Burst transfer. When the trigger for this.."
bitfld.long 0x0 5. "TRIGTYPE,Trigger Type. Selects hardware trigger as edge triggered or level triggered." "0: Edge. Hardware trigger is edge triggered.,1: Level. Hardware trigger is level triggered. Note.."
newline
bitfld.long 0x0 4. "TRIGPOL,Trigger Polarity. Selects the polarity of a hardware trigger for this channel." "0: Active low - falling edge. Hardware trigger is..,1: Active high - rising edge. Hardware trigger is.."
bitfld.long 0x0 1. "HWTRIGEN,Hardware Triggering Enable for this channel." "0: Disabled. Hardware triggering is not used.,1: Enabled. Use hardware triggering."
newline
bitfld.long 0x0 0. "PERIPHREQEN,Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move  any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller." "0: Disabled. Peripheral DMA requests are disabled.,1: Enabled. Peripheral DMA requests are enabled."
rgroup.long ($2+0x4)++0x3
line.long 0x0 "CTLSTAT,Control and status register for DMA channel ."
bitfld.long 0x0 2. "TRIG,Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1." "0: Not triggered. The trigger for this DMA channel..,1: Triggered. The trigger for this DMA channel is.."
bitfld.long 0x0 0. "VALIDPENDING,Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel." "0: No effect. No effect on DMA operation.,1: Valid pending."
group.long ($2+0x8)++0x3
line.long 0x0 "XFERCFG,Transfer configuration register for DMA channel ."
hexmask.long.word 0x0 16.--25. 1. "XFERCOUNT,Total number of transfers to be performed  minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence  it cannot.."
bitfld.long 0x0 14.--15. "DSTINC,Determines whether the destination address is incremented for each DMA transfer." "0: No increment. The destination address is not..,1: 1 x width. The destination address is..,2: 2 x width. The destination address is..,3: 4 x width. The destination address is.."
newline
bitfld.long 0x0 12.--13. "SRCINC,Determines whether the source address is incremented for each DMA transfer." "0: No increment. The source address is not..,1: 1 x width. The source address is incremented by..,2: 2 x width. The source address is incremented by..,3: 4 x width. The source address is incremented by.."
bitfld.long 0x0 8.--9. "WIDTH,Transfer width used for this DMA channel." "0: 8-bit. 8-bit transfers are performed (8-bit..,1: 16-bit. 6-bit transfers are performed (16-bit..,2: 32-bit. 32-bit transfers are performed (32-bit..,?"
newline
bitfld.long 0x0 5. "SETINTB,Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention  interrupt A may be used when only one interrupt flag is.." "0: No effect.,1: Set. The INTB flag for this channel will be set.."
bitfld.long 0x0 4. "SETINTA,Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention  interrupt A may be used when only one interrupt flag is.." "0: No effect.,1: Set. The INTA flag for this channel will be set.."
newline
bitfld.long 0x0 3. "CLRTRIG,Clear Trigger." "0: Not cleared. The trigger is not cleared when..,1: Cleared. The trigger is cleared when this.."
bitfld.long 0x0 2. "SWTRIG,Software Trigger." "0: Not set. When written by software the trigger..,1: Set. When written by software the trigger for.."
newline
bitfld.long 0x0 1. "RELOAD,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers." "0: Disabled. Do not reload the channels' control..,1: Enabled. Reload the channels' control structure.."
bitfld.long 0x0 0. "CFGVALID,Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon  if all other activation criteria are fulfilled." "0: Not valid. The channel descriptor is not..,1: Valid. The current channel descriptor is.."
tree.end
repeat.end
endif
sif (cpuis("LPC54608*"))
repeat 14. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D)(list ad:0x40082500 ad:0x40082510 ad:0x40082520 ad:0x40082530 ad:0x40082540 ad:0x40082550 ad:0x40082560 ad:0x40082570 ad:0x40082580 ad:0x40082590 ad:0x400825A0 ad:0x400825B0 ad:0x400825C0 ad:0x400825D0)
tree "CHANNEL[$1]"
base $2
group.long ($2)++0x3
line.long 0x0 "CFG,Configuration register for DMA channel ."
bitfld.long 0x0 16.--18. "CHPRIORITY,Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported: 0x0 = highest priority. 0x7 = lowest priority." "0: highest priority,?,?,?,?,?,?,7: lowest priority"
bitfld.long 0x0 15. "DSTBURSTWRAP,Destination Burst Wrap. When enabled  the destination data address for the DMA is 'wrapped'  meaning that the destination address range for each burst will be the same. As an example  this could be used to write several sequential registers.." "0: Disabled. Destination burst wrapping is not..,1: Enabled. Destination burst wrapping is enabled.."
newline
bitfld.long 0x0 14. "SRCBURSTWRAP,Source Burst Wrap. When enabled  the source data address for the DMA is 'wrapped'  meaning that the source address range for each burst will be the same. As an example  this could be used to read several sequential registers from a.." "0: Disabled. Source burst wrapping is not enabled..,1: Enabled. Source burst wrapping is enabled for.."
hexmask.long.byte 0x0 8.--11. 1. "BURSTPOWER,Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1  Burst.."
newline
bitfld.long 0x0 6. "TRIGBURST,Trigger Burst. Selects whether hardware triggers cause a single or burst transfer." "0: Single transfer. Hardware trigger causes a..,1: Burst transfer. When the trigger for this.."
bitfld.long 0x0 5. "TRIGTYPE,Trigger Type. Selects hardware trigger as edge triggered or level triggered." "0: Edge. Hardware trigger is edge triggered.,1: Level. Hardware trigger is level triggered. Note.."
newline
bitfld.long 0x0 4. "TRIGPOL,Trigger Polarity. Selects the polarity of a hardware trigger for this channel." "0: Active low - falling edge. Hardware trigger is..,1: Active high - rising edge. Hardware trigger is.."
bitfld.long 0x0 1. "HWTRIGEN,Hardware Triggering Enable for this channel." "0: Disabled. Hardware triggering is not used.,1: Enabled. Use hardware triggering."
newline
bitfld.long 0x0 0. "PERIPHREQEN,Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move  any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller." "0: Disabled. Peripheral DMA requests are disabled.,1: Enabled. Peripheral DMA requests are enabled."
rgroup.long ($2+0x4)++0x3
line.long 0x0 "CTLSTAT,Control and status register for DMA channel ."
bitfld.long 0x0 2. "TRIG,Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1." "0: Not triggered. The trigger for this DMA channel..,1: Triggered. The trigger for this DMA channel is.."
bitfld.long 0x0 0. "VALIDPENDING,Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel." "0: No effect. No effect on DMA operation.,1: Valid pending."
group.long ($2+0x8)++0x3
line.long 0x0 "XFERCFG,Transfer configuration register for DMA channel ."
hexmask.long.word 0x0 16.--25. 1. "XFERCOUNT,Total number of transfers to be performed  minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence  it cannot.."
bitfld.long 0x0 14.--15. "DSTINC,Determines whether the destination address is incremented for each DMA transfer." "0: No increment. The destination address is not..,1: 1 x width. The destination address is..,2: 2 x width. The destination address is..,3: 4 x width. The destination address is.."
newline
bitfld.long 0x0 12.--13. "SRCINC,Determines whether the source address is incremented for each DMA transfer." "0: No increment. The source address is not..,1: 1 x width. The source address is incremented by..,2: 2 x width. The source address is incremented by..,3: 4 x width. The source address is incremented by.."
bitfld.long 0x0 8.--9. "WIDTH,Transfer width used for this DMA channel." "0: 8-bit. 8-bit transfers are performed (8-bit..,1: 16-bit. 6-bit transfers are performed (16-bit..,2: 32-bit. 32-bit transfers are performed (32-bit..,?"
newline
bitfld.long 0x0 5. "SETINTB,Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention  interrupt A may be used when only one interrupt flag is.." "0: No effect.,1: Set. The INTB flag for this channel will be set.."
bitfld.long 0x0 4. "SETINTA,Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention  interrupt A may be used when only one interrupt flag is.." "0: No effect.,1: Set. The INTA flag for this channel will be set.."
newline
bitfld.long 0x0 3. "CLRTRIG,Clear Trigger." "0: Not cleared. The trigger is not cleared when..,1: Cleared. The trigger is cleared when this.."
bitfld.long 0x0 2. "SWTRIG,Software Trigger." "0: Not set. When written by software the trigger..,1: Set. When written by software the trigger for.."
newline
bitfld.long 0x0 1. "RELOAD,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers." "0: Disabled. Do not reload the channels' control..,1: Enabled. Reload the channels' control structure.."
bitfld.long 0x0 0. "CFGVALID,Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon  if all other activation criteria are fulfilled." "0: Not valid. The channel descriptor is not..,1: Valid. The current channel descriptor is.."
tree.end
repeat.end
endif
sif (cpuis("LPC54616*"))
repeat 14. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D)(list ad:0x40082500 ad:0x40082510 ad:0x40082520 ad:0x40082530 ad:0x40082540 ad:0x40082550 ad:0x40082560 ad:0x40082570 ad:0x40082580 ad:0x40082590 ad:0x400825A0 ad:0x400825B0 ad:0x400825C0 ad:0x400825D0)
tree "CHANNEL[$1]"
base $2
group.long ($2)++0x3
line.long 0x0 "CFG,Configuration register for DMA channel ."
bitfld.long 0x0 16.--18. "CHPRIORITY,Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported: 0x0 = highest priority. 0x7 = lowest priority." "0: highest priority,?,?,?,?,?,?,7: lowest priority"
bitfld.long 0x0 15. "DSTBURSTWRAP,Destination Burst Wrap. When enabled  the destination data address for the DMA is 'wrapped'  meaning that the destination address range for each burst will be the same. As an example  this could be used to write several sequential registers.." "0: Disabled. Destination burst wrapping is not..,1: Enabled. Destination burst wrapping is enabled.."
newline
bitfld.long 0x0 14. "SRCBURSTWRAP,Source Burst Wrap. When enabled  the source data address for the DMA is 'wrapped'  meaning that the source address range for each burst will be the same. As an example  this could be used to read several sequential registers from a.." "0: Disabled. Source burst wrapping is not enabled..,1: Enabled. Source burst wrapping is enabled for.."
hexmask.long.byte 0x0 8.--11. 1. "BURSTPOWER,Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1  Burst.."
newline
bitfld.long 0x0 6. "TRIGBURST,Trigger Burst. Selects whether hardware triggers cause a single or burst transfer." "0: Single transfer. Hardware trigger causes a..,1: Burst transfer. When the trigger for this.."
bitfld.long 0x0 5. "TRIGTYPE,Trigger Type. Selects hardware trigger as edge triggered or level triggered." "0: Edge. Hardware trigger is edge triggered.,1: Level. Hardware trigger is level triggered. Note.."
newline
bitfld.long 0x0 4. "TRIGPOL,Trigger Polarity. Selects the polarity of a hardware trigger for this channel." "0: Active low - falling edge. Hardware trigger is..,1: Active high - rising edge. Hardware trigger is.."
bitfld.long 0x0 1. "HWTRIGEN,Hardware Triggering Enable for this channel." "0: Disabled. Hardware triggering is not used.,1: Enabled. Use hardware triggering."
newline
bitfld.long 0x0 0. "PERIPHREQEN,Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move  any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller." "0: Disabled. Peripheral DMA requests are disabled.,1: Enabled. Peripheral DMA requests are enabled."
rgroup.long ($2+0x4)++0x3
line.long 0x0 "CTLSTAT,Control and status register for DMA channel ."
bitfld.long 0x0 2. "TRIG,Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1." "0: Not triggered. The trigger for this DMA channel..,1: Triggered. The trigger for this DMA channel is.."
bitfld.long 0x0 0. "VALIDPENDING,Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel." "0: No effect. No effect on DMA operation.,1: Valid pending."
group.long ($2+0x8)++0x3
line.long 0x0 "XFERCFG,Transfer configuration register for DMA channel ."
hexmask.long.word 0x0 16.--25. 1. "XFERCOUNT,Total number of transfers to be performed  minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence  it cannot.."
bitfld.long 0x0 14.--15. "DSTINC,Determines whether the destination address is incremented for each DMA transfer." "0: No increment. The destination address is not..,1: 1 x width. The destination address is..,2: 2 x width. The destination address is..,3: 4 x width. The destination address is.."
newline
bitfld.long 0x0 12.--13. "SRCINC,Determines whether the source address is incremented for each DMA transfer." "0: No increment. The source address is not..,1: 1 x width. The source address is incremented by..,2: 2 x width. The source address is incremented by..,3: 4 x width. The source address is incremented by.."
bitfld.long 0x0 8.--9. "WIDTH,Transfer width used for this DMA channel." "0: 8-bit. 8-bit transfers are performed (8-bit..,1: 16-bit. 6-bit transfers are performed (16-bit..,2: 32-bit. 32-bit transfers are performed (32-bit..,?"
newline
bitfld.long 0x0 5. "SETINTB,Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention  interrupt A may be used when only one interrupt flag is.." "0: No effect.,1: Set. The INTB flag for this channel will be set.."
bitfld.long 0x0 4. "SETINTA,Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention  interrupt A may be used when only one interrupt flag is.." "0: No effect.,1: Set. The INTA flag for this channel will be set.."
newline
bitfld.long 0x0 3. "CLRTRIG,Clear Trigger." "0: Not cleared. The trigger is not cleared when..,1: Cleared. The trigger is cleared when this.."
bitfld.long 0x0 2. "SWTRIG,Software Trigger." "0: Not set. When written by software the trigger..,1: Set. When written by software the trigger for.."
newline
bitfld.long 0x0 1. "RELOAD,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers." "0: Disabled. Do not reload the channels' control..,1: Enabled. Reload the channels' control structure.."
bitfld.long 0x0 0. "CFGVALID,Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon  if all other activation criteria are fulfilled." "0: Not valid. The channel descriptor is not..,1: Valid. The current channel descriptor is.."
tree.end
repeat.end
endif
sif (cpuis("LPC54618*"))
repeat 14. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D)(list ad:0x40082500 ad:0x40082510 ad:0x40082520 ad:0x40082530 ad:0x40082540 ad:0x40082550 ad:0x40082560 ad:0x40082570 ad:0x40082580 ad:0x40082590 ad:0x400825A0 ad:0x400825B0 ad:0x400825C0 ad:0x400825D0)
tree "CHANNEL[$1]"
base $2
group.long ($2)++0x3
line.long 0x0 "CFG,Configuration register for DMA channel ."
bitfld.long 0x0 16.--18. "CHPRIORITY,Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported: 0x0 = highest priority. 0x7 = lowest priority." "0: highest priority,?,?,?,?,?,?,7: lowest priority"
bitfld.long 0x0 15. "DSTBURSTWRAP,Destination Burst Wrap. When enabled  the destination data address for the DMA is 'wrapped'  meaning that the destination address range for each burst will be the same. As an example  this could be used to write several sequential registers.." "0: Disabled. Destination burst wrapping is not..,1: Enabled. Destination burst wrapping is enabled.."
newline
bitfld.long 0x0 14. "SRCBURSTWRAP,Source Burst Wrap. When enabled  the source data address for the DMA is 'wrapped'  meaning that the source address range for each burst will be the same. As an example  this could be used to read several sequential registers from a.." "0: Disabled. Source burst wrapping is not enabled..,1: Enabled. Source burst wrapping is enabled for.."
hexmask.long.byte 0x0 8.--11. 1. "BURSTPOWER,Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1  Burst.."
newline
bitfld.long 0x0 6. "TRIGBURST,Trigger Burst. Selects whether hardware triggers cause a single or burst transfer." "0: Single transfer. Hardware trigger causes a..,1: Burst transfer. When the trigger for this.."
bitfld.long 0x0 5. "TRIGTYPE,Trigger Type. Selects hardware trigger as edge triggered or level triggered." "0: Edge. Hardware trigger is edge triggered.,1: Level. Hardware trigger is level triggered. Note.."
newline
bitfld.long 0x0 4. "TRIGPOL,Trigger Polarity. Selects the polarity of a hardware trigger for this channel." "0: Active low - falling edge. Hardware trigger is..,1: Active high - rising edge. Hardware trigger is.."
bitfld.long 0x0 1. "HWTRIGEN,Hardware Triggering Enable for this channel." "0: Disabled. Hardware triggering is not used.,1: Enabled. Use hardware triggering."
newline
bitfld.long 0x0 0. "PERIPHREQEN,Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move  any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller." "0: Disabled. Peripheral DMA requests are disabled.,1: Enabled. Peripheral DMA requests are enabled."
rgroup.long ($2+0x4)++0x3
line.long 0x0 "CTLSTAT,Control and status register for DMA channel ."
bitfld.long 0x0 2. "TRIG,Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1." "0: Not triggered. The trigger for this DMA channel..,1: Triggered. The trigger for this DMA channel is.."
bitfld.long 0x0 0. "VALIDPENDING,Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel." "0: No effect. No effect on DMA operation.,1: Valid pending."
group.long ($2+0x8)++0x3
line.long 0x0 "XFERCFG,Transfer configuration register for DMA channel ."
hexmask.long.word 0x0 16.--25. 1. "XFERCOUNT,Total number of transfers to be performed  minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence  it cannot.."
bitfld.long 0x0 14.--15. "DSTINC,Determines whether the destination address is incremented for each DMA transfer." "0: No increment. The destination address is not..,1: 1 x width. The destination address is..,2: 2 x width. The destination address is..,3: 4 x width. The destination address is.."
newline
bitfld.long 0x0 12.--13. "SRCINC,Determines whether the source address is incremented for each DMA transfer." "0: No increment. The source address is not..,1: 1 x width. The source address is incremented by..,2: 2 x width. The source address is incremented by..,3: 4 x width. The source address is incremented by.."
bitfld.long 0x0 8.--9. "WIDTH,Transfer width used for this DMA channel." "0: 8-bit. 8-bit transfers are performed (8-bit..,1: 16-bit. 6-bit transfers are performed (16-bit..,2: 32-bit. 32-bit transfers are performed (32-bit..,?"
newline
bitfld.long 0x0 5. "SETINTB,Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention  interrupt A may be used when only one interrupt flag is.." "0: No effect.,1: Set. The INTB flag for this channel will be set.."
bitfld.long 0x0 4. "SETINTA,Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention  interrupt A may be used when only one interrupt flag is.." "0: No effect.,1: Set. The INTA flag for this channel will be set.."
newline
bitfld.long 0x0 3. "CLRTRIG,Clear Trigger." "0: Not cleared. The trigger is not cleared when..,1: Cleared. The trigger is cleared when this.."
bitfld.long 0x0 2. "SWTRIG,Software Trigger." "0: Not set. When written by software the trigger..,1: Set. When written by software the trigger for.."
newline
bitfld.long 0x0 1. "RELOAD,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers." "0: Disabled. Do not reload the channels' control..,1: Enabled. Reload the channels' control structure.."
bitfld.long 0x0 0. "CFGVALID,Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon  if all other activation criteria are fulfilled." "0: Not valid. The channel descriptor is not..,1: Valid. The current channel descriptor is.."
tree.end
repeat.end
endif
sif (cpuis("LPC54628*"))
repeat 14. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D)(list ad:0x40082500 ad:0x40082510 ad:0x40082520 ad:0x40082530 ad:0x40082540 ad:0x40082550 ad:0x40082560 ad:0x40082570 ad:0x40082580 ad:0x40082590 ad:0x400825A0 ad:0x400825B0 ad:0x400825C0 ad:0x400825D0)
tree "CHANNEL[$1]"
base $2
group.long ($2)++0x3
line.long 0x0 "CFG,Configuration register for DMA channel ."
bitfld.long 0x0 16.--18. "CHPRIORITY,Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported: 0x0 = highest priority. 0x7 = lowest priority." "0: highest priority,?,?,?,?,?,?,7: lowest priority"
bitfld.long 0x0 15. "DSTBURSTWRAP,Destination Burst Wrap. When enabled  the destination data address for the DMA is 'wrapped'  meaning that the destination address range for each burst will be the same. As an example  this could be used to write several sequential registers.." "0: Disabled. Destination burst wrapping is not..,1: Enabled. Destination burst wrapping is enabled.."
newline
bitfld.long 0x0 14. "SRCBURSTWRAP,Source Burst Wrap. When enabled  the source data address for the DMA is 'wrapped'  meaning that the source address range for each burst will be the same. As an example  this could be used to read several sequential registers from a.." "0: Disabled. Source burst wrapping is not enabled..,1: Enabled. Source burst wrapping is enabled for.."
hexmask.long.byte 0x0 8.--11. 1. "BURSTPOWER,Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1  Burst.."
newline
bitfld.long 0x0 6. "TRIGBURST,Trigger Burst. Selects whether hardware triggers cause a single or burst transfer." "0: Single transfer. Hardware trigger causes a..,1: Burst transfer. When the trigger for this.."
bitfld.long 0x0 5. "TRIGTYPE,Trigger Type. Selects hardware trigger as edge triggered or level triggered." "0: Edge. Hardware trigger is edge triggered.,1: Level. Hardware trigger is level triggered. Note.."
newline
bitfld.long 0x0 4. "TRIGPOL,Trigger Polarity. Selects the polarity of a hardware trigger for this channel." "0: Active low - falling edge. Hardware trigger is..,1: Active high - rising edge. Hardware trigger is.."
bitfld.long 0x0 1. "HWTRIGEN,Hardware Triggering Enable for this channel." "0: Disabled. Hardware triggering is not used.,1: Enabled. Use hardware triggering."
newline
bitfld.long 0x0 0. "PERIPHREQEN,Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move  any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller." "0: Disabled. Peripheral DMA requests are disabled.,1: Enabled. Peripheral DMA requests are enabled."
rgroup.long ($2+0x4)++0x3
line.long 0x0 "CTLSTAT,Control and status register for DMA channel ."
bitfld.long 0x0 2. "TRIG,Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1." "0: Not triggered. The trigger for this DMA channel..,1: Triggered. The trigger for this DMA channel is.."
bitfld.long 0x0 0. "VALIDPENDING,Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel." "0: No effect. No effect on DMA operation.,1: Valid pending."
group.long ($2+0x8)++0x3
line.long 0x0 "XFERCFG,Transfer configuration register for DMA channel ."
hexmask.long.word 0x0 16.--25. 1. "XFERCOUNT,Total number of transfers to be performed  minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence  it cannot.."
bitfld.long 0x0 14.--15. "DSTINC,Determines whether the destination address is incremented for each DMA transfer." "0: No increment. The destination address is not..,1: 1 x width. The destination address is..,2: 2 x width. The destination address is..,3: 4 x width. The destination address is.."
newline
bitfld.long 0x0 12.--13. "SRCINC,Determines whether the source address is incremented for each DMA transfer." "0: No increment. The source address is not..,1: 1 x width. The source address is incremented by..,2: 2 x width. The source address is incremented by..,3: 4 x width. The source address is incremented by.."
bitfld.long 0x0 8.--9. "WIDTH,Transfer width used for this DMA channel." "0: 8-bit. 8-bit transfers are performed (8-bit..,1: 16-bit. 6-bit transfers are performed (16-bit..,2: 32-bit. 32-bit transfers are performed (32-bit..,?"
newline
bitfld.long 0x0 5. "SETINTB,Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention  interrupt A may be used when only one interrupt flag is.." "0: No effect.,1: Set. The INTB flag for this channel will be set.."
bitfld.long 0x0 4. "SETINTA,Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention  interrupt A may be used when only one interrupt flag is.." "0: No effect.,1: Set. The INTA flag for this channel will be set.."
newline
bitfld.long 0x0 3. "CLRTRIG,Clear Trigger." "0: Not cleared. The trigger is not cleared when..,1: Cleared. The trigger is cleared when this.."
bitfld.long 0x0 2. "SWTRIG,Software Trigger." "0: Not set. When written by software the trigger..,1: Set. When written by software the trigger for.."
newline
bitfld.long 0x0 1. "RELOAD,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers." "0: Disabled. Do not reload the channels' control..,1: Enabled. Reload the channels' control structure.."
bitfld.long 0x0 0. "CFGVALID,Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon  if all other activation criteria are fulfilled." "0: Not valid. The channel descriptor is not..,1: Valid. The current channel descriptor is.."
tree.end
repeat.end
endif
tree.end
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54113*")||cpuis("LPC54114*")||cpuis("LPC54605*")||cpuis("LPC54606*")||cpuis("LPC54607*")||cpuis("LPC54608*")||cpuis("LPC54616*")||cpuis("LPC54618*")||cpuis("LPC54628*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
tree "DMIC (Digital Microphone Interface)"
base ad:0x40090000
repeat 2. (list 0x0 0x1)(list ad:0x40090000 ad:0x40090100)
tree "CHANNEL[$1]"
base $2
group.long ($2)++0x13
line.long 0x0 "OSR,Oversample Rate register 0"
hexmask.long.byte 0x0 0.--7. 1. "OSR,Selects the oversample rate for the related input channel."
line.long 0x4 "DIVHFCLK,DMIC Clock Register 0"
hexmask.long.byte 0x4 0.--3. 1. "PDMDIV,PDM clock divider value. 0 = divide by 1 1 = divide by 2 2 = divide by 3 3 = divide by 4 4 = divide by 6 5 = divide by 8 6 = divide by 12 7 = divide by 16 8 = divide by 24 9 = divide by 32 10 = divide by 48 11 = divide by 64 12 = divide by 96 13 =.."
line.long 0x8 "PREAC2FSCOEF,Pre-Emphasis Filter Coefficient for 2 FS register"
bitfld.long 0x8 0.--1. "COMP,Pre-emphasis filer coefficient for 2 FS mode. 0 = Compensation = 0 1 = Compensation = 16 2 = Compensation = 15 3 = Compensation = 13" "0: Compensation = 0,1: Compensation = 16,2: Compensation = 15,3: Compensation = 13"
line.long 0xC "PREAC4FSCOEF,Pre-Emphasis Filter Coefficient for 4 FS register"
bitfld.long 0xC 0.--1. "COMP,Pre-emphasis filer coefficient for 4 FS mode. 0 = Compensation = 0 1 = Compensation = 16 2 = Compensation = 15 3 = Compensation = 13" "0: Compensation = 0,1: Compensation = 16,2: Compensation = 15,3: Compensation = 13"
line.long 0x10 "GAINSHIFT,Decimator Gain Shift register"
hexmask.long.byte 0x10 0.--5. 1. "GAIN,Gain control  as a positive or negative (two's complement) number of bits to shift."
group.long ($2+0x80)++0x13
line.long 0x0 "FIFO_CTRL,FIFO Control register 0"
hexmask.long.byte 0x0 16.--20. 1. "TRIGLVL,FIFO trigger level. Selects the data trigger level for interrupt or DMA operation. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode See Section 4.5.66 'Hardware Wake-up.."
bitfld.long 0x0 3. "DMAEN,DMA enable" "0: DMA requests are not enabled.,1: DMA requests based on FIFO level are enabled."
newline
bitfld.long 0x0 2. "INTEN,Interrupt enable." "0: FIFO level interrupts are not enabled.,1: FIFO level interrupts are enabled."
bitfld.long 0x0 1. "RESETN,FIFO reset." "0: Reset the FIFO.,1: Normal operation"
newline
bitfld.long 0x0 0. "ENABLE,FIFO enable." "0: FIFO is not enabled. Enabling a DMIC channel..,1: FIFO is enabled. The FIFO must be enabled in.."
line.long 0x4 "FIFO_STATUS,FIFO Status register 0"
bitfld.long 0x4 2. "UNDERRUN,Underrun flag. Indicates that a FIFO underflow has occurred at some point. Writing a one to this bit clears the flag." "0,1"
bitfld.long 0x4 1. "OVERRUN,Overrun flag. Indicates that a FIFO overflow has occurred at some point. Writing a one to this bit clears the flag. This flag does not cause an interrupt." "0,1"
newline
bitfld.long 0x4 0. "INT,Interrupt flag. Asserted when FIFO data reaches the level specified in the FIFOCTRL register. Writing a one to this bit clears the flag. Remark: note that the bus clock to the DMIC subsystem must be running in order for an interrupt to occur." "0,1"
line.long 0x8 "FIFO_DATA,FIFO Data Register 0"
hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Data from the top of the input filter FIFO."
line.long 0xC "PHY_CTRL,PDM Source Configuration register 0"
bitfld.long 0xC 1. "PHY_HALF,Half rate sampling" "0: Standard half rate sampling. The clock to the..,1: Use half rate sampling. The clock to the DMIC is.."
bitfld.long 0xC 0. "PHY_FALL,Capture PDM_DATA" "0: Capture PDM_DATA on the rising edge of PDM_CLK.,1: Capture PDM_DATA on the falling edge of PDM_CLK."
line.long 0x10 "DC_CTRL,DC Control register 0"
bitfld.long 0x10 8. "SATURATEAT16BIT,Selects 16-bit saturation." "0: Results roll over if out range and do not..,1: If the result overflows it saturates at 0xFFFF.."
hexmask.long.byte 0x10 4.--7. 1. "DCGAIN,Fine gain adjustment in the form of a number of bits to downshift."
newline
bitfld.long 0x10 0.--1. "DCPOLE,DC block filter" "0: Flat response no filter.,1: 155 Hz.,2: 78 Hz.,3: 39 Hz"
tree.end
repeat.end
base ad:0x40090000
group.long 0xF00++0x3
line.long 0x0 "CHANEN,Channel Enable register"
bitfld.long 0x0 1. "EN_CH1,Enable channel 1. When 1  PDM channel 1 is enabled." "0,1"
bitfld.long 0x0 0. "EN_CH0,Enable channel 0. When 1  PDM channel 0 is enabled." "0,1"
group.long 0xF0C++0x7
line.long 0x0 "IOCFG,I/O Configuration register"
bitfld.long 0x0 2. "STEREO_DATA0,Stereo PDM select. When 1  PDM_DATA0 is routed to both PDM channels in a configuration that supports a single stereo digital microphone." "0,1"
bitfld.long 0x0 1. "CLK_BYPASS1,Bypass CLK1. When 1  PDM_DATA1 becomes the clock for PDM channel 1. This provides for the possibility of an external codec taking over the PDM bus." "0,1"
bitfld.long 0x0 0. "CLK_BYPASS0,Bypass CLK0. When 1  PDM_DATA1 becomes the clock for PDM channel 0. This provides for the possibility of an external codec taking over the PDM bus." "0,1"
line.long 0x4 "USE2FS,Use 2FS register"
bitfld.long 0x4 0. "USE2FS,Use 2FS register" "0: Use 1FS output for PCM data.,1: Use 2FS output for PCM data."
group.long 0xF80++0x17
line.long 0x0 "HWVADGAIN,HWVAD input gain register"
hexmask.long.byte 0x0 0.--3. 1. "INPUTGAIN,Shift value for input bits 0x00 -10 bits 0x01 -8 bits 0x02 -6 bits 0x03 -4 bits 0x04 -2 bits 0x05 0 bits (default) 0x06 +2 bits 0x07 +4 bits 0x08 +6 bits 0x09 +8 bits 0x0A +10 bits 0x0B +12 bits 0x0C +14 bits 0x0D to 0x0F Reserved."
line.long 0x4 "HWVADHPFS,HWVAD filter control register"
bitfld.long 0x4 0.--1. "HPFS,High pass filter" "0: First filter by-pass.,1: High pass filter with -3dB cut-off at 1750Hz.,2: High pass filter with -3dB cut-off at 215Hz.,?"
line.long 0x8 "HWVADST10,HWVAD control register"
bitfld.long 0x8 0. "ST10,Stage 0" "0: Normal operation waiting for HWVAD trigger event..,1: Reset internal interrupt flag by writing a '1'.."
line.long 0xC "HWVADRSTT,HWVAD filter reset register"
bitfld.long 0xC 0. "RSTT,Writing a 1 resets all filter values" "0,1"
line.long 0x10 "HWVADTHGN,HWVAD noise estimator gain register"
hexmask.long.byte 0x10 0.--3. 1. "THGN,Gain value for the noise estimator. Values 0 to 14. 0 corresponds to a gain of 1."
line.long 0x14 "HWVADTHGS,HWVAD signal estimator gain register"
hexmask.long.byte 0x14 0.--3. 1. "THGS,Gain value for the signal estimator. Values 0 to 14. 0 corresponds to a gain of 1."
rgroup.long 0xF98++0x3
line.long 0x0 "HWVADLOWZ,HWVAD noise envelope estimator register"
hexmask.long.word 0x0 0.--15. 1. "LOWZ,Noise envelope estimator value."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Module Identification register"
hexmask.long 0x0 0.--31. 1. "ID,Indicates module ID and the number of channels in this DMIC interface."
tree.end
endif
sif (cpuis("LPC54605*")||cpuis("LPC54606*")||cpuis("LPC54607*")||cpuis("LPC54608*")||cpuis("LPC54616*")||cpuis("LPC54618*")||cpuis("LPC54628*"))
tree "EEPROM (EEPROM Controller)"
base ad:0x40014000
group.long 0x0++0x3
line.long 0x0 "CMD,EEPROM command register"
bitfld.long 0x0 0.--2. "CMD,Command." "0,1,2,3,4,5,6,7"
group.long 0x8++0x13
line.long 0x0 "RWSTATE,EEPROM read wait state register"
hexmask.long.byte 0x0 8.--15. 1. "RPHASE1,Wait states 1 (minus 1 encoded)."
hexmask.long.byte 0x0 0.--7. 1. "RPHASE2,Wait states 2 (minus 1 encoded)."
line.long 0x4 "AUTOPROG,EEPROM auto programming register"
bitfld.long 0x4 0.--1. "AUTOPROG,Auto programming mode: 00 = auto programming off 01 = erase/program cycle is triggered after 1 word is written 10 = erase/program cycle is triggered after a write to AHB address ending with ." "0: auto programming off,1: erase/program cycle is triggered after 1 word is..,?,?"
line.long 0x8 "WSTATE,EEPROM wait state register"
bitfld.long 0x8 31. "LCK_PARWEP,Lock timing parameters for write  erase and program operation 0 = WSTATE and CLKDIV registers have R/W access 1 = WSTATE and CLKDIV registers have R only access." "0: WSTATE and CLKDIV registers have R/W access,1: WSTATE and CLKDIV registers have R only access"
hexmask.long.byte 0x8 16.--23. 1. "PHASE1,Wait states for phase 1 (minus 1 encoded)."
hexmask.long.byte 0x8 8.--15. 1. "PHASE2,Wait states for phase 2 (minus 1 encoded)."
hexmask.long.byte 0x8 0.--7. 1. "PHASE3,Wait states for phase 3 (minus 1 encoded)."
line.long 0xC "CLKDIV,EEPROM clock divider register"
hexmask.long.word 0xC 0.--15. 1. "CLKDIV,Division factor (minus 1 encoded)."
line.long 0x10 "PWRDWN,EEPROM power-down register"
bitfld.long 0x10 0. "PWRDWN,Power down mode bit." "0,1"
wgroup.long 0xFD8++0x7
line.long 0x0 "INTENCLR,EEPROM interrupt enable clear"
bitfld.long 0x0 2. "PROG_CLR_EN,Clear program operation finished interrupt enable bit for EEPROM." "0,1"
line.long 0x4 "INTENSET,EEPROM interrupt enable set"
bitfld.long 0x4 2. "PROG_SET_EN,Set program operation finished interrupt enable bit for EEPROM device 1." "0,1"
rgroup.long 0xFE0++0x7
line.long 0x0 "INTSTAT,EEPROM interrupt status"
bitfld.long 0x0 2. "END_OF_PROG,EEPROM program operation finished interrupt status bit." "0,1"
line.long 0x4 "INTEN,EEPROM interrupt enable"
bitfld.long 0x4 2. "EE_PROG_DONE,EEPROM program operation finished interrupt enable bit." "0,1"
wgroup.long 0xFE8++0x7
line.long 0x0 "INTSTATCLR,EEPROM interrupt status clear"
bitfld.long 0x0 2. "PROG_CLR_ST,Clear program operation finished interrupt status bit for EEPROM device." "0,1"
line.long 0x4 "INTSTATSET,EEPROM interrupt status set"
bitfld.long 0x4 2. "PROG_SET_ST,Set program operation finished interrupt status bit for EEPROM device." "0,1"
tree.end
endif
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54605*")||cpuis("LPC54606*")||cpuis("LPC54607*")||cpuis("LPC54608*")||cpuis("LPC54616*")||cpuis("LPC54618*")||cpuis("LPC54628*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
tree "EMC (External Memory Controller)"
base ad:0x40081000
group.long 0x0++0x3
line.long 0x0 "CONTROL,Controls operation of the memory controller"
bitfld.long 0x0 2. "L,Low-power mode." "0,1"
bitfld.long 0x0 1. "M,Address mirror." "0,1"
bitfld.long 0x0 0. "E,EMC Enable." "0,1"
rgroup.long 0x4++0x3
line.long 0x0 "STATUS,Provides EMC status information"
bitfld.long 0x0 2. "SA,Self-refresh acknowledge." "0,1"
bitfld.long 0x0 1. "S,Write buffer status." "0,1"
bitfld.long 0x0 0. "B,Busy." "0,1"
group.long 0x8++0x3
line.long 0x0 "CONFIG,Configures operation of the memory controller"
bitfld.long 0x0 8. "CLKR,This bit must contain 0 for proper operation of the EMC." "0,1"
bitfld.long 0x0 0. "EM,Endian mode." "0,1"
group.long 0x20++0xB
line.long 0x0 "DYNAMICCONTROL,Controls dynamic memory operation"
bitfld.long 0x0 7.--8. "I,SDRAM initialization." "0,1,2,3"
bitfld.long 0x0 5. "MMC,Memory clock control." "0,1"
bitfld.long 0x0 2. "SR,Self-refresh request  EMCSREFREQ." "0,1"
bitfld.long 0x0 1. "CS,Dynamic memory clock control." "0,1"
bitfld.long 0x0 0. "CE,Dynamic memory clock enable." "0,1"
line.long 0x4 "DYNAMICREFRESH,Configures dynamic memory refresh"
hexmask.long.word 0x4 0.--10. 1. "REFRESH,Refresh timer."
line.long 0x8 "DYNAMICREADCONFIG,Configures dynamic memory read strategy"
bitfld.long 0x8 0.--1. "RD,Read data strategy." "0,1,2,3"
group.long 0x30++0x2B
line.long 0x0 "DYNAMICRP,Precharge command period"
hexmask.long.byte 0x0 0.--3. 1. "TRP,Precharge command period."
line.long 0x4 "DYNAMICRAS,Active to precharge command period"
hexmask.long.byte 0x4 0.--3. 1. "TRAS,Active to precharge command period."
line.long 0x8 "DYNAMICSREX,Self-refresh exit time"
hexmask.long.byte 0x8 0.--3. 1. "TSREX,Self-refresh exit time."
line.long 0xC "DYNAMICAPR,Last-data-out to active command time"
hexmask.long.byte 0xC 0.--3. 1. "TAPR,Last-data-out to active command time."
line.long 0x10 "DYNAMICDAL,Data-in to active command time"
hexmask.long.byte 0x10 0.--3. 1. "TDAL,Data-in to active command."
line.long 0x14 "DYNAMICWR,Write recovery time"
hexmask.long.byte 0x14 0.--3. 1. "TWR,Write recovery time."
line.long 0x18 "DYNAMICRC,Selects the active to active command period"
hexmask.long.byte 0x18 0.--4. 1. "TRC,Active to active command period."
line.long 0x1C "DYNAMICRFC,Selects the auto-refresh period"
hexmask.long.byte 0x1C 0.--4. 1. "TRFC,Auto-refresh period and auto-refresh to active command period."
line.long 0x20 "DYNAMICXSR,Time for exit self-refresh to active command"
hexmask.long.byte 0x20 0.--4. 1. "TXSR,Exit self-refresh to active command time."
line.long 0x24 "DYNAMICRRD,Latency for active bank A to active bank B"
hexmask.long.byte 0x24 0.--3. 1. "TRRD,Active bank A to active bank B latency 0x0 - 0xE = n + 1 clock cycles."
line.long 0x28 "DYNAMICMRD,Time for load mode register to active command"
hexmask.long.byte 0x28 0.--3. 1. "TMRD,Load mode register to active command time."
group.long 0x80++0x3
line.long 0x0 "STATICEXTENDEDWAIT,Time for long static memory read and write transfers"
hexmask.long.word 0x0 0.--9. 1. "EXTENDEDWAIT,Extended wait time out."
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x40081100 ad:0x40081120 ad:0x40081140 ad:0x40081160)
tree "DYNAMIC[$1]"
base $2
group.long ($2)++0x7
line.long 0x0 "DYNAMICCONFIG,Configuration information for EMC_DYCSx"
bitfld.long 0x0 20. "P,Write protect." "0,1"
bitfld.long 0x0 19. "B,Buffer enable." "0,1"
bitfld.long 0x0 14. "AM1,See Table 933." "0,1"
hexmask.long.byte 0x0 7.--12. 1. "AM0,See Table 933."
bitfld.long 0x0 3.--4. "MD,Memory device." "0,1,2,3"
line.long 0x4 "DYNAMICRASCAS,RAS and CAS latencies for EMC_DYCSx"
bitfld.long 0x4 8.--9. "CAS,CAS latency." "0,1,2,3"
bitfld.long 0x4 0.--1. "RAS,RAS latency (active to read/write delay)." "0,1,2,3"
tree.end
repeat.end
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x40081200 ad:0x40081220 ad:0x40081240 ad:0x40081260)
tree "STATIC[$1]"
base $2
group.long ($2)++0x1B
line.long 0x0 "STATICCONFIG,Configuration for EMC_CSx"
bitfld.long 0x0 20. "P,Write protect." "0,1"
bitfld.long 0x0 19. "B,Buffer enable [2]." "0,1"
bitfld.long 0x0 8. "EW,Extended wait (EW) uses the EMCStaticExtendedWait register to time both the read and write transfers rather than the EMCStaticWaitRd and EMCStaticWaitWr registers." "0,1"
bitfld.long 0x0 7. "PB,Byte lane state." "0,1"
bitfld.long 0x0 6. "PC,Chip select polarity." "0,1"
bitfld.long 0x0 3. "PM,Page mode." "0,1"
bitfld.long 0x0 0.--1. "MW,Memory width." "0,1,2,3"
line.long 0x4 "STATICWAITWEN,Delay from EMC_CSx to write enable"
hexmask.long.byte 0x4 0.--3. 1. "WAITWEN,Wait write enable."
line.long 0x8 "STATICWAITOEN,Delay from EMC_CSx or address change. whichever is later. to output enable"
hexmask.long.byte 0x8 0.--3. 1. "WAITOEN,Wait output enable."
line.long 0xC "STATICWAITRD,Delay from EMC_CSx to a read access"
hexmask.long.byte 0xC 0.--4. 1. "WAITRD,."
line.long 0x10 "STATICWAITPAGE,Delay for asynchronous page mode sequential accesses for EMC_CSx"
hexmask.long.byte 0x10 0.--4. 1. "WAITPAGE,Asynchronous page mode read after the first read wait states."
line.long 0x14 "STATICWAITWR,Delay from EMC_CSx to a write access"
hexmask.long.byte 0x14 0.--4. 1. "WAITWR,Write wait states."
line.long 0x18 "STATICWAITTURN,Number of bus turnaround cycles EMC_CSx"
hexmask.long.byte 0x18 0.--3. 1. "WAITTURN,Bus turn-around cycles."
tree.end
repeat.end
tree.end
endif
sif (cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54606*")||cpuis("LPC54608*")||cpuis("LPC54616*")||cpuis("LPC54618*")||cpuis("LPC54628*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
tree "ENET (Ethernet Controller)"
base ad:0x40092000
group.long 0x0++0xF
line.long 0x0 "MAC_CONFIG,MAC configuration register"
bitfld.long 0x0 27. "IPC,Checksum Offload When set  this bit enables the IPv4 header checksum checking and IPv4 or IPv6 TCP  UDP  or ICMP payload checksum checking." "0,1"
newline
bitfld.long 0x0 24.--26. "IPG,Inter-Packet Gap These bits control the minimum IPG between packets during transmission." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 23. "GPSLCE,Giant Packet Size Limit Control Enable When this bit is set  the MAC considers the value in GPSL field in MAC Ext Configuration register to declare a received packet as Giant packet." "0,1"
newline
bitfld.long 0x0 22. "S2KP,IEEE 802." "0,1"
newline
bitfld.long 0x0 21. "CST,CRC stripping for Type packets When this bit is set  the last four bytes (FCS) of all packets of Ether type (type field greater than 1 536) are stripped and dropped before forwarding the packet to the application." "0,1"
newline
bitfld.long 0x0 20. "ACS,Automatic Pad or CRC Stripping When this bit is set  the MAC strips the Pad or FCS field on the incoming packets only if the value of the length field is less than 1 536 bytes." "0,1"
newline
bitfld.long 0x0 19. "WD,Watchdog Disable When this bit is set  the MAC disables the watchdog timer on the receiver  and can receive frames of up to 16 384 bytes." "0,1"
newline
bitfld.long 0x0 18. "BE,Packet Burst Enable When this bit is set  the MAC allows packet bursting during transmission in the MII half-duplex mode." "0,1"
newline
bitfld.long 0x0 17. "JD,Jabber Disable When this bit is set  the MAC disables the jabber timer on the transmitter  and can transfer frames of up to 16 384 bytes." "0,1"
newline
bitfld.long 0x0 16. "JE,Jumbo Frame Enable When this bit is set  MAC allows Jumbo frames of 9 018 bytes (9 022 bytes for tagged frames) without reporting a giant frame error in the receive frame status." "0,1"
newline
rbitfld.long 0x0 15. "PS,Portselect." "0,1"
newline
bitfld.long 0x0 14. "FES,Speed Indicates the speed in Fast Ethernet (MII) mode: This bit is reserved (RO) by default and is enabled only when RMII/SMII is enabled during configuration." "0,1"
newline
bitfld.long 0x0 13. "DM,Duplex Mode When this bit is set  the MAC operates in a Full-Duplex mode where it can transmit and receive simultaneously." "0,1"
newline
bitfld.long 0x0 12. "LM,Loopback Mode When this bit is set  the MAC operates in loopback mode at MII." "0,1"
newline
bitfld.long 0x0 11. "ECRSFD,Enable Carrier Sense Before Transmission in Full-Duplex Mode When this bit is set  the MAC transmitter checks the CRS signal before packet transmission in the full-duplex mode." "0,1"
newline
bitfld.long 0x0 10. "DO,Disable Receive Own When this bit is set  the MAC disables the reception of frames when the gmii_txen_o is asserted in Half-Duplex mode." "0,1"
newline
bitfld.long 0x0 9. "DCRS,Disable Carrier Sense During Transmission When this bit is set  the MAC transmitter ignores the MII CRS signal during packet transmission in the half-duplex mode." "0,1"
newline
bitfld.long 0x0 8. "DR,Disable Retry When this bit is set  the MAC will attempt only one transmission." "0,1"
newline
bitfld.long 0x0 5.--6. "BL,Back-Off Limit The Back-Off limit determines the random integer number (r) of slot time delays (4 096 bit times for 1000 Mbps and 512 bit times for 10/100 Mbps) the MAC waits before rescheduling a transmission attempt during retries after a collision." "0,1,2,3"
newline
bitfld.long 0x0 4. "DC,Deferral Check When this bit is set  the deferral check function is enabled in the MAC." "0,1"
newline
bitfld.long 0x0 2.--3. "PRELEN,Preamble Length for Transmit packets These bits control the number of preamble bytes that are added to the beginning of every Tx packet." "0,1,2,3"
newline
bitfld.long 0x0 1. "TE,Transmitter Enable When this bit is set  the transmit state machine of the MAC is enabled for transmission on the MII." "0,1"
newline
bitfld.long 0x0 0. "RE,Receiver Enable When this bit is set  the receiver state machine of the MAC is enabled for receiving frames from the MII." "0,1"
line.long 0x4 "MAC_EXT_CONFIG,no description available"
bitfld.long 0x4 18. "USP,Unicast Slow Protocol Packet Detect When this bit is set  the MAC detects the Slow Protocol packets with unicast address of the station specified in the MAC Address High Table 747 and MAC Address Low Table 748 registers." "0,1"
newline
bitfld.long 0x4 17. "SPEN,Slow Protocol Detection Enable When this bit is set  MAC processes the Slow Protocol packets (Ether Type 0x8809) and provides the Rx status." "0,1"
newline
bitfld.long 0x4 16. "DCRCC,Disable CRC Checking for Received Packets When this bit is set  the MAC receiver does not check the CRC field in the received packets." "0,1"
newline
hexmask.long.word 0x4 0.--13. 1. "GPSL,Giant Packet Size Limit If the received packet size is greater than the value programmed in this field in units of bytes  the MAC declares the received packet as Giant packet."
line.long 0x8 "MAC_FRAME_FILTER,MAC frame filter register"
bitfld.long 0x8 31. "RA,Receive all When this bit is set  the MAC Receiver module passes to the Application all frames received irrespective of whether they pass the address filter." "0,1"
newline
rbitfld.long 0x8 9. "SAF,Source Address Filter Enable When this bit is set  the MAC compares the SA field of the received packets with the values programmed in the enabled SA registers." "0,1"
newline
rbitfld.long 0x8 8. "SAIF,SA Inverse Filtering When this bit is set  the Address Check block operates in the inverse filtering mode for SA address comparison." "0,1"
newline
bitfld.long 0x8 6.--7. "PCF,Pass Control Frames These bits control the forwarding of all control frames (including unicast and multicast PAUSE frames)." "0,1,2,3"
newline
bitfld.long 0x8 5. "DBF,Disable Broadcast Frames When this bit is set  the AFM module filters all incoming broadcast frames." "0,1"
newline
bitfld.long 0x8 4. "PM,Pass All Multicast When set  this bit indicates that all received frames with a multicast destination address (first bit in the destination address field is '1') are passed." "0,1"
newline
bitfld.long 0x8 3. "DAIF,DA Inverse Filtering When this bit is set  the Address Check block operates in inverse filtering mode for the DA address comparison for both unicast and multicast frames." "0,1"
newline
bitfld.long 0x8 0. "PR,Promiscuous Mode When this bit is set  the Address Filter module passes all incoming frames regardless of its destination or source address." "0,1"
line.long 0xC "MAC_WD_TIMEROUT,MAC watchdog Timeout register"
bitfld.long 0xC 8. "PWE,Programmable Watchdog Enable When this bit is set and the WD bit of the MAC Configuration register Table 722 is reset  the WTO field is used as watchdog timeout for a received packet." "0,1"
newline
hexmask.long.byte 0xC 0.--3. 1. "WTO,Watchdog Timeout When the PWE bit is set and the WD bit of the MAC Configuration register Table 722 is reset  this field is used as watchdog timeout for a received packet."
group.long 0x50++0x3
line.long 0x0 "MAC_VLAN_TAG,MAC vlan tag register"
bitfld.long 0x0 31. "EIVLRXS,Enable Inner VLAN Tag in Rx Status." "0,1"
newline
bitfld.long 0x0 28.--29. "EIVLS,Enable Inner VLAN Tag Stripping on Receive." "0,1,2,3"
newline
bitfld.long 0x0 27. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 26. "EDVLP,Enable Double VLAN Processing." "0,1"
newline
bitfld.long 0x0 25. "VTHM,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 24. "EVLRXS,Enable VLAN Tag in Rx status." "0,1"
newline
bitfld.long 0x0 21.--22. "EVLS,Enable VLAN Tag Stripping on Receive." "0,1,2,3"
newline
bitfld.long 0x0 20. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "ESVL,Enable S-VLAN." "0,1"
newline
bitfld.long 0x0 17. "VTIM,VLAN Tag Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 16. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VL,VLAN Tag Identifier for Receive Packets."
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x70)++0x3
line.long 0x0 "MAC_TX_FLOW_CTRL_Q[$1],Transmit flow control register"
hexmask.long.word 0x0 16.--31. 1. "PT,Pause time This field holds the value to be used in the Pause Time field in the transmit control frame."
newline
bitfld.long 0x0 7. "DZPQ,Disable Zero-Quanta Pause When set  this bit disables the automatic generation of Zero-Quanta Pause Control frames on the deassertion of the flow-control signal from the FIFO layer." "0,1"
newline
bitfld.long 0x0 4.--6. "PLT,Pause Low Threshold This field configures the threshold of the PAUSE timer at which the input flow control signal is checked for automatic retransmission of PAUSE Frame." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 1. "TFE,Transmit Flow Control Enable In Full-Duplex mode  when this bit is set  the MAC enables the flow control operation to transmit Pause frames." "0,1"
newline
bitfld.long 0x0 0. "FCB,Flow Control Busy/Backpressure Activate This register field can be read by the application (Read)  can be set to 1 by the application with a register write of 1 (Write Set)  and is cleared to 0 by the core (Self Clear)." "0,1"
repeat.end
group.long 0x90++0x3
line.long 0x0 "MAC_RX_FLOW_CTRL,Receive flow control register"
bitfld.long 0x0 1. "UP,Unicast Pause Packet Detect A pause packet is processed when it has the unique multicast address specified in the IEEE 802." "0,1"
newline
bitfld.long 0x0 0. "RFE,Receive Flow Control Enable When this bit is set and the MAC is operating in full-duplex mode  the MAC decodes the received Pause packet and disables its transmitter for a specified (Pause) time." "0,1"
group.long 0x98++0x3
line.long 0x0 "MAC_TXQ_PRIO_MAP,no description available"
hexmask.long.byte 0x0 8.--15. 1. "PSTQ1,Priorities Selected in Transmit Queue 1 This bit is similar to the PSTQ0 bit."
newline
hexmask.long.byte 0x0 0.--7. 1. "PSTQ0,Priorities Selected in Transmit Queue 0 This field holds the priorities assigned to Tx Queue 0 by the software."
group.long 0xA0++0xB
line.long 0x0 "MAC_RXQ_CTRL0,Receive Queue Control 0 register 0x0000"
bitfld.long 0x0 2.--3. "RXQ1EN,Receive Queue 1 Enable." "0,1,2,3"
newline
bitfld.long 0x0 0.--1. "RXQ0EN,Receive Queue 0 Enable." "0,1,2,3"
line.long 0x4 "MAC_RXQ_CTRL1,Receive Queue Control 0 register 0x0000"
bitfld.long 0x4 20. "MCBCQEN,Multicast and Broadcast Queue Enable." "0,1"
newline
bitfld.long 0x4 16.--18. "MCBCQ,Multicast and Broadcast Queue." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 12.--14. "UPQ,Untagged Packet Queue." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 4.--6. "AVPTPQ,AV PTP Packets Queue." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 0.--2. "AVCPQ,AV Untagged Control Packets Queue." "0,1,2,3,4,5,6,7"
line.long 0x8 "MAC_RXQ_CTRL2,Receive Queue Control 0 register 0x0000"
hexmask.long.byte 0x8 24.--31. 1. "PSRQ3,Priorities Selected in the Receive Queue 3."
newline
hexmask.long.byte 0x8 16.--23. 1. "PSRQ2,Priorities Selected in the Receive Queue 2."
newline
hexmask.long.byte 0x8 8.--15. 1. "PSRQ1,Priorities Selected in the Receive Queue 1."
newline
hexmask.long.byte 0x8 0.--7. 1. "PSRQ0,Priorities Selected in the Receive Queue 0."
rgroup.long 0xB0++0x3
line.long 0x0 "MAC_INTR_STAT,Interrupt status register 0x0000"
bitfld.long 0x0 14. "RXSTSIS,Receive Status Interrupt." "0,1"
newline
bitfld.long 0x0 13. "TXSTSIS,Transmit Status Interrupt." "0,1"
newline
bitfld.long 0x0 12. "TSIS,Timestamp interrupt status." "0,1"
newline
bitfld.long 0x0 5. "LPIIS,LPI Interrupt Status." "0,1"
newline
bitfld.long 0x0 4. "PMTIS,PMT Interrupt Status." "0,1"
newline
bitfld.long 0x0 3. "PHYIS,PHY Interrupt." "0,1"
group.long 0xB4++0x3
line.long 0x0 "MAC_INTR_EN,Interrupt enable register 0x0000"
bitfld.long 0x0 14. "RXSTSIS,Receive Status Interrupt Enable." "0,1"
newline
bitfld.long 0x0 13. "TXSTSIE,Transmit Status Interrupt Enable." "0,1"
newline
bitfld.long 0x0 12. "TSIE,Timestamp Interrupt Enable." "0,1"
newline
bitfld.long 0x0 5. "LPIIE,LPI Interrupt Enable." "0,1"
newline
bitfld.long 0x0 4. "PMTIE,PMT Interrupt Enable." "0,1"
newline
bitfld.long 0x0 3. "PHYIE,PHY Interrupt Enable." "0,1"
rgroup.long 0xB8++0x3
line.long 0x0 "MAC_RXTX_STAT,Receive Transmit Status register"
bitfld.long 0x0 8. "RWT,Receive Watchdog Timeout This bit is set when a packet with length greater than 2 048 bytes is received (10 240 bytes when Jumbo Packet mode is enabled) and the WD bit is reset in the MAC Configuration register Table 722." "0,1"
newline
bitfld.long 0x0 5. "EXCOL,Excessive Collisions When the DTXSTS bit is set in the MTL Operation Mode register Table 758  this bit indicates that the transmission aborted after 16 successive collisions while attempting to transmit the current packet." "0,1"
newline
bitfld.long 0x0 4. "LCOL,Late Collision When the DTXSTS bit is set in the MTL Operation Mode register Table 758  this bit indicates that the packet transmission aborted because a collision occurred after the collision window (64 bytes including Preamble in MII mode)." "0,1"
newline
bitfld.long 0x0 3. "EXDEF,Excessive Deferral When the DTXSTS bit is set in the MTL Operation Mode register Table 758 and the DC bit is set in the MAC Configuration register Table 758  this bit indicates that the transmission ended because of excessive deferral of over.." "0,1"
newline
bitfld.long 0x0 2. "LCARR,Loss of Carrier When the DTXSTS bit is set in the MTL Operation Mode register Table 758  this bit indicates that the loss of carrier occurred during packet transmission  that is  the PHY Carrier signal was inactive for one or more transmission.." "0,1"
newline
bitfld.long 0x0 1. "NCARR,No Carrier When the DTXSTS bit is set in the MTL Operation Mode register Table 758  this bit indicates that the carrier signal from the PHY is not present at the end of preamble transmission." "0,1"
newline
bitfld.long 0x0 0. "TJT,PHY Interrupt Enable When this bit is set  it enables the assertion of the interrupt signal because of the setting of PHYIS bit in MAC Interrupt Status register Table 731." "0,1"
group.long 0xC0++0x7
line.long 0x0 "MAC_PMT_CRTL_STAT,no description available"
bitfld.long 0x0 31. "RWKFILTRST,Remote Wake-Up Packet Filter Register Pointer Reset When this bit is set  the remote wake-up packet filter register pointer is reset to 3'b000." "0,1"
newline
hexmask.long.byte 0x0 24.--28. 1. "RWKPTR,Remote Wake-up FIFO Pointer This field gives the current value (0 to 7) of the Remote Wake-up Packet Filter register pointer."
newline
bitfld.long 0x0 10. "RWKPFE,Remote Wake-up Packet Forwarding Enable When this bit is set along with RWKPKTEN  the MAC receiver drops all received frames until it receives the expected wake-up frame." "0,1"
newline
bitfld.long 0x0 9. "GLBLUCAST,Global Unicast When this bit set  any unicast packet filtered by the MAC (DAF) address recognition is detected as a remote wake-up packet." "0,1"
newline
rbitfld.long 0x0 6. "RWKPRCVD,Remote Wake-Up Packet Received." "0,1"
newline
rbitfld.long 0x0 5. "MGKPRCVD,Magic Packet Received." "0,1"
newline
rbitfld.long 0x0 2. "RWKPKTEN,Remote Wake-Up Packet Enable When this bit is set  a power management event is generated when the MAC receives a remote wake-up packet." "0,1"
newline
rbitfld.long 0x0 1. "MGKPKTEN,Magic Packet Enable." "0,1"
newline
rbitfld.long 0x0 0. "PWRDWN,Transmit LPI Entry When this bit is set  it indicates that the MAC Transmitter has entered the LPI state because of the setting of the LPIEN bit." "0,1"
line.long 0x4 "MAC_RWAKE_FRFLT,Remote wake-up frame filter"
hexmask.long 0x4 0.--31. 1. "ADDR,WKUPFMFILTER address."
group.long 0xD0++0xF
line.long 0x0 "MAC_LPI_CTRL_STAT,LPI Control and Status Register"
bitfld.long 0x0 21. "LPITCSE,LPI Tx Clock Stop Enable When this bit is set  the MAC asserts LPI Tx Clock Gating Control signal high after it enters Tx LPI mode to indicate that the Tx clock to MAC can be stopped." "0,1"
newline
bitfld.long 0x0 20. "LPIATE,LPI Timer Enable This bit controls the automatic entry of the MAC Transmitter into and exit out of the LPI state." "0,1"
newline
bitfld.long 0x0 19. "LPITXA,LPI Tx Automate This bit controls the behavior of the MAC when it is entering or coming out of the LPI mode on the Transmit side." "0,1"
newline
bitfld.long 0x0 17. "PLS,PHY Link Status This bit indicates the link status of the PHY." "0,1"
newline
bitfld.long 0x0 16. "LPIEN,LPI Enable When this bit is set  it instructs the MAC Transmitter to enter the LPI state." "0,1"
newline
rbitfld.long 0x0 9. "RLPIST,Receive LPI State When this bit is set  it indicates that the MAC is receiving the LPI pattern on the MII interface." "0,1"
newline
rbitfld.long 0x0 8. "TLPIST,Transmit LPI State When this bit is set  it indicates that the MAC is transmitting the LPI pattern on the MII interface." "0,1"
newline
rbitfld.long 0x0 3. "RLPIEX,Receive LPI Exit When this bit is set  it indicates that the MAC Receiver has stopped receiving the LPI pattern on the MII interface  exited the LPI state  and resumed the normal reception." "0,1"
newline
rbitfld.long 0x0 2. "RLPIEN,Receive LPI Entry When this bit is set  it indicates that the MAC Receiver has received an LPI pattern and entered the LPI state." "0,1"
newline
rbitfld.long 0x0 1. "TLPIEX,Transmit LPI Exit When this bit is set  it indicates that the MAC transmitter exited the LPI state after the application cleared the LPIEN bit and the LPI TW Timer has expired." "0,1"
newline
rbitfld.long 0x0 0. "TLPIEN,Transmit LPI Entry When this bit is set  it indicates that the MAC Transmitter has entered the LPI state because of the setting of the LPIEN bit." "0,1"
line.long 0x4 "MAC_LPI_TIMER_CTRL,LPI Timers Control register"
hexmask.long.word 0x4 16.--25. 1. "LST,LPI LS Timer This field specifies the minimum time (in milliseconds) for which the link status from the PHY should be up (OKAY) before the LPI pattern can be transmitted to the PHY."
newline
hexmask.long.word 0x4 0.--15. 1. "TWT,LPI TW Timer This field specifies the minimum time (in microseconds) for which the MAC waits after it stops transmitting the LPI pattern to the PHY and before it resumes the normal transmission."
line.long 0x8 "MAC_LPI_ENTR_TIMR,LPI entry Timer register"
hexmask.long.tbyte 0x8 3.--19. 1. "LPIET,LPI Entry Timer This field specifies the time in microseconds the MAC will wait to enter LPI mode  after it has transmitted all the frames."
line.long 0xC "MAC_1US_TIC_COUNTR,no description available"
hexmask.long.word 0xC 0.--11. 1. "TIC_1US_CNTR,1US TIC Counter The application must program this counter so that the number of clock cycles of CSR clock is 1us."
rgroup.long 0x110++0x7
line.long 0x0 "MAC_VERSION,MAC version register"
sif (cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
hexmask.long.byte 0x0 8.--15. 1. "USERVER,User defined version."
newline
hexmask.long.byte 0x0 0.--7. 1. "SNPVER,NXP defined version."
newline
endif
sif (cpuis("LPC54606*"))
hexmask.long.byte 0x0 8.--15. 1. "USERVER,User defined version."
newline
hexmask.long.byte 0x0 0.--7. 1. "SNPVER,NXP defined version."
newline
endif
sif (cpuis("LPC54608*"))
hexmask.long.byte 0x0 8.--15. 1. "USERVER,User defined version."
newline
hexmask.long.byte 0x0 0.--7. 1. "SNPVER,NXP defined version."
newline
endif
sif (cpuis("LPC54616*"))
hexmask.long.byte 0x0 8.--15. 1. "USERVER,User defined version."
newline
hexmask.long.byte 0x0 0.--7. 1. "SNPVER,NXP defined version."
newline
endif
sif (cpuis("LPC54618*"))
hexmask.long.byte 0x0 8.--15. 1. "USERVER,User defined version."
newline
hexmask.long.byte 0x0 0.--7. 1. "SNPVER,NXP defined version."
newline
endif
sif (cpuis("LPC54628*"))
hexmask.long.byte 0x0 8.--15. 1. "USERVER,User defined version."
newline
hexmask.long.byte 0x0 0.--7. 1. "SNPVER,NXP defined version."
endif
line.long 0x4 "MAC_DBG,MAC debug register"
bitfld.long 0x4 17.--18. "TFCSTS,MAC Transmit Packet Controller Status This field indicates the state of the MAC Transmit Packet Controller module." "0,1,2,3"
newline
bitfld.long 0x4 16. "TPESTS,MAC MII Transmit Protocol Engine Status When this bit is set  it indicates that the MAC or MII transmit protocol engine is actively transmitting data  and it is not in the Idle state." "0,1"
newline
bitfld.long 0x4 1.--2. "RFCFCSTS,MAC Receive Packet Controller FIFO Status When this bit is set  this field indicates the active state of the small FIFO Read and Write controllers of the MAC Receive Packet Controller module." "0,1,2,3"
newline
bitfld.long 0x4 0. "REPESTS,MAC MII Receive Protocol Engine Status When this bit is set  it indicates that the MAC MII receive protocol engine is actively receiving data  and it is not in the Idle state." "0,1"
rgroup.long 0x11C++0xB
line.long 0x0 "MAC_HW_FEAT0,MAC hardware feature register 0x0201"
rbitfld.long 0x0 28.--30. "ACTPHYSEL,Active PHY Selected." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 25.--26. "TSSTSSEL,Timestamp System Time Source." "0,1,2,3"
newline
sif (cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
rbitfld.long 0x0 16. "RXCOESEL,Receive Checksum Offload Support." "0,1"
newline
rbitfld.long 0x0 7. "MGKSEL,PMT magic packet detection." "0,1"
newline
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x0 16. "RXCOESEL,Receive Checksum Offload Support." "0,1"
newline
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x0 16. "RXCOESEL,Receive Checksum Offload Support." "0,1"
newline
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x0 16. "RXCOESEL,Receive Checksum Offload Support." "0,1"
newline
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x0 16. "RXCOESEL,Receive Checksum Offload Support." "0,1"
newline
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x0 16. "RXCOESEL,Receive Checksum Offload Support." "0,1"
newline
endif
rbitfld.long 0x0 14. "TXCOESEL,Transmit Checksum Offload Support." "0,1"
newline
rbitfld.long 0x0 13. "EEESEL,Energy Efficient Ethernet Support ." "0,1"
newline
rbitfld.long 0x0 12. "TSSEL,IEEE 1588-2008 Timestamp support ." "0,1"
newline
rbitfld.long 0x0 9. "ARPOFFSEL,ARP Offload Enabled." "0,1"
newline
rbitfld.long 0x0 8. "MMCSEL,RMON Module Enable." "0,1"
newline
sif (cpuis("LPC54606*"))
bitfld.long 0x0 7. "MGKSEL,PMT magic packet detection." "0,1"
newline
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x0 7. "MGKSEL,PMT magic packet detection." "0,1"
newline
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x0 7. "MGKSEL,PMT magic packet detection." "0,1"
newline
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x0 7. "MGKSEL,PMT magic packet detection." "0,1"
newline
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x0 7. "MGKSEL,PMT magic packet detection." "0,1"
newline
endif
rbitfld.long 0x0 6. "RWKSEL,PMT Remote Wake-up Packet Detection." "0,1"
newline
rbitfld.long 0x0 5. "SMASEL,SMA (MDIO) Interface." "0,1"
newline
rbitfld.long 0x0 4. "VLHASH,Hash Table Based Filtering option." "0,1"
newline
rbitfld.long 0x0 2. "HDSEL,Half-duplex Support." "0,1"
newline
rbitfld.long 0x0 0. "MIISEL,10 or 100 Mbps Support." "0,1"
line.long 0x4 "MAC_HW_FEAT1,MAC hardware feature register 0x0201"
hexmask.long.byte 0x4 27.--30. 1. "L3_L4_FILTER,Total Number of L3 and L4 Filters ."
newline
bitfld.long 0x4 24.--25. "HASHTBLSZ,Hash Table Size." "0,1,2,3"
newline
bitfld.long 0x4 23. "LPMODEEN,Low Power Mode Feature Support ." "0,1"
newline
bitfld.long 0x4 20. "AVSEL,Audio Video Bridging Feature." "0,1"
newline
bitfld.long 0x4 19. "DBGMEMA,DMA Debug Register Feature." "0,1"
newline
bitfld.long 0x4 18. "TSOEN,TCP Segment Offload Feature." "0,1"
newline
bitfld.long 0x4 17. "SPEN,Split Header Structure feature." "0,1"
newline
bitfld.long 0x4 16. "DCBEN,Data Center Bridging feature." "0,1"
newline
bitfld.long 0x4 14.--15. "ADDR64,Address width." "0,1,2,3"
newline
bitfld.long 0x4 13. "ADVTHWORD,IEEE 1588 High Word Register Feature." "0,1"
newline
bitfld.long 0x4 12. "PTOEN,PTP OffLoad Feature." "0,1"
newline
bitfld.long 0x4 11. "OSTEN,One-Step Timestamping Feature." "0,1"
newline
hexmask.long.byte 0x4 6.--10. 1. "TXFIFOSIZE,MTL Transmit FIFO Size."
newline
hexmask.long.byte 0x4 0.--4. 1. "RXFIFOSIZE,MTL Receive FIFO Size."
line.long 0x8 "MAC_HW_FEAT2,MAC hardware feature register 0x0201"
bitfld.long 0x8 28.--30. "AUXSNAPNUM,Number of Auxiliary Snapshot Inputs." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x8 24.--26. "PPSOUTNUM,Number of PPS Outputs." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x8 18.--21. 1. "TXCHCNT,Number of DMA Transmit Channels."
newline
hexmask.long.byte 0x8 12.--15. 1. "RXCHCNT,Number of DMA Receive Channels."
newline
hexmask.long.byte 0x8 6.--9. 1. "TXQCNT,Number of MTL Transmit Queues."
newline
hexmask.long.byte 0x8 0.--3. 1. "RXQCNT,Number of MTL Receive Queues."
group.long 0x200++0x7
line.long 0x0 "MAC_MDIO_ADDR,MIDO address Register"
bitfld.long 0x0 27. "PSE,Preamble Suppression Enable When this bit is set  the SMA will suppress the 32-bit preamble and transmit MDIO frames with only 1 preamble bit." "0,1"
newline
bitfld.long 0x0 26. "BTB,Back to Back transactions When this bit is set and the NTC has value greater than 0  then the MAC will inform the completion of a read or write command at the end of frame transfer (before the trailing clocks are transmitted)." "0,1"
newline
hexmask.long.byte 0x0 21.--25. 1. "PA,Physical Layer Address This field indicates which PHY devices (out of 32 devices) the MAC is accessing."
newline
hexmask.long.byte 0x0 16.--20. 1. "RDA,Register/Device Address These bits select the PHY register in selected PHY device."
newline
bitfld.long 0x0 12.--14. "NTC,Number of Training Clocks This field controls the number of trailing clock cycles generated on MDC after the end of transmission of MDIO frame." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 8.--11. 1. "CR,CSR Clock Range."
newline
bitfld.long 0x0 2.--3. "MOC,MII Operation Command." "0,1,2,3"
newline
bitfld.long 0x0 0. "MB,MII busy." "0,1"
line.long 0x4 "MAC_MDIO_DATA,MDIO Data register"
hexmask.long.word 0x4 0.--15. 1. "MD,MII Data This field contains the 16-bit data value read from the PHY after a Management Read operation or the 16-bit data value to be written to the PHY before a Management Write operation."
group.long 0x300++0x7
line.long 0x0 "MAC_ADDR_HIGH,MAC address0 high register"
rbitfld.long 0x0 31. "AE,Address Enable." "0,1"
newline
bitfld.long 0x0 16. "DCS,DMA Channel Select This field contains the DMA Channel number to which the Rx packet whose DA matches the MAC Address content is routed." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "A47_32,MAC Address0 [47:32] This field contains the upper 16 bits (47:32) of the 6-byte first MAC address."
line.long 0x4 "MAC_ADDR_LOW,MAC address0 low register"
hexmask.long 0x4 0.--31. 1. "A31_0,MAC Address0 [31:0] This field contains the lower 32 bits of the 6-byte first MAC address."
group.long 0xB00++0x7
line.long 0x0 "MAC_TIMESTAMP_CTRL,Time stamp control register"
bitfld.long 0x0 28. "AV8021ASMEN,AV 802." "0,1"
newline
bitfld.long 0x0 24. "TXTTSSTSM,Transmit Timestamp Status Mode When this bit is set  the MAC overwrites the earlier transmit timestamp status even if it is not read by the software." "0,1"
newline
bitfld.long 0x0 18. "TSENMACADDR,Enable MAC Address for PTP Packet Filtering When this bit is set  the DA MAC address (that matches any MAC Address register) is used to filter the PTP packets when PTP is directly sent over Ethernet." "0,1"
newline
bitfld.long 0x0 16.--17. "SNAPTYPSEL,Select PTP packets for Taking Snapshots These bits  along with Bits 15 and 14  decide the set of PTP packet types for which snapshot needs to be taken." "0,1,2,3"
newline
bitfld.long 0x0 15. "TSMSTRENA,Enable Snapshot for Messages Relevant to Master When this bit is set  the snapshot is taken only for the messages that are relevant to the master node." "0,1"
newline
bitfld.long 0x0 14. "TSEVTENA,Enable Timestamp Snapshot for Event Messages When this bit is set  the timestamp snapshot is taken only for event messages (SYNC  Delay_Req  Pdelay_Req  or Pdelay_Resp)." "0,1"
newline
bitfld.long 0x0 13. "TSIPV4ENA,Enable Processing of PTP Packets Sent over IPv4-UDP When this bit is set  the MAC receiver processes the PTP packets encapsulated in IPv4-UDP packets." "0,1"
newline
bitfld.long 0x0 12. "TSIPV6ENA,Enable Processing of PTP Packets Sent over 1Pv6-UDP When this bit is set  the MAC receiver processes the PTP packets encapsulated in IPv6-UDP packets." "0,1"
newline
bitfld.long 0x0 11. "TSIPENA,Enable Processing of PTP over Ethernet Packets When this bit is set  the MAC receiver processes the PTP packets encapsulated directly in the Ethernet packets." "0,1"
newline
bitfld.long 0x0 10. "TSVER2ENA,Enable PTP Packet Processing for Version 2 Format When this bit is set  the IEEE 1588 version 2 format is used to process the PTP packets." "0,1"
newline
bitfld.long 0x0 9. "TSCTRLSSR,Timestamp Digital or Binary Rollover Control When this bit is set  the Timestamp Low register rolls over after 0x3B9AC9FF value (that is  1 nanosecond accuracy) and increments the timestamp (High) seconds." "0,1"
newline
bitfld.long 0x0 8. "TSENALL,Enable Timestamp for All Packets When this bit is set  the timestamp snapshot is enabled for all packets received by the MAC." "0,1"
newline
bitfld.long 0x0 5. "TADDREG,Update Addend Register When this bit is set  the content of the Timestamp Addend register is updated in the PTP block for fine correction." "0,1"
newline
bitfld.long 0x0 4. "TSTRIG,Enable Timestamp Interrupt Trigger When this bit is set  the timestamp interrupt is generated when the System Time becomes greater than the value written in the Target Time register." "0,1"
newline
bitfld.long 0x0 3. "TSUPDT,Update Timestamp When this bit is set  the system time is updated (added or subtracted) with the value specified in MAC System Time Seconds Update Table 753 and MAC System Time Nanoseconds Update Table 754." "0,1"
newline
bitfld.long 0x0 2. "TSINIT,Initialize Timestamp When this bit is set  the system time is initialized (overwritten) with the value specified in the MAC Register 80 (System Time Seconds Update." "0,1"
newline
bitfld.long 0x0 1. "TSCFUPDT,Fine or Coarse Timestamp Update When this bit is set  the Fine method is used to update system timestamp." "0,1"
newline
bitfld.long 0x0 0. "TSENA,Enable Timestamp When this bit is set  the timestamp is added for Transmit and Receive packets." "0,1"
line.long 0x4 "MAC_SUB_SCND_INCR,Sub-second increment register"
hexmask.long.byte 0x4 16.--23. 1. "SSINC,Sub-second increment value."
rgroup.long 0xB08++0x7
line.long 0x0 "MAC_SYS_TIME_SCND,System time seconds register"
hexmask.long 0x0 0.--31. 1. "TSS,Time stamp second The value in this field indicates the current value in seconds of the System Time maintained by the MAC."
line.long 0x4 "MAC_SYS_TIME_NSCND,System time nanoseconds register"
hexmask.long 0x4 0.--30. 1. "TSSS,Time stamp sub seconds The value in this field has the sub second representation of time  with an accuracy of 0."
group.long 0xB10++0xF
line.long 0x0 "MAC_SYS_TIME_SCND_UPD,no description available"
hexmask.long 0x0 0.--31. 1. "TSS,Time stamp second The value in this field indicates the time  in seconds  to be initialized or added to the system time."
line.long 0x4 "MAC_SYS_TIME_NSCND_UPD,no description available"
bitfld.long 0x4 31. "ADDSUB,Add or subtract time When this bit is set  the time value is subtracted with the contents of the update register." "0,1"
newline
hexmask.long 0x4 0.--30. 1. "TSSS,Time stamp sub seconds The value in this field has the sub second representation of time  with an accuracy of 0."
line.long 0x8 "MAC_SYS_TIMESTMP_ADDEND,Time stamp addend register"
hexmask.long 0x8 0.--31. 1. "TSAR,Time stamp addend This register indicates the 32-bit time value to be added to the Accumulator register to achieve time synchronization."
line.long 0xC "MAC_SYS_TIME_HWORD_SCND,no description available"
hexmask.long.word 0xC 0.--15. 1. "TSHWR,Time stamp higher word Contains the most significant 16-bits of the Time stamp seconds value."
rgroup.long 0xB20++0x3
line.long 0x0 "MAC_SYS_TIMESTMP_STAT,Time stamp status register"
bitfld.long 0x0 0. "TSSOVF,Time stamp seconds overflow When set  indicates that the seconds value of the Time stamp has overflowed beyond 0xFFFF_FFFF." "0,1"
rgroup.long 0xB30++0x7
line.long 0x0 "MAC_Tx_TIMESTAMP_STATUS_NANOSECONDS,Tx timestamp status nanoseconds"
bitfld.long 0x0 31. "TXTSSTSMIS,Transmit timestamp status missed." "0,1"
newline
hexmask.long 0x0 0.--30. 1. "TXTSSTSLO,Transmit timestamp status low."
line.long 0x4 "MAC_Tx_TIMESTAMP_STATUS_SECONDS,Tx timestamp status seconds"
hexmask.long 0x4 0.--31. 1. "TXTSSTSHI,Transmit timestamp status high."
group.long 0xB58++0x7
line.long 0x0 "MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND,Timestamp ingress correction"
hexmask.long 0x0 0.--31. 1. "TSIC,Transmit ingress correction."
line.long 0x4 "MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND,Timestamp egress correction"
hexmask.long 0x4 0.--31. 1. "TSEC,Transmit egress correction."
group.long 0xC00++0x3
line.long 0x0 "MTL_OP_MODE,MTL Operation Mode Register"
bitfld.long 0x0 9. "CNTCLR,Counters Reset When this bit is set  all counters are reset." "0,1"
newline
bitfld.long 0x0 8. "CNTPRST,Counters Preset When this bit is set  MTL TxQ0 Underflow register (Table 762) and MTL_TxQ1_Underflow (Table 762) registers are initialized/preset to 0x7F0." "0,1"
newline
bitfld.long 0x0 5.--6. "SCHALG,Tx Scheduling Algorithm This field indicates the algorithm for Tx scheduling: 0x00: WRR algorithm 0x1: Reserved 0x2: Reserved 0x3: Strict priority algorithm." "0: WRR algorithm,1: Reserved,2: Reserved,3: Strict priority algorithm"
newline
rbitfld.long 0x0 2. "RAA,Receive Arbitration Algorithm This field is used to select the arbitration algorithm for the Rx side." "0,1"
newline
bitfld.long 0x0 1. "DTXSTS,Drop Transmit Status When this bit is set  the Tx packet status received from the MAC is dropped in the MTL." "0,1"
rgroup.long 0xC20++0x3
line.long 0x0 "MTL_INTR_STAT,MTL Interrupt Status register"
bitfld.long 0x0 1. "Q1IS,Queue 1 Interrupt status This bit indicates that there is an interrupt from Queue 1." "0,1"
newline
bitfld.long 0x0 0. "Q0IS,Queue 0 Interrupt status This bit indicates that there is an interrupt from Queue 0." "0,1"
group.long 0xC30++0x3
line.long 0x0 "MTL_RXQ_DMA_MAP,MTL Receive Queue and DMA Channel Mapping register"
bitfld.long 0x0 12. "Q1DDMACH,Queue 1 Enabled for DA-based DMA Channel Selection When set  this bit indicates that the packets received in Queue 1 are routed to a particular DMA channel as decided in the MAC Receiver based on the DMA channel number programmed in the L3-L4.." "0,1"
newline
bitfld.long 0x0 8. "Q1MDMACH,Queue 1 Mapped to DMA Channel This field controls the routing of the received packet in Queue 1 to the DMA channel: 0: DMA Channel 0 1: DMA Channel 1 This field is valid when the Q1DDMACH field is reset." "0: DMA Channel 0,1: DMA Channel 1 This field is valid when the.."
newline
bitfld.long 0x0 4. "Q0DDMACH,Queue 0 Enabled for DA-based DMA Channel Selection When set  this bit indicates that the packets received in Queue 0 are routed to a particular DMA channel as decided in the MAC Receiver based on the DMA channel number programmed in the L3-L4.." "0,1"
newline
bitfld.long 0x0 0. "Q0MDMACH,Queue 0 Mapped to DMA Channel This field controls the routing of the packet received in Queue 0 to the DMA channel: 0: DMA Channel 0 1: DMA Channel 1 This field is valid when the Q0DDMACH field is reset." "0: DMA Channel 0,1: DMA Channel 1 This field is valid when the.."
repeat 2. (list 0x0 0x1)(list ad:0x40092D00 ad:0x40092D40)
tree "MTL_QUEUE[$1]"
base $2
group.long ($2)++0x3
line.long 0x0 "MTL_TXQx_OP_MODE,MTL TxQx Operation Mode register"
bitfld.long 0x0 16.--18. "TQS,Transmit Queue Size This field indicates the size of the allocated Transmit queues in blocks of 256 bytes." "0,1,2,3,4,5,6,7"
bitfld.long 0x0 4.--6. "TTC,Transmit Threshold Control These bits control the threshold level of the MTL Tx Queue." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 2.--3. "TXQEN,Transmit Queue Enable This field is used to enable/disable the transmit queue 0." "0,1,2,3"
bitfld.long 0x0 1. "TSF,Transmit Store and Forward When this bit is set  the transmission starts when a full packet resides in the MTL Tx queue." "0,1"
newline
bitfld.long 0x0 0. "FTQ,Flush Transmit Queue When this bit is set  the Tx queue controller logic is reset to its default values." "0,1"
rgroup.long ($2+0x4)++0x7
line.long 0x0 "MTL_TXQx_UNDRFLW,MTL TxQx Underflow register"
bitfld.long 0x0 11. "UFCNTOVF,Overflow Bit for Underflow Packet Counter This bit is set every time the Tx queue Underflow Packet Counter field overflows  that is  it has crossed the maximum count." "0,1"
hexmask.long.word 0x0 0.--10. 1. "UFFRMCNT,Underflow Packet Counter This field indicates the number of packets aborted by the controller because of Tx Queue Underflow."
line.long 0x4 "MTL_TXQx_DBG,MTL TxQx Debug register"
bitfld.long 0x4 20.--22. "STSXSTSF,Number of Status Words in Tx Status FIFO of Queue This field indicates the current number of status in the Tx Status FIFO of this queue." "0,1,2,3,4,5,6,7"
bitfld.long 0x4 16.--18. "PTXQ,Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx Queue." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 5. "TXSTSFSTS,MTL Tx Status FIFO Full Status When high  this bit indicates that the MTL Tx Status FIFO is full." "0,1"
bitfld.long 0x4 4. "TXQSTS,MTL Tx Queue Not Empty Status When this bit is high  it indicates that the MTL Tx Queue is not empty and some data is left for transmission." "0,1"
newline
bitfld.long 0x4 3. "TWCSTS,MTL Tx Queue Write Controller Status When high  this bit indicates that the MTL Tx Queue Write Controller is active  and it is transferring the data to the Tx Queue." "0,1"
bitfld.long 0x4 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read Controller: 00: Idle state 01: Read state (transferring data to the MAC transmitter) 10: Waiting for pending Tx Status from the MAC transmitter 11: Flushing.." "0: Idle state,1: Read state,?,?"
newline
bitfld.long 0x4 0. "TXQPAUSED,Transmit Queue in Pause When this bit is high and the Rx flow control is enabled  it indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because of the following: - Reception of the PFC packet for the priorities.." "0,1"
group.long ($2+0x10)++0x3
line.long 0x0 "MTL_TXQx_ETS_CTRL,MTL TxQx ETS control register. only TxQ1 support"
rbitfld.long 0x0 4.--6. "SLC,Credit Control." "0,1,2,3,4,5,6,7"
bitfld.long 0x0 3. "CC,Credit Control." "0,1"
newline
bitfld.long 0x0 2. "AVALG,AV Algorithm." "0,1"
rgroup.long ($2+0x14)++0x3
line.long 0x0 "MTL_TXQx_ETS_STAT,MTL TxQx ETS Status register"
hexmask.long.tbyte 0x0 0.--23. 1. "ABS,Average Bits per Slot."
group.long ($2+0x18)++0xF
line.long 0x0 "MTL_TXQx_QNTM_WGHT,no description available"
hexmask.long.tbyte 0x0 0.--20. 1. "ISCQW,Average Bits per Slot."
line.long 0x4 "MTL_TXQx_SNDSLP_CRDT,MTL TxQx SendSlopCredit register. only TxQ1 support"
hexmask.long.word 0x4 0.--13. 1. "SSC,sendSlopeCredit."
line.long 0x8 "MTL_TXQx_HI_CRDT,MTL TxQx hiCredit register. only TxQ1 support"
hexmask.long 0x8 0.--28. 1. "HC,hiCredit."
line.long 0xC "MTL_TXQx_LO_CRDT,MTL TxQx loCredit register. only TxQ1 support"
hexmask.long 0xC 0.--28. 1. "LC,loCredit."
group.long ($2+0x2C)++0x7
line.long 0x0 "MTL_TXQx_INTCTRL_STAT,no description available"
bitfld.long 0x0 24. "RXOIE,Receive Queue Overflow Interrupt Enable When this bit is set  the Receive Queue Overflow interrupt is enabled." "0,1"
bitfld.long 0x0 16. "RXOVFIS,Receive Queue Overflow Interrupt Status This bit indicates that the Receive Queue had an overflow while receiving the packet." "0,1"
newline
bitfld.long 0x0 9. "ABPSIE,Average Bits Per Slot Interrupt Enable When this bit is set  the MAC asserts the interrupt when the average bits per slot status is updated." "0,1"
bitfld.long 0x0 8. "TXUIE,Transmit Queue Underflow Interrupt Enable When this bit is set  the Transmit Queue Underflow interrupt is enabled." "0,1"
newline
bitfld.long 0x0 1. "ABPSIS,Average Bits Per Slot Interrupt Status When set  this bit indicates that the MAC has updated the ABS value." "0,1"
bitfld.long 0x0 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status This bit indicates that the Transmit Queue had an underflow while transmitting the packet." "0,1"
line.long 0x4 "MTL_RXQx_OP_MODE,MTL RxQx Operation Mode register"
bitfld.long 0x4 20.--22. "RQS,This field indicates the size of the allocated Receive queues in blocks of 256 bytes." "0,1,2,3,4,5,6,7"
bitfld.long 0x4 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets When this bit is set  the MAC does not drop the packets which only have the errors detected by the Receive Checksum Offload engine." "0,1"
newline
bitfld.long 0x4 5. "RSF,Receive Queue Store and Forward When this bit is set  the ethernet block on this chip reads a packet from the Rx queue only after the complete packet has been written to it  ignoring the RTC field of this register." "0,1"
bitfld.long 0x4 4. "FEP,Forward Error Packets When this bit is reset  the Rx queue drops packets with error status (CRC error  Mll_ER  watchdog timeout  or overflow)." "0,1"
newline
bitfld.long 0x4 3. "FUP,Forward Undersized Good Packets When this bit is set  the Rx queue forwards the undersized good packets (packets with no error and length less than 64 bytes)  including pad-bytes and CRC." "0,1"
bitfld.long 0x4 0.--1. "RTC,Receive Queue Threshold Control These bits control the threshold level of the MTL Rx queue (in bytes): 00: 64 01: 32 10: 96 11: 128 The packet received is transferred to the application or DMA when the packet size within the MTL Rx queue is larger.." "0: 64,1: 32,?,?"
rgroup.long ($2+0x34)++0x7
line.long 0x0 "MTL_RXQx_MISSPKT_OVRFLW_CNT,MTL RxQx Missed Packet Overflow Counter register"
bitfld.long 0x0 11. "OVFCNTOVF,Overflow Counter Overflow Bit When set  this bit indicates that the Rx Queue Overflow Packet Counter field crossed the maximum limit." "0,1"
hexmask.long.word 0x0 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter This field indicates the number of packets discarded by the Ethernet block because of Receive queue overflow."
line.long 0x4 "MTL_RXQx_DBG,MTL RxQx Debug register"
hexmask.long.word 0x4 16.--29. 1. "PRXQ,Number of Packets in Receive Queue This field indicates the current number of packets in the Rx Queue."
bitfld.long 0x4 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status This field gives the status of the fill-level of the Rx Queue: 0x0: Rx Queue empty 0x1: Rx Queue fill-level below flow-control deactivate threshold 0x2: Rx Queue fill-level above flow-control activate threshold 0x3:.." "0: Rx Queue empty,1: Rx Queue fill-level below flow-control..,2: Rx Queue fill-level above flow-control activate..,3: Rx Queue full"
newline
bitfld.long 0x4 1.--2. "RRCSTS,MTL Rx Queue Read Controller State This field gives the state of the Rx queue Read controller: 00: Idle state 01: Reading packet data 10: Reading packet status (or timestamp) 11: Flushing the packet data and status." "0: Idle state,1: Reading packet data,?,?"
bitfld.long 0x4 0. "RWCSTS,MTL Rx Queue Write Controller Active Status When high  this bit indicates that the MTL Rx queue Write controller is active  and it is transferring a received packet to the Rx Queue." "0,1"
group.long ($2+0x3C)++0x3
line.long 0x0 "MTL_RXQx_CTRL,MTL RxQx Control register"
bitfld.long 0x0 3. "RXQ_FRM_ARBIT,Receive Queue Packet Arbitration When this bit is set  the The ethernet block drives the packet data to the ARI interface such that the entire packet data of currently-selected queue is transmitted before switching to other queue." "0,1"
bitfld.long 0x0 0.--2. "RXQ_WEGT,Receive Queue Weight This field indicates the weight assigned to the Rx Queue 0." "0,1,2,3,4,5,6,7"
tree.end
repeat.end
base ad:0x40092000
group.long 0x1000++0xF
line.long 0x0 "DMA_MODE,DMA mode register"
bitfld.long 0x0 12.--14. "PR,Priority Ratio These bits control the priority ratio in weighted round-robin arbitration between the Rx DMA and Tx DMA." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 11. "TXPR,Transmit Priority When set  this bit indicates that the Tx DMA has higher priority than the Rx DMA during arbitration for the system-side bus." "0,1"
newline
bitfld.long 0x0 2.--4. "TAA,Transmit Arbitration Algorithm This field is used to select the arbitration algorithm for the Transmit side when multiple Tx DMAs are selected." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 1. "DA,DMA Tx or Rx Arbitration Scheme This bit specifies the arbitration scheme between the Transmit and Receive paths of all channels: The Tx path has priority over the Rx path when the TXPR bit is set." "0,1"
newline
bitfld.long 0x0 0. "SWR,Software Reset When this bit is set  the MAC and the OMA controller reset the logic and all internal registers of the OMA  MTL  and MAC." "0,1"
line.long 0x4 "DMA_SYSBUS_MODE,DMA System Bus mode"
bitfld.long 0x4 15. "RB,Rebuild INCRx Burst When this bit is set high and the AHB master gets SPLIT  RETRY  or EarlyBurst Termination (EBT) response  the AHB master interface rebuilds the pending beats of any initiated burst transfer with INCRx and SINGLEtransfers." "0,1"
newline
bitfld.long 0x4 14. "MB,Mixed Burst When this bit is set high and the FB bit is low  the AHB master performs undefined bursts transfers (INCR) for burst length of 16 or more." "0,1"
newline
bitfld.long 0x4 12. "AAL,Address-Aligned Beats When this bit is set to 1  the AHB master performs address-aligned burst transfers on Read and Write channels." "0,1"
newline
bitfld.long 0x4 0. "FB,Fixed Burst Length When this bit is set to 1  the AHB master will initiate burst transfers of specified length (INCRx or SINGLE)." "0,1"
line.long 0x8 "DMA_INTR_STAT,DMA Interrupt status"
rbitfld.long 0x8 17. "MACIS,MAC Interrupt Status This bit indicates an interrupt event in the MAC." "0,1"
newline
rbitfld.long 0x8 16. "MTLIS,MTL Interrupt Status This bit indicates an interrupt event in the MTL." "0,1"
newline
bitfld.long 0x8 1. "DC1IS,DMA Channel 1 Interrupt Status This bit indicates an interrupt event in DMA Channel 1." "0,1"
newline
bitfld.long 0x8 0. "DC0IS,DMA Channel 0 Interrupt Status This bit indicates an interrupt event in DMA Channel 0." "0,1"
line.long 0xC "DMA_DBG_STAT,DMA Debug Status"
hexmask.long.byte 0xC 20.--23. 1. "TPS1,DMA Channel 1 Transmit Process State This field indicates the Tx DMA FSM state for Channel 1."
newline
hexmask.long.byte 0xC 16.--19. 1. "RPS1,DMA Channel 1 Receive Process State This field indicates the Rx DMA FSM state for Channel 1."
newline
hexmask.long.byte 0xC 12.--15. 1. "TPS0,DMA Channel 0 Transmit Process State This field indicates the Tx DMA FSM state for Channel 0: 000: Stopped (Reset or Stop Transmit Command issued) 0x1: Running (Fetching Tx Transfer) 0x2: Running (Waiting for status) 0x3: Running (Reading Data from.."
newline
hexmask.long.byte 0xC 8.--11. 1. "RPS0,DMA Channel 0 Receive Process State This field indicates the Rx DMA FSM state for Channel 0: 0x0: Stopped (Reset or Stop Receive Command issued) 0x1: Running (Fetching Rx Transfer ) 0x2: Reserved 0x3: Running (Waiting for Rx packet) 0x4: Suspended.."
newline
sif (cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
rbitfld.long 0xC 0. "AHSTS,AHB Master Status When high  this bit indicates that the AHB master FSMs are in the non-idle state." "0,1"
newline
endif
sif (cpuis("LPC54608*"))
bitfld.long 0xC 0. "AHSTS,AHB Master Status When high  this bit indicates that the AHB master FSMs are in the non-idle state." "0,1"
newline
endif
sif (cpuis("LPC54616*"))
bitfld.long 0xC 0. "AHSTS,AHB Master Status When high  this bit indicates that the AHB master FSMs are in the non-idle state." "0,1"
newline
endif
sif (cpuis("LPC54618*"))
bitfld.long 0xC 0. "AHSTS,AHB Master Status When high  this bit indicates that the AHB master FSMs are in the non-idle state." "0,1"
newline
endif
sif (cpuis("LPC54628*"))
bitfld.long 0xC 0. "AHSTS,AHB Master Status When high  this bit indicates that the AHB master FSMs are in the non-idle state." "0,1"
newline
endif
sif (cpuis("LPC54606*"))
bitfld.long 0xC 0. "AHSTS,AHB Master Status When high  this bit indicates that the AHB master FSMs are in the non-idle state." "0,1"
endif
repeat 2. (list 0x0 0x1)(list ad:0x40093100 ad:0x40093180)
tree "DMA_CH[$1]"
base $2
group.long ($2)++0xB
line.long 0x0 "DMA_CHx_CTRL,DMA Channelx Control"
bitfld.long 0x0 18.--20. "DSL,Skip Length This bit specifies the Word  Dword  or Lword number (depending on the 32- bit  64-bit  or 128-bit bus) to skip between two unchained s." "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16. "PBLx8,8xPBL mode When this bit is set  the PBL value programmed in Bits[21:16] in DMA Channel Transmit Control Table 780 is multiplied eight times." "0,1"
line.long 0x4 "DMA_CHx_TX_CTRL,DMA Channelx Transmit Control"
hexmask.long.byte 0x4 16.--21. 1. "TxPBL,Transmit Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA data transfer."
bitfld.long 0x4 4. "OSF,Operate on Second Frame When this bit is set  it instructs the DMA to process the second packet of the Transmit data even before the status for the first packet is obtained." "0,1"
bitfld.long 0x4 1.--3. "TCW,Transmit Channel Weight This field indicates the weight assigned to the corresponding Transmit channel." "0,1,2,3,4,5,6,7"
bitfld.long 0x4 0. "ST,Start or Stop Transmission Command When this bit is set  transmission is placed in the Running state." "0,1"
line.long 0x8 "DMA_CHx_RX_CTRL,DMA Channelx Receive Control"
bitfld.long 0x8 31. "RPF,DMA Rx Channel 0 Packet Flush When this bit is set to 1  the DMA will automatically flush the packet from the Rx Queues destined to DMA Rx Channel 0 when the DMA Rx Channel 0 is stopped after a system bus error has occurred." "0,1"
hexmask.long.byte 0x8 16.--21. 1. "RxPBL,Receive Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA data transfer."
hexmask.long.word 0x8 3.--14. 1. "RBSZ,Receive Buffer size This field indicates the size of the Rx buffers specified in bytes."
bitfld.long 0x8 0. "SR,Start or Stop Receive When this bit is set  the DMA tries to acquire the from the receive list and processes the incoming packets." "0,1"
group.long ($2+0x14)++0x3
line.long 0x0 "DMA_CHx_TXDESC_LIST_ADDR,no description available"
hexmask.long 0x0 2.--31. 1. "STL,Start of transmit list This field contains the base address of the first in the Transmit list."
group.long ($2+0x1C)++0x7
line.long 0x0 "DMA_CHx_RXDESC_LIST_ADDR,no description available"
hexmask.long 0x0 2.--31. 1. "SRL,Start of receive list This field contains the base address of the First in the Receive list."
line.long 0x4 "DMA_CHx_TXDESC_TAIL_PTR,no description available"
hexmask.long 0x4 2.--31. 1. "TDTP,Transmit Tail Pointer This field contains the tail pointer for the Tx ring."
group.long ($2+0x28)++0x17
line.long 0x0 "DMA_CHx_RXDESC_TAIL_PTR,no description available"
hexmask.long 0x0 2.--31. 1. "RDTP,Receive Tail Pointer This field contains the tail pointer for the Rx ring."
line.long 0x4 "DMA_CHx_TXDESC_RING_LENGTH,no description available"
hexmask.long.word 0x4 0.--9. 1. "TDRL,Transmit Ring Length This field sets the maximum number of Tx descriptors in the circular ring."
line.long 0x8 "DMA_CHx_RXDESC_RING_LENGTH,Channelx Rx descriptor Ring Length"
hexmask.long.word 0x8 0.--9. 1. "RDRL,Receive Ring Length This register sets the maximum number of Rx descriptors in the circular ring."
line.long 0xC "DMA_CHx_INT_EN,Channelx Interrupt Enable"
bitfld.long 0xC 15. "NIE,Normal interrupt summary enable When this bit is set  a normal interrupt is enabled." "0,1"
bitfld.long 0xC 14. "AIE,Abnormal interrupt summary enable When this bit is set  an Abnormal Interrupt summary is enabled." "0,1"
bitfld.long 0xC 12. "FBEE,Fatal bus error enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register)  the Fatal Bus Error Interrupt is enabled." "0,1"
bitfld.long 0xC 11. "ERIE,Early receive interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register)  Early Receive Interrupt is enabled." "0,1"
bitfld.long 0xC 10. "ETIE,Early transmit interrupt enable When this bit is set with an Abnormal Interrupt Summary Enable (bit 15 in this register)  Early Transmit Interrupt is enabled." "0,1"
bitfld.long 0xC 9. "RWTE,Receive watchdog timeout enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register)  the Receive Watchdog Timeout Interrupt is enabled." "0,1"
newline
bitfld.long 0xC 8. "RSE,Received stopped enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register)  Receive Stopped Interrupt is enabled." "0,1"
bitfld.long 0xC 7. "RBUE,Receive buffer unavailable enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register)  Receive Buffer Unavailable Interrupt is enabled." "0,1"
bitfld.long 0xC 6. "RIE,Receive interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register)  Receive Interrupt is enabled." "0,1"
bitfld.long 0xC 2. "TBUE,Transmit buffer unavailable enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register)  Transmit Buffer Unavailable Interrupt is enabled." "0,1"
bitfld.long 0xC 1. "TSE,Transmit stopped enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register)  Transmission Stopped Interrupt is enabled." "0,1"
bitfld.long 0xC 0. "TIE,Transmit interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register)  Transmit Interrupt is enabled." "0,1"
line.long 0x10 "DMA_CHx_RX_INT_WDTIMER,Receive Interrupt Watchdog Timer"
hexmask.long.byte 0x10 0.--7. 1. "RIWT,Receive Interrupt Watchdog Timer Count Indicates the number of system clock cycles multiplied by 256 for which the watchdog timer is set."
line.long 0x14 "DMA_CHx_SLOT_FUNC_CTRL_STAT,Slot Function Control and Status"
hexmask.long.byte 0x14 16.--19. 1. "RSN,Reference Slot Number This field gives the current value of the reference slot number in the DMA."
bitfld.long 0x14 1. "ASC,Advance Slot Check When set  this bit enables the D MA to fetch the data from the buffer when the slot number (SLOTNUM) programmed in the Tx descriptor is equal to the reference slot number given in the RSN field or  ahead of the reference slot.." "0,1"
bitfld.long 0x14 0. "ESC,Enable Slot Comparison When set  this bit enables the checking of the slot numbers programmed in the Tx descriptor with the current reference given in the RSN field." "0,1"
rgroup.long ($2+0x44)++0x3
line.long 0x0 "DMA_CHx_CUR_HST_TXDESC,Channelx Current Host Transmit descriptor"
hexmask.long 0x0 0.--31. 1. "HTD,Host Transmit descriptor Address Pointer Cleared on Reset."
rgroup.long ($2+0x4C)++0x3
line.long 0x0 "DMA_CHx_CUR_HST_RXDESC,no description available"
hexmask.long 0x0 0.--31. 1. "HRD,Host Receive descriptor Address Pointer Cleared on Reset."
rgroup.long ($2+0x54)++0x3
line.long 0x0 "DMA_CHx_CUR_HST_TXBUF,no description available"
hexmask.long 0x0 0.--31. 1. "HTB,Host Transmit Buffer Address Pointer Cleared on Reset."
rgroup.long ($2+0x5C)++0x3
line.long 0x0 "DMA_CHx_CUR_HST_RXBUF,Channelx Current Application Receive Buffer Address"
hexmask.long 0x0 0.--31. 1. "HRB,Host Receive Buffer Address Pointer Cleared on Reset."
group.long ($2+0x60)++0x3
line.long 0x0 "DMA_CHx_STAT,Channelx DMA status register"
bitfld.long 0x0 16.--18. "EB,DMA Error Bits This field indicates the type of error that caused a Bus Error." "0,1,2,3,4,5,6,7"
bitfld.long 0x0 15. "NIS,Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in the DMA Channel Interrupt Enable register Table 778: Bit 0: Transmit Interrupt Bit 2: Transmit.." "0: Transmit Interrupt Bit,?"
bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA Channel Interrupt Enable register Table 778: Bit 1: Transmit Process Stopped Bit 7:.." "?,1: Transmit Process Stopped Bit"
bitfld.long 0x0 12. "FBE,Fatal Bus Error This bit indicates that a bus error occurred (as described in the EB field)." "0,1"
bitfld.long 0x0 11. "ERI,Early Receive Interrupt This bit indicates that the DMA filled the first data buffer of the packet." "0,1"
bitfld.long 0x0 10. "ETI,Early Transmit Interrupt This bit indicates that the packet to be transmitted is fully transferred to the MTL Tx FIFO." "0,1"
newline
bitfld.long 0x0 9. "RWT,Receive Watchdog time out This bit is asserted when a packet with length greater than 2 048 bytes (10 240 bytes when Jumbo Packet mode is enabled) is received." "0,1"
bitfld.long 0x0 8. "RPS,Receive Process Stopped This bit is asserted when the Rx process enters the Stopped state." "0,1"
bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable This bit indicates that the application owns the next in the receive list  and the DMA cannot acquire it." "0,1"
bitfld.long 0x0 6. "RI,Receive Interrupt This bit indicates that the packet reception is complete." "0,1"
bitfld.long 0x0 2. "TBU,Transmit Buffer Unavailable This bit indicates that the application owns the next descriptor in the transmit list  and the DMA cannot acquire it." "0,1"
bitfld.long 0x0 1. "TPS,Transmit Process Stopped This bit is set when the transmission is stopped." "0,1"
newline
bitfld.long 0x0 0. "TI,Transmit Interrupt This bit indicates that the packet transmission is complete." "0,1"
group.long ($2+0x6C)++0x3
line.long 0x0 "DMA_CHx_MISS_FRAME_CNT,Channelx missed frame count."
bitfld.long 0x0 15. "MFCO,Overflow status of the MFC counter." "0,1"
hexmask.long.word 0x0 0.--10. 1. "MFC,Dropped packet counters."
tree.end
repeat.end
base ad:0x40092000
sif (cpuis("LPC54606*"))
group.long 0x110++0x3
line.long 0x0 "MAC_VERSION,MAC version register"
endif
sif (cpuis("LPC54606*"))
rgroup.long 0x11C++0x3
line.long 0x0 "MAC_HW_FEAT0,MAC hardware feature register 0x0201"
bitfld.long 0x0 28.--30. "ACTPHYSEL,Active PHY Selected." "0,1,2,3,4,5,6,7"
bitfld.long 0x0 25.--26. "TSSTSSEL,Timestamp System Time Source." "0,1,2,3"
newline
bitfld.long 0x0 14. "TXCOESEL,Transmit Checksum Offload Support." "0,1"
bitfld.long 0x0 13. "EEESEL,Energy Efficient Ethernet Support ." "0,1"
newline
bitfld.long 0x0 12. "TSSEL,IEEE 1588-2008 Timestamp support ." "0,1"
bitfld.long 0x0 9. "ARPOFFSEL,ARP Offload Enabled." "0,1"
newline
bitfld.long 0x0 8. "MMCSEL,RMON Module Enable." "0,1"
bitfld.long 0x0 6. "RWKSEL,PMT Remote Wake-up Packet Detection." "0,1"
newline
bitfld.long 0x0 5. "SMASEL,SMA (MDIO) Interface." "0,1"
bitfld.long 0x0 4. "VLHASH,Hash Table Based Filtering option." "0,1"
newline
bitfld.long 0x0 2. "HDSEL,Half-duplex Support." "0,1"
bitfld.long 0x0 0. "MIISEL,10 or 100 Mbps Support." "0,1"
endif
sif (cpuis("LPC54606*"))
repeat 2. (list 0x0 0x1)(list ad:0x40092D00 ad:0x40092D40)
tree "MTL_QUEUE[$1]"
base $2
group.long ($2)++0x3
line.long 0x0 "MTL_TXQx_OP_MODE,MTL TxQx Operation Mode register"
bitfld.long 0x0 16.--18. "TQS,Transmit Queue Size This field indicates the size of the allocated Transmit queues in blocks of 256 bytes." "0,1,2,3,4,5,6,7"
bitfld.long 0x0 4.--6. "TTC,Transmit Threshold Control These bits control the threshold level of the MTL Tx Queue." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 2.--3. "TXQEN,Transmit Queue Enable This field is used to enable/disable the transmit queue 0." "0,1,2,3"
bitfld.long 0x0 1. "TSF,Transmit Store and Forward When this bit is set  the transmission starts when a full packet resides in the MTL Tx queue." "0,1"
newline
bitfld.long 0x0 0. "FTQ,Flush Transmit Queue When this bit is set  the Tx queue controller logic is reset to its default values." "0,1"
rgroup.long ($2+0x4)++0x7
line.long 0x0 "MTL_TXQx_UNDRFLW,MTL TxQx Underflow register"
bitfld.long 0x0 11. "UFCNTOVF,Overflow Bit for Underflow Packet Counter This bit is set every time the Tx queue Underflow Packet Counter field overflows  that is  it has crossed the maximum count." "0,1"
hexmask.long.word 0x0 0.--10. 1. "UFFRMCNT,Underflow Packet Counter This field indicates the number of packets aborted by the controller because of Tx Queue Underflow."
line.long 0x4 "MTL_TXQx_DBG,MTL TxQx Debug register"
bitfld.long 0x4 20.--22. "STSXSTSF,Number of Status Words in Tx Status FIFO of Queue This field indicates the current number of status in the Tx Status FIFO of this queue." "0,1,2,3,4,5,6,7"
bitfld.long 0x4 16.--18. "PTXQ,Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx Queue." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 5. "TXSTSFSTS,MTL Tx Status FIFO Full Status When high  this bit indicates that the MTL Tx Status FIFO is full." "0,1"
bitfld.long 0x4 4. "TXQSTS,MTL Tx Queue Not Empty Status When this bit is high  it indicates that the MTL Tx Queue is not empty and some data is left for transmission." "0,1"
newline
bitfld.long 0x4 3. "TWCSTS,MTL Tx Queue Write Controller Status When high  this bit indicates that the MTL Tx Queue Write Controller is active  and it is transferring the data to the Tx Queue." "0,1"
bitfld.long 0x4 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read Controller: 00: Idle state 01: Read state (transferring data to the MAC transmitter) 10: Waiting for pending Tx Status from the MAC transmitter 11: Flushing.." "0: Idle state,1: Read state,?,?"
newline
bitfld.long 0x4 0. "TXQPAUSED,Transmit Queue in Pause When this bit is high and the Rx flow control is enabled  it indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because of the following: - Reception of the PFC packet for the priorities.." "0,1"
group.long ($2+0x10)++0x17
line.long 0x0 "MTL_TXQx_ETS_CTRL,MTL TxQx ETS control register. only TxQ1 support"
rbitfld.long 0x0 4.--6. "SLC,Credit Control." "0,1,2,3,4,5,6,7"
bitfld.long 0x0 3. "CC,Credit Control." "0,1"
newline
bitfld.long 0x0 2. "AVALG,AV Algorithm." "0,1"
line.long 0x4 "MTL_TXQx_ETS_STAT,MTL TxQx ETS Status register"
hexmask.long.tbyte 0x4 0.--23. 1. "ABS,Average Bits per Slot."
line.long 0x8 "MTL_TXQx_QNTM_WGHT,no description available"
hexmask.long.tbyte 0x8 0.--20. 1. "ISCQW,Average Bits per Slot."
line.long 0xC "MTL_TXQx_SNDSLP_CRDT,MTL TxQx SendSlopCredit register. only TxQ1 support"
hexmask.long.word 0xC 0.--13. 1. "SSC,sendSlopeCredit."
line.long 0x10 "MTL_TXQx_HI_CRDT,MTL TxQx hiCredit register. only TxQ1 support"
hexmask.long 0x10 0.--28. 1. "HC,hiCredit."
line.long 0x14 "MTL_TXQx_LO_CRDT,MTL TxQx loCredit register. only TxQ1 support"
hexmask.long 0x14 0.--28. 1. "LC,loCredit."
group.long ($2+0x2C)++0x13
line.long 0x0 "MTL_TXQx_INTCTRL_STAT,no description available"
bitfld.long 0x0 24. "RXOIE,Receive Queue Overflow Interrupt Enable When this bit is set  the Receive Queue Overflow interrupt is enabled." "0,1"
bitfld.long 0x0 16. "RXOVFIS,Receive Queue Overflow Interrupt Status This bit indicates that the Receive Queue had an overflow while receiving the packet." "0,1"
newline
bitfld.long 0x0 9. "ABPSIE,Average Bits Per Slot Interrupt Enable When this bit is set  the MAC asserts the interrupt when the average bits per slot status is updated." "0,1"
bitfld.long 0x0 8. "TXUIE,Transmit Queue Underflow Interrupt Enable When this bit is set  the Transmit Queue Underflow interrupt is enabled." "0,1"
newline
bitfld.long 0x0 1. "ABPSIS,Average Bits Per Slot Interrupt Status When set  this bit indicates that the MAC has updated the ABS value." "0,1"
bitfld.long 0x0 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status This bit indicates that the Transmit Queue had an underflow while transmitting the packet." "0,1"
line.long 0x4 "MTL_RXQx_OP_MODE,MTL RxQx Operation Mode register"
bitfld.long 0x4 20.--22. "RQS,This field indicates the size of the allocated Receive queues in blocks of 256 bytes." "0,1,2,3,4,5,6,7"
bitfld.long 0x4 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets When this bit is set  the MAC does not drop the packets which only have the errors detected by the Receive Checksum Offload engine." "0,1"
newline
bitfld.long 0x4 5. "RSF,Receive Queue Store and Forward When this bit is set  the ethernet block on this chip reads a packet from the Rx queue only after the complete packet has been written to it  ignoring the RTC field of this register." "0,1"
bitfld.long 0x4 4. "FEP,Forward Error Packets When this bit is reset  the Rx queue drops packets with error status (CRC error  Mll_ER  watchdog timeout  or overflow)." "0,1"
newline
bitfld.long 0x4 3. "FUP,Forward Undersized Good Packets When this bit is set  the Rx queue forwards the undersized good packets (packets with no error and length less than 64 bytes)  including pad-bytes and CRC." "0,1"
bitfld.long 0x4 0.--1. "RTC,Receive Queue Threshold Control These bits control the threshold level of the MTL Rx queue (in bytes): 00: 64 01: 32 10: 96 11: 128 The packet received is transferred to the application or DMA when the packet size within the MTL Rx queue is larger.." "0: 64,1: 32,?,?"
line.long 0x8 "MTL_RXQx_MISSPKT_OVRFLW_CNT,MTL RxQx Missed Packet Overflow Counter register"
rbitfld.long 0x8 11. "OVFCNTOVF,Overflow Counter Overflow Bit When set  this bit indicates that the Rx Queue Overflow Packet Counter field crossed the maximum limit." "0,1"
hexmask.long.word 0x8 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter This field indicates the number of packets discarded by the Ethernet block because of Receive queue overflow."
line.long 0xC "MTL_RXQx_DBG,MTL RxQx Debug register"
hexmask.long.word 0xC 16.--29. 1. "PRXQ,Number of Packets in Receive Queue This field indicates the current number of packets in the Rx Queue."
rbitfld.long 0xC 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status This field gives the status of the fill-level of the Rx Queue: 0x0: Rx Queue empty 0x1: Rx Queue fill-level below flow-control deactivate threshold 0x2: Rx Queue fill-level above flow-control activate threshold 0x3:.." "0: Rx Queue empty,1: Rx Queue fill-level below flow-control..,2: Rx Queue fill-level above flow-control activate..,3: Rx Queue full"
newline
rbitfld.long 0xC 1.--2. "RRCSTS,MTL Rx Queue Read Controller State This field gives the state of the Rx queue Read controller: 00: Idle state 01: Reading packet data 10: Reading packet status (or timestamp) 11: Flushing the packet data and status." "0: Idle state,1: Reading packet data,?,?"
bitfld.long 0xC 0. "RWCSTS,MTL Rx Queue Write Controller Active Status When high  this bit indicates that the MTL Rx queue Write controller is active  and it is transferring a received packet to the Rx Queue." "0,1"
line.long 0x10 "MTL_RXQx_CTRL,MTL RxQx Control register"
bitfld.long 0x10 3. "RXQ_FRM_ARBIT,Receive Queue Packet Arbitration When this bit is set  the The ethernet block drives the packet data to the ARI interface such that the entire packet data of currently-selected queue is transmitted before switching to other queue." "0,1"
bitfld.long 0x10 0.--2. "RXQ_WEGT,Receive Queue Weight This field indicates the weight assigned to the Rx Queue 0." "0,1,2,3,4,5,6,7"
tree.end
repeat.end
endif
sif (cpuis("LPC54606*"))
repeat 2. (list 0x0 0x1)(list ad:0x40093100 ad:0x40093180)
tree "DMA_CH[$1]"
base $2
group.long ($2)++0xB
line.long 0x0 "DMA_CHx_CTRL,DMA Channelx Control"
bitfld.long 0x0 18.--20. "DSL,Skip Length This bit specifies the Word  Dword  or Lword number (depending on the 32- bit  64-bit  or 128-bit bus) to skip between two unchained s." "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16. "PBLx8,8xPBL mode When this bit is set  the PBL value programmed in Bits[21:16] in DMA Channel Transmit Control Table 780 is multiplied eight times." "0,1"
line.long 0x4 "DMA_CHx_TX_CTRL,DMA Channelx Transmit Control"
hexmask.long.byte 0x4 16.--21. 1. "TxPBL,Transmit Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA data transfer."
bitfld.long 0x4 4. "OSF,Operate on Second Frame When this bit is set  it instructs the DMA to process the second packet of the Transmit data even before the status for the first packet is obtained." "0,1"
bitfld.long 0x4 1.--3. "TCW,Transmit Channel Weight This field indicates the weight assigned to the corresponding Transmit channel." "0,1,2,3,4,5,6,7"
bitfld.long 0x4 0. "ST,Start or Stop Transmission Command When this bit is set  transmission is placed in the Running state." "0,1"
line.long 0x8 "DMA_CHx_RX_CTRL,DMA Channelx Receive Control"
bitfld.long 0x8 31. "RPF,DMA Rx Channel 0 Packet Flush When this bit is set to 1  the DMA will automatically flush the packet from the Rx Queues destined to DMA Rx Channel 0 when the DMA Rx Channel 0 is stopped after a system bus error has occurred." "0,1"
hexmask.long.byte 0x8 16.--21. 1. "RxPBL,Receive Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA data transfer."
hexmask.long.word 0x8 3.--14. 1. "RBSZ,Receive Buffer size This field indicates the size of the Rx buffers specified in bytes."
bitfld.long 0x8 0. "SR,Start or Stop Receive When this bit is set  the DMA tries to acquire the from the receive list and processes the incoming packets." "0,1"
group.long ($2+0x14)++0x3
line.long 0x0 "DMA_CHx_TXDESC_LIST_ADDR,no description available"
hexmask.long 0x0 2.--31. 1. "STL,Start of transmit list This field contains the base address of the first in the Transmit list."
group.long ($2+0x1C)++0x7
line.long 0x0 "DMA_CHx_RXDESC_LIST_ADDR,no description available"
hexmask.long 0x0 2.--31. 1. "SRL,Start of receive list This field contains the base address of the First in the Receive list."
line.long 0x4 "DMA_CHx_TXDESC_TAIL_PTR,no description available"
hexmask.long 0x4 2.--31. 1. "TDTP,Transmit Tail Pointer This field contains the tail pointer for the Tx ring."
group.long ($2+0x28)++0x17
line.long 0x0 "DMA_CHx_RXDESC_TAIL_PTR,no description available"
hexmask.long 0x0 2.--31. 1. "RDTP,Receive Tail Pointer This field contains the tail pointer for the Rx ring."
line.long 0x4 "DMA_CHx_TXDESC_RING_LENGTH,no description available"
hexmask.long.word 0x4 0.--9. 1. "TDRL,Transmit Ring Length This field sets the maximum number of Tx descriptors in the circular ring."
line.long 0x8 "DMA_CHx_RXDESC_RING_LENGTH,Channelx Rx descriptor Ring Length"
hexmask.long.word 0x8 0.--9. 1. "RDRL,Receive Ring Length This register sets the maximum number of Rx descriptors in the circular ring."
line.long 0xC "DMA_CHx_INT_EN,Channelx Interrupt Enable"
bitfld.long 0xC 15. "NIE,Normal interrupt summary enable When this bit is set  a normal interrupt is enabled." "0,1"
bitfld.long 0xC 14. "AIE,Abnormal interrupt summary enable When this bit is set  an Abnormal Interrupt summary is enabled." "0,1"
bitfld.long 0xC 12. "FBEE,Fatal bus error enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register)  the Fatal Bus Error Interrupt is enabled." "0,1"
bitfld.long 0xC 11. "ERIE,Early receive interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register)  Early Receive Interrupt is enabled." "0,1"
bitfld.long 0xC 10. "ETIE,Early transmit interrupt enable When this bit is set with an Abnormal Interrupt Summary Enable (bit 15 in this register)  Early Transmit Interrupt is enabled." "0,1"
bitfld.long 0xC 9. "RWTE,Receive watchdog timeout enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register)  the Receive Watchdog Timeout Interrupt is enabled." "0,1"
newline
bitfld.long 0xC 8. "RSE,Received stopped enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register)  Receive Stopped Interrupt is enabled." "0,1"
bitfld.long 0xC 7. "RBUE,Receive buffer unavailable enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register)  Receive Buffer Unavailable Interrupt is enabled." "0,1"
bitfld.long 0xC 6. "RIE,Receive interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register)  Receive Interrupt is enabled." "0,1"
bitfld.long 0xC 2. "TBUE,Transmit buffer unavailable enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register)  Transmit Buffer Unavailable Interrupt is enabled." "0,1"
bitfld.long 0xC 1. "TSE,Transmit stopped enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register)  Transmission Stopped Interrupt is enabled." "0,1"
bitfld.long 0xC 0. "TIE,Transmit interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register)  Transmit Interrupt is enabled." "0,1"
line.long 0x10 "DMA_CHx_RX_INT_WDTIMER,Receive Interrupt Watchdog Timer"
hexmask.long.byte 0x10 0.--7. 1. "RIWT,Receive Interrupt Watchdog Timer Count Indicates the number of system clock cycles multiplied by 256 for which the watchdog timer is set."
line.long 0x14 "DMA_CHx_SLOT_FUNC_CTRL_STAT,Slot Function Control and Status"
hexmask.long.byte 0x14 16.--19. 1. "RSN,Reference Slot Number This field gives the current value of the reference slot number in the DMA."
bitfld.long 0x14 1. "ASC,Advance Slot Check When set  this bit enables the D MA to fetch the data from the buffer when the slot number (SLOTNUM) programmed in the Tx descriptor is equal to the reference slot number given in the RSN field or  ahead of the reference slot.." "0,1"
bitfld.long 0x14 0. "ESC,Enable Slot Comparison When set  this bit enables the checking of the slot numbers programmed in the Tx descriptor with the current reference given in the RSN field." "0,1"
rgroup.long ($2+0x44)++0x3
line.long 0x0 "DMA_CHx_CUR_HST_TXDESC,Channelx Current Host Transmit descriptor"
hexmask.long 0x0 0.--31. 1. "HTD,Host Transmit descriptor Address Pointer Cleared on Reset."
rgroup.long ($2+0x4C)++0x3
line.long 0x0 "DMA_CHx_CUR_HST_RXDESC,no description available"
hexmask.long 0x0 0.--31. 1. "HRD,Host Receive descriptor Address Pointer Cleared on Reset."
rgroup.long ($2+0x54)++0x3
line.long 0x0 "DMA_CHx_CUR_HST_TXBUF,no description available"
hexmask.long 0x0 0.--31. 1. "HTB,Host Transmit Buffer Address Pointer Cleared on Reset."
rgroup.long ($2+0x5C)++0x3
line.long 0x0 "DMA_CHx_CUR_HST_RXBUF,Channelx Current Application Receive Buffer Address"
hexmask.long 0x0 0.--31. 1. "HRB,Host Receive Buffer Address Pointer Cleared on Reset."
group.long ($2+0x60)++0x3
line.long 0x0 "DMA_CHx_STAT,Channelx DMA status register"
bitfld.long 0x0 16.--18. "EB,DMA Error Bits This field indicates the type of error that caused a Bus Error." "0,1,2,3,4,5,6,7"
bitfld.long 0x0 15. "NIS,Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in the DMA Channel Interrupt Enable register Table 778: Bit 0: Transmit Interrupt Bit 2: Transmit.." "0: Transmit Interrupt Bit,?"
bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA Channel Interrupt Enable register Table 778: Bit 1: Transmit Process Stopped Bit 7:.." "?,1: Transmit Process Stopped Bit"
bitfld.long 0x0 12. "FBE,Fatal Bus Error This bit indicates that a bus error occurred (as described in the EB field)." "0,1"
bitfld.long 0x0 11. "ERI,Early Receive Interrupt This bit indicates that the DMA filled the first data buffer of the packet." "0,1"
bitfld.long 0x0 10. "ETI,Early Transmit Interrupt This bit indicates that the packet to be transmitted is fully transferred to the MTL Tx FIFO." "0,1"
newline
bitfld.long 0x0 9. "RWT,Receive Watchdog time out This bit is asserted when a packet with length greater than 2 048 bytes (10 240 bytes when Jumbo Packet mode is enabled) is received." "0,1"
bitfld.long 0x0 8. "RPS,Receive Process Stopped This bit is asserted when the Rx process enters the Stopped state." "0,1"
bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable This bit indicates that the application owns the next in the receive list  and the DMA cannot acquire it." "0,1"
bitfld.long 0x0 6. "RI,Receive Interrupt This bit indicates that the packet reception is complete." "0,1"
bitfld.long 0x0 2. "TBU,Transmit Buffer Unavailable This bit indicates that the application owns the next descriptor in the transmit list  and the DMA cannot acquire it." "0,1"
bitfld.long 0x0 1. "TPS,Transmit Process Stopped This bit is set when the transmission is stopped." "0,1"
newline
bitfld.long 0x0 0. "TI,Transmit Interrupt This bit indicates that the packet transmission is complete." "0,1"
tree.end
repeat.end
endif
sif (cpuis("LPC54608*"))
group.long 0x110++0x3
line.long 0x0 "MAC_VERSION,MAC version register"
endif
sif (cpuis("LPC54608*"))
rgroup.long 0x11C++0x3
line.long 0x0 "MAC_HW_FEAT0,MAC hardware feature register 0x0201"
bitfld.long 0x0 28.--30. "ACTPHYSEL,Active PHY Selected." "0,1,2,3,4,5,6,7"
bitfld.long 0x0 25.--26. "TSSTSSEL,Timestamp System Time Source." "0,1,2,3"
newline
bitfld.long 0x0 14. "TXCOESEL,Transmit Checksum Offload Support." "0,1"
bitfld.long 0x0 13. "EEESEL,Energy Efficient Ethernet Support ." "0,1"
newline
bitfld.long 0x0 12. "TSSEL,IEEE 1588-2008 Timestamp support ." "0,1"
bitfld.long 0x0 9. "ARPOFFSEL,ARP Offload Enabled." "0,1"
newline
bitfld.long 0x0 8. "MMCSEL,RMON Module Enable." "0,1"
bitfld.long 0x0 6. "RWKSEL,PMT Remote Wake-up Packet Detection." "0,1"
newline
bitfld.long 0x0 5. "SMASEL,SMA (MDIO) Interface." "0,1"
bitfld.long 0x0 4. "VLHASH,Hash Table Based Filtering option." "0,1"
newline
bitfld.long 0x0 2. "HDSEL,Half-duplex Support." "0,1"
bitfld.long 0x0 0. "MIISEL,10 or 100 Mbps Support." "0,1"
endif
sif (cpuis("LPC54608*"))
repeat 2. (list 0x0 0x1)(list ad:0x40092D00 ad:0x40092D40)
tree "MTL_QUEUE[$1]"
base $2
group.long ($2)++0x3
line.long 0x0 "MTL_TXQx_OP_MODE,MTL TxQx Operation Mode register"
bitfld.long 0x0 16.--18. "TQS,Transmit Queue Size This field indicates the size of the allocated Transmit queues in blocks of 256 bytes." "0,1,2,3,4,5,6,7"
bitfld.long 0x0 4.--6. "TTC,Transmit Threshold Control These bits control the threshold level of the MTL Tx Queue." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 2.--3. "TXQEN,Transmit Queue Enable This field is used to enable/disable the transmit queue 0." "0,1,2,3"
bitfld.long 0x0 1. "TSF,Transmit Store and Forward When this bit is set  the transmission starts when a full packet resides in the MTL Tx queue." "0,1"
newline
bitfld.long 0x0 0. "FTQ,Flush Transmit Queue When this bit is set  the Tx queue controller logic is reset to its default values." "0,1"
rgroup.long ($2+0x4)++0x7
line.long 0x0 "MTL_TXQx_UNDRFLW,MTL TxQx Underflow register"
bitfld.long 0x0 11. "UFCNTOVF,Overflow Bit for Underflow Packet Counter This bit is set every time the Tx queue Underflow Packet Counter field overflows  that is  it has crossed the maximum count." "0,1"
hexmask.long.word 0x0 0.--10. 1. "UFFRMCNT,Underflow Packet Counter This field indicates the number of packets aborted by the controller because of Tx Queue Underflow."
line.long 0x4 "MTL_TXQx_DBG,MTL TxQx Debug register"
bitfld.long 0x4 20.--22. "STSXSTSF,Number of Status Words in Tx Status FIFO of Queue This field indicates the current number of status in the Tx Status FIFO of this queue." "0,1,2,3,4,5,6,7"
bitfld.long 0x4 16.--18. "PTXQ,Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx Queue." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 5. "TXSTSFSTS,MTL Tx Status FIFO Full Status When high  this bit indicates that the MTL Tx Status FIFO is full." "0,1"
bitfld.long 0x4 4. "TXQSTS,MTL Tx Queue Not Empty Status When this bit is high  it indicates that the MTL Tx Queue is not empty and some data is left for transmission." "0,1"
newline
bitfld.long 0x4 3. "TWCSTS,MTL Tx Queue Write Controller Status When high  this bit indicates that the MTL Tx Queue Write Controller is active  and it is transferring the data to the Tx Queue." "0,1"
bitfld.long 0x4 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read Controller: 00: Idle state 01: Read state (transferring data to the MAC transmitter) 10: Waiting for pending Tx Status from the MAC transmitter 11: Flushing.." "0: Idle state,1: Read state,?,?"
newline
bitfld.long 0x4 0. "TXQPAUSED,Transmit Queue in Pause When this bit is high and the Rx flow control is enabled  it indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because of the following: - Reception of the PFC packet for the priorities.." "0,1"
group.long ($2+0x10)++0x17
line.long 0x0 "MTL_TXQx_ETS_CTRL,MTL TxQx ETS control register. only TxQ1 support"
rbitfld.long 0x0 4.--6. "SLC,Credit Control." "0,1,2,3,4,5,6,7"
bitfld.long 0x0 3. "CC,Credit Control." "0,1"
newline
bitfld.long 0x0 2. "AVALG,AV Algorithm." "0,1"
line.long 0x4 "MTL_TXQx_ETS_STAT,MTL TxQx ETS Status register"
hexmask.long.tbyte 0x4 0.--23. 1. "ABS,Average Bits per Slot."
line.long 0x8 "MTL_TXQx_QNTM_WGHT,no description available"
hexmask.long.tbyte 0x8 0.--20. 1. "ISCQW,Average Bits per Slot."
line.long 0xC "MTL_TXQx_SNDSLP_CRDT,MTL TxQx SendSlopCredit register. only TxQ1 support"
hexmask.long.word 0xC 0.--13. 1. "SSC,sendSlopeCredit."
line.long 0x10 "MTL_TXQx_HI_CRDT,MTL TxQx hiCredit register. only TxQ1 support"
hexmask.long 0x10 0.--28. 1. "HC,hiCredit."
line.long 0x14 "MTL_TXQx_LO_CRDT,MTL TxQx loCredit register. only TxQ1 support"
hexmask.long 0x14 0.--28. 1. "LC,loCredit."
group.long ($2+0x2C)++0x13
line.long 0x0 "MTL_TXQx_INTCTRL_STAT,no description available"
bitfld.long 0x0 24. "RXOIE,Receive Queue Overflow Interrupt Enable When this bit is set  the Receive Queue Overflow interrupt is enabled." "0,1"
bitfld.long 0x0 16. "RXOVFIS,Receive Queue Overflow Interrupt Status This bit indicates that the Receive Queue had an overflow while receiving the packet." "0,1"
newline
bitfld.long 0x0 9. "ABPSIE,Average Bits Per Slot Interrupt Enable When this bit is set  the MAC asserts the interrupt when the average bits per slot status is updated." "0,1"
bitfld.long 0x0 8. "TXUIE,Transmit Queue Underflow Interrupt Enable When this bit is set  the Transmit Queue Underflow interrupt is enabled." "0,1"
newline
bitfld.long 0x0 1. "ABPSIS,Average Bits Per Slot Interrupt Status When set  this bit indicates that the MAC has updated the ABS value." "0,1"
bitfld.long 0x0 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status This bit indicates that the Transmit Queue had an underflow while transmitting the packet." "0,1"
line.long 0x4 "MTL_RXQx_OP_MODE,MTL RxQx Operation Mode register"
bitfld.long 0x4 20.--22. "RQS,This field indicates the size of the allocated Receive queues in blocks of 256 bytes." "0,1,2,3,4,5,6,7"
bitfld.long 0x4 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets When this bit is set  the MAC does not drop the packets which only have the errors detected by the Receive Checksum Offload engine." "0,1"
newline
bitfld.long 0x4 5. "RSF,Receive Queue Store and Forward When this bit is set  the ethernet block on this chip reads a packet from the Rx queue only after the complete packet has been written to it  ignoring the RTC field of this register." "0,1"
bitfld.long 0x4 4. "FEP,Forward Error Packets When this bit is reset  the Rx queue drops packets with error status (CRC error  Mll_ER  watchdog timeout  or overflow)." "0,1"
newline
bitfld.long 0x4 3. "FUP,Forward Undersized Good Packets When this bit is set  the Rx queue forwards the undersized good packets (packets with no error and length less than 64 bytes)  including pad-bytes and CRC." "0,1"
bitfld.long 0x4 0.--1. "RTC,Receive Queue Threshold Control These bits control the threshold level of the MTL Rx queue (in bytes): 00: 64 01: 32 10: 96 11: 128 The packet received is transferred to the application or DMA when the packet size within the MTL Rx queue is larger.." "0: 64,1: 32,?,?"
line.long 0x8 "MTL_RXQx_MISSPKT_OVRFLW_CNT,MTL RxQx Missed Packet Overflow Counter register"
rbitfld.long 0x8 11. "OVFCNTOVF,Overflow Counter Overflow Bit When set  this bit indicates that the Rx Queue Overflow Packet Counter field crossed the maximum limit." "0,1"
hexmask.long.word 0x8 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter This field indicates the number of packets discarded by the Ethernet block because of Receive queue overflow."
line.long 0xC "MTL_RXQx_DBG,MTL RxQx Debug register"
hexmask.long.word 0xC 16.--29. 1. "PRXQ,Number of Packets in Receive Queue This field indicates the current number of packets in the Rx Queue."
rbitfld.long 0xC 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status This field gives the status of the fill-level of the Rx Queue: 0x0: Rx Queue empty 0x1: Rx Queue fill-level below flow-control deactivate threshold 0x2: Rx Queue fill-level above flow-control activate threshold 0x3:.." "0: Rx Queue empty,1: Rx Queue fill-level below flow-control..,2: Rx Queue fill-level above flow-control activate..,3: Rx Queue full"
newline
rbitfld.long 0xC 1.--2. "RRCSTS,MTL Rx Queue Read Controller State This field gives the state of the Rx queue Read controller: 00: Idle state 01: Reading packet data 10: Reading packet status (or timestamp) 11: Flushing the packet data and status." "0: Idle state,1: Reading packet data,?,?"
bitfld.long 0xC 0. "RWCSTS,MTL Rx Queue Write Controller Active Status When high  this bit indicates that the MTL Rx queue Write controller is active  and it is transferring a received packet to the Rx Queue." "0,1"
line.long 0x10 "MTL_RXQx_CTRL,MTL RxQx Control register"
bitfld.long 0x10 3. "RXQ_FRM_ARBIT,Receive Queue Packet Arbitration When this bit is set  the The ethernet block drives the packet data to the ARI interface such that the entire packet data of currently-selected queue is transmitted before switching to other queue." "0,1"
bitfld.long 0x10 0.--2. "RXQ_WEGT,Receive Queue Weight This field indicates the weight assigned to the Rx Queue 0." "0,1,2,3,4,5,6,7"
tree.end
repeat.end
endif
sif (cpuis("LPC54608*"))
repeat 2. (list 0x0 0x1)(list ad:0x40093100 ad:0x40093180)
tree "DMA_CH[$1]"
base $2
group.long ($2)++0xB
line.long 0x0 "DMA_CHx_CTRL,DMA Channelx Control"
bitfld.long 0x0 18.--20. "DSL,Skip Length This bit specifies the Word  Dword  or Lword number (depending on the 32- bit  64-bit  or 128-bit bus) to skip between two unchained s." "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16. "PBLx8,8xPBL mode When this bit is set  the PBL value programmed in Bits[21:16] in DMA Channel Transmit Control Table 780 is multiplied eight times." "0,1"
line.long 0x4 "DMA_CHx_TX_CTRL,DMA Channelx Transmit Control"
hexmask.long.byte 0x4 16.--21. 1. "TxPBL,Transmit Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA data transfer."
bitfld.long 0x4 4. "OSF,Operate on Second Frame When this bit is set  it instructs the DMA to process the second packet of the Transmit data even before the status for the first packet is obtained." "0,1"
bitfld.long 0x4 1.--3. "TCW,Transmit Channel Weight This field indicates the weight assigned to the corresponding Transmit channel." "0,1,2,3,4,5,6,7"
bitfld.long 0x4 0. "ST,Start or Stop Transmission Command When this bit is set  transmission is placed in the Running state." "0,1"
line.long 0x8 "DMA_CHx_RX_CTRL,DMA Channelx Receive Control"
bitfld.long 0x8 31. "RPF,DMA Rx Channel 0 Packet Flush When this bit is set to 1  the DMA will automatically flush the packet from the Rx Queues destined to DMA Rx Channel 0 when the DMA Rx Channel 0 is stopped after a system bus error has occurred." "0,1"
hexmask.long.byte 0x8 16.--21. 1. "RxPBL,Receive Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA data transfer."
hexmask.long.word 0x8 3.--14. 1. "RBSZ,Receive Buffer size This field indicates the size of the Rx buffers specified in bytes."
bitfld.long 0x8 0. "SR,Start or Stop Receive When this bit is set  the DMA tries to acquire the from the receive list and processes the incoming packets." "0,1"
group.long ($2+0x14)++0x3
line.long 0x0 "DMA_CHx_TXDESC_LIST_ADDR,no description available"
hexmask.long 0x0 2.--31. 1. "STL,Start of transmit list This field contains the base address of the first in the Transmit list."
group.long ($2+0x1C)++0x7
line.long 0x0 "DMA_CHx_RXDESC_LIST_ADDR,no description available"
hexmask.long 0x0 2.--31. 1. "SRL,Start of receive list This field contains the base address of the First in the Receive list."
line.long 0x4 "DMA_CHx_TXDESC_TAIL_PTR,no description available"
hexmask.long 0x4 2.--31. 1. "TDTP,Transmit Tail Pointer This field contains the tail pointer for the Tx ring."
group.long ($2+0x28)++0x17
line.long 0x0 "DMA_CHx_RXDESC_TAIL_PTR,no description available"
hexmask.long 0x0 2.--31. 1. "RDTP,Receive Tail Pointer This field contains the tail pointer for the Rx ring."
line.long 0x4 "DMA_CHx_TXDESC_RING_LENGTH,no description available"
hexmask.long.word 0x4 0.--9. 1. "TDRL,Transmit Ring Length This field sets the maximum number of Tx descriptors in the circular ring."
line.long 0x8 "DMA_CHx_RXDESC_RING_LENGTH,Channelx Rx descriptor Ring Length"
hexmask.long.word 0x8 0.--9. 1. "RDRL,Receive Ring Length This register sets the maximum number of Rx descriptors in the circular ring."
line.long 0xC "DMA_CHx_INT_EN,Channelx Interrupt Enable"
bitfld.long 0xC 15. "NIE,Normal interrupt summary enable When this bit is set  a normal interrupt is enabled." "0,1"
bitfld.long 0xC 14. "AIE,Abnormal interrupt summary enable When this bit is set  an Abnormal Interrupt summary is enabled." "0,1"
bitfld.long 0xC 12. "FBEE,Fatal bus error enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register)  the Fatal Bus Error Interrupt is enabled." "0,1"
bitfld.long 0xC 11. "ERIE,Early receive interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register)  Early Receive Interrupt is enabled." "0,1"
bitfld.long 0xC 10. "ETIE,Early transmit interrupt enable When this bit is set with an Abnormal Interrupt Summary Enable (bit 15 in this register)  Early Transmit Interrupt is enabled." "0,1"
bitfld.long 0xC 9. "RWTE,Receive watchdog timeout enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register)  the Receive Watchdog Timeout Interrupt is enabled." "0,1"
newline
bitfld.long 0xC 8. "RSE,Received stopped enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register)  Receive Stopped Interrupt is enabled." "0,1"
bitfld.long 0xC 7. "RBUE,Receive buffer unavailable enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register)  Receive Buffer Unavailable Interrupt is enabled." "0,1"
bitfld.long 0xC 6. "RIE,Receive interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register)  Receive Interrupt is enabled." "0,1"
bitfld.long 0xC 2. "TBUE,Transmit buffer unavailable enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register)  Transmit Buffer Unavailable Interrupt is enabled." "0,1"
bitfld.long 0xC 1. "TSE,Transmit stopped enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register)  Transmission Stopped Interrupt is enabled." "0,1"
bitfld.long 0xC 0. "TIE,Transmit interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register)  Transmit Interrupt is enabled." "0,1"
line.long 0x10 "DMA_CHx_RX_INT_WDTIMER,Receive Interrupt Watchdog Timer"
hexmask.long.byte 0x10 0.--7. 1. "RIWT,Receive Interrupt Watchdog Timer Count Indicates the number of system clock cycles multiplied by 256 for which the watchdog timer is set."
line.long 0x14 "DMA_CHx_SLOT_FUNC_CTRL_STAT,Slot Function Control and Status"
hexmask.long.byte 0x14 16.--19. 1. "RSN,Reference Slot Number This field gives the current value of the reference slot number in the DMA."
bitfld.long 0x14 1. "ASC,Advance Slot Check When set  this bit enables the D MA to fetch the data from the buffer when the slot number (SLOTNUM) programmed in the Tx descriptor is equal to the reference slot number given in the RSN field or  ahead of the reference slot.." "0,1"
bitfld.long 0x14 0. "ESC,Enable Slot Comparison When set  this bit enables the checking of the slot numbers programmed in the Tx descriptor with the current reference given in the RSN field." "0,1"
rgroup.long ($2+0x44)++0x3
line.long 0x0 "DMA_CHx_CUR_HST_TXDESC,Channelx Current Host Transmit descriptor"
hexmask.long 0x0 0.--31. 1. "HTD,Host Transmit descriptor Address Pointer Cleared on Reset."
rgroup.long ($2+0x4C)++0x3
line.long 0x0 "DMA_CHx_CUR_HST_RXDESC,no description available"
hexmask.long 0x0 0.--31. 1. "HRD,Host Receive descriptor Address Pointer Cleared on Reset."
rgroup.long ($2+0x54)++0x3
line.long 0x0 "DMA_CHx_CUR_HST_TXBUF,no description available"
hexmask.long 0x0 0.--31. 1. "HTB,Host Transmit Buffer Address Pointer Cleared on Reset."
rgroup.long ($2+0x5C)++0x3
line.long 0x0 "DMA_CHx_CUR_HST_RXBUF,Channelx Current Application Receive Buffer Address"
hexmask.long 0x0 0.--31. 1. "HRB,Host Receive Buffer Address Pointer Cleared on Reset."
group.long ($2+0x60)++0x3
line.long 0x0 "DMA_CHx_STAT,Channelx DMA status register"
bitfld.long 0x0 16.--18. "EB,DMA Error Bits This field indicates the type of error that caused a Bus Error." "0,1,2,3,4,5,6,7"
bitfld.long 0x0 15. "NIS,Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in the DMA Channel Interrupt Enable register Table 778: Bit 0: Transmit Interrupt Bit 2: Transmit.." "0: Transmit Interrupt Bit,?"
bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA Channel Interrupt Enable register Table 778: Bit 1: Transmit Process Stopped Bit 7:.." "?,1: Transmit Process Stopped Bit"
bitfld.long 0x0 12. "FBE,Fatal Bus Error This bit indicates that a bus error occurred (as described in the EB field)." "0,1"
bitfld.long 0x0 11. "ERI,Early Receive Interrupt This bit indicates that the DMA filled the first data buffer of the packet." "0,1"
bitfld.long 0x0 10. "ETI,Early Transmit Interrupt This bit indicates that the packet to be transmitted is fully transferred to the MTL Tx FIFO." "0,1"
newline
bitfld.long 0x0 9. "RWT,Receive Watchdog time out This bit is asserted when a packet with length greater than 2 048 bytes (10 240 bytes when Jumbo Packet mode is enabled) is received." "0,1"
bitfld.long 0x0 8. "RPS,Receive Process Stopped This bit is asserted when the Rx process enters the Stopped state." "0,1"
bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable This bit indicates that the application owns the next in the receive list  and the DMA cannot acquire it." "0,1"
bitfld.long 0x0 6. "RI,Receive Interrupt This bit indicates that the packet reception is complete." "0,1"
bitfld.long 0x0 2. "TBU,Transmit Buffer Unavailable This bit indicates that the application owns the next descriptor in the transmit list  and the DMA cannot acquire it." "0,1"
bitfld.long 0x0 1. "TPS,Transmit Process Stopped This bit is set when the transmission is stopped." "0,1"
newline
bitfld.long 0x0 0. "TI,Transmit Interrupt This bit indicates that the packet transmission is complete." "0,1"
tree.end
repeat.end
endif
sif (cpuis("LPC54616*"))
group.long 0x110++0x3
line.long 0x0 "MAC_VERSION,MAC version register"
endif
sif (cpuis("LPC54616*"))
rgroup.long 0x11C++0x3
line.long 0x0 "MAC_HW_FEAT0,MAC hardware feature register 0x0201"
bitfld.long 0x0 28.--30. "ACTPHYSEL,Active PHY Selected." "0,1,2,3,4,5,6,7"
bitfld.long 0x0 25.--26. "TSSTSSEL,Timestamp System Time Source." "0,1,2,3"
newline
bitfld.long 0x0 14. "TXCOESEL,Transmit Checksum Offload Support." "0,1"
bitfld.long 0x0 13. "EEESEL,Energy Efficient Ethernet Support ." "0,1"
newline
bitfld.long 0x0 12. "TSSEL,IEEE 1588-2008 Timestamp support ." "0,1"
bitfld.long 0x0 9. "ARPOFFSEL,ARP Offload Enabled." "0,1"
newline
bitfld.long 0x0 8. "MMCSEL,RMON Module Enable." "0,1"
bitfld.long 0x0 6. "RWKSEL,PMT Remote Wake-up Packet Detection." "0,1"
newline
bitfld.long 0x0 5. "SMASEL,SMA (MDIO) Interface." "0,1"
bitfld.long 0x0 4. "VLHASH,Hash Table Based Filtering option." "0,1"
newline
bitfld.long 0x0 2. "HDSEL,Half-duplex Support." "0,1"
bitfld.long 0x0 0. "MIISEL,10 or 100 Mbps Support." "0,1"
endif
sif (cpuis("LPC54616*"))
repeat 2. (list 0x0 0x1)(list ad:0x40092D00 ad:0x40092D40)
tree "MTL_QUEUE[$1]"
base $2
group.long ($2)++0x3
line.long 0x0 "MTL_TXQx_OP_MODE,MTL TxQx Operation Mode register"
bitfld.long 0x0 16.--18. "TQS,Transmit Queue Size This field indicates the size of the allocated Transmit queues in blocks of 256 bytes." "0,1,2,3,4,5,6,7"
bitfld.long 0x0 4.--6. "TTC,Transmit Threshold Control These bits control the threshold level of the MTL Tx Queue." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 2.--3. "TXQEN,Transmit Queue Enable This field is used to enable/disable the transmit queue 0." "0,1,2,3"
bitfld.long 0x0 1. "TSF,Transmit Store and Forward When this bit is set  the transmission starts when a full packet resides in the MTL Tx queue." "0,1"
newline
bitfld.long 0x0 0. "FTQ,Flush Transmit Queue When this bit is set  the Tx queue controller logic is reset to its default values." "0,1"
rgroup.long ($2+0x4)++0x7
line.long 0x0 "MTL_TXQx_UNDRFLW,MTL TxQx Underflow register"
bitfld.long 0x0 11. "UFCNTOVF,Overflow Bit for Underflow Packet Counter This bit is set every time the Tx queue Underflow Packet Counter field overflows  that is  it has crossed the maximum count." "0,1"
hexmask.long.word 0x0 0.--10. 1. "UFFRMCNT,Underflow Packet Counter This field indicates the number of packets aborted by the controller because of Tx Queue Underflow."
line.long 0x4 "MTL_TXQx_DBG,MTL TxQx Debug register"
bitfld.long 0x4 20.--22. "STSXSTSF,Number of Status Words in Tx Status FIFO of Queue This field indicates the current number of status in the Tx Status FIFO of this queue." "0,1,2,3,4,5,6,7"
bitfld.long 0x4 16.--18. "PTXQ,Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx Queue." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 5. "TXSTSFSTS,MTL Tx Status FIFO Full Status When high  this bit indicates that the MTL Tx Status FIFO is full." "0,1"
bitfld.long 0x4 4. "TXQSTS,MTL Tx Queue Not Empty Status When this bit is high  it indicates that the MTL Tx Queue is not empty and some data is left for transmission." "0,1"
newline
bitfld.long 0x4 3. "TWCSTS,MTL Tx Queue Write Controller Status When high  this bit indicates that the MTL Tx Queue Write Controller is active  and it is transferring the data to the Tx Queue." "0,1"
bitfld.long 0x4 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read Controller: 00: Idle state 01: Read state (transferring data to the MAC transmitter) 10: Waiting for pending Tx Status from the MAC transmitter 11: Flushing.." "0: Idle state,1: Read state,?,?"
newline
bitfld.long 0x4 0. "TXQPAUSED,Transmit Queue in Pause When this bit is high and the Rx flow control is enabled  it indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because of the following: - Reception of the PFC packet for the priorities.." "0,1"
group.long ($2+0x10)++0x17
line.long 0x0 "MTL_TXQx_ETS_CTRL,MTL TxQx ETS control register. only TxQ1 support"
rbitfld.long 0x0 4.--6. "SLC,Credit Control." "0,1,2,3,4,5,6,7"
bitfld.long 0x0 3. "CC,Credit Control." "0,1"
newline
bitfld.long 0x0 2. "AVALG,AV Algorithm." "0,1"
line.long 0x4 "MTL_TXQx_ETS_STAT,MTL TxQx ETS Status register"
hexmask.long.tbyte 0x4 0.--23. 1. "ABS,Average Bits per Slot."
line.long 0x8 "MTL_TXQx_QNTM_WGHT,no description available"
hexmask.long.tbyte 0x8 0.--20. 1. "ISCQW,Average Bits per Slot."
line.long 0xC "MTL_TXQx_SNDSLP_CRDT,MTL TxQx SendSlopCredit register. only TxQ1 support"
hexmask.long.word 0xC 0.--13. 1. "SSC,sendSlopeCredit."
line.long 0x10 "MTL_TXQx_HI_CRDT,MTL TxQx hiCredit register. only TxQ1 support"
hexmask.long 0x10 0.--28. 1. "HC,hiCredit."
line.long 0x14 "MTL_TXQx_LO_CRDT,MTL TxQx loCredit register. only TxQ1 support"
hexmask.long 0x14 0.--28. 1. "LC,loCredit."
group.long ($2+0x2C)++0x13
line.long 0x0 "MTL_TXQx_INTCTRL_STAT,no description available"
bitfld.long 0x0 24. "RXOIE,Receive Queue Overflow Interrupt Enable When this bit is set  the Receive Queue Overflow interrupt is enabled." "0,1"
bitfld.long 0x0 16. "RXOVFIS,Receive Queue Overflow Interrupt Status This bit indicates that the Receive Queue had an overflow while receiving the packet." "0,1"
newline
bitfld.long 0x0 9. "ABPSIE,Average Bits Per Slot Interrupt Enable When this bit is set  the MAC asserts the interrupt when the average bits per slot status is updated." "0,1"
bitfld.long 0x0 8. "TXUIE,Transmit Queue Underflow Interrupt Enable When this bit is set  the Transmit Queue Underflow interrupt is enabled." "0,1"
newline
bitfld.long 0x0 1. "ABPSIS,Average Bits Per Slot Interrupt Status When set  this bit indicates that the MAC has updated the ABS value." "0,1"
bitfld.long 0x0 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status This bit indicates that the Transmit Queue had an underflow while transmitting the packet." "0,1"
line.long 0x4 "MTL_RXQx_OP_MODE,MTL RxQx Operation Mode register"
bitfld.long 0x4 20.--22. "RQS,This field indicates the size of the allocated Receive queues in blocks of 256 bytes." "0,1,2,3,4,5,6,7"
bitfld.long 0x4 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets When this bit is set  the MAC does not drop the packets which only have the errors detected by the Receive Checksum Offload engine." "0,1"
newline
bitfld.long 0x4 5. "RSF,Receive Queue Store and Forward When this bit is set  the ethernet block on this chip reads a packet from the Rx queue only after the complete packet has been written to it  ignoring the RTC field of this register." "0,1"
bitfld.long 0x4 4. "FEP,Forward Error Packets When this bit is reset  the Rx queue drops packets with error status (CRC error  Mll_ER  watchdog timeout  or overflow)." "0,1"
newline
bitfld.long 0x4 3. "FUP,Forward Undersized Good Packets When this bit is set  the Rx queue forwards the undersized good packets (packets with no error and length less than 64 bytes)  including pad-bytes and CRC." "0,1"
bitfld.long 0x4 0.--1. "RTC,Receive Queue Threshold Control These bits control the threshold level of the MTL Rx queue (in bytes): 00: 64 01: 32 10: 96 11: 128 The packet received is transferred to the application or DMA when the packet size within the MTL Rx queue is larger.." "0: 64,1: 32,?,?"
line.long 0x8 "MTL_RXQx_MISSPKT_OVRFLW_CNT,MTL RxQx Missed Packet Overflow Counter register"
rbitfld.long 0x8 11. "OVFCNTOVF,Overflow Counter Overflow Bit When set  this bit indicates that the Rx Queue Overflow Packet Counter field crossed the maximum limit." "0,1"
hexmask.long.word 0x8 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter This field indicates the number of packets discarded by the Ethernet block because of Receive queue overflow."
line.long 0xC "MTL_RXQx_DBG,MTL RxQx Debug register"
hexmask.long.word 0xC 16.--29. 1. "PRXQ,Number of Packets in Receive Queue This field indicates the current number of packets in the Rx Queue."
rbitfld.long 0xC 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status This field gives the status of the fill-level of the Rx Queue: 0x0: Rx Queue empty 0x1: Rx Queue fill-level below flow-control deactivate threshold 0x2: Rx Queue fill-level above flow-control activate threshold 0x3:.." "0: Rx Queue empty,1: Rx Queue fill-level below flow-control..,2: Rx Queue fill-level above flow-control activate..,3: Rx Queue full"
newline
rbitfld.long 0xC 1.--2. "RRCSTS,MTL Rx Queue Read Controller State This field gives the state of the Rx queue Read controller: 00: Idle state 01: Reading packet data 10: Reading packet status (or timestamp) 11: Flushing the packet data and status." "0: Idle state,1: Reading packet data,?,?"
bitfld.long 0xC 0. "RWCSTS,MTL Rx Queue Write Controller Active Status When high  this bit indicates that the MTL Rx queue Write controller is active  and it is transferring a received packet to the Rx Queue." "0,1"
line.long 0x10 "MTL_RXQx_CTRL,MTL RxQx Control register"
bitfld.long 0x10 3. "RXQ_FRM_ARBIT,Receive Queue Packet Arbitration When this bit is set  the The ethernet block drives the packet data to the ARI interface such that the entire packet data of currently-selected queue is transmitted before switching to other queue." "0,1"
bitfld.long 0x10 0.--2. "RXQ_WEGT,Receive Queue Weight This field indicates the weight assigned to the Rx Queue 0." "0,1,2,3,4,5,6,7"
tree.end
repeat.end
endif
sif (cpuis("LPC54616*"))
repeat 2. (list 0x0 0x1)(list ad:0x40093100 ad:0x40093180)
tree "DMA_CH[$1]"
base $2
group.long ($2)++0xB
line.long 0x0 "DMA_CHx_CTRL,DMA Channelx Control"
bitfld.long 0x0 18.--20. "DSL,Skip Length This bit specifies the Word  Dword  or Lword number (depending on the 32- bit  64-bit  or 128-bit bus) to skip between two unchained s." "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16. "PBLx8,8xPBL mode When this bit is set  the PBL value programmed in Bits[21:16] in DMA Channel Transmit Control Table 780 is multiplied eight times." "0,1"
line.long 0x4 "DMA_CHx_TX_CTRL,DMA Channelx Transmit Control"
hexmask.long.byte 0x4 16.--21. 1. "TxPBL,Transmit Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA data transfer."
bitfld.long 0x4 4. "OSF,Operate on Second Frame When this bit is set  it instructs the DMA to process the second packet of the Transmit data even before the status for the first packet is obtained." "0,1"
bitfld.long 0x4 1.--3. "TCW,Transmit Channel Weight This field indicates the weight assigned to the corresponding Transmit channel." "0,1,2,3,4,5,6,7"
bitfld.long 0x4 0. "ST,Start or Stop Transmission Command When this bit is set  transmission is placed in the Running state." "0,1"
line.long 0x8 "DMA_CHx_RX_CTRL,DMA Channelx Receive Control"
bitfld.long 0x8 31. "RPF,DMA Rx Channel 0 Packet Flush When this bit is set to 1  the DMA will automatically flush the packet from the Rx Queues destined to DMA Rx Channel 0 when the DMA Rx Channel 0 is stopped after a system bus error has occurred." "0,1"
hexmask.long.byte 0x8 16.--21. 1. "RxPBL,Receive Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA data transfer."
hexmask.long.word 0x8 3.--14. 1. "RBSZ,Receive Buffer size This field indicates the size of the Rx buffers specified in bytes."
bitfld.long 0x8 0. "SR,Start or Stop Receive When this bit is set  the DMA tries to acquire the from the receive list and processes the incoming packets." "0,1"
group.long ($2+0x14)++0x3
line.long 0x0 "DMA_CHx_TXDESC_LIST_ADDR,no description available"
hexmask.long 0x0 2.--31. 1. "STL,Start of transmit list This field contains the base address of the first in the Transmit list."
group.long ($2+0x1C)++0x7
line.long 0x0 "DMA_CHx_RXDESC_LIST_ADDR,no description available"
hexmask.long 0x0 2.--31. 1. "SRL,Start of receive list This field contains the base address of the First in the Receive list."
line.long 0x4 "DMA_CHx_TXDESC_TAIL_PTR,no description available"
hexmask.long 0x4 2.--31. 1. "TDTP,Transmit Tail Pointer This field contains the tail pointer for the Tx ring."
group.long ($2+0x28)++0x17
line.long 0x0 "DMA_CHx_RXDESC_TAIL_PTR,no description available"
hexmask.long 0x0 2.--31. 1. "RDTP,Receive Tail Pointer This field contains the tail pointer for the Rx ring."
line.long 0x4 "DMA_CHx_TXDESC_RING_LENGTH,no description available"
hexmask.long.word 0x4 0.--9. 1. "TDRL,Transmit Ring Length This field sets the maximum number of Tx descriptors in the circular ring."
line.long 0x8 "DMA_CHx_RXDESC_RING_LENGTH,Channelx Rx descriptor Ring Length"
hexmask.long.word 0x8 0.--9. 1. "RDRL,Receive Ring Length This register sets the maximum number of Rx descriptors in the circular ring."
line.long 0xC "DMA_CHx_INT_EN,Channelx Interrupt Enable"
bitfld.long 0xC 15. "NIE,Normal interrupt summary enable When this bit is set  a normal interrupt is enabled." "0,1"
bitfld.long 0xC 14. "AIE,Abnormal interrupt summary enable When this bit is set  an Abnormal Interrupt summary is enabled." "0,1"
bitfld.long 0xC 12. "FBEE,Fatal bus error enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register)  the Fatal Bus Error Interrupt is enabled." "0,1"
bitfld.long 0xC 11. "ERIE,Early receive interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register)  Early Receive Interrupt is enabled." "0,1"
bitfld.long 0xC 10. "ETIE,Early transmit interrupt enable When this bit is set with an Abnormal Interrupt Summary Enable (bit 15 in this register)  Early Transmit Interrupt is enabled." "0,1"
bitfld.long 0xC 9. "RWTE,Receive watchdog timeout enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register)  the Receive Watchdog Timeout Interrupt is enabled." "0,1"
newline
bitfld.long 0xC 8. "RSE,Received stopped enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register)  Receive Stopped Interrupt is enabled." "0,1"
bitfld.long 0xC 7. "RBUE,Receive buffer unavailable enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register)  Receive Buffer Unavailable Interrupt is enabled." "0,1"
bitfld.long 0xC 6. "RIE,Receive interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register)  Receive Interrupt is enabled." "0,1"
bitfld.long 0xC 2. "TBUE,Transmit buffer unavailable enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register)  Transmit Buffer Unavailable Interrupt is enabled." "0,1"
bitfld.long 0xC 1. "TSE,Transmit stopped enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register)  Transmission Stopped Interrupt is enabled." "0,1"
bitfld.long 0xC 0. "TIE,Transmit interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register)  Transmit Interrupt is enabled." "0,1"
line.long 0x10 "DMA_CHx_RX_INT_WDTIMER,Receive Interrupt Watchdog Timer"
hexmask.long.byte 0x10 0.--7. 1. "RIWT,Receive Interrupt Watchdog Timer Count Indicates the number of system clock cycles multiplied by 256 for which the watchdog timer is set."
line.long 0x14 "DMA_CHx_SLOT_FUNC_CTRL_STAT,Slot Function Control and Status"
hexmask.long.byte 0x14 16.--19. 1. "RSN,Reference Slot Number This field gives the current value of the reference slot number in the DMA."
bitfld.long 0x14 1. "ASC,Advance Slot Check When set  this bit enables the D MA to fetch the data from the buffer when the slot number (SLOTNUM) programmed in the Tx descriptor is equal to the reference slot number given in the RSN field or  ahead of the reference slot.." "0,1"
bitfld.long 0x14 0. "ESC,Enable Slot Comparison When set  this bit enables the checking of the slot numbers programmed in the Tx descriptor with the current reference given in the RSN field." "0,1"
rgroup.long ($2+0x44)++0x3
line.long 0x0 "DMA_CHx_CUR_HST_TXDESC,Channelx Current Host Transmit descriptor"
hexmask.long 0x0 0.--31. 1. "HTD,Host Transmit descriptor Address Pointer Cleared on Reset."
rgroup.long ($2+0x4C)++0x3
line.long 0x0 "DMA_CHx_CUR_HST_RXDESC,no description available"
hexmask.long 0x0 0.--31. 1. "HRD,Host Receive descriptor Address Pointer Cleared on Reset."
rgroup.long ($2+0x54)++0x3
line.long 0x0 "DMA_CHx_CUR_HST_TXBUF,no description available"
hexmask.long 0x0 0.--31. 1. "HTB,Host Transmit Buffer Address Pointer Cleared on Reset."
rgroup.long ($2+0x5C)++0x3
line.long 0x0 "DMA_CHx_CUR_HST_RXBUF,Channelx Current Application Receive Buffer Address"
hexmask.long 0x0 0.--31. 1. "HRB,Host Receive Buffer Address Pointer Cleared on Reset."
group.long ($2+0x60)++0x3
line.long 0x0 "DMA_CHx_STAT,Channelx DMA status register"
bitfld.long 0x0 16.--18. "EB,DMA Error Bits This field indicates the type of error that caused a Bus Error." "0,1,2,3,4,5,6,7"
bitfld.long 0x0 15. "NIS,Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in the DMA Channel Interrupt Enable register Table 778: Bit 0: Transmit Interrupt Bit 2: Transmit.." "0: Transmit Interrupt Bit,?"
bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA Channel Interrupt Enable register Table 778: Bit 1: Transmit Process Stopped Bit 7:.." "?,1: Transmit Process Stopped Bit"
bitfld.long 0x0 12. "FBE,Fatal Bus Error This bit indicates that a bus error occurred (as described in the EB field)." "0,1"
bitfld.long 0x0 11. "ERI,Early Receive Interrupt This bit indicates that the DMA filled the first data buffer of the packet." "0,1"
bitfld.long 0x0 10. "ETI,Early Transmit Interrupt This bit indicates that the packet to be transmitted is fully transferred to the MTL Tx FIFO." "0,1"
newline
bitfld.long 0x0 9. "RWT,Receive Watchdog time out This bit is asserted when a packet with length greater than 2 048 bytes (10 240 bytes when Jumbo Packet mode is enabled) is received." "0,1"
bitfld.long 0x0 8. "RPS,Receive Process Stopped This bit is asserted when the Rx process enters the Stopped state." "0,1"
bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable This bit indicates that the application owns the next in the receive list  and the DMA cannot acquire it." "0,1"
bitfld.long 0x0 6. "RI,Receive Interrupt This bit indicates that the packet reception is complete." "0,1"
bitfld.long 0x0 2. "TBU,Transmit Buffer Unavailable This bit indicates that the application owns the next descriptor in the transmit list  and the DMA cannot acquire it." "0,1"
bitfld.long 0x0 1. "TPS,Transmit Process Stopped This bit is set when the transmission is stopped." "0,1"
newline
bitfld.long 0x0 0. "TI,Transmit Interrupt This bit indicates that the packet transmission is complete." "0,1"
tree.end
repeat.end
endif
sif (cpuis("LPC54618*"))
group.long 0x110++0x3
line.long 0x0 "MAC_VERSION,MAC version register"
endif
sif (cpuis("LPC54618*"))
rgroup.long 0x11C++0x3
line.long 0x0 "MAC_HW_FEAT0,MAC hardware feature register 0x0201"
bitfld.long 0x0 28.--30. "ACTPHYSEL,Active PHY Selected." "0,1,2,3,4,5,6,7"
bitfld.long 0x0 25.--26. "TSSTSSEL,Timestamp System Time Source." "0,1,2,3"
newline
bitfld.long 0x0 14. "TXCOESEL,Transmit Checksum Offload Support." "0,1"
bitfld.long 0x0 13. "EEESEL,Energy Efficient Ethernet Support ." "0,1"
newline
bitfld.long 0x0 12. "TSSEL,IEEE 1588-2008 Timestamp support ." "0,1"
bitfld.long 0x0 9. "ARPOFFSEL,ARP Offload Enabled." "0,1"
newline
bitfld.long 0x0 8. "MMCSEL,RMON Module Enable." "0,1"
bitfld.long 0x0 6. "RWKSEL,PMT Remote Wake-up Packet Detection." "0,1"
newline
bitfld.long 0x0 5. "SMASEL,SMA (MDIO) Interface." "0,1"
bitfld.long 0x0 4. "VLHASH,Hash Table Based Filtering option." "0,1"
newline
bitfld.long 0x0 2. "HDSEL,Half-duplex Support." "0,1"
bitfld.long 0x0 0. "MIISEL,10 or 100 Mbps Support." "0,1"
endif
sif (cpuis("LPC54618*"))
repeat 2. (list 0x0 0x1)(list ad:0x40092D00 ad:0x40092D40)
tree "MTL_QUEUE[$1]"
base $2
group.long ($2)++0x3
line.long 0x0 "MTL_TXQx_OP_MODE,MTL TxQx Operation Mode register"
bitfld.long 0x0 16.--18. "TQS,Transmit Queue Size This field indicates the size of the allocated Transmit queues in blocks of 256 bytes." "0,1,2,3,4,5,6,7"
bitfld.long 0x0 4.--6. "TTC,Transmit Threshold Control These bits control the threshold level of the MTL Tx Queue." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 2.--3. "TXQEN,Transmit Queue Enable This field is used to enable/disable the transmit queue 0." "0,1,2,3"
bitfld.long 0x0 1. "TSF,Transmit Store and Forward When this bit is set  the transmission starts when a full packet resides in the MTL Tx queue." "0,1"
newline
bitfld.long 0x0 0. "FTQ,Flush Transmit Queue When this bit is set  the Tx queue controller logic is reset to its default values." "0,1"
rgroup.long ($2+0x4)++0x7
line.long 0x0 "MTL_TXQx_UNDRFLW,MTL TxQx Underflow register"
bitfld.long 0x0 11. "UFCNTOVF,Overflow Bit for Underflow Packet Counter This bit is set every time the Tx queue Underflow Packet Counter field overflows  that is  it has crossed the maximum count." "0,1"
hexmask.long.word 0x0 0.--10. 1. "UFFRMCNT,Underflow Packet Counter This field indicates the number of packets aborted by the controller because of Tx Queue Underflow."
line.long 0x4 "MTL_TXQx_DBG,MTL TxQx Debug register"
bitfld.long 0x4 20.--22. "STSXSTSF,Number of Status Words in Tx Status FIFO of Queue This field indicates the current number of status in the Tx Status FIFO of this queue." "0,1,2,3,4,5,6,7"
bitfld.long 0x4 16.--18. "PTXQ,Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx Queue." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 5. "TXSTSFSTS,MTL Tx Status FIFO Full Status When high  this bit indicates that the MTL Tx Status FIFO is full." "0,1"
bitfld.long 0x4 4. "TXQSTS,MTL Tx Queue Not Empty Status When this bit is high  it indicates that the MTL Tx Queue is not empty and some data is left for transmission." "0,1"
newline
bitfld.long 0x4 3. "TWCSTS,MTL Tx Queue Write Controller Status When high  this bit indicates that the MTL Tx Queue Write Controller is active  and it is transferring the data to the Tx Queue." "0,1"
bitfld.long 0x4 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read Controller: 00: Idle state 01: Read state (transferring data to the MAC transmitter) 10: Waiting for pending Tx Status from the MAC transmitter 11: Flushing.." "0: Idle state,1: Read state,?,?"
newline
bitfld.long 0x4 0. "TXQPAUSED,Transmit Queue in Pause When this bit is high and the Rx flow control is enabled  it indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because of the following: - Reception of the PFC packet for the priorities.." "0,1"
group.long ($2+0x10)++0x17
line.long 0x0 "MTL_TXQx_ETS_CTRL,MTL TxQx ETS control register. only TxQ1 support"
rbitfld.long 0x0 4.--6. "SLC,Credit Control." "0,1,2,3,4,5,6,7"
bitfld.long 0x0 3. "CC,Credit Control." "0,1"
newline
bitfld.long 0x0 2. "AVALG,AV Algorithm." "0,1"
line.long 0x4 "MTL_TXQx_ETS_STAT,MTL TxQx ETS Status register"
hexmask.long.tbyte 0x4 0.--23. 1. "ABS,Average Bits per Slot."
line.long 0x8 "MTL_TXQx_QNTM_WGHT,no description available"
hexmask.long.tbyte 0x8 0.--20. 1. "ISCQW,Average Bits per Slot."
line.long 0xC "MTL_TXQx_SNDSLP_CRDT,MTL TxQx SendSlopCredit register. only TxQ1 support"
hexmask.long.word 0xC 0.--13. 1. "SSC,sendSlopeCredit."
line.long 0x10 "MTL_TXQx_HI_CRDT,MTL TxQx hiCredit register. only TxQ1 support"
hexmask.long 0x10 0.--28. 1. "HC,hiCredit."
line.long 0x14 "MTL_TXQx_LO_CRDT,MTL TxQx loCredit register. only TxQ1 support"
hexmask.long 0x14 0.--28. 1. "LC,loCredit."
group.long ($2+0x2C)++0x13
line.long 0x0 "MTL_TXQx_INTCTRL_STAT,no description available"
bitfld.long 0x0 24. "RXOIE,Receive Queue Overflow Interrupt Enable When this bit is set  the Receive Queue Overflow interrupt is enabled." "0,1"
bitfld.long 0x0 16. "RXOVFIS,Receive Queue Overflow Interrupt Status This bit indicates that the Receive Queue had an overflow while receiving the packet." "0,1"
newline
bitfld.long 0x0 9. "ABPSIE,Average Bits Per Slot Interrupt Enable When this bit is set  the MAC asserts the interrupt when the average bits per slot status is updated." "0,1"
bitfld.long 0x0 8. "TXUIE,Transmit Queue Underflow Interrupt Enable When this bit is set  the Transmit Queue Underflow interrupt is enabled." "0,1"
newline
bitfld.long 0x0 1. "ABPSIS,Average Bits Per Slot Interrupt Status When set  this bit indicates that the MAC has updated the ABS value." "0,1"
bitfld.long 0x0 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status This bit indicates that the Transmit Queue had an underflow while transmitting the packet." "0,1"
line.long 0x4 "MTL_RXQx_OP_MODE,MTL RxQx Operation Mode register"
bitfld.long 0x4 20.--22. "RQS,This field indicates the size of the allocated Receive queues in blocks of 256 bytes." "0,1,2,3,4,5,6,7"
bitfld.long 0x4 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets When this bit is set  the MAC does not drop the packets which only have the errors detected by the Receive Checksum Offload engine." "0,1"
newline
bitfld.long 0x4 5. "RSF,Receive Queue Store and Forward When this bit is set  the ethernet block on this chip reads a packet from the Rx queue only after the complete packet has been written to it  ignoring the RTC field of this register." "0,1"
bitfld.long 0x4 4. "FEP,Forward Error Packets When this bit is reset  the Rx queue drops packets with error status (CRC error  Mll_ER  watchdog timeout  or overflow)." "0,1"
newline
bitfld.long 0x4 3. "FUP,Forward Undersized Good Packets When this bit is set  the Rx queue forwards the undersized good packets (packets with no error and length less than 64 bytes)  including pad-bytes and CRC." "0,1"
bitfld.long 0x4 0.--1. "RTC,Receive Queue Threshold Control These bits control the threshold level of the MTL Rx queue (in bytes): 00: 64 01: 32 10: 96 11: 128 The packet received is transferred to the application or DMA when the packet size within the MTL Rx queue is larger.." "0: 64,1: 32,?,?"
line.long 0x8 "MTL_RXQx_MISSPKT_OVRFLW_CNT,MTL RxQx Missed Packet Overflow Counter register"
rbitfld.long 0x8 11. "OVFCNTOVF,Overflow Counter Overflow Bit When set  this bit indicates that the Rx Queue Overflow Packet Counter field crossed the maximum limit." "0,1"
hexmask.long.word 0x8 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter This field indicates the number of packets discarded by the Ethernet block because of Receive queue overflow."
line.long 0xC "MTL_RXQx_DBG,MTL RxQx Debug register"
hexmask.long.word 0xC 16.--29. 1. "PRXQ,Number of Packets in Receive Queue This field indicates the current number of packets in the Rx Queue."
rbitfld.long 0xC 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status This field gives the status of the fill-level of the Rx Queue: 0x0: Rx Queue empty 0x1: Rx Queue fill-level below flow-control deactivate threshold 0x2: Rx Queue fill-level above flow-control activate threshold 0x3:.." "0: Rx Queue empty,1: Rx Queue fill-level below flow-control..,2: Rx Queue fill-level above flow-control activate..,3: Rx Queue full"
newline
rbitfld.long 0xC 1.--2. "RRCSTS,MTL Rx Queue Read Controller State This field gives the state of the Rx queue Read controller: 00: Idle state 01: Reading packet data 10: Reading packet status (or timestamp) 11: Flushing the packet data and status." "0: Idle state,1: Reading packet data,?,?"
bitfld.long 0xC 0. "RWCSTS,MTL Rx Queue Write Controller Active Status When high  this bit indicates that the MTL Rx queue Write controller is active  and it is transferring a received packet to the Rx Queue." "0,1"
line.long 0x10 "MTL_RXQx_CTRL,MTL RxQx Control register"
bitfld.long 0x10 3. "RXQ_FRM_ARBIT,Receive Queue Packet Arbitration When this bit is set  the The ethernet block drives the packet data to the ARI interface such that the entire packet data of currently-selected queue is transmitted before switching to other queue." "0,1"
bitfld.long 0x10 0.--2. "RXQ_WEGT,Receive Queue Weight This field indicates the weight assigned to the Rx Queue 0." "0,1,2,3,4,5,6,7"
tree.end
repeat.end
endif
sif (cpuis("LPC54618*"))
repeat 2. (list 0x0 0x1)(list ad:0x40093100 ad:0x40093180)
tree "DMA_CH[$1]"
base $2
group.long ($2)++0xB
line.long 0x0 "DMA_CHx_CTRL,DMA Channelx Control"
bitfld.long 0x0 18.--20. "DSL,Skip Length This bit specifies the Word  Dword  or Lword number (depending on the 32- bit  64-bit  or 128-bit bus) to skip between two unchained s." "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16. "PBLx8,8xPBL mode When this bit is set  the PBL value programmed in Bits[21:16] in DMA Channel Transmit Control Table 780 is multiplied eight times." "0,1"
line.long 0x4 "DMA_CHx_TX_CTRL,DMA Channelx Transmit Control"
hexmask.long.byte 0x4 16.--21. 1. "TxPBL,Transmit Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA data transfer."
bitfld.long 0x4 4. "OSF,Operate on Second Frame When this bit is set  it instructs the DMA to process the second packet of the Transmit data even before the status for the first packet is obtained." "0,1"
bitfld.long 0x4 1.--3. "TCW,Transmit Channel Weight This field indicates the weight assigned to the corresponding Transmit channel." "0,1,2,3,4,5,6,7"
bitfld.long 0x4 0. "ST,Start or Stop Transmission Command When this bit is set  transmission is placed in the Running state." "0,1"
line.long 0x8 "DMA_CHx_RX_CTRL,DMA Channelx Receive Control"
bitfld.long 0x8 31. "RPF,DMA Rx Channel 0 Packet Flush When this bit is set to 1  the DMA will automatically flush the packet from the Rx Queues destined to DMA Rx Channel 0 when the DMA Rx Channel 0 is stopped after a system bus error has occurred." "0,1"
hexmask.long.byte 0x8 16.--21. 1. "RxPBL,Receive Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA data transfer."
hexmask.long.word 0x8 3.--14. 1. "RBSZ,Receive Buffer size This field indicates the size of the Rx buffers specified in bytes."
bitfld.long 0x8 0. "SR,Start or Stop Receive When this bit is set  the DMA tries to acquire the from the receive list and processes the incoming packets." "0,1"
group.long ($2+0x14)++0x3
line.long 0x0 "DMA_CHx_TXDESC_LIST_ADDR,no description available"
hexmask.long 0x0 2.--31. 1. "STL,Start of transmit list This field contains the base address of the first in the Transmit list."
group.long ($2+0x1C)++0x7
line.long 0x0 "DMA_CHx_RXDESC_LIST_ADDR,no description available"
hexmask.long 0x0 2.--31. 1. "SRL,Start of receive list This field contains the base address of the First in the Receive list."
line.long 0x4 "DMA_CHx_TXDESC_TAIL_PTR,no description available"
hexmask.long 0x4 2.--31. 1. "TDTP,Transmit Tail Pointer This field contains the tail pointer for the Tx ring."
group.long ($2+0x28)++0x17
line.long 0x0 "DMA_CHx_RXDESC_TAIL_PTR,no description available"
hexmask.long 0x0 2.--31. 1. "RDTP,Receive Tail Pointer This field contains the tail pointer for the Rx ring."
line.long 0x4 "DMA_CHx_TXDESC_RING_LENGTH,no description available"
hexmask.long.word 0x4 0.--9. 1. "TDRL,Transmit Ring Length This field sets the maximum number of Tx descriptors in the circular ring."
line.long 0x8 "DMA_CHx_RXDESC_RING_LENGTH,Channelx Rx descriptor Ring Length"
hexmask.long.word 0x8 0.--9. 1. "RDRL,Receive Ring Length This register sets the maximum number of Rx descriptors in the circular ring."
line.long 0xC "DMA_CHx_INT_EN,Channelx Interrupt Enable"
bitfld.long 0xC 15. "NIE,Normal interrupt summary enable When this bit is set  a normal interrupt is enabled." "0,1"
bitfld.long 0xC 14. "AIE,Abnormal interrupt summary enable When this bit is set  an Abnormal Interrupt summary is enabled." "0,1"
bitfld.long 0xC 12. "FBEE,Fatal bus error enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register)  the Fatal Bus Error Interrupt is enabled." "0,1"
bitfld.long 0xC 11. "ERIE,Early receive interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register)  Early Receive Interrupt is enabled." "0,1"
bitfld.long 0xC 10. "ETIE,Early transmit interrupt enable When this bit is set with an Abnormal Interrupt Summary Enable (bit 15 in this register)  Early Transmit Interrupt is enabled." "0,1"
bitfld.long 0xC 9. "RWTE,Receive watchdog timeout enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register)  the Receive Watchdog Timeout Interrupt is enabled." "0,1"
newline
bitfld.long 0xC 8. "RSE,Received stopped enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register)  Receive Stopped Interrupt is enabled." "0,1"
bitfld.long 0xC 7. "RBUE,Receive buffer unavailable enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register)  Receive Buffer Unavailable Interrupt is enabled." "0,1"
bitfld.long 0xC 6. "RIE,Receive interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register)  Receive Interrupt is enabled." "0,1"
bitfld.long 0xC 2. "TBUE,Transmit buffer unavailable enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register)  Transmit Buffer Unavailable Interrupt is enabled." "0,1"
bitfld.long 0xC 1. "TSE,Transmit stopped enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register)  Transmission Stopped Interrupt is enabled." "0,1"
bitfld.long 0xC 0. "TIE,Transmit interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register)  Transmit Interrupt is enabled." "0,1"
line.long 0x10 "DMA_CHx_RX_INT_WDTIMER,Receive Interrupt Watchdog Timer"
hexmask.long.byte 0x10 0.--7. 1. "RIWT,Receive Interrupt Watchdog Timer Count Indicates the number of system clock cycles multiplied by 256 for which the watchdog timer is set."
line.long 0x14 "DMA_CHx_SLOT_FUNC_CTRL_STAT,Slot Function Control and Status"
hexmask.long.byte 0x14 16.--19. 1. "RSN,Reference Slot Number This field gives the current value of the reference slot number in the DMA."
bitfld.long 0x14 1. "ASC,Advance Slot Check When set  this bit enables the D MA to fetch the data from the buffer when the slot number (SLOTNUM) programmed in the Tx descriptor is equal to the reference slot number given in the RSN field or  ahead of the reference slot.." "0,1"
bitfld.long 0x14 0. "ESC,Enable Slot Comparison When set  this bit enables the checking of the slot numbers programmed in the Tx descriptor with the current reference given in the RSN field." "0,1"
rgroup.long ($2+0x44)++0x3
line.long 0x0 "DMA_CHx_CUR_HST_TXDESC,Channelx Current Host Transmit descriptor"
hexmask.long 0x0 0.--31. 1. "HTD,Host Transmit descriptor Address Pointer Cleared on Reset."
rgroup.long ($2+0x4C)++0x3
line.long 0x0 "DMA_CHx_CUR_HST_RXDESC,no description available"
hexmask.long 0x0 0.--31. 1. "HRD,Host Receive descriptor Address Pointer Cleared on Reset."
rgroup.long ($2+0x54)++0x3
line.long 0x0 "DMA_CHx_CUR_HST_TXBUF,no description available"
hexmask.long 0x0 0.--31. 1. "HTB,Host Transmit Buffer Address Pointer Cleared on Reset."
rgroup.long ($2+0x5C)++0x3
line.long 0x0 "DMA_CHx_CUR_HST_RXBUF,Channelx Current Application Receive Buffer Address"
hexmask.long 0x0 0.--31. 1. "HRB,Host Receive Buffer Address Pointer Cleared on Reset."
group.long ($2+0x60)++0x3
line.long 0x0 "DMA_CHx_STAT,Channelx DMA status register"
bitfld.long 0x0 16.--18. "EB,DMA Error Bits This field indicates the type of error that caused a Bus Error." "0,1,2,3,4,5,6,7"
bitfld.long 0x0 15. "NIS,Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in the DMA Channel Interrupt Enable register Table 778: Bit 0: Transmit Interrupt Bit 2: Transmit.." "0: Transmit Interrupt Bit,?"
bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA Channel Interrupt Enable register Table 778: Bit 1: Transmit Process Stopped Bit 7:.." "?,1: Transmit Process Stopped Bit"
bitfld.long 0x0 12. "FBE,Fatal Bus Error This bit indicates that a bus error occurred (as described in the EB field)." "0,1"
bitfld.long 0x0 11. "ERI,Early Receive Interrupt This bit indicates that the DMA filled the first data buffer of the packet." "0,1"
bitfld.long 0x0 10. "ETI,Early Transmit Interrupt This bit indicates that the packet to be transmitted is fully transferred to the MTL Tx FIFO." "0,1"
newline
bitfld.long 0x0 9. "RWT,Receive Watchdog time out This bit is asserted when a packet with length greater than 2 048 bytes (10 240 bytes when Jumbo Packet mode is enabled) is received." "0,1"
bitfld.long 0x0 8. "RPS,Receive Process Stopped This bit is asserted when the Rx process enters the Stopped state." "0,1"
bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable This bit indicates that the application owns the next in the receive list  and the DMA cannot acquire it." "0,1"
bitfld.long 0x0 6. "RI,Receive Interrupt This bit indicates that the packet reception is complete." "0,1"
bitfld.long 0x0 2. "TBU,Transmit Buffer Unavailable This bit indicates that the application owns the next descriptor in the transmit list  and the DMA cannot acquire it." "0,1"
bitfld.long 0x0 1. "TPS,Transmit Process Stopped This bit is set when the transmission is stopped." "0,1"
newline
bitfld.long 0x0 0. "TI,Transmit Interrupt This bit indicates that the packet transmission is complete." "0,1"
tree.end
repeat.end
endif
sif (cpuis("LPC54628*"))
group.long 0x110++0x3
line.long 0x0 "MAC_VERSION,MAC version register"
endif
sif (cpuis("LPC54628*"))
rgroup.long 0x11C++0x3
line.long 0x0 "MAC_HW_FEAT0,MAC hardware feature register 0x0201"
bitfld.long 0x0 28.--30. "ACTPHYSEL,Active PHY Selected." "0,1,2,3,4,5,6,7"
bitfld.long 0x0 25.--26. "TSSTSSEL,Timestamp System Time Source." "0,1,2,3"
newline
bitfld.long 0x0 14. "TXCOESEL,Transmit Checksum Offload Support." "0,1"
bitfld.long 0x0 13. "EEESEL,Energy Efficient Ethernet Support ." "0,1"
newline
bitfld.long 0x0 12. "TSSEL,IEEE 1588-2008 Timestamp support ." "0,1"
bitfld.long 0x0 9. "ARPOFFSEL,ARP Offload Enabled." "0,1"
newline
bitfld.long 0x0 8. "MMCSEL,RMON Module Enable." "0,1"
bitfld.long 0x0 6. "RWKSEL,PMT Remote Wake-up Packet Detection." "0,1"
newline
bitfld.long 0x0 5. "SMASEL,SMA (MDIO) Interface." "0,1"
bitfld.long 0x0 4. "VLHASH,Hash Table Based Filtering option." "0,1"
newline
bitfld.long 0x0 2. "HDSEL,Half-duplex Support." "0,1"
bitfld.long 0x0 0. "MIISEL,10 or 100 Mbps Support." "0,1"
endif
sif (cpuis("LPC54628*"))
repeat 2. (list 0x0 0x1)(list ad:0x40092D00 ad:0x40092D40)
tree "MTL_QUEUE[$1]"
base $2
group.long ($2)++0x3
line.long 0x0 "MTL_TXQx_OP_MODE,MTL TxQx Operation Mode register"
bitfld.long 0x0 16.--18. "TQS,Transmit Queue Size This field indicates the size of the allocated Transmit queues in blocks of 256 bytes." "0,1,2,3,4,5,6,7"
bitfld.long 0x0 4.--6. "TTC,Transmit Threshold Control These bits control the threshold level of the MTL Tx Queue." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 2.--3. "TXQEN,Transmit Queue Enable This field is used to enable/disable the transmit queue 0." "0,1,2,3"
bitfld.long 0x0 1. "TSF,Transmit Store and Forward When this bit is set  the transmission starts when a full packet resides in the MTL Tx queue." "0,1"
newline
bitfld.long 0x0 0. "FTQ,Flush Transmit Queue When this bit is set  the Tx queue controller logic is reset to its default values." "0,1"
rgroup.long ($2+0x4)++0x7
line.long 0x0 "MTL_TXQx_UNDRFLW,MTL TxQx Underflow register"
bitfld.long 0x0 11. "UFCNTOVF,Overflow Bit for Underflow Packet Counter This bit is set every time the Tx queue Underflow Packet Counter field overflows  that is  it has crossed the maximum count." "0,1"
hexmask.long.word 0x0 0.--10. 1. "UFFRMCNT,Underflow Packet Counter This field indicates the number of packets aborted by the controller because of Tx Queue Underflow."
line.long 0x4 "MTL_TXQx_DBG,MTL TxQx Debug register"
bitfld.long 0x4 20.--22. "STSXSTSF,Number of Status Words in Tx Status FIFO of Queue This field indicates the current number of status in the Tx Status FIFO of this queue." "0,1,2,3,4,5,6,7"
bitfld.long 0x4 16.--18. "PTXQ,Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx Queue." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 5. "TXSTSFSTS,MTL Tx Status FIFO Full Status When high  this bit indicates that the MTL Tx Status FIFO is full." "0,1"
bitfld.long 0x4 4. "TXQSTS,MTL Tx Queue Not Empty Status When this bit is high  it indicates that the MTL Tx Queue is not empty and some data is left for transmission." "0,1"
newline
bitfld.long 0x4 3. "TWCSTS,MTL Tx Queue Write Controller Status When high  this bit indicates that the MTL Tx Queue Write Controller is active  and it is transferring the data to the Tx Queue." "0,1"
bitfld.long 0x4 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read Controller: 00: Idle state 01: Read state (transferring data to the MAC transmitter) 10: Waiting for pending Tx Status from the MAC transmitter 11: Flushing.." "0: Idle state,1: Read state,?,?"
newline
bitfld.long 0x4 0. "TXQPAUSED,Transmit Queue in Pause When this bit is high and the Rx flow control is enabled  it indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because of the following: - Reception of the PFC packet for the priorities.." "0,1"
group.long ($2+0x10)++0x17
line.long 0x0 "MTL_TXQx_ETS_CTRL,MTL TxQx ETS control register. only TxQ1 support"
rbitfld.long 0x0 4.--6. "SLC,Credit Control." "0,1,2,3,4,5,6,7"
bitfld.long 0x0 3. "CC,Credit Control." "0,1"
newline
bitfld.long 0x0 2. "AVALG,AV Algorithm." "0,1"
line.long 0x4 "MTL_TXQx_ETS_STAT,MTL TxQx ETS Status register"
hexmask.long.tbyte 0x4 0.--23. 1. "ABS,Average Bits per Slot."
line.long 0x8 "MTL_TXQx_QNTM_WGHT,no description available"
hexmask.long.tbyte 0x8 0.--20. 1. "ISCQW,Average Bits per Slot."
line.long 0xC "MTL_TXQx_SNDSLP_CRDT,MTL TxQx SendSlopCredit register. only TxQ1 support"
hexmask.long.word 0xC 0.--13. 1. "SSC,sendSlopeCredit."
line.long 0x10 "MTL_TXQx_HI_CRDT,MTL TxQx hiCredit register. only TxQ1 support"
hexmask.long 0x10 0.--28. 1. "HC,hiCredit."
line.long 0x14 "MTL_TXQx_LO_CRDT,MTL TxQx loCredit register. only TxQ1 support"
hexmask.long 0x14 0.--28. 1. "LC,loCredit."
group.long ($2+0x2C)++0x13
line.long 0x0 "MTL_TXQx_INTCTRL_STAT,no description available"
bitfld.long 0x0 24. "RXOIE,Receive Queue Overflow Interrupt Enable When this bit is set  the Receive Queue Overflow interrupt is enabled." "0,1"
bitfld.long 0x0 16. "RXOVFIS,Receive Queue Overflow Interrupt Status This bit indicates that the Receive Queue had an overflow while receiving the packet." "0,1"
newline
bitfld.long 0x0 9. "ABPSIE,Average Bits Per Slot Interrupt Enable When this bit is set  the MAC asserts the interrupt when the average bits per slot status is updated." "0,1"
bitfld.long 0x0 8. "TXUIE,Transmit Queue Underflow Interrupt Enable When this bit is set  the Transmit Queue Underflow interrupt is enabled." "0,1"
newline
bitfld.long 0x0 1. "ABPSIS,Average Bits Per Slot Interrupt Status When set  this bit indicates that the MAC has updated the ABS value." "0,1"
bitfld.long 0x0 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status This bit indicates that the Transmit Queue had an underflow while transmitting the packet." "0,1"
line.long 0x4 "MTL_RXQx_OP_MODE,MTL RxQx Operation Mode register"
bitfld.long 0x4 20.--22. "RQS,This field indicates the size of the allocated Receive queues in blocks of 256 bytes." "0,1,2,3,4,5,6,7"
bitfld.long 0x4 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets When this bit is set  the MAC does not drop the packets which only have the errors detected by the Receive Checksum Offload engine." "0,1"
newline
bitfld.long 0x4 5. "RSF,Receive Queue Store and Forward When this bit is set  the ethernet block on this chip reads a packet from the Rx queue only after the complete packet has been written to it  ignoring the RTC field of this register." "0,1"
bitfld.long 0x4 4. "FEP,Forward Error Packets When this bit is reset  the Rx queue drops packets with error status (CRC error  Mll_ER  watchdog timeout  or overflow)." "0,1"
newline
bitfld.long 0x4 3. "FUP,Forward Undersized Good Packets When this bit is set  the Rx queue forwards the undersized good packets (packets with no error and length less than 64 bytes)  including pad-bytes and CRC." "0,1"
bitfld.long 0x4 0.--1. "RTC,Receive Queue Threshold Control These bits control the threshold level of the MTL Rx queue (in bytes): 00: 64 01: 32 10: 96 11: 128 The packet received is transferred to the application or DMA when the packet size within the MTL Rx queue is larger.." "0: 64,1: 32,?,?"
line.long 0x8 "MTL_RXQx_MISSPKT_OVRFLW_CNT,MTL RxQx Missed Packet Overflow Counter register"
rbitfld.long 0x8 11. "OVFCNTOVF,Overflow Counter Overflow Bit When set  this bit indicates that the Rx Queue Overflow Packet Counter field crossed the maximum limit." "0,1"
hexmask.long.word 0x8 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter This field indicates the number of packets discarded by the Ethernet block because of Receive queue overflow."
line.long 0xC "MTL_RXQx_DBG,MTL RxQx Debug register"
hexmask.long.word 0xC 16.--29. 1. "PRXQ,Number of Packets in Receive Queue This field indicates the current number of packets in the Rx Queue."
rbitfld.long 0xC 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status This field gives the status of the fill-level of the Rx Queue: 0x0: Rx Queue empty 0x1: Rx Queue fill-level below flow-control deactivate threshold 0x2: Rx Queue fill-level above flow-control activate threshold 0x3:.." "0: Rx Queue empty,1: Rx Queue fill-level below flow-control..,2: Rx Queue fill-level above flow-control activate..,3: Rx Queue full"
newline
rbitfld.long 0xC 1.--2. "RRCSTS,MTL Rx Queue Read Controller State This field gives the state of the Rx queue Read controller: 00: Idle state 01: Reading packet data 10: Reading packet status (or timestamp) 11: Flushing the packet data and status." "0: Idle state,1: Reading packet data,?,?"
bitfld.long 0xC 0. "RWCSTS,MTL Rx Queue Write Controller Active Status When high  this bit indicates that the MTL Rx queue Write controller is active  and it is transferring a received packet to the Rx Queue." "0,1"
line.long 0x10 "MTL_RXQx_CTRL,MTL RxQx Control register"
bitfld.long 0x10 3. "RXQ_FRM_ARBIT,Receive Queue Packet Arbitration When this bit is set  the The ethernet block drives the packet data to the ARI interface such that the entire packet data of currently-selected queue is transmitted before switching to other queue." "0,1"
bitfld.long 0x10 0.--2. "RXQ_WEGT,Receive Queue Weight This field indicates the weight assigned to the Rx Queue 0." "0,1,2,3,4,5,6,7"
tree.end
repeat.end
endif
sif (cpuis("LPC54628*"))
repeat 2. (list 0x0 0x1)(list ad:0x40093100 ad:0x40093180)
tree "DMA_CH[$1]"
base $2
group.long ($2)++0xB
line.long 0x0 "DMA_CHx_CTRL,DMA Channelx Control"
bitfld.long 0x0 18.--20. "DSL,Skip Length This bit specifies the Word  Dword  or Lword number (depending on the 32- bit  64-bit  or 128-bit bus) to skip between two unchained s." "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16. "PBLx8,8xPBL mode When this bit is set  the PBL value programmed in Bits[21:16] in DMA Channel Transmit Control Table 780 is multiplied eight times." "0,1"
line.long 0x4 "DMA_CHx_TX_CTRL,DMA Channelx Transmit Control"
hexmask.long.byte 0x4 16.--21. 1. "TxPBL,Transmit Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA data transfer."
bitfld.long 0x4 4. "OSF,Operate on Second Frame When this bit is set  it instructs the DMA to process the second packet of the Transmit data even before the status for the first packet is obtained." "0,1"
bitfld.long 0x4 1.--3. "TCW,Transmit Channel Weight This field indicates the weight assigned to the corresponding Transmit channel." "0,1,2,3,4,5,6,7"
bitfld.long 0x4 0. "ST,Start or Stop Transmission Command When this bit is set  transmission is placed in the Running state." "0,1"
line.long 0x8 "DMA_CHx_RX_CTRL,DMA Channelx Receive Control"
bitfld.long 0x8 31. "RPF,DMA Rx Channel 0 Packet Flush When this bit is set to 1  the DMA will automatically flush the packet from the Rx Queues destined to DMA Rx Channel 0 when the DMA Rx Channel 0 is stopped after a system bus error has occurred." "0,1"
hexmask.long.byte 0x8 16.--21. 1. "RxPBL,Receive Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA data transfer."
hexmask.long.word 0x8 3.--14. 1. "RBSZ,Receive Buffer size This field indicates the size of the Rx buffers specified in bytes."
bitfld.long 0x8 0. "SR,Start or Stop Receive When this bit is set  the DMA tries to acquire the from the receive list and processes the incoming packets." "0,1"
group.long ($2+0x14)++0x3
line.long 0x0 "DMA_CHx_TXDESC_LIST_ADDR,no description available"
hexmask.long 0x0 2.--31. 1. "STL,Start of transmit list This field contains the base address of the first in the Transmit list."
group.long ($2+0x1C)++0x7
line.long 0x0 "DMA_CHx_RXDESC_LIST_ADDR,no description available"
hexmask.long 0x0 2.--31. 1. "SRL,Start of receive list This field contains the base address of the First in the Receive list."
line.long 0x4 "DMA_CHx_TXDESC_TAIL_PTR,no description available"
hexmask.long 0x4 2.--31. 1. "TDTP,Transmit Tail Pointer This field contains the tail pointer for the Tx ring."
group.long ($2+0x28)++0x17
line.long 0x0 "DMA_CHx_RXDESC_TAIL_PTR,no description available"
hexmask.long 0x0 2.--31. 1. "RDTP,Receive Tail Pointer This field contains the tail pointer for the Rx ring."
line.long 0x4 "DMA_CHx_TXDESC_RING_LENGTH,no description available"
hexmask.long.word 0x4 0.--9. 1. "TDRL,Transmit Ring Length This field sets the maximum number of Tx descriptors in the circular ring."
line.long 0x8 "DMA_CHx_RXDESC_RING_LENGTH,Channelx Rx descriptor Ring Length"
hexmask.long.word 0x8 0.--9. 1. "RDRL,Receive Ring Length This register sets the maximum number of Rx descriptors in the circular ring."
line.long 0xC "DMA_CHx_INT_EN,Channelx Interrupt Enable"
bitfld.long 0xC 15. "NIE,Normal interrupt summary enable When this bit is set  a normal interrupt is enabled." "0,1"
bitfld.long 0xC 14. "AIE,Abnormal interrupt summary enable When this bit is set  an Abnormal Interrupt summary is enabled." "0,1"
bitfld.long 0xC 12. "FBEE,Fatal bus error enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register)  the Fatal Bus Error Interrupt is enabled." "0,1"
bitfld.long 0xC 11. "ERIE,Early receive interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register)  Early Receive Interrupt is enabled." "0,1"
bitfld.long 0xC 10. "ETIE,Early transmit interrupt enable When this bit is set with an Abnormal Interrupt Summary Enable (bit 15 in this register)  Early Transmit Interrupt is enabled." "0,1"
bitfld.long 0xC 9. "RWTE,Receive watchdog timeout enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register)  the Receive Watchdog Timeout Interrupt is enabled." "0,1"
newline
bitfld.long 0xC 8. "RSE,Received stopped enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register)  Receive Stopped Interrupt is enabled." "0,1"
bitfld.long 0xC 7. "RBUE,Receive buffer unavailable enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register)  Receive Buffer Unavailable Interrupt is enabled." "0,1"
bitfld.long 0xC 6. "RIE,Receive interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register)  Receive Interrupt is enabled." "0,1"
bitfld.long 0xC 2. "TBUE,Transmit buffer unavailable enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register)  Transmit Buffer Unavailable Interrupt is enabled." "0,1"
bitfld.long 0xC 1. "TSE,Transmit stopped enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register)  Transmission Stopped Interrupt is enabled." "0,1"
bitfld.long 0xC 0. "TIE,Transmit interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register)  Transmit Interrupt is enabled." "0,1"
line.long 0x10 "DMA_CHx_RX_INT_WDTIMER,Receive Interrupt Watchdog Timer"
hexmask.long.byte 0x10 0.--7. 1. "RIWT,Receive Interrupt Watchdog Timer Count Indicates the number of system clock cycles multiplied by 256 for which the watchdog timer is set."
line.long 0x14 "DMA_CHx_SLOT_FUNC_CTRL_STAT,Slot Function Control and Status"
hexmask.long.byte 0x14 16.--19. 1. "RSN,Reference Slot Number This field gives the current value of the reference slot number in the DMA."
bitfld.long 0x14 1. "ASC,Advance Slot Check When set  this bit enables the D MA to fetch the data from the buffer when the slot number (SLOTNUM) programmed in the Tx descriptor is equal to the reference slot number given in the RSN field or  ahead of the reference slot.." "0,1"
bitfld.long 0x14 0. "ESC,Enable Slot Comparison When set  this bit enables the checking of the slot numbers programmed in the Tx descriptor with the current reference given in the RSN field." "0,1"
rgroup.long ($2+0x44)++0x3
line.long 0x0 "DMA_CHx_CUR_HST_TXDESC,Channelx Current Host Transmit descriptor"
hexmask.long 0x0 0.--31. 1. "HTD,Host Transmit descriptor Address Pointer Cleared on Reset."
rgroup.long ($2+0x4C)++0x3
line.long 0x0 "DMA_CHx_CUR_HST_RXDESC,no description available"
hexmask.long 0x0 0.--31. 1. "HRD,Host Receive descriptor Address Pointer Cleared on Reset."
rgroup.long ($2+0x54)++0x3
line.long 0x0 "DMA_CHx_CUR_HST_TXBUF,no description available"
hexmask.long 0x0 0.--31. 1. "HTB,Host Transmit Buffer Address Pointer Cleared on Reset."
rgroup.long ($2+0x5C)++0x3
line.long 0x0 "DMA_CHx_CUR_HST_RXBUF,Channelx Current Application Receive Buffer Address"
hexmask.long 0x0 0.--31. 1. "HRB,Host Receive Buffer Address Pointer Cleared on Reset."
group.long ($2+0x60)++0x3
line.long 0x0 "DMA_CHx_STAT,Channelx DMA status register"
bitfld.long 0x0 16.--18. "EB,DMA Error Bits This field indicates the type of error that caused a Bus Error." "0,1,2,3,4,5,6,7"
bitfld.long 0x0 15. "NIS,Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in the DMA Channel Interrupt Enable register Table 778: Bit 0: Transmit Interrupt Bit 2: Transmit.." "0: Transmit Interrupt Bit,?"
bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA Channel Interrupt Enable register Table 778: Bit 1: Transmit Process Stopped Bit 7:.." "?,1: Transmit Process Stopped Bit"
bitfld.long 0x0 12. "FBE,Fatal Bus Error This bit indicates that a bus error occurred (as described in the EB field)." "0,1"
bitfld.long 0x0 11. "ERI,Early Receive Interrupt This bit indicates that the DMA filled the first data buffer of the packet." "0,1"
bitfld.long 0x0 10. "ETI,Early Transmit Interrupt This bit indicates that the packet to be transmitted is fully transferred to the MTL Tx FIFO." "0,1"
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bitfld.long 0x0 9. "RWT,Receive Watchdog time out This bit is asserted when a packet with length greater than 2 048 bytes (10 240 bytes when Jumbo Packet mode is enabled) is received." "0,1"
bitfld.long 0x0 8. "RPS,Receive Process Stopped This bit is asserted when the Rx process enters the Stopped state." "0,1"
bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable This bit indicates that the application owns the next in the receive list  and the DMA cannot acquire it." "0,1"
bitfld.long 0x0 6. "RI,Receive Interrupt This bit indicates that the packet reception is complete." "0,1"
bitfld.long 0x0 2. "TBU,Transmit Buffer Unavailable This bit indicates that the application owns the next descriptor in the transmit list  and the DMA cannot acquire it." "0,1"
bitfld.long 0x0 1. "TPS,Transmit Process Stopped This bit is set when the transmission is stopped." "0,1"
newline
bitfld.long 0x0 0. "TI,Transmit Interrupt This bit indicates that the packet transmission is complete." "0,1"
tree.end
repeat.end
endif
tree.end
endif
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54605*")||cpuis("LPC54606*")||cpuis("LPC54607*")||cpuis("LPC54608*")||cpuis("LPC54616*")||cpuis("LPC54618*")||cpuis("LPC54628*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
tree "ETM (Embedded Trace Macrocell)"
base ad:0xE0041000
group.long 0x0++0x3
line.long 0x0 "CR,Main Control Register"
bitfld.long 0x0 28. "TE,When set  this bit enables timestamping. An ETM reset sets this bit to 0." "0,1"
newline
bitfld.long 0x0 21. "PS3,This bit is implemented but has no function. An ETM reset sets this bit to 0." "0,1"
newline
bitfld.long 0x0 16.--17. "PM,These bits are implemented but have no function. An ETM reset sets these bits to 0." "0,1,2,3"
newline
bitfld.long 0x0 13. "PM2,This bit is implemented but has no function. An ETM reset sets this bit to 0." "0,1"
newline
bitfld.long 0x0 11. "ETMPS,ETM port selection. This bit can be used to control other trace components in an implementation. This bit must be set by the trace software tools to ensure that trace output is enabled from this ETM. An ETM reset sets this bit to 0." "0: ETMEN is LOW.,1: ETMEN is HIGH."
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bitfld.long 0x0 10. "ETMP,ETM programming. This bit must be set to 1 at the start of the ETM programming sequence. Tracing is prevented while this bit is set to 1. On an ETM reset this bit is set to b1." "0,1"
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bitfld.long 0x0 9. "DRC,Debug request control. When set to 1 and the trigger event occurs  the DBGRQ output is asserted until DBGACK is observed. This enables the ARM processor to be forced into Debug state. An ETM reset sets this bit to 0." "0,1"
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bitfld.long 0x0 8. "BO,Branch output. When set to 1 all branch addresses are output  even if the branch was because of a direct branch instruction. Setting this bit enables reconstruction of the program flow without having access to the memory image of the code being.." "0,1"
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bitfld.long 0x0 7. "SP,Stall processor. The FIFOFULL output can be used to stall the processor to prevent overflow. The FIFOFULL output is only enabled when the stall processor bit is set to 1. When the bit is 0 the FIFOFULL output remains LOW at all times and the FIFO.." "0,1"
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bitfld.long 0x0 4.--6. "PS,Port size. The ETM-M4 has no influence over the external pins used for trace. These bits are implemented but not used. On an ETM reset these bits reset to 0b001." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 0. "ETMPD,ETM power down. This bit can be used by an implementation to control if the ETM is in a low power state. This bit must be cleared by the trace software tools at the beginning of a debug session. When this bit is set to 1  writes to some registers.." "0,1"
rgroup.long 0x4++0x3
line.long 0x0 "CCR,Configuration Code Register"
bitfld.long 0x0 31. "ETMIDRP,The value of this bit is 1  indicating that the ETMIDR  register 0x79  is present and defines the ETM architecture version in use." "0,1"
newline
bitfld.long 0x0 27. "CMA,Coprocessor and memory access. The value of this bit is 1  indicating that memory-mapped access to registers is supported." "0,1"
newline
bitfld.long 0x0 26. "TSSBP,Trace start/stop block present. The value of this bit is 1  indicating that the Trace start/stop block is present." "0,1"
newline
bitfld.long 0x0 24.--25. "NCIDC,Number of Context ID comparators. The value of these bits is b00  indicating that Context ID comparators are not implemented." "0,1,2,3"
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bitfld.long 0x0 23. "FFLP,FIFOFULL logic present. The value of this bit is 1  indicating that FIFOFULL logic is present in the ETM. To use FIFOFULL the system must also support the function  as indicated by bit [8] of ETMSCR." "0,1"
newline
bitfld.long 0x0 20.--22. "NEO,Number of external outputs. The value of these bits is b000  indicating that no external outputs are supported." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 17.--19. "NEI,Number of external inputs. The value of these bits is between b000 and b010  indicating the number of external inputs  from 0 to 2  implemented in the system." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 16. "SP,Sequencer present. The value of this bit is 0  indicating that the sequencer is not implemented." "0,1"
newline
bitfld.long 0x0 13.--15. "NC,Number of counters. The value of these bits is b001  indicating that one counter is implemented." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 8.--12. 1. "NMMD,Number of memory map decoders. The value of these bits is b00000  indicating that memory map decoder inputs are not implemented."
newline
hexmask.long.byte 0x0 4.--7. 1. "NDVC,Number of data value comparators. The value of these bits is b0000  indicating that data value comparators are not implemented."
newline
hexmask.long.byte 0x0 0.--3. 1. "NumberOfAddressComparatorPairs,Number of address comparator pairs. The value of these bits is b0000  indicating that address comparator pairs are not implemented."
group.long 0x8++0x3
line.long 0x0 "TRIGGER,Trigger Event Register"
hexmask.long.tbyte 0x0 0.--16. 1. "TriggerEvent,Trigger event"
group.long 0x10++0x3
line.long 0x0 "SR,ETM Status Register"
bitfld.long 0x0 3. "Trigger,Trigger bit. Set when the trigger occurs  and prevents the trigger from being output until the ETM is next programmed." "0,1"
newline
bitfld.long 0x0 2. "Status,Holds the current status of the trace start/stop resource. If set to 1  it indicates that a trace on address has been matched  without a corresponding trace off address match." "0,1"
newline
rbitfld.long 0x0 1. "Progbit,ETM programming bit value (Progbit). The current effective value of the ETM Programming bit (ETM Control Register bit [10]). Tou must wait for this bit to go to 1 before you start to program the ETM." "0,1"
newline
rbitfld.long 0x0 0. "UOF,Untraced overflow flag. If set to 1  there is an overflow that has not yet been traced. This bit is cleared to 0 when either: - trace is restarted - the ETM Power Down bit  bit [0] of the ETM Control Register  0x00  is set to 1. Note: Setting or.." "0,1"
rgroup.long 0x14++0x3
line.long 0x0 "SCR,System Configuration Register"
bitfld.long 0x0 17. "NoFetchComparisons,No Fetch comparisons. The value of this bit is 1  indicating that fetch comparisons are not implemented." "0,1"
newline
bitfld.long 0x0 12.--14. "N,These bits give the number of supported processors minus 1. The value of these bits is b000  indicating that there is only one processor connected." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 11. "PortModeSupported,Port mode supported. This bit reads as 1 if the currently selected port mode is supported. This has no effect on the TPIU trace port." "0,1"
newline
bitfld.long 0x0 10. "PortSizeSupported,Port size supported. This bit reads as 1 if the currently selected port size is supported. This has no effect on the TPIU trace port." "0,1"
newline
bitfld.long 0x0 9. "MaximumPortSize3,Maximum ETM port size bit [3]. This bit is used in conjunction with bits [2:0]. Its value is 0. This has no effect on the TPIU trace port." "0,1"
newline
bitfld.long 0x0 8. "FIFOFULLsupported,FIFOFULL supported. The value of this bit is 1  indicating that FIFOFULL is supported. This bit is used in conjunction with bit [23] of the ETMCCR." "0,1"
newline
bitfld.long 0x0 0.--2. "MaximumPortSize,Maximum ETM port size bits [2:0]. These bits are used in conjunction with bit [9]. The value of these bits is b001." "0,1,2,3,4,5,6,7"
group.long 0x20++0xB
line.long 0x0 "EEVR,Trace Enable Event Register"
hexmask.long.tbyte 0x0 0.--16. 1. "TraceEnableEvent,Trace Enable event."
line.long 0x4 "TECR1,Trace Enable Control 1 Register"
bitfld.long 0x4 25. "TraceControlEnable,Trace start/stop enable. The trace start/stop resource  resource 0x5F  is unaffected by the value of this bit." "0: Tracing is unaffected by the trace start/stop..,1: Tracing is controlled by the trace on and off.."
line.long 0x8 "FFLR,FIFOFULL Level Register"
hexmask.long.byte 0x8 0.--7. 1. "FIFOFullLevel,FIFO full level. The number of bytes left in FIFO  below which the FIFOFULL or SupressData signal is asserted. For example  setting this value to 15 causes data trace suppression or processor stalling  if enabled  when there are less than.."
group.long 0x140++0x3
line.long 0x0 "CNTRLDVR1,Free-running counter reload value"
hexmask.long.word 0x0 0.--15. 1. "IntitialCount,Initial count."
rgroup.long 0x1E0++0xB
line.long 0x0 "SYNCFR,Synchronization Frequency Register"
hexmask.long.word 0x0 0.--11. 1. "SyncFrequency,Synchronization frequency. Default value is 1024."
line.long 0x4 "IDR,ID Register"
hexmask.long.byte 0x4 24.--31. 1. "ImplementorCode,Implementor code. These bits identify ARM as the implementor of the processor. The value of these bits is 01000001."
newline
bitfld.long 0x4 20. "BranchPacketEncoding,Branch packet encoding. The value of this bit is 1  indicating that alternative branch packet encoding is implemented." "0: The ETM implements the original branch packet..,1: The ETM implements the alternative branch packet.."
newline
bitfld.long 0x4 19. "SecurityExtensionSupport,Security Extensions support. The value of this bit is 0  indicating that the ETM behaves as if the processor is in Secure state at all times." "0: The ETM behaves as if the processor is in Secure..,1: The ARM architecture Security Extensions are.."
newline
bitfld.long 0x4 18. "ThumbInstructionTracing,32-bit Thumb instruction tracing. The value of this bit is 1  indicating that a 32-bit Thumb instruction is traced as a single instruction." "0: A 32-bit Thumb instruction is traced as two..,1: A 32-bit Thimb instruction is traced as a single.."
newline
bitfld.long 0x4 16. "LoadPCfirst,Load PC first. The value of this bit is 0  indicating that data tracing is not supported." "0,1"
newline
hexmask.long.byte 0x4 12.--15. 1. "ProcessorFamily,Processor family. The value of these bits is 0b1111  indicating that the processor family is not identified in this register."
newline
hexmask.long.byte 0x4 8.--11. 1. "MajorETMarchitectureVersion,Major ETM architecture version. The value of these bits is 0b0010  indicating major architecture version number 3  ETMv3."
newline
hexmask.long.byte 0x4 4.--7. 1. "MinorETMarchitectureVersion,Minor ETM architecture version. The value of these bits is 0b0101  indicating minor architecture version number 5."
newline
hexmask.long.byte 0x4 0.--3. 1. "ImplementationRevision,Implementation revision. The value of these bits is b0000  indicating implementation revision  0."
line.long 0x8 "CCER,Configuration Code Extension Register"
bitfld.long 0x8 29. "TimestampSize,Timestamp size. Set to 0 to indicate a size of 48 bits." "0,1"
newline
bitfld.long 0x8 28. "TimestampEncoding,Timestamp encoding. Set to 1 to indicate that the timestamp is encoded as a natural binary number." "0,1"
newline
bitfld.long 0x8 27. "ReducedFunctionCounter,Reduced function counter. Set to 1 to indicate that Counter 1 is a reduced function counter." "0,1"
newline
bitfld.long 0x8 22. "TimestampingImplemented,Timestamping implemented. This bit is set to 1  indicating that timestamping is implemented." "0,1"
newline
bitfld.long 0x8 21. "EmbeddedICEbehaviorControlImplemented,EmbeddedICE behavior control implemented. The value of this bit is 0  indicating that the ETMEIBCR is not implemented." "0,1"
newline
bitfld.long 0x8 20. "TraceStartStopBlockUsesEmbeddedICEwatchpointInputs,Trace Start/Stop block uses EmbeddedICE watchpoint inputs. The value of this bit is 1  indicating that the Trace Start/Stop block uses the EmbeddedICE watchpoint inputs." "0,1"
newline
hexmask.long.byte 0x8 16.--19. 1. "EmbeddedICEwatchpointInputs,EmbeddedICE watchpoint inputs. The value of these bits is 0b0100  indicating that the number of EmbeddedICE watchpoint inputs implemented is four. These inputs come from the DWT."
newline
bitfld.long 0x8 13.--15. "InstrumentationResources,Instrumentation resources. The value of these bits is 0b000  indicating that no Instrumentation resources are supported." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x8 12. "DataAddressComparisons,Data address comparisons. The value of this bit is 1  indicating that data address comparisons are not supported." "0,1"
newline
bitfld.long 0x8 11. "ReadableRegisters,Readable registers. The value of this bit is 1  indicating that all registers are readable." "0,1"
newline
hexmask.long.byte 0x8 3.--10. 1. "ExtendedExternalInputBus,Extended external input bus. The value of these bits is 0  indicating that the extended external input bus is not implemented."
newline
bitfld.long 0x8 0.--2. "ExtendedExternalInputSelectors,Extended external input selectors. The value of these bits is 0  indicating that extended external input selectors are not implemented." "0,1,2,3,4,5,6,7"
group.long 0x1F0++0x3
line.long 0x0 "TESSEICR,TraceEnable Start/Stop EmbeddedICE Control Register"
hexmask.long.byte 0x0 16.--19. 1. "StopResourceSelection,Stop resource selection. Setting any of these bits to 1 selects the corresponding EmbeddedICE watchpoint input as a TraceEnable stop resource. Bit [16] corresponds to input 1  bit [17] corresponds to input 2  bit [18] corresponds to.."
newline
hexmask.long.byte 0x0 0.--3. 1. "StartResourceSelection,Start resource selection. Setting any of these bits to 1 selects the corresponding EmbeddedICE watchpoint input as a TraceEnable start resource. Bit [0] corresponds to input 1  bit [1] corresponds to input 2  bit [2] corresponds to.."
group.long 0x1F8++0x3
line.long 0x0 "TSEVR,Timestamp Event Register"
hexmask.long.word 0x0 0.--11. 1. "TimestampEvent,Timestamp event."
group.long 0x200++0x3
line.long 0x0 "TRACEIDR,CoreSight Trace ID Register"
hexmask.long.byte 0x0 0.--6. 1. "TraceID,Trace ID to output onto the trace bus. On an ETM reset this field is cleared to 0x00."
rgroup.long 0x208++0x3
line.long 0x0 "IDR2,ETM ID Register 2"
rgroup.long 0x314++0x3
line.long 0x0 "PDSR,Device Power-Down Status Register"
bitfld.long 0x0 0. "ETMpoweredup,The value of this bit indicates whether you can access the ETM Trace Registers. The value of this bit is always 1  indicating that the ETM Trace Registers can be accessed." "0,1"
rgroup.long 0xEE0++0x3
line.long 0x0 "_ITMISCIN,Integration Test Miscelaneous Inputs Register"
bitfld.long 0x0 4. "COREHALT,A read of this bit returns the value of the COREHALT input pin." "0,1"
newline
bitfld.long 0x0 0.--1. "EXTIN,A read of these bits returns the value of the EXTIN[1:0] input pins." "0,1,2,3"
wgroup.long 0xEE8++0x3
line.long 0x0 "_ITTRIGOUT,Integration Test Trigger Out Register"
bitfld.long 0x0 0. "TRIGGER,A write to this bit sets the TRIGGER output." "0,1"
rgroup.long 0xEF0++0x3
line.long 0x0 "_ITATBCTR2,ETM Integration Test ATB Control 2 Register"
bitfld.long 0x0 0. "ATREADY,A read of this bit returns the value of the ETM ATREADY input." "0,1"
wgroup.long 0xEF8++0x3
line.long 0x0 "_ITATBCTR0,ETM Integration Test ATB Control 0 Register"
bitfld.long 0x0 0. "ATVALID,A write to this bit sets the value of the ETM ATVALID output." "0,1"
group.long 0xF00++0x3
line.long 0x0 "ITCTRL,Integration Mode Control Register"
bitfld.long 0x0 0. "Mode,Enable integration mode. When this bit is set to 1  the device enters integration mode to enable Topology Detection or Integration Testing to be checked. On an ETM reset this bit is cleared to 0." "0,1"
group.long 0xFA0++0x7
line.long 0x0 "CLAIMSET,Claim Tag Set Register"
hexmask.long.byte 0x0 0.--3. 1. "CLAIMSET,A bit programmable register bank which sets the Claim Tag Value. Write 1 to set the bit in the claim tag. A read will return a logic 1 for all implemented locations."
line.long 0x4 "CLAIMCLR,Claim Tag Clear Register"
hexmask.long.byte 0x4 0.--3. 1. "CLAIMCLR,A bit programmable register bank that is zero at reset. Write 1 to clear the bit in the claim tag. On reads  returns the current setting of the claim tag."
group.long 0xFB0++0x3
line.long 0x0 "LAR,Lock Access Register"
hexmask.long 0x0 0.--31. 1. "WriteAccessCode,Write Access Code. A write of 0xC5ACCE55 enables further write access to this device. An invalid write will have the affect of removing write access."
rgroup.long 0xFB4++0x7
line.long 0x0 "LSR,Lock Status Register"
bitfld.long 0x0 2. "s8BIT,Access Lock Register size. This bit reads 0 to indicate a 32-bit register is present." "0,1"
newline
bitfld.long 0x0 1. "STATUS,Lock Status. This bit is HIGH when the device is locked  and LOW when unlocked." "0: Access permitted.,1: Write access to the component is blocked. All.."
newline
bitfld.long 0x0 0. "IMP,Lock mechanism is implemented. This bit always reads 1." "0,1"
line.long 0x4 "AUTHSTATUS,Authentication Status Register"
bitfld.long 0x4 6.--7. "SNID,Permission for Secure non-invasive debug." "0,1,2,3"
newline
bitfld.long 0x4 4.--5. "SID,Reads as b00  Secure invasive debug not supported by the ETM." "0,1,2,3"
newline
bitfld.long 0x4 2.--3. "NSNID,Permission for Non-secure non-invasive debug." "?,?,2: Non-secure non-invasive debug disabled,3: Non-secure non-invasive debug enabled"
newline
bitfld.long 0x4 0.--1. "NSID,Reads as b00  Non-secure invasive debug not supported by the ETM." "0,1,2,3"
rgroup.long 0xFCC++0x33
line.long 0x0 "DEVTYPE,CoreSight Device Type Register"
hexmask.long.byte 0x0 4.--7. 1. "SubType,Sub Type"
newline
hexmask.long.byte 0x0 0.--3. 1. "MajorType,Major Type and Class"
line.long 0x4 "PIDR4,Peripheral Identification Register 4"
hexmask.long.byte 0x4 4.--7. 1. "c4KB,4KB Count"
newline
hexmask.long.byte 0x4 0.--3. 1. "JEP106,JEP106 continuation code."
line.long 0x8 "PIDR5,Peripheral Identification Register 5"
line.long 0xC "PIDR6,Peripheral Identification Register 6"
line.long 0x10 "PIDR7,Peripheral Identification Register 7"
line.long 0x14 "PIDR0,Peripheral Identification Register 0"
hexmask.long.byte 0x14 0.--7. 1. "PartNumber,Part Number [7:0]"
line.long 0x18 "PIDR1,Peripheral Identification Register 1"
hexmask.long.byte 0x18 4.--7. 1. "JEP106_identity_code,JEP106 identity code [3:0]"
newline
hexmask.long.byte 0x18 0.--3. 1. "PartNumber,Part Number [11:8]"
line.long 0x1C "PIDR2,Peripheral Identification Register 2"
hexmask.long.byte 0x1C 4.--7. 1. "Revision,Revision"
newline
bitfld.long 0x1C 0.--2. "JEP106_identity_code,JEP106 identity code [6:4]" "0,1,2,3,4,5,6,7"
line.long 0x20 "PIDR3,Peripheral Identification Register 3"
hexmask.long.byte 0x20 4.--7. 1. "RevAnd,RevAnd"
newline
hexmask.long.byte 0x20 0.--3. 1. "CustomerModified,Customer Modified."
line.long 0x24 "CIDR0,Component Identification Register 0"
hexmask.long.byte 0x24 0.--7. 1. "Preamble,Preamble"
line.long 0x28 "CIDR1,Component Identification Register 1"
hexmask.long.byte 0x28 4.--7. 1. "ComponentClass,Component class"
newline
hexmask.long.byte 0x28 0.--3. 1. "Preamble,Preamble"
line.long 0x2C "CIDR2,Component Identification Register 2"
hexmask.long.byte 0x2C 0.--7. 1. "Preamble,Preamble"
line.long 0x30 "CIDR3,Component Identification Register 3"
hexmask.long.byte 0x30 0.--7. 1. "Preamble,Preamble"
sif (cpuis("LPC54605*"))
wgroup.long 0xEE8++0x3
line.long 0x0 "_ITTRIGOUT,Integration Test Trigger Out Register"
bitfld.long 0x0 0. "TRIGGER,A write to this bit sets the TRIGGER output." "0,1"
endif
sif (cpuis("LPC54605*"))
wgroup.long 0xEF8++0x3
line.long 0x0 "_ITATBCTR0,ETM Integration Test ATB Control 0 Register"
bitfld.long 0x0 0. "ATVALID,A write to this bit sets the value of the ETM ATVALID output." "0,1"
endif
sif (cpuis("LPC54606*"))
wgroup.long 0xEE8++0x3
line.long 0x0 "_ITTRIGOUT,Integration Test Trigger Out Register"
bitfld.long 0x0 0. "TRIGGER,A write to this bit sets the TRIGGER output." "0,1"
endif
sif (cpuis("LPC54606*"))
wgroup.long 0xEF8++0x3
line.long 0x0 "_ITATBCTR0,ETM Integration Test ATB Control 0 Register"
bitfld.long 0x0 0. "ATVALID,A write to this bit sets the value of the ETM ATVALID output." "0,1"
endif
sif (cpuis("LPC54607*"))
wgroup.long 0xEE8++0x3
line.long 0x0 "_ITTRIGOUT,Integration Test Trigger Out Register"
bitfld.long 0x0 0. "TRIGGER,A write to this bit sets the TRIGGER output." "0,1"
endif
sif (cpuis("LPC54607*"))
wgroup.long 0xEF8++0x3
line.long 0x0 "_ITATBCTR0,ETM Integration Test ATB Control 0 Register"
bitfld.long 0x0 0. "ATVALID,A write to this bit sets the value of the ETM ATVALID output." "0,1"
endif
sif (cpuis("LPC54608*"))
wgroup.long 0xEE8++0x3
line.long 0x0 "_ITTRIGOUT,Integration Test Trigger Out Register"
bitfld.long 0x0 0. "TRIGGER,A write to this bit sets the TRIGGER output." "0,1"
endif
sif (cpuis("LPC54608*"))
wgroup.long 0xEF8++0x3
line.long 0x0 "_ITATBCTR0,ETM Integration Test ATB Control 0 Register"
bitfld.long 0x0 0. "ATVALID,A write to this bit sets the value of the ETM ATVALID output." "0,1"
endif
sif (cpuis("LPC54616*"))
wgroup.long 0xEE8++0x3
line.long 0x0 "_ITTRIGOUT,Integration Test Trigger Out Register"
bitfld.long 0x0 0. "TRIGGER,A write to this bit sets the TRIGGER output." "0,1"
endif
sif (cpuis("LPC54616*"))
wgroup.long 0xEF8++0x3
line.long 0x0 "_ITATBCTR0,ETM Integration Test ATB Control 0 Register"
bitfld.long 0x0 0. "ATVALID,A write to this bit sets the value of the ETM ATVALID output." "0,1"
endif
sif (cpuis("LPC54618*"))
wgroup.long 0xEE8++0x3
line.long 0x0 "_ITTRIGOUT,Integration Test Trigger Out Register"
bitfld.long 0x0 0. "TRIGGER,A write to this bit sets the TRIGGER output." "0,1"
endif
sif (cpuis("LPC54618*"))
wgroup.long 0xEF8++0x3
line.long 0x0 "_ITATBCTR0,ETM Integration Test ATB Control 0 Register"
bitfld.long 0x0 0. "ATVALID,A write to this bit sets the value of the ETM ATVALID output." "0,1"
endif
sif (cpuis("LPC54628*"))
wgroup.long 0xEE8++0x3
line.long 0x0 "_ITTRIGOUT,Integration Test Trigger Out Register"
bitfld.long 0x0 0. "TRIGGER,A write to this bit sets the TRIGGER output." "0,1"
endif
sif (cpuis("LPC54628*"))
wgroup.long 0xEF8++0x3
line.long 0x0 "_ITATBCTR0,ETM Integration Test ATB Control 0 Register"
bitfld.long 0x0 0. "ATVALID,A write to this bit sets the value of the ETM ATVALID output." "0,1"
endif
tree.end
endif
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54113*")||cpuis("LPC54114*")||cpuis("LPC54605*")||cpuis("LPC54606*")||cpuis("LPC54607*")||cpuis("LPC54608*")||cpuis("LPC54616*")||cpuis("LPC54618*")||cpuis("LPC54628*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
tree "FLEXCOMM (Flexcomm Serial Communication)"
base ad:0x0
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54113*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
tree "FLEXCOMM0"
base ad:0x40086000
group.long 0xFF8++0x3
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
rgroup.long 0xFFC++0x3
line.long 0x0 "PID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x0 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
sif (cpuis("LPC54113*"))
rgroup.long 0xFFC++0x3
line.long 0x0 "PID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x0 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
endif
tree.end
endif
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54113*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
tree "FLEXCOMM1"
base ad:0x40087000
group.long 0xFF8++0x3
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
rgroup.long 0xFFC++0x3
line.long 0x0 "PID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x0 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
sif (cpuis("LPC54113*"))
rgroup.long 0xFFC++0x3
line.long 0x0 "PID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x0 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
endif
tree.end
endif
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54113*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
tree "FLEXCOMM2"
base ad:0x40088000
group.long 0xFF8++0x3
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
rgroup.long 0xFFC++0x3
line.long 0x0 "PID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x0 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
sif (cpuis("LPC54113*"))
rgroup.long 0xFFC++0x3
line.long 0x0 "PID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x0 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
endif
tree.end
endif
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54113*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
tree "FLEXCOMM3"
base ad:0x40089000
group.long 0xFF8++0x3
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
rgroup.long 0xFFC++0x3
line.long 0x0 "PID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x0 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
sif (cpuis("LPC54113*"))
rgroup.long 0xFFC++0x3
line.long 0x0 "PID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x0 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
endif
tree.end
endif
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54113*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
tree "FLEXCOMM4"
base ad:0x4008A000
group.long 0xFF8++0x3
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
rgroup.long 0xFFC++0x3
line.long 0x0 "PID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x0 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
sif (cpuis("LPC54113*"))
rgroup.long 0xFFC++0x3
line.long 0x0 "PID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x0 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
endif
tree.end
endif
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54113*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
tree "FLEXCOMM5"
base ad:0x40096000
group.long 0xFF8++0x3
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
rgroup.long 0xFFC++0x3
line.long 0x0 "PID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x0 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
sif (cpuis("LPC54113*"))
rgroup.long 0xFFC++0x3
line.long 0x0 "PID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x0 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
endif
tree.end
endif
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54113*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
tree "FLEXCOMM6"
base ad:0x40097000
group.long 0xFF8++0x3
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
rgroup.long 0xFFC++0x3
line.long 0x0 "PID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x0 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
sif (cpuis("LPC54113*"))
rgroup.long 0xFFC++0x3
line.long 0x0 "PID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x0 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
endif
tree.end
endif
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54113*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
tree "FLEXCOMM7"
base ad:0x40098000
group.long 0xFF8++0x3
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
rgroup.long 0xFFC++0x3
line.long 0x0 "PID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x0 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
sif (cpuis("LPC54113*"))
rgroup.long 0xFFC++0x3
line.long 0x0 "PID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x0 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
endif
tree.end
endif
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
tree "FLEXCOMM8"
base ad:0x40099000
group.long 0xFF8++0x3
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
rgroup.long 0xFFC++0x3
line.long 0x0 "PID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x0 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM9"
base ad:0x4009A000
group.long 0xFF8++0x3
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
rgroup.long 0xFFC++0x3
line.long 0x0 "PID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x0 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM10"
base ad:0x4009F000
group.long 0xFF8++0x3
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
rgroup.long 0xFFC++0x3
line.long 0x0 "PID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x0 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
endif
sif (cpuis("LPC54114*"))
tree "FLEXCOMM0"
base ad:0x40086000
group.long 0xFF8++0x3
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
rgroup.long 0xFFC++0x3
line.long 0x0 "PID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x0 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM1"
base ad:0x40087000
group.long 0xFF8++0x3
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
rgroup.long 0xFFC++0x3
line.long 0x0 "PID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x0 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM2"
base ad:0x40088000
group.long 0xFF8++0x3
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
rgroup.long 0xFFC++0x3
line.long 0x0 "PID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x0 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM3"
base ad:0x40089000
group.long 0xFF8++0x3
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
rgroup.long 0xFFC++0x3
line.long 0x0 "PID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x0 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM4"
base ad:0x4008A000
group.long 0xFF8++0x3
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
rgroup.long 0xFFC++0x3
line.long 0x0 "PID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x0 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM5"
base ad:0x40096000
group.long 0xFF8++0x3
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
rgroup.long 0xFFC++0x3
line.long 0x0 "PID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x0 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM6"
base ad:0x40097000
group.long 0xFF8++0x3
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
rgroup.long 0xFFC++0x3
line.long 0x0 "PID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x0 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM7"
base ad:0x40098000
group.long 0xFF8++0x3
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
rgroup.long 0xFFC++0x3
line.long 0x0 "PID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x0 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
endif
sif (cpuis("LPC54605*"))
tree "FLEXCOMM0"
base ad:0x40086000
group.long 0xFF8++0x7
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
line.long 0x4 "PID,Peripheral identification register."
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM1"
base ad:0x40087000
group.long 0xFF8++0x7
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
line.long 0x4 "PID,Peripheral identification register."
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM2"
base ad:0x40088000
group.long 0xFF8++0x7
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
line.long 0x4 "PID,Peripheral identification register."
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM3"
base ad:0x40089000
group.long 0xFF8++0x7
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
line.long 0x4 "PID,Peripheral identification register."
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM4"
base ad:0x4008A000
group.long 0xFF8++0x7
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
line.long 0x4 "PID,Peripheral identification register."
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM5"
base ad:0x40096000
group.long 0xFF8++0x7
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
line.long 0x4 "PID,Peripheral identification register."
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM6"
base ad:0x40097000
group.long 0xFF8++0x7
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
line.long 0x4 "PID,Peripheral identification register."
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM7"
base ad:0x40098000
group.long 0xFF8++0x7
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
line.long 0x4 "PID,Peripheral identification register."
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM8"
base ad:0x40099000
group.long 0xFF8++0x7
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
line.long 0x4 "PID,Peripheral identification register."
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM9"
base ad:0x4009A000
group.long 0xFF8++0x7
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
line.long 0x4 "PID,Peripheral identification register."
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
endif
sif (cpuis("LPC54606*"))
tree "FLEXCOMM0"
base ad:0x40086000
group.long 0xFF8++0x7
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
line.long 0x4 "PID,Peripheral identification register."
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM1"
base ad:0x40087000
group.long 0xFF8++0x7
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
line.long 0x4 "PID,Peripheral identification register."
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM2"
base ad:0x40088000
group.long 0xFF8++0x7
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
line.long 0x4 "PID,Peripheral identification register."
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM3"
base ad:0x40089000
group.long 0xFF8++0x7
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
line.long 0x4 "PID,Peripheral identification register."
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM4"
base ad:0x4008A000
group.long 0xFF8++0x7
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
line.long 0x4 "PID,Peripheral identification register."
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM5"
base ad:0x40096000
group.long 0xFF8++0x7
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
line.long 0x4 "PID,Peripheral identification register."
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM6"
base ad:0x40097000
group.long 0xFF8++0x7
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
line.long 0x4 "PID,Peripheral identification register."
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM7"
base ad:0x40098000
group.long 0xFF8++0x7
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
line.long 0x4 "PID,Peripheral identification register."
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM8"
base ad:0x40099000
group.long 0xFF8++0x7
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
line.long 0x4 "PID,Peripheral identification register."
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM9"
base ad:0x4009A000
group.long 0xFF8++0x7
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
line.long 0x4 "PID,Peripheral identification register."
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
endif
sif (cpuis("LPC54607*"))
tree "FLEXCOMM0"
base ad:0x40086000
group.long 0xFF8++0x7
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
line.long 0x4 "PID,Peripheral identification register."
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM1"
base ad:0x40087000
group.long 0xFF8++0x7
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
line.long 0x4 "PID,Peripheral identification register."
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM2"
base ad:0x40088000
group.long 0xFF8++0x7
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
line.long 0x4 "PID,Peripheral identification register."
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM3"
base ad:0x40089000
group.long 0xFF8++0x7
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
line.long 0x4 "PID,Peripheral identification register."
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM4"
base ad:0x4008A000
group.long 0xFF8++0x7
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
line.long 0x4 "PID,Peripheral identification register."
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM5"
base ad:0x40096000
group.long 0xFF8++0x7
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
line.long 0x4 "PID,Peripheral identification register."
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM6"
base ad:0x40097000
group.long 0xFF8++0x7
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
line.long 0x4 "PID,Peripheral identification register."
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM7"
base ad:0x40098000
group.long 0xFF8++0x7
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
line.long 0x4 "PID,Peripheral identification register."
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM8"
base ad:0x40099000
group.long 0xFF8++0x7
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
line.long 0x4 "PID,Peripheral identification register."
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM9"
base ad:0x4009A000
group.long 0xFF8++0x7
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
line.long 0x4 "PID,Peripheral identification register."
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
endif
sif (cpuis("LPC54608*"))
tree "FLEXCOMM0"
base ad:0x40086000
group.long 0xFF8++0x7
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
line.long 0x4 "PID,Peripheral identification register."
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM1"
base ad:0x40087000
group.long 0xFF8++0x7
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
line.long 0x4 "PID,Peripheral identification register."
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM2"
base ad:0x40088000
group.long 0xFF8++0x7
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
line.long 0x4 "PID,Peripheral identification register."
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM3"
base ad:0x40089000
group.long 0xFF8++0x7
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
line.long 0x4 "PID,Peripheral identification register."
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM4"
base ad:0x4008A000
group.long 0xFF8++0x7
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
line.long 0x4 "PID,Peripheral identification register."
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM5"
base ad:0x40096000
group.long 0xFF8++0x7
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
line.long 0x4 "PID,Peripheral identification register."
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM6"
base ad:0x40097000
group.long 0xFF8++0x7
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
line.long 0x4 "PID,Peripheral identification register."
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM7"
base ad:0x40098000
group.long 0xFF8++0x7
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
line.long 0x4 "PID,Peripheral identification register."
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM8"
base ad:0x40099000
group.long 0xFF8++0x7
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
line.long 0x4 "PID,Peripheral identification register."
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM9"
base ad:0x4009A000
group.long 0xFF8++0x7
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
line.long 0x4 "PID,Peripheral identification register."
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
endif
sif (cpuis("LPC54616*"))
tree "FLEXCOMM0"
base ad:0x40086000
group.long 0xFF8++0x7
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
line.long 0x4 "PID,Peripheral identification register."
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM1"
base ad:0x40087000
group.long 0xFF8++0x7
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
line.long 0x4 "PID,Peripheral identification register."
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM2"
base ad:0x40088000
group.long 0xFF8++0x7
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
line.long 0x4 "PID,Peripheral identification register."
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM3"
base ad:0x40089000
group.long 0xFF8++0x7
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
line.long 0x4 "PID,Peripheral identification register."
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM4"
base ad:0x4008A000
group.long 0xFF8++0x7
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
line.long 0x4 "PID,Peripheral identification register."
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM5"
base ad:0x40096000
group.long 0xFF8++0x7
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
line.long 0x4 "PID,Peripheral identification register."
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM6"
base ad:0x40097000
group.long 0xFF8++0x7
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
line.long 0x4 "PID,Peripheral identification register."
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM7"
base ad:0x40098000
group.long 0xFF8++0x7
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
line.long 0x4 "PID,Peripheral identification register."
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM8"
base ad:0x40099000
group.long 0xFF8++0x7
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
line.long 0x4 "PID,Peripheral identification register."
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM9"
base ad:0x4009A000
group.long 0xFF8++0x7
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
line.long 0x4 "PID,Peripheral identification register."
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
endif
sif (cpuis("LPC54618*"))
tree "FLEXCOMM0"
base ad:0x40086000
group.long 0xFF8++0x7
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
line.long 0x4 "PID,Peripheral identification register."
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM1"
base ad:0x40087000
group.long 0xFF8++0x7
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
line.long 0x4 "PID,Peripheral identification register."
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM2"
base ad:0x40088000
group.long 0xFF8++0x7
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
line.long 0x4 "PID,Peripheral identification register."
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM3"
base ad:0x40089000
group.long 0xFF8++0x7
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
line.long 0x4 "PID,Peripheral identification register."
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM4"
base ad:0x4008A000
group.long 0xFF8++0x7
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
line.long 0x4 "PID,Peripheral identification register."
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM5"
base ad:0x40096000
group.long 0xFF8++0x7
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
line.long 0x4 "PID,Peripheral identification register."
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM6"
base ad:0x40097000
group.long 0xFF8++0x7
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
line.long 0x4 "PID,Peripheral identification register."
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM7"
base ad:0x40098000
group.long 0xFF8++0x7
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
line.long 0x4 "PID,Peripheral identification register."
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM8"
base ad:0x40099000
group.long 0xFF8++0x7
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
line.long 0x4 "PID,Peripheral identification register."
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM9"
base ad:0x4009A000
group.long 0xFF8++0x7
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
line.long 0x4 "PID,Peripheral identification register."
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
endif
sif (cpuis("LPC54628*"))
tree "FLEXCOMM0"
base ad:0x40086000
group.long 0xFF8++0x7
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
line.long 0x4 "PID,Peripheral identification register."
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM1"
base ad:0x40087000
group.long 0xFF8++0x7
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
line.long 0x4 "PID,Peripheral identification register."
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM2"
base ad:0x40088000
group.long 0xFF8++0x7
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
line.long 0x4 "PID,Peripheral identification register."
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM3"
base ad:0x40089000
group.long 0xFF8++0x7
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
line.long 0x4 "PID,Peripheral identification register."
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM4"
base ad:0x4008A000
group.long 0xFF8++0x7
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
line.long 0x4 "PID,Peripheral identification register."
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM5"
base ad:0x40096000
group.long 0xFF8++0x7
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
line.long 0x4 "PID,Peripheral identification register."
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM6"
base ad:0x40097000
group.long 0xFF8++0x7
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
line.long 0x4 "PID,Peripheral identification register."
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM7"
base ad:0x40098000
group.long 0xFF8++0x7
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
line.long 0x4 "PID,Peripheral identification register."
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM8"
base ad:0x40099000
group.long 0xFF8++0x7
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
line.long 0x4 "PID,Peripheral identification register."
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
tree "FLEXCOMM9"
base ad:0x4009A000
group.long 0xFF8++0x7
line.long 0x0 "PSELID,Peripheral Select and Flexcomm ID register."
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID."
rbitfld.long 0x0 7. "I2SPRESENT,I 2S present indicator. This field is Read-only." "0: This Flexcomm does not include the I2S function.,1: This Flexcomm includes the I2S function."
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator. This field is Read-only." "0: This Flexcomm does not include the I2C function.,1: This Flexcomm includes the I2C function."
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator. This field is Read-only." "0: This Flexcomm does not include the SPI function.,1: This Flexcomm includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator. This field is Read-only." "0: This Flexcomm does not include the USART function.,1: This Flexcomm includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select. This field is writable by software." "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select. This field is writable by software." "0: No peripheral selected.,1: USART function selected.,2: SPI function selected.,3: I2C function selected.,4: I2S transmit function selected.,5: I2S receive function selected.,?,?"
line.long 0x4 "PID,Peripheral identification register."
hexmask.long.word 0x4 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x4 12.--15. 1. "Major_Rev,Major revision of module implementation."
newline
hexmask.long.byte 0x4 8.--11. 1. "Minor_Rev,Minor revision of module implementation."
tree.end
endif
tree.end
endif
sif (cpuis("LPC54605*")||cpuis("LPC54606*")||cpuis("LPC54607*")||cpuis("LPC54608*")||cpuis("LPC54616*")||cpuis("LPC54618*")||cpuis("LPC54628*"))
tree "FMC (Flash Signature Generator)"
base ad:0x40034000
group.long 0x0++0x3
line.long 0x0 "FCTR,Control register"
bitfld.long 0x0 4. "FS_RD1,Value must be 1 for signature generation." "0,1"
bitfld.long 0x0 3. "FS_RD0,Value must be 0 for signature generation." "0,1"
group.long 0x10++0x3
line.long 0x0 "FBWST,Wait state register"
hexmask.long.byte 0x0 0.--7. 1. "WAITSTATES,Wait states for signature generation."
group.long 0x20++0x7
line.long 0x0 "FMSSTART,Signature start address register"
hexmask.long.tbyte 0x0 0.--16. 1. "START,Signature generation start address (corresponds to AHB byte address bits[20:4])."
line.long 0x4 "FMSSTOP,Signature stop-address register"
bitfld.long 0x4 17. "SIG_START,When this bit is written to 1  signature generation starts." "0,1"
hexmask.long.tbyte 0x4 0.--16. 1. "STOP,Stop address for signature generation (the word specified by STOP is included in the address range)."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x2C)++0x3
line.long 0x0 "FMSW[$1],Words of 128-bit signature word"
hexmask.long 0x0 0.--31. 1. "SW,Words of 128-bit signature (bits)."
repeat.end
rgroup.long 0xFE0++0x3
line.long 0x0 "FMSTAT,Signature generation status register"
bitfld.long 0x0 2. "SIG_DONE,When 1  a previously started signature generation has completed." "0,1"
wgroup.long 0xFE8++0x3
line.long 0x0 "FMSTATCLR,Signature generation status clear register"
bitfld.long 0x0 2. "SIG_DONE_CLR,Writing a 1 to this bits clears the signature generation completion flag (SIG_DONE) in the FMSTAT register." "0,1"
tree.end
endif
tree "GINT (GPIO Input Interrupt)"
base ad:0x0
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
base ad:0x40002000
elif (cpuis("LPC54101*"))
base ad:0x40010000
endif
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54101*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
tree "GINT0"
group.long 0x0++0x3
line.long 0x0 "CTRL,GPIO grouped interrupt control register"
bitfld.long 0x0 2. "TRIG,Group interrupt trigger" "0: Edge-triggered.,1: Level-triggered."
bitfld.long 0x0 1. "COMB,Combine enabled inputs for group interrupt" "0: Or. OR functionality: A grouped interrupt is..,1: And. AND functionality: An interrupt is.."
bitfld.long 0x0 0. "INT,Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect." "0: No request. No interrupt request is pending.,1: Request active. Interrupt request is active."
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x20)++0x3
line.long 0x0 "PORT_POL[$1],GPIO grouped interrupt port 0 polarity register"
hexmask.long 0x0 0.--31. 1. "POL,Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW  the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on.."
repeat.end
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x40)++0x3
line.long 0x0 "PORT_ENA[$1],GPIO grouped interrupt port 0 enable register"
hexmask.long 0x0 0.--31. 1. "ENA,Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt."
repeat.end
tree.end
endif
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
base ad:0x40003000
elif (cpuis("LPC54101*"))
base ad:0x40014000
endif
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54101*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
tree "GINT1"
group.long 0x0++0x3
line.long 0x0 "CTRL,GPIO grouped interrupt control register"
bitfld.long 0x0 2. "TRIG,Group interrupt trigger" "0: Edge-triggered.,1: Level-triggered."
bitfld.long 0x0 1. "COMB,Combine enabled inputs for group interrupt" "0: Or. OR functionality: A grouped interrupt is..,1: And. AND functionality: An interrupt is.."
bitfld.long 0x0 0. "INT,Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect." "0: No request. No interrupt request is pending.,1: Request active. Interrupt request is active."
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x20)++0x3
line.long 0x0 "PORT_POL[$1],GPIO grouped interrupt port 0 polarity register"
hexmask.long 0x0 0.--31. 1. "POL,Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW  the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on.."
repeat.end
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x40)++0x3
line.long 0x0 "PORT_ENA[$1],GPIO grouped interrupt port 0 enable register"
hexmask.long 0x0 0.--31. 1. "ENA,Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt."
repeat.end
tree.end
endif
sif (cpuis("LPC54102*"))
tree "GINT0"
base ad:0x40010000
group.long 0x0++0x3
line.long 0x0 "CTRL,GPIO grouped interrupt control register"
bitfld.long 0x0 2. "TRIG,Group interrupt trigger" "0: Edge-triggered.,1: Level-triggered."
bitfld.long 0x0 1. "COMB,Combine enabled inputs for group interrupt" "0: Or. OR functionality: A grouped interrupt is..,1: And. AND functionality: An interrupt is.."
bitfld.long 0x0 0. "INT,Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect." "0: No request. No interrupt request is pending.,1: Request active. Interrupt request is active."
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x20)++0x3
line.long 0x0 "PORT_POL[$1],GPIO grouped interrupt port 0 polarity register"
hexmask.long 0x0 0.--31. 1. "POL,Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW  the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on.."
repeat.end
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x40)++0x3
line.long 0x0 "PORT_ENA[$1],GPIO grouped interrupt port 0 enable register"
hexmask.long 0x0 0.--31. 1. "ENA,Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt."
repeat.end
tree.end
tree "GINT1"
base ad:0x40014000
group.long 0x0++0x3
line.long 0x0 "CTRL,GPIO grouped interrupt control register"
bitfld.long 0x0 2. "TRIG,Group interrupt trigger" "0: Edge-triggered.,1: Level-triggered."
bitfld.long 0x0 1. "COMB,Combine enabled inputs for group interrupt" "0: Or. OR functionality: A grouped interrupt is..,1: And. AND functionality: An interrupt is.."
bitfld.long 0x0 0. "INT,Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect." "0: No request. No interrupt request is pending.,1: Request active. Interrupt request is active."
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x20)++0x3
line.long 0x0 "PORT_POL[$1],GPIO grouped interrupt port 0 polarity register"
hexmask.long 0x0 0.--31. 1. "POL,Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW  the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on.."
repeat.end
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x40)++0x3
line.long 0x0 "PORT_ENA[$1],GPIO grouped interrupt port 0 enable register"
hexmask.long 0x0 0.--31. 1. "ENA,Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt."
repeat.end
tree.end
endif
sif (cpuis("LPC54113*"))
tree "GINT0"
base ad:0x40002000
group.long 0x0++0x3
line.long 0x0 "CTRL,GPIO grouped interrupt control register"
bitfld.long 0x0 2. "TRIG,Group interrupt trigger" "0: Edge-triggered.,1: Level-triggered."
bitfld.long 0x0 1. "COMB,Combine enabled inputs for group interrupt" "0: Or. OR functionality: A grouped interrupt is..,1: And. AND functionality: An interrupt is.."
bitfld.long 0x0 0. "INT,Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect." "0: No request. No interrupt request is pending.,1: Request active. Interrupt request is active."
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x20)++0x3
line.long 0x0 "PORT_POL[$1],GPIO grouped interrupt port 0 polarity register"
hexmask.long 0x0 0.--31. 1. "POL,Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW  the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on.."
repeat.end
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x40)++0x3
line.long 0x0 "PORT_ENA[$1],GPIO grouped interrupt port 0 enable register"
hexmask.long 0x0 0.--31. 1. "ENA,Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt."
repeat.end
tree.end
tree "GINT1"
base ad:0x40003000
group.long 0x0++0x3
line.long 0x0 "CTRL,GPIO grouped interrupt control register"
bitfld.long 0x0 2. "TRIG,Group interrupt trigger" "0: Edge-triggered.,1: Level-triggered."
bitfld.long 0x0 1. "COMB,Combine enabled inputs for group interrupt" "0: Or. OR functionality: A grouped interrupt is..,1: And. AND functionality: An interrupt is.."
bitfld.long 0x0 0. "INT,Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect." "0: No request. No interrupt request is pending.,1: Request active. Interrupt request is active."
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x20)++0x3
line.long 0x0 "PORT_POL[$1],GPIO grouped interrupt port 0 polarity register"
hexmask.long 0x0 0.--31. 1. "POL,Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW  the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on.."
repeat.end
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x40)++0x3
line.long 0x0 "PORT_ENA[$1],GPIO grouped interrupt port 0 enable register"
hexmask.long 0x0 0.--31. 1. "ENA,Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt."
repeat.end
tree.end
endif
sif (cpuis("LPC54114*"))
tree "GINT0"
base ad:0x40002000
group.long 0x0++0x3
line.long 0x0 "CTRL,GPIO grouped interrupt control register"
bitfld.long 0x0 2. "TRIG,Group interrupt trigger" "0: Edge-triggered.,1: Level-triggered."
bitfld.long 0x0 1. "COMB,Combine enabled inputs for group interrupt" "0: Or. OR functionality: A grouped interrupt is..,1: And. AND functionality: An interrupt is.."
bitfld.long 0x0 0. "INT,Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect." "0: No request. No interrupt request is pending.,1: Request active. Interrupt request is active."
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x20)++0x3
line.long 0x0 "PORT_POL[$1],GPIO grouped interrupt port 0 polarity register"
hexmask.long 0x0 0.--31. 1. "POL,Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW  the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on.."
repeat.end
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x40)++0x3
line.long 0x0 "PORT_ENA[$1],GPIO grouped interrupt port 0 enable register"
hexmask.long 0x0 0.--31. 1. "ENA,Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt."
repeat.end
tree.end
tree "GINT1"
base ad:0x40003000
group.long 0x0++0x3
line.long 0x0 "CTRL,GPIO grouped interrupt control register"
bitfld.long 0x0 2. "TRIG,Group interrupt trigger" "0: Edge-triggered.,1: Level-triggered."
bitfld.long 0x0 1. "COMB,Combine enabled inputs for group interrupt" "0: Or. OR functionality: A grouped interrupt is..,1: And. AND functionality: An interrupt is.."
bitfld.long 0x0 0. "INT,Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect." "0: No request. No interrupt request is pending.,1: Request active. Interrupt request is active."
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x20)++0x3
line.long 0x0 "PORT_POL[$1],GPIO grouped interrupt port 0 polarity register"
hexmask.long 0x0 0.--31. 1. "POL,Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW  the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on.."
repeat.end
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x40)++0x3
line.long 0x0 "PORT_ENA[$1],GPIO grouped interrupt port 0 enable register"
hexmask.long 0x0 0.--31. 1. "ENA,Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt."
repeat.end
tree.end
endif
sif (cpuis("LPC54605*"))
tree "GINT0"
base ad:0x40002000
group.long 0x0++0x3
line.long 0x0 "CTRL,GPIO grouped interrupt control register"
bitfld.long 0x0 2. "TRIG,Group interrupt trigger" "0: Edge-triggered.,1: Level-triggered."
bitfld.long 0x0 1. "COMB,Combine enabled inputs for group interrupt" "0: Or. OR functionality: A grouped interrupt is..,1: And. AND functionality: An interrupt is.."
bitfld.long 0x0 0. "INT,Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect." "0: No request. No interrupt request is pending.,1: Request active. Interrupt request is active."
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x20)++0x3
line.long 0x0 "PORT_POL[$1],GPIO grouped interrupt port 0 polarity register"
hexmask.long 0x0 0.--31. 1. "POL,Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW  the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on.."
repeat.end
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x40)++0x3
line.long 0x0 "PORT_ENA[$1],GPIO grouped interrupt port 0 enable register"
hexmask.long 0x0 0.--31. 1. "ENA,Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt."
repeat.end
tree.end
tree "GINT1"
base ad:0x40003000
group.long 0x0++0x3
line.long 0x0 "CTRL,GPIO grouped interrupt control register"
bitfld.long 0x0 2. "TRIG,Group interrupt trigger" "0: Edge-triggered.,1: Level-triggered."
bitfld.long 0x0 1. "COMB,Combine enabled inputs for group interrupt" "0: Or. OR functionality: A grouped interrupt is..,1: And. AND functionality: An interrupt is.."
bitfld.long 0x0 0. "INT,Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect." "0: No request. No interrupt request is pending.,1: Request active. Interrupt request is active."
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x20)++0x3
line.long 0x0 "PORT_POL[$1],GPIO grouped interrupt port 0 polarity register"
hexmask.long 0x0 0.--31. 1. "POL,Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW  the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on.."
repeat.end
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x40)++0x3
line.long 0x0 "PORT_ENA[$1],GPIO grouped interrupt port 0 enable register"
hexmask.long 0x0 0.--31. 1. "ENA,Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt."
repeat.end
tree.end
endif
sif (cpuis("LPC54606*"))
tree "GINT0"
base ad:0x40002000
group.long 0x0++0x3
line.long 0x0 "CTRL,GPIO grouped interrupt control register"
bitfld.long 0x0 2. "TRIG,Group interrupt trigger" "0: Edge-triggered.,1: Level-triggered."
bitfld.long 0x0 1. "COMB,Combine enabled inputs for group interrupt" "0: Or. OR functionality: A grouped interrupt is..,1: And. AND functionality: An interrupt is.."
bitfld.long 0x0 0. "INT,Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect." "0: No request. No interrupt request is pending.,1: Request active. Interrupt request is active."
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x20)++0x3
line.long 0x0 "PORT_POL[$1],GPIO grouped interrupt port 0 polarity register"
hexmask.long 0x0 0.--31. 1. "POL,Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW  the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on.."
repeat.end
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x40)++0x3
line.long 0x0 "PORT_ENA[$1],GPIO grouped interrupt port 0 enable register"
hexmask.long 0x0 0.--31. 1. "ENA,Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt."
repeat.end
tree.end
tree "GINT1"
base ad:0x40003000
group.long 0x0++0x3
line.long 0x0 "CTRL,GPIO grouped interrupt control register"
bitfld.long 0x0 2. "TRIG,Group interrupt trigger" "0: Edge-triggered.,1: Level-triggered."
bitfld.long 0x0 1. "COMB,Combine enabled inputs for group interrupt" "0: Or. OR functionality: A grouped interrupt is..,1: And. AND functionality: An interrupt is.."
bitfld.long 0x0 0. "INT,Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect." "0: No request. No interrupt request is pending.,1: Request active. Interrupt request is active."
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x20)++0x3
line.long 0x0 "PORT_POL[$1],GPIO grouped interrupt port 0 polarity register"
hexmask.long 0x0 0.--31. 1. "POL,Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW  the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on.."
repeat.end
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x40)++0x3
line.long 0x0 "PORT_ENA[$1],GPIO grouped interrupt port 0 enable register"
hexmask.long 0x0 0.--31. 1. "ENA,Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt."
repeat.end
tree.end
endif
sif (cpuis("LPC54607*"))
tree "GINT0"
base ad:0x40002000
group.long 0x0++0x3
line.long 0x0 "CTRL,GPIO grouped interrupt control register"
bitfld.long 0x0 2. "TRIG,Group interrupt trigger" "0: Edge-triggered.,1: Level-triggered."
bitfld.long 0x0 1. "COMB,Combine enabled inputs for group interrupt" "0: Or. OR functionality: A grouped interrupt is..,1: And. AND functionality: An interrupt is.."
bitfld.long 0x0 0. "INT,Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect." "0: No request. No interrupt request is pending.,1: Request active. Interrupt request is active."
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x20)++0x3
line.long 0x0 "PORT_POL[$1],GPIO grouped interrupt port 0 polarity register"
hexmask.long 0x0 0.--31. 1. "POL,Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW  the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on.."
repeat.end
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x40)++0x3
line.long 0x0 "PORT_ENA[$1],GPIO grouped interrupt port 0 enable register"
hexmask.long 0x0 0.--31. 1. "ENA,Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt."
repeat.end
tree.end
tree "GINT1"
base ad:0x40003000
group.long 0x0++0x3
line.long 0x0 "CTRL,GPIO grouped interrupt control register"
bitfld.long 0x0 2. "TRIG,Group interrupt trigger" "0: Edge-triggered.,1: Level-triggered."
bitfld.long 0x0 1. "COMB,Combine enabled inputs for group interrupt" "0: Or. OR functionality: A grouped interrupt is..,1: And. AND functionality: An interrupt is.."
bitfld.long 0x0 0. "INT,Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect." "0: No request. No interrupt request is pending.,1: Request active. Interrupt request is active."
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x20)++0x3
line.long 0x0 "PORT_POL[$1],GPIO grouped interrupt port 0 polarity register"
hexmask.long 0x0 0.--31. 1. "POL,Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW  the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on.."
repeat.end
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x40)++0x3
line.long 0x0 "PORT_ENA[$1],GPIO grouped interrupt port 0 enable register"
hexmask.long 0x0 0.--31. 1. "ENA,Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt."
repeat.end
tree.end
endif
sif (cpuis("LPC54608*"))
tree "GINT0"
base ad:0x40002000
group.long 0x0++0x3
line.long 0x0 "CTRL,GPIO grouped interrupt control register"
bitfld.long 0x0 2. "TRIG,Group interrupt trigger" "0: Edge-triggered.,1: Level-triggered."
bitfld.long 0x0 1. "COMB,Combine enabled inputs for group interrupt" "0: Or. OR functionality: A grouped interrupt is..,1: And. AND functionality: An interrupt is.."
bitfld.long 0x0 0. "INT,Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect." "0: No request. No interrupt request is pending.,1: Request active. Interrupt request is active."
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x20)++0x3
line.long 0x0 "PORT_POL[$1],GPIO grouped interrupt port 0 polarity register"
hexmask.long 0x0 0.--31. 1. "POL,Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW  the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on.."
repeat.end
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x40)++0x3
line.long 0x0 "PORT_ENA[$1],GPIO grouped interrupt port 0 enable register"
hexmask.long 0x0 0.--31. 1. "ENA,Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt."
repeat.end
tree.end
tree "GINT1"
base ad:0x40003000
group.long 0x0++0x3
line.long 0x0 "CTRL,GPIO grouped interrupt control register"
bitfld.long 0x0 2. "TRIG,Group interrupt trigger" "0: Edge-triggered.,1: Level-triggered."
bitfld.long 0x0 1. "COMB,Combine enabled inputs for group interrupt" "0: Or. OR functionality: A grouped interrupt is..,1: And. AND functionality: An interrupt is.."
bitfld.long 0x0 0. "INT,Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect." "0: No request. No interrupt request is pending.,1: Request active. Interrupt request is active."
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x20)++0x3
line.long 0x0 "PORT_POL[$1],GPIO grouped interrupt port 0 polarity register"
hexmask.long 0x0 0.--31. 1. "POL,Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW  the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on.."
repeat.end
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x40)++0x3
line.long 0x0 "PORT_ENA[$1],GPIO grouped interrupt port 0 enable register"
hexmask.long 0x0 0.--31. 1. "ENA,Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt."
repeat.end
tree.end
endif
sif (cpuis("LPC54616*"))
tree "GINT0"
base ad:0x40002000
group.long 0x0++0x3
line.long 0x0 "CTRL,GPIO grouped interrupt control register"
bitfld.long 0x0 2. "TRIG,Group interrupt trigger" "0: Edge-triggered.,1: Level-triggered."
bitfld.long 0x0 1. "COMB,Combine enabled inputs for group interrupt" "0: Or. OR functionality: A grouped interrupt is..,1: And. AND functionality: An interrupt is.."
bitfld.long 0x0 0. "INT,Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect." "0: No request. No interrupt request is pending.,1: Request active. Interrupt request is active."
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x20)++0x3
line.long 0x0 "PORT_POL[$1],GPIO grouped interrupt port 0 polarity register"
hexmask.long 0x0 0.--31. 1. "POL,Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW  the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on.."
repeat.end
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x40)++0x3
line.long 0x0 "PORT_ENA[$1],GPIO grouped interrupt port 0 enable register"
hexmask.long 0x0 0.--31. 1. "ENA,Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt."
repeat.end
tree.end
tree "GINT1"
base ad:0x40003000
group.long 0x0++0x3
line.long 0x0 "CTRL,GPIO grouped interrupt control register"
bitfld.long 0x0 2. "TRIG,Group interrupt trigger" "0: Edge-triggered.,1: Level-triggered."
bitfld.long 0x0 1. "COMB,Combine enabled inputs for group interrupt" "0: Or. OR functionality: A grouped interrupt is..,1: And. AND functionality: An interrupt is.."
bitfld.long 0x0 0. "INT,Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect." "0: No request. No interrupt request is pending.,1: Request active. Interrupt request is active."
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x20)++0x3
line.long 0x0 "PORT_POL[$1],GPIO grouped interrupt port 0 polarity register"
hexmask.long 0x0 0.--31. 1. "POL,Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW  the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on.."
repeat.end
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x40)++0x3
line.long 0x0 "PORT_ENA[$1],GPIO grouped interrupt port 0 enable register"
hexmask.long 0x0 0.--31. 1. "ENA,Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt."
repeat.end
tree.end
endif
sif (cpuis("LPC54618*"))
tree "GINT0"
base ad:0x40002000
group.long 0x0++0x3
line.long 0x0 "CTRL,GPIO grouped interrupt control register"
bitfld.long 0x0 2. "TRIG,Group interrupt trigger" "0: Edge-triggered.,1: Level-triggered."
bitfld.long 0x0 1. "COMB,Combine enabled inputs for group interrupt" "0: Or. OR functionality: A grouped interrupt is..,1: And. AND functionality: An interrupt is.."
bitfld.long 0x0 0. "INT,Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect." "0: No request. No interrupt request is pending.,1: Request active. Interrupt request is active."
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x20)++0x3
line.long 0x0 "PORT_POL[$1],GPIO grouped interrupt port 0 polarity register"
hexmask.long 0x0 0.--31. 1. "POL,Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW  the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on.."
repeat.end
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x40)++0x3
line.long 0x0 "PORT_ENA[$1],GPIO grouped interrupt port 0 enable register"
hexmask.long 0x0 0.--31. 1. "ENA,Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt."
repeat.end
tree.end
tree "GINT1"
base ad:0x40003000
group.long 0x0++0x3
line.long 0x0 "CTRL,GPIO grouped interrupt control register"
bitfld.long 0x0 2. "TRIG,Group interrupt trigger" "0: Edge-triggered.,1: Level-triggered."
bitfld.long 0x0 1. "COMB,Combine enabled inputs for group interrupt" "0: Or. OR functionality: A grouped interrupt is..,1: And. AND functionality: An interrupt is.."
bitfld.long 0x0 0. "INT,Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect." "0: No request. No interrupt request is pending.,1: Request active. Interrupt request is active."
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x20)++0x3
line.long 0x0 "PORT_POL[$1],GPIO grouped interrupt port 0 polarity register"
hexmask.long 0x0 0.--31. 1. "POL,Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW  the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on.."
repeat.end
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x40)++0x3
line.long 0x0 "PORT_ENA[$1],GPIO grouped interrupt port 0 enable register"
hexmask.long 0x0 0.--31. 1. "ENA,Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt."
repeat.end
tree.end
endif
sif (cpuis("LPC54628*"))
tree "GINT0"
base ad:0x40002000
group.long 0x0++0x3
line.long 0x0 "CTRL,GPIO grouped interrupt control register"
bitfld.long 0x0 2. "TRIG,Group interrupt trigger" "0: Edge-triggered.,1: Level-triggered."
bitfld.long 0x0 1. "COMB,Combine enabled inputs for group interrupt" "0: Or. OR functionality: A grouped interrupt is..,1: And. AND functionality: An interrupt is.."
bitfld.long 0x0 0. "INT,Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect." "0: No request. No interrupt request is pending.,1: Request active. Interrupt request is active."
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x20)++0x3
line.long 0x0 "PORT_POL[$1],GPIO grouped interrupt port 0 polarity register"
hexmask.long 0x0 0.--31. 1. "POL,Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW  the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on.."
repeat.end
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x40)++0x3
line.long 0x0 "PORT_ENA[$1],GPIO grouped interrupt port 0 enable register"
hexmask.long 0x0 0.--31. 1. "ENA,Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt."
repeat.end
tree.end
tree "GINT1"
base ad:0x40003000
group.long 0x0++0x3
line.long 0x0 "CTRL,GPIO grouped interrupt control register"
bitfld.long 0x0 2. "TRIG,Group interrupt trigger" "0: Edge-triggered.,1: Level-triggered."
bitfld.long 0x0 1. "COMB,Combine enabled inputs for group interrupt" "0: Or. OR functionality: A grouped interrupt is..,1: And. AND functionality: An interrupt is.."
bitfld.long 0x0 0. "INT,Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect." "0: No request. No interrupt request is pending.,1: Request active. Interrupt request is active."
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x20)++0x3
line.long 0x0 "PORT_POL[$1],GPIO grouped interrupt port 0 polarity register"
hexmask.long 0x0 0.--31. 1. "POL,Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW  the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on.."
repeat.end
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x40)++0x3
line.long 0x0 "PORT_ENA[$1],GPIO grouped interrupt port 0 enable register"
hexmask.long 0x0 0.--31. 1. "ENA,Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt."
repeat.end
tree.end
endif
tree.end
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54113*")||cpuis("LPC54114*")||cpuis("LPC54605*")||cpuis("LPC54606*")||cpuis("LPC54607*")||cpuis("LPC54608*")||cpuis("LPC54616*")||cpuis("LPC54618*")||cpuis("LPC54628*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
base ad:0x4008C000
elif (cpuis("LPC54101*")||cpuis("LPC54102*"))
base ad:0x1C000000
endif
tree "GPIO (General Purpose I/O)"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
repeat 6. (list 0x0 0x1 0x2 0x3 0x4 0x5)(list ad:0x4008C000 ad:0x4008C020 ad:0x4008C040 ad:0x4008C060 ad:0x4008C080 ad:0x4008C0A0)
tree "B[$1]"
base $2
repeat 32. (increment 0x0 0x1)(increment 0x0 0x1)
group.byte ($2)++0x0
line.byte 0x0 "B_[$1],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x0 0. "PBYTE,Read: state of the pin PIOm_n  regardless of direction  masking  or alternate function  except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write:.." "0,1"
repeat.end
tree.end
repeat.end
repeat 6. (list 0x0 0x1 0x2 0x3 0x4 0x5)(list ad:0x4008D000 ad:0x4008D080 ad:0x4008D100 ad:0x4008D180 ad:0x4008D200 ad:0x4008D280)
tree "W[$1]"
base $2
repeat 32. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2)++0x3
line.long 0x0 "W_[$1],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x0 0.--31. 1. "PWORD,Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One.."
repeat.end
tree.end
repeat.end
base ad:0x4008D000
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2000)++0x3
line.long 0x0 "DIR[$1],Direction registers"
hexmask.long 0x0 0.--31. 1. "DIRP,Selects pin direction for pin PIOm_n (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = input. 1 = output."
repeat.end
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2080)++0x3
line.long 0x0 "MASK[$1],Mask register"
hexmask.long 0x0 0.--31. 1. "MASKP,Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT:.."
repeat.end
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2100)++0x3
line.long 0x0 "PIN[$1],Port pin register"
hexmask.long 0x0 0.--31. 1. "PORT,Reads pin states or loads output bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."
repeat.end
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2180)++0x3
line.long 0x0 "MPIN[$1],Masked port register"
hexmask.long 0x0 0.--31. 1. "MPORTP,Masked port register (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit.."
repeat.end
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2200)++0x3
line.long 0x0 "SET[$1],Write: Set register for port Read: output bits for port"
hexmask.long 0x0 0.--31. 1. "SETP,Read or set output bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."
repeat.end
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x2280)++0x3
line.long 0x0 "CLR[$1],Clear port"
hexmask.long 0x0 0.--31. 1. "CLRP,Clear output bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear output bit."
repeat.end
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x2300)++0x3
line.long 0x0 "NOT[$1],Toggle port"
hexmask.long 0x0 0.--31. 1. "NOTP,Toggle output bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle output bit."
repeat.end
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x2380)++0x3
line.long 0x0 "DIRSET[$1],Set pin direction bits for port"
hexmask.long 0x0 0.--28. 1. "DIRSETP,Set direction bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Set direction bit."
repeat.end
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x2400)++0x3
line.long 0x0 "DIRCLR[$1],Clear pin direction bits for port"
hexmask.long 0x0 0.--28. 1. "DIRCLRP,Clear direction bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear direction bit."
repeat.end
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x2480)++0x3
line.long 0x0 "DIRNOT[$1],Toggle pin direction bits for port"
hexmask.long 0x0 0.--28. 1. "DIRNOTP,Toggle direction bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle direction bit."
repeat.end
endif
sif (cpuis("LPC54101*"))
repeat 50. (increment 0x0 0x1)(increment 0x0 0x1)
group.byte ($2)++0x0
line.byte 0x0 "B[$1],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x0 0. "PBYTE,Read: state of the pin PIOm_n  regardless of direction  masking  or alternate function  except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write:.." "0,1"
repeat.end
endif
sif (cpuis("LPC54101*"))
repeat 50. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x1000)++0x3
line.long 0x0 "W[$1],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x0 0.--31. 1. "PWORD,Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One.."
repeat.end
endif
sif (cpuis("LPC54101*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2000)++0x3
line.long 0x0 "DIR[$1],Direction registers"
hexmask.long 0x0 0.--31. 1. "DIRP,Selects pin direction for pin PIOm_n (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = input. 1 = output."
repeat.end
endif
sif (cpuis("LPC54101*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2080)++0x3
line.long 0x0 "MASK[$1],Mask register"
hexmask.long 0x0 0.--31. 1. "MASKP,Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT:.."
repeat.end
endif
sif (cpuis("LPC54101*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2100)++0x3
line.long 0x0 "PIN[$1],Port pin register"
hexmask.long 0x0 0.--31. 1. "PORT,Reads pin states or loads output bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."
repeat.end
endif
sif (cpuis("LPC54101*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2180)++0x3
line.long 0x0 "MPIN[$1],Masked port register"
hexmask.long 0x0 0.--31. 1. "MPORTP,Masked port register (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit.."
repeat.end
endif
sif (cpuis("LPC54101*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2200)++0x3
line.long 0x0 "SET[$1],Write: Set register for port Read: output bits for port"
hexmask.long 0x0 0.--31. 1. "SETP,Read or set output bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."
repeat.end
endif
sif (cpuis("LPC54101*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x2280)++0x3
line.long 0x0 "CLR[$1],Clear port"
hexmask.long 0x0 0.--31. 1. "CLRP,Clear output bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear output bit."
repeat.end
endif
sif (cpuis("LPC54101*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x2300)++0x3
line.long 0x0 "NOT[$1],Toggle port"
hexmask.long 0x0 0.--31. 1. "NOTP,Toggle output bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle output bit."
repeat.end
endif
sif (cpuis("LPC54101*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x2380)++0x3
line.long 0x0 "DIRSET[$1],Set pin direction bits for port"
hexmask.long 0x0 0.--28. 1. "DIRSETP,Set direction bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Set direction bit."
repeat.end
endif
sif (cpuis("LPC54101*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x2400)++0x3
line.long 0x0 "DIRCLR[$1],Clear pin direction bits for port"
hexmask.long 0x0 0.--28. 1. "DIRCLRP,Clear direction bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear direction bit."
repeat.end
endif
sif (cpuis("LPC54101*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x2480)++0x3
line.long 0x0 "DIRNOT[$1],Toggle pin direction bits for port"
hexmask.long 0x0 0.--28. 1. "DIRNOTP,Toggle direction bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle direction bit."
repeat.end
endif
sif (cpuis("LPC54102*"))
repeat 50. (increment 0x0 0x1)(increment 0x0 0x1)
group.byte ($2)++0x0
line.byte 0x0 "B[$1],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x0 0. "PBYTE,Read: state of the pin PIOm_n  regardless of direction  masking  or alternate function  except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write:.." "0,1"
repeat.end
endif
sif (cpuis("LPC54102*"))
repeat 50. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x1000)++0x3
line.long 0x0 "W[$1],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x0 0.--31. 1. "PWORD,Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One.."
repeat.end
endif
sif (cpuis("LPC54102*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2000)++0x3
line.long 0x0 "DIR[$1],Direction registers"
hexmask.long 0x0 0.--31. 1. "DIRP,Selects pin direction for pin PIOm_n (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = input. 1 = output."
repeat.end
endif
sif (cpuis("LPC54102*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2080)++0x3
line.long 0x0 "MASK[$1],Mask register"
hexmask.long 0x0 0.--31. 1. "MASKP,Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT:.."
repeat.end
endif
sif (cpuis("LPC54102*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2100)++0x3
line.long 0x0 "PIN[$1],Port pin register"
hexmask.long 0x0 0.--31. 1. "PORT,Reads pin states or loads output bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."
repeat.end
endif
sif (cpuis("LPC54102*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2180)++0x3
line.long 0x0 "MPIN[$1],Masked port register"
hexmask.long 0x0 0.--31. 1. "MPORTP,Masked port register (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit.."
repeat.end
endif
sif (cpuis("LPC54102*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2200)++0x3
line.long 0x0 "SET[$1],Write: Set register for port Read: output bits for port"
hexmask.long 0x0 0.--31. 1. "SETP,Read or set output bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."
repeat.end
endif
sif (cpuis("LPC54102*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x2280)++0x3
line.long 0x0 "CLR[$1],Clear port"
hexmask.long 0x0 0.--31. 1. "CLRP,Clear output bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear output bit."
repeat.end
endif
sif (cpuis("LPC54102*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x2300)++0x3
line.long 0x0 "NOT[$1],Toggle port"
hexmask.long 0x0 0.--31. 1. "NOTP,Toggle output bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle output bit."
repeat.end
endif
sif (cpuis("LPC54102*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x2380)++0x3
line.long 0x0 "DIRSET[$1],Set pin direction bits for port"
hexmask.long 0x0 0.--28. 1. "DIRSETP,Set direction bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Set direction bit."
repeat.end
endif
sif (cpuis("LPC54102*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x2400)++0x3
line.long 0x0 "DIRCLR[$1],Clear pin direction bits for port"
hexmask.long 0x0 0.--28. 1. "DIRCLRP,Clear direction bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear direction bit."
repeat.end
endif
sif (cpuis("LPC54102*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x2480)++0x3
line.long 0x0 "DIRNOT[$1],Toggle pin direction bits for port"
hexmask.long 0x0 0.--28. 1. "DIRNOTP,Toggle direction bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle direction bit."
repeat.end
endif
sif (cpuis("LPC54113*"))
repeat 50. (increment 0x0 0x1)(increment 0x0 0x1)
group.byte ($2)++0x0
line.byte 0x0 "B[$1],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x0 0. "PBYTE,Read: state of the pin PIOm_n  regardless of direction  masking  or alternate function  except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write:.." "0,1"
repeat.end
endif
sif (cpuis("LPC54113*"))
repeat 50. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x1000)++0x3
line.long 0x0 "W[$1],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x0 0.--31. 1. "PWORD,Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One.."
repeat.end
endif
sif (cpuis("LPC54113*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2000)++0x3
line.long 0x0 "DIR[$1],Direction registers"
hexmask.long 0x0 0.--31. 1. "DIRP,Selects pin direction for pin PIOm_n (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = input. 1 = output."
repeat.end
endif
sif (cpuis("LPC54113*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2080)++0x3
line.long 0x0 "MASK[$1],Mask register"
hexmask.long 0x0 0.--31. 1. "MASKP,Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT:.."
repeat.end
endif
sif (cpuis("LPC54113*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2100)++0x3
line.long 0x0 "PIN[$1],Port pin register"
hexmask.long 0x0 0.--31. 1. "PORT,Reads pin states or loads output bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."
repeat.end
endif
sif (cpuis("LPC54113*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2180)++0x3
line.long 0x0 "MPIN[$1],Masked port register"
hexmask.long 0x0 0.--31. 1. "MPORTP,Masked port register (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit.."
repeat.end
endif
sif (cpuis("LPC54113*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2200)++0x3
line.long 0x0 "SET[$1],Write: Set register for port Read: output bits for port"
hexmask.long 0x0 0.--31. 1. "SETP,Read or set output bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."
repeat.end
endif
sif (cpuis("LPC54113*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x2280)++0x3
line.long 0x0 "CLR[$1],Clear port"
hexmask.long 0x0 0.--31. 1. "CLRP,Clear output bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear output bit."
repeat.end
endif
sif (cpuis("LPC54113*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x2300)++0x3
line.long 0x0 "NOT[$1],Toggle port"
hexmask.long 0x0 0.--31. 1. "NOTP,Toggle output bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle output bit."
repeat.end
endif
sif (cpuis("LPC54113*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x2380)++0x3
line.long 0x0 "DIRSET[$1],Set pin direction bits for port"
hexmask.long 0x0 0.--28. 1. "DIRSETP,Set direction bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Set direction bit."
repeat.end
endif
sif (cpuis("LPC54113*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x2400)++0x3
line.long 0x0 "DIRCLR[$1],Clear pin direction bits for port"
hexmask.long 0x0 0.--28. 1. "DIRCLRP,Clear direction bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear direction bit."
repeat.end
endif
sif (cpuis("LPC54113*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x2480)++0x3
line.long 0x0 "DIRNOT[$1],Toggle pin direction bits for port"
hexmask.long 0x0 0.--28. 1. "DIRNOTP,Toggle direction bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle direction bit."
repeat.end
endif
sif (cpuis("LPC54114*"))
repeat 50. (increment 0x0 0x1)(increment 0x0 0x1)
group.byte ($2)++0x0
line.byte 0x0 "B[$1],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x0 0. "PBYTE,Read: state of the pin PIOm_n  regardless of direction  masking  or alternate function  except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write:.." "0,1"
repeat.end
endif
sif (cpuis("LPC54114*"))
repeat 50. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x1000)++0x3
line.long 0x0 "W[$1],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x0 0.--31. 1. "PWORD,Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One.."
repeat.end
endif
sif (cpuis("LPC54114*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2000)++0x3
line.long 0x0 "DIR[$1],Direction registers"
hexmask.long 0x0 0.--31. 1. "DIRP,Selects pin direction for pin PIOm_n (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = input. 1 = output."
repeat.end
endif
sif (cpuis("LPC54114*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2080)++0x3
line.long 0x0 "MASK[$1],Mask register"
hexmask.long 0x0 0.--31. 1. "MASKP,Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT:.."
repeat.end
endif
sif (cpuis("LPC54114*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2100)++0x3
line.long 0x0 "PIN[$1],Port pin register"
hexmask.long 0x0 0.--31. 1. "PORT,Reads pin states or loads output bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."
repeat.end
endif
sif (cpuis("LPC54114*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2180)++0x3
line.long 0x0 "MPIN[$1],Masked port register"
hexmask.long 0x0 0.--31. 1. "MPORTP,Masked port register (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit.."
repeat.end
endif
sif (cpuis("LPC54114*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2200)++0x3
line.long 0x0 "SET[$1],Write: Set register for port Read: output bits for port"
hexmask.long 0x0 0.--31. 1. "SETP,Read or set output bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."
repeat.end
endif
sif (cpuis("LPC54114*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x2280)++0x3
line.long 0x0 "CLR[$1],Clear port"
hexmask.long 0x0 0.--31. 1. "CLRP,Clear output bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear output bit."
repeat.end
endif
sif (cpuis("LPC54114*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x2300)++0x3
line.long 0x0 "NOT[$1],Toggle port"
hexmask.long 0x0 0.--31. 1. "NOTP,Toggle output bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle output bit."
repeat.end
endif
sif (cpuis("LPC54114*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x2380)++0x3
line.long 0x0 "DIRSET[$1],Set pin direction bits for port"
hexmask.long 0x0 0.--28. 1. "DIRSETP,Set direction bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Set direction bit."
repeat.end
endif
sif (cpuis("LPC54114*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x2400)++0x3
line.long 0x0 "DIRCLR[$1],Clear pin direction bits for port"
hexmask.long 0x0 0.--28. 1. "DIRCLRP,Clear direction bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear direction bit."
repeat.end
endif
sif (cpuis("LPC54114*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x2480)++0x3
line.long 0x0 "DIRNOT[$1],Toggle pin direction bits for port"
hexmask.long 0x0 0.--28. 1. "DIRNOTP,Toggle direction bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle direction bit."
repeat.end
endif
sif (cpuis("LPC54605*"))
repeat 6. (list 0x0 0x1 0x2 0x3 0x4 0x5)(list ad:0x4008C000 ad:0x4008C020 ad:0x4008C040 ad:0x4008C060 ad:0x4008C080 ad:0x4008C0A0)
tree "B[$1]"
base $2
repeat 32. (increment 0x0 0x1)(increment 0x0 0x1)
group.byte ($2)++0x0
line.byte 0x0 "B_[$1],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x0 0. "PBYTE,Read: state of the pin PIOm_n  regardless of direction  masking  or alternate function  except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write:.." "0,1"
repeat.end
tree.end
repeat.end
endif
sif (cpuis("LPC54605*"))
repeat 6. (list 0x0 0x1 0x2 0x3 0x4 0x5)(list ad:0x4008D000 ad:0x4008D080 ad:0x4008D100 ad:0x4008D180 ad:0x4008D200 ad:0x4008D280)
tree "W[$1]"
base $2
repeat 32. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2)++0x3
line.long 0x0 "W_[$1],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x0 0.--31. 1. "PWORD,Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One.."
repeat.end
tree.end
repeat.end
endif
sif (cpuis("LPC54605*"))
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2000)++0x3
line.long 0x0 "DIR[$1],Direction registers"
hexmask.long 0x0 0.--31. 1. "DIRP,Selects pin direction for pin PIOm_n (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = input. 1 = output."
repeat.end
endif
sif (cpuis("LPC54605*"))
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2080)++0x3
line.long 0x0 "MASK[$1],Mask register"
hexmask.long 0x0 0.--31. 1. "MASKP,Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT:.."
repeat.end
endif
sif (cpuis("LPC54605*"))
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2100)++0x3
line.long 0x0 "PIN[$1],Port pin register"
hexmask.long 0x0 0.--31. 1. "PORT,Reads pin states or loads output bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."
repeat.end
endif
sif (cpuis("LPC54605*"))
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2180)++0x3
line.long 0x0 "MPIN[$1],Masked port register"
hexmask.long 0x0 0.--31. 1. "MPORTP,Masked port register (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit.."
repeat.end
endif
sif (cpuis("LPC54605*"))
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2200)++0x3
line.long 0x0 "SET[$1],Write: Set register for port Read: output bits for port"
hexmask.long 0x0 0.--31. 1. "SETP,Read or set output bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."
repeat.end
endif
sif (cpuis("LPC54605*"))
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x2280)++0x3
line.long 0x0 "CLR[$1],Clear port"
hexmask.long 0x0 0.--31. 1. "CLRP,Clear output bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear output bit."
repeat.end
endif
sif (cpuis("LPC54605*"))
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x2300)++0x3
line.long 0x0 "NOT[$1],Toggle port"
hexmask.long 0x0 0.--31. 1. "NOTP,Toggle output bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle output bit."
repeat.end
endif
sif (cpuis("LPC54605*"))
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x2380)++0x3
line.long 0x0 "DIRSET[$1],Set pin direction bits for port"
hexmask.long 0x0 0.--28. 1. "DIRSETP,Set direction bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Set direction bit."
repeat.end
endif
sif (cpuis("LPC54605*"))
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x2400)++0x3
line.long 0x0 "DIRCLR[$1],Clear pin direction bits for port"
hexmask.long 0x0 0.--28. 1. "DIRCLRP,Clear direction bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear direction bit."
repeat.end
endif
sif (cpuis("LPC54605*"))
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x2480)++0x3
line.long 0x0 "DIRNOT[$1],Toggle pin direction bits for port"
hexmask.long 0x0 0.--28. 1. "DIRNOTP,Toggle direction bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle direction bit."
repeat.end
endif
sif (cpuis("LPC54606*"))
repeat 6. (list 0x0 0x1 0x2 0x3 0x4 0x5)(list ad:0x4008C000 ad:0x4008C020 ad:0x4008C040 ad:0x4008C060 ad:0x4008C080 ad:0x4008C0A0)
tree "B[$1]"
base $2
repeat 32. (increment 0x0 0x1)(increment 0x0 0x1)
group.byte ($2)++0x0
line.byte 0x0 "B_[$1],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x0 0. "PBYTE,Read: state of the pin PIOm_n  regardless of direction  masking  or alternate function  except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write:.." "0,1"
repeat.end
tree.end
repeat.end
endif
sif (cpuis("LPC54606*"))
repeat 6. (list 0x0 0x1 0x2 0x3 0x4 0x5)(list ad:0x4008D000 ad:0x4008D080 ad:0x4008D100 ad:0x4008D180 ad:0x4008D200 ad:0x4008D280)
tree "W[$1]"
base $2
repeat 32. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2)++0x3
line.long 0x0 "W_[$1],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x0 0.--31. 1. "PWORD,Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One.."
repeat.end
tree.end
repeat.end
endif
sif (cpuis("LPC54606*"))
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2000)++0x3
line.long 0x0 "DIR[$1],Direction registers"
hexmask.long 0x0 0.--31. 1. "DIRP,Selects pin direction for pin PIOm_n (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = input. 1 = output."
repeat.end
endif
sif (cpuis("LPC54606*"))
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2080)++0x3
line.long 0x0 "MASK[$1],Mask register"
hexmask.long 0x0 0.--31. 1. "MASKP,Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT:.."
repeat.end
endif
sif (cpuis("LPC54606*"))
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2100)++0x3
line.long 0x0 "PIN[$1],Port pin register"
hexmask.long 0x0 0.--31. 1. "PORT,Reads pin states or loads output bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."
repeat.end
endif
sif (cpuis("LPC54606*"))
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2180)++0x3
line.long 0x0 "MPIN[$1],Masked port register"
hexmask.long 0x0 0.--31. 1. "MPORTP,Masked port register (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit.."
repeat.end
endif
sif (cpuis("LPC54606*"))
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2200)++0x3
line.long 0x0 "SET[$1],Write: Set register for port Read: output bits for port"
hexmask.long 0x0 0.--31. 1. "SETP,Read or set output bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."
repeat.end
endif
sif (cpuis("LPC54606*"))
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x2280)++0x3
line.long 0x0 "CLR[$1],Clear port"
hexmask.long 0x0 0.--31. 1. "CLRP,Clear output bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear output bit."
repeat.end
endif
sif (cpuis("LPC54606*"))
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x2300)++0x3
line.long 0x0 "NOT[$1],Toggle port"
hexmask.long 0x0 0.--31. 1. "NOTP,Toggle output bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle output bit."
repeat.end
endif
sif (cpuis("LPC54606*"))
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x2380)++0x3
line.long 0x0 "DIRSET[$1],Set pin direction bits for port"
hexmask.long 0x0 0.--28. 1. "DIRSETP,Set direction bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Set direction bit."
repeat.end
endif
sif (cpuis("LPC54606*"))
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x2400)++0x3
line.long 0x0 "DIRCLR[$1],Clear pin direction bits for port"
hexmask.long 0x0 0.--28. 1. "DIRCLRP,Clear direction bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear direction bit."
repeat.end
endif
sif (cpuis("LPC54606*"))
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x2480)++0x3
line.long 0x0 "DIRNOT[$1],Toggle pin direction bits for port"
hexmask.long 0x0 0.--28. 1. "DIRNOTP,Toggle direction bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle direction bit."
repeat.end
endif
sif (cpuis("LPC54607*"))
repeat 6. (list 0x0 0x1 0x2 0x3 0x4 0x5)(list ad:0x4008C000 ad:0x4008C020 ad:0x4008C040 ad:0x4008C060 ad:0x4008C080 ad:0x4008C0A0)
tree "B[$1]"
base $2
repeat 32. (increment 0x0 0x1)(increment 0x0 0x1)
group.byte ($2)++0x0
line.byte 0x0 "B_[$1],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x0 0. "PBYTE,Read: state of the pin PIOm_n  regardless of direction  masking  or alternate function  except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write:.." "0,1"
repeat.end
tree.end
repeat.end
endif
sif (cpuis("LPC54607*"))
repeat 6. (list 0x0 0x1 0x2 0x3 0x4 0x5)(list ad:0x4008D000 ad:0x4008D080 ad:0x4008D100 ad:0x4008D180 ad:0x4008D200 ad:0x4008D280)
tree "W[$1]"
base $2
repeat 32. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2)++0x3
line.long 0x0 "W_[$1],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x0 0.--31. 1. "PWORD,Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One.."
repeat.end
tree.end
repeat.end
endif
sif (cpuis("LPC54607*"))
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2000)++0x3
line.long 0x0 "DIR[$1],Direction registers"
hexmask.long 0x0 0.--31. 1. "DIRP,Selects pin direction for pin PIOm_n (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = input. 1 = output."
repeat.end
endif
sif (cpuis("LPC54607*"))
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2080)++0x3
line.long 0x0 "MASK[$1],Mask register"
hexmask.long 0x0 0.--31. 1. "MASKP,Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT:.."
repeat.end
endif
sif (cpuis("LPC54607*"))
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2100)++0x3
line.long 0x0 "PIN[$1],Port pin register"
hexmask.long 0x0 0.--31. 1. "PORT,Reads pin states or loads output bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."
repeat.end
endif
sif (cpuis("LPC54607*"))
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2180)++0x3
line.long 0x0 "MPIN[$1],Masked port register"
hexmask.long 0x0 0.--31. 1. "MPORTP,Masked port register (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit.."
repeat.end
endif
sif (cpuis("LPC54607*"))
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2200)++0x3
line.long 0x0 "SET[$1],Write: Set register for port Read: output bits for port"
hexmask.long 0x0 0.--31. 1. "SETP,Read or set output bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."
repeat.end
endif
sif (cpuis("LPC54607*"))
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x2280)++0x3
line.long 0x0 "CLR[$1],Clear port"
hexmask.long 0x0 0.--31. 1. "CLRP,Clear output bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear output bit."
repeat.end
endif
sif (cpuis("LPC54607*"))
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x2300)++0x3
line.long 0x0 "NOT[$1],Toggle port"
hexmask.long 0x0 0.--31. 1. "NOTP,Toggle output bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle output bit."
repeat.end
endif
sif (cpuis("LPC54607*"))
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x2380)++0x3
line.long 0x0 "DIRSET[$1],Set pin direction bits for port"
hexmask.long 0x0 0.--28. 1. "DIRSETP,Set direction bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Set direction bit."
repeat.end
endif
sif (cpuis("LPC54607*"))
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x2400)++0x3
line.long 0x0 "DIRCLR[$1],Clear pin direction bits for port"
hexmask.long 0x0 0.--28. 1. "DIRCLRP,Clear direction bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear direction bit."
repeat.end
endif
sif (cpuis("LPC54607*"))
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x2480)++0x3
line.long 0x0 "DIRNOT[$1],Toggle pin direction bits for port"
hexmask.long 0x0 0.--28. 1. "DIRNOTP,Toggle direction bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle direction bit."
repeat.end
endif
sif (cpuis("LPC54608*"))
repeat 6. (list 0x0 0x1 0x2 0x3 0x4 0x5)(list ad:0x4008C000 ad:0x4008C020 ad:0x4008C040 ad:0x4008C060 ad:0x4008C080 ad:0x4008C0A0)
tree "B[$1]"
base $2
repeat 32. (increment 0x0 0x1)(increment 0x0 0x1)
group.byte ($2)++0x0
line.byte 0x0 "B_[$1],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x0 0. "PBYTE,Read: state of the pin PIOm_n  regardless of direction  masking  or alternate function  except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write:.." "0,1"
repeat.end
tree.end
repeat.end
endif
sif (cpuis("LPC54608*"))
repeat 6. (list 0x0 0x1 0x2 0x3 0x4 0x5)(list ad:0x4008D000 ad:0x4008D080 ad:0x4008D100 ad:0x4008D180 ad:0x4008D200 ad:0x4008D280)
tree "W[$1]"
base $2
repeat 32. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2)++0x3
line.long 0x0 "W_[$1],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x0 0.--31. 1. "PWORD,Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One.."
repeat.end
tree.end
repeat.end
endif
sif (cpuis("LPC54608*"))
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2000)++0x3
line.long 0x0 "DIR[$1],Direction registers"
hexmask.long 0x0 0.--31. 1. "DIRP,Selects pin direction for pin PIOm_n (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = input. 1 = output."
repeat.end
endif
sif (cpuis("LPC54608*"))
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2080)++0x3
line.long 0x0 "MASK[$1],Mask register"
hexmask.long 0x0 0.--31. 1. "MASKP,Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT:.."
repeat.end
endif
sif (cpuis("LPC54608*"))
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2100)++0x3
line.long 0x0 "PIN[$1],Port pin register"
hexmask.long 0x0 0.--31. 1. "PORT,Reads pin states or loads output bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."
repeat.end
endif
sif (cpuis("LPC54608*"))
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2180)++0x3
line.long 0x0 "MPIN[$1],Masked port register"
hexmask.long 0x0 0.--31. 1. "MPORTP,Masked port register (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit.."
repeat.end
endif
sif (cpuis("LPC54608*"))
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2200)++0x3
line.long 0x0 "SET[$1],Write: Set register for port Read: output bits for port"
hexmask.long 0x0 0.--31. 1. "SETP,Read or set output bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."
repeat.end
endif
sif (cpuis("LPC54608*"))
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x2280)++0x3
line.long 0x0 "CLR[$1],Clear port"
hexmask.long 0x0 0.--31. 1. "CLRP,Clear output bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear output bit."
repeat.end
endif
sif (cpuis("LPC54608*"))
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x2300)++0x3
line.long 0x0 "NOT[$1],Toggle port"
hexmask.long 0x0 0.--31. 1. "NOTP,Toggle output bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle output bit."
repeat.end
endif
sif (cpuis("LPC54608*"))
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x2380)++0x3
line.long 0x0 "DIRSET[$1],Set pin direction bits for port"
hexmask.long 0x0 0.--28. 1. "DIRSETP,Set direction bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Set direction bit."
repeat.end
endif
sif (cpuis("LPC54608*"))
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x2400)++0x3
line.long 0x0 "DIRCLR[$1],Clear pin direction bits for port"
hexmask.long 0x0 0.--28. 1. "DIRCLRP,Clear direction bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear direction bit."
repeat.end
endif
sif (cpuis("LPC54608*"))
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x2480)++0x3
line.long 0x0 "DIRNOT[$1],Toggle pin direction bits for port"
hexmask.long 0x0 0.--28. 1. "DIRNOTP,Toggle direction bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle direction bit."
repeat.end
endif
sif (cpuis("LPC54616*"))
repeat 6. (list 0x0 0x1 0x2 0x3 0x4 0x5)(list ad:0x4008C000 ad:0x4008C020 ad:0x4008C040 ad:0x4008C060 ad:0x4008C080 ad:0x4008C0A0)
tree "B[$1]"
base $2
repeat 32. (increment 0x0 0x1)(increment 0x0 0x1)
group.byte ($2)++0x0
line.byte 0x0 "B_[$1],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x0 0. "PBYTE,Read: state of the pin PIOm_n  regardless of direction  masking  or alternate function  except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write:.." "0,1"
repeat.end
tree.end
repeat.end
endif
sif (cpuis("LPC54616*"))
repeat 6. (list 0x0 0x1 0x2 0x3 0x4 0x5)(list ad:0x4008D000 ad:0x4008D080 ad:0x4008D100 ad:0x4008D180 ad:0x4008D200 ad:0x4008D280)
tree "W[$1]"
base $2
repeat 32. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2)++0x3
line.long 0x0 "W_[$1],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x0 0.--31. 1. "PWORD,Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One.."
repeat.end
tree.end
repeat.end
endif
sif (cpuis("LPC54616*"))
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2000)++0x3
line.long 0x0 "DIR[$1],Direction registers"
hexmask.long 0x0 0.--31. 1. "DIRP,Selects pin direction for pin PIOm_n (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = input. 1 = output."
repeat.end
endif
sif (cpuis("LPC54616*"))
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2080)++0x3
line.long 0x0 "MASK[$1],Mask register"
hexmask.long 0x0 0.--31. 1. "MASKP,Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT:.."
repeat.end
endif
sif (cpuis("LPC54616*"))
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2100)++0x3
line.long 0x0 "PIN[$1],Port pin register"
hexmask.long 0x0 0.--31. 1. "PORT,Reads pin states or loads output bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."
repeat.end
endif
sif (cpuis("LPC54616*"))
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2180)++0x3
line.long 0x0 "MPIN[$1],Masked port register"
hexmask.long 0x0 0.--31. 1. "MPORTP,Masked port register (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit.."
repeat.end
endif
sif (cpuis("LPC54616*"))
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2200)++0x3
line.long 0x0 "SET[$1],Write: Set register for port Read: output bits for port"
hexmask.long 0x0 0.--31. 1. "SETP,Read or set output bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."
repeat.end
endif
sif (cpuis("LPC54616*"))
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x2280)++0x3
line.long 0x0 "CLR[$1],Clear port"
hexmask.long 0x0 0.--31. 1. "CLRP,Clear output bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear output bit."
repeat.end
endif
sif (cpuis("LPC54616*"))
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x2300)++0x3
line.long 0x0 "NOT[$1],Toggle port"
hexmask.long 0x0 0.--31. 1. "NOTP,Toggle output bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle output bit."
repeat.end
endif
sif (cpuis("LPC54616*"))
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x2380)++0x3
line.long 0x0 "DIRSET[$1],Set pin direction bits for port"
hexmask.long 0x0 0.--28. 1. "DIRSETP,Set direction bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Set direction bit."
repeat.end
endif
sif (cpuis("LPC54616*"))
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x2400)++0x3
line.long 0x0 "DIRCLR[$1],Clear pin direction bits for port"
hexmask.long 0x0 0.--28. 1. "DIRCLRP,Clear direction bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear direction bit."
repeat.end
endif
sif (cpuis("LPC54616*"))
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x2480)++0x3
line.long 0x0 "DIRNOT[$1],Toggle pin direction bits for port"
hexmask.long 0x0 0.--28. 1. "DIRNOTP,Toggle direction bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle direction bit."
repeat.end
endif
sif (cpuis("LPC54618*"))
repeat 6. (list 0x0 0x1 0x2 0x3 0x4 0x5)(list ad:0x4008C000 ad:0x4008C020 ad:0x4008C040 ad:0x4008C060 ad:0x4008C080 ad:0x4008C0A0)
tree "B[$1]"
base $2
repeat 32. (increment 0x0 0x1)(increment 0x0 0x1)
group.byte ($2)++0x0
line.byte 0x0 "B_[$1],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x0 0. "PBYTE,Read: state of the pin PIOm_n  regardless of direction  masking  or alternate function  except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write:.." "0,1"
repeat.end
tree.end
repeat.end
endif
sif (cpuis("LPC54618*"))
repeat 6. (list 0x0 0x1 0x2 0x3 0x4 0x5)(list ad:0x4008D000 ad:0x4008D080 ad:0x4008D100 ad:0x4008D180 ad:0x4008D200 ad:0x4008D280)
tree "W[$1]"
base $2
repeat 32. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2)++0x3
line.long 0x0 "W_[$1],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x0 0.--31. 1. "PWORD,Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One.."
repeat.end
tree.end
repeat.end
endif
sif (cpuis("LPC54618*"))
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2000)++0x3
line.long 0x0 "DIR[$1],Direction registers"
hexmask.long 0x0 0.--31. 1. "DIRP,Selects pin direction for pin PIOm_n (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = input. 1 = output."
repeat.end
endif
sif (cpuis("LPC54618*"))
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2080)++0x3
line.long 0x0 "MASK[$1],Mask register"
hexmask.long 0x0 0.--31. 1. "MASKP,Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT:.."
repeat.end
endif
sif (cpuis("LPC54618*"))
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2100)++0x3
line.long 0x0 "PIN[$1],Port pin register"
hexmask.long 0x0 0.--31. 1. "PORT,Reads pin states or loads output bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."
repeat.end
endif
sif (cpuis("LPC54618*"))
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2180)++0x3
line.long 0x0 "MPIN[$1],Masked port register"
hexmask.long 0x0 0.--31. 1. "MPORTP,Masked port register (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit.."
repeat.end
endif
sif (cpuis("LPC54618*"))
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2200)++0x3
line.long 0x0 "SET[$1],Write: Set register for port Read: output bits for port"
hexmask.long 0x0 0.--31. 1. "SETP,Read or set output bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."
repeat.end
endif
sif (cpuis("LPC54618*"))
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x2280)++0x3
line.long 0x0 "CLR[$1],Clear port"
hexmask.long 0x0 0.--31. 1. "CLRP,Clear output bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear output bit."
repeat.end
endif
sif (cpuis("LPC54618*"))
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x2300)++0x3
line.long 0x0 "NOT[$1],Toggle port"
hexmask.long 0x0 0.--31. 1. "NOTP,Toggle output bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle output bit."
repeat.end
endif
sif (cpuis("LPC54618*"))
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x2380)++0x3
line.long 0x0 "DIRSET[$1],Set pin direction bits for port"
hexmask.long 0x0 0.--28. 1. "DIRSETP,Set direction bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Set direction bit."
repeat.end
endif
sif (cpuis("LPC54618*"))
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x2400)++0x3
line.long 0x0 "DIRCLR[$1],Clear pin direction bits for port"
hexmask.long 0x0 0.--28. 1. "DIRCLRP,Clear direction bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear direction bit."
repeat.end
endif
sif (cpuis("LPC54618*"))
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x2480)++0x3
line.long 0x0 "DIRNOT[$1],Toggle pin direction bits for port"
hexmask.long 0x0 0.--28. 1. "DIRNOTP,Toggle direction bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle direction bit."
repeat.end
endif
sif (cpuis("LPC54628*"))
repeat 6. (list 0x0 0x1 0x2 0x3 0x4 0x5)(list ad:0x4008C000 ad:0x4008C020 ad:0x4008C040 ad:0x4008C060 ad:0x4008C080 ad:0x4008C0A0)
tree "B[$1]"
base $2
repeat 32. (increment 0x0 0x1)(increment 0x0 0x1)
group.byte ($2)++0x0
line.byte 0x0 "B_[$1],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x0 0. "PBYTE,Read: state of the pin PIOm_n  regardless of direction  masking  or alternate function  except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write:.." "0,1"
repeat.end
tree.end
repeat.end
endif
sif (cpuis("LPC54628*"))
repeat 6. (list 0x0 0x1 0x2 0x3 0x4 0x5)(list ad:0x4008D000 ad:0x4008D080 ad:0x4008D100 ad:0x4008D180 ad:0x4008D200 ad:0x4008D280)
tree "W[$1]"
base $2
repeat 32. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2)++0x3
line.long 0x0 "W_[$1],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x0 0.--31. 1. "PWORD,Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One.."
repeat.end
tree.end
repeat.end
endif
sif (cpuis("LPC54628*"))
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2000)++0x3
line.long 0x0 "DIR[$1],Direction registers"
hexmask.long 0x0 0.--31. 1. "DIRP,Selects pin direction for pin PIOm_n (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = input. 1 = output."
repeat.end
endif
sif (cpuis("LPC54628*"))
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2080)++0x3
line.long 0x0 "MASK[$1],Mask register"
hexmask.long 0x0 0.--31. 1. "MASKP,Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT:.."
repeat.end
endif
sif (cpuis("LPC54628*"))
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2100)++0x3
line.long 0x0 "PIN[$1],Port pin register"
hexmask.long 0x0 0.--31. 1. "PORT,Reads pin states or loads output bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit."
repeat.end
endif
sif (cpuis("LPC54628*"))
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2180)++0x3
line.long 0x0 "MPIN[$1],Masked port register"
hexmask.long 0x0 0.--31. 1. "MPORTP,Masked port register (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit.."
repeat.end
endif
sif (cpuis("LPC54628*"))
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2200)++0x3
line.long 0x0 "SET[$1],Write: Set register for port Read: output bits for port"
hexmask.long 0x0 0.--31. 1. "SETP,Read or set output bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit."
repeat.end
endif
sif (cpuis("LPC54628*"))
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x2280)++0x3
line.long 0x0 "CLR[$1],Clear port"
hexmask.long 0x0 0.--31. 1. "CLRP,Clear output bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear output bit."
repeat.end
endif
sif (cpuis("LPC54628*"))
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x2300)++0x3
line.long 0x0 "NOT[$1],Toggle port"
hexmask.long 0x0 0.--31. 1. "NOTP,Toggle output bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle output bit."
repeat.end
endif
sif (cpuis("LPC54628*"))
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x2380)++0x3
line.long 0x0 "DIRSET[$1],Set pin direction bits for port"
hexmask.long 0x0 0.--28. 1. "DIRSETP,Set direction bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Set direction bit."
repeat.end
endif
sif (cpuis("LPC54628*"))
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x2400)++0x3
line.long 0x0 "DIRCLR[$1],Clear pin direction bits for port"
hexmask.long 0x0 0.--28. 1. "DIRCLRP,Clear direction bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear direction bit."
repeat.end
endif
sif (cpuis("LPC54628*"))
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x2480)++0x3
line.long 0x0 "DIRNOT[$1],Toggle pin direction bits for port"
hexmask.long 0x0 0.--28. 1. "DIRNOTP,Toggle direction bits (bit 0 = PIOn_0  bit 1 = PIOn_1  etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle direction bit."
repeat.end
endif
tree.end
tree "I2C (Inter-Integrated Circuit)"
base ad:0x0
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
base ad:0x40086000
elif (cpuis("LPC54101*"))
base ad:0x40094000
endif
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54101*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
tree "I2C0"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
newline
bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
newline
bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
newline
bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
newline
bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
newline
bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
newline
rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
newline
rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
newline
bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
newline
rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
newline
bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
newline
bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
newline
bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
newline
bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
newline
bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
newline
bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
newline
bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
newline
bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
newline
bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
newline
bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
newline
bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
newline
bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
newline
bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
newline
bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
newline
bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
newline
bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
newline
bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
newline
hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
endif
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
newline
bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
sif (cpuis("LPC54101*"))
group.long 0x0++0x1B
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: master  slave  and monitor." "0: Fast-mode plus. The I2C block will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The monitor function will not perform..,1: Enabled. The monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C monitor function is disabled.,1: Enabled. The I2C monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
bitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
bitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
bitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address. It is cleared when another address cycle presents an address that does not match an enabled address on the Slave function .." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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bitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
bitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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bitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 347 for state values and actions." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
bitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
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bitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
bitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
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bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
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bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
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bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
line.long 0xC "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0xC 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0xC 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
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bitfld.long 0xC 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0xC 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
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bitfld.long 0xC 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0xC 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
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bitfld.long 0xC 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0xC 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
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bitfld.long 0xC 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0xC 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
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bitfld.long 0xC 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
line.long 0x10 "TIMEOUT,Time-out value register."
hexmask.long.word 0x10 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I2C function clocks  as defined by the CLKDIV register. To change this value while I 2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x10 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x14 "CLKDIV,Clock pre-divider for the entire I2C block. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x14 0.--15. 1. "DIVVAL,This field controls how the clock (PCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = PCLK is used directly by the I2C. 0x0001 = PCLK is divided by 2 before use. 0x0002 = PCLK is divided by 3 before use."
line.long 0x18 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x18 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x18 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x18 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x18 17. "MONOV,Monitor Overflow flag." "0,1"
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bitfld.long 0x18 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x18 15. "SLVDESEL,Slave Deselected flag." "0,1"
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bitfld.long 0x18 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x18 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x18 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x18 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
newline
bitfld.long 0x18 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x20++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. When a DMA data transfer is complete .." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter tLOW in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x40++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
endif
sif (cpuis("LPC54101*"))
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x48)++0x3
line.long 0x0 "SLVADR[$1],Slave address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x58++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
group.long 0x80++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The monitor function..,1: Repeated start detected. The monitor function.."
newline
bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The monitor function has not..,1: Start detected. The monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
endif
tree.end
endif
tree "I2C3"
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
newline
bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
newline
bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
newline
bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
newline
bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
newline
rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
newline
rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
newline
bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
newline
rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
newline
bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
newline
bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
newline
bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
newline
bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
newline
bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
newline
bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
newline
bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
newline
bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
newline
bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
newline
bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
newline
bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
newline
bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
newline
bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
newline
bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
newline
bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2C4"
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
newline
bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
newline
bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
newline
bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
newline
bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
newline
bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
newline
rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
newline
rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
newline
bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
newline
rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
newline
bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
newline
bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
newline
bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
newline
bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
newline
bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
newline
bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
newline
bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
newline
bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
newline
bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
newline
bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
newline
bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
newline
bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
newline
bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
newline
bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
newline
bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
newline
bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
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bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2C5"
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
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rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
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bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
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bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
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bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
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bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
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bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
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bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
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bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
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bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2C6"
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
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rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
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bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
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bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
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bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
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bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
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bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
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bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
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bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
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bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2C7"
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
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rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
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bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
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bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
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bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
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bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
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bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
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bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
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bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
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bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2C8"
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
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rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
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bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
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bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
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bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
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bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
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bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
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bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
newline
bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2C9"
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
newline
bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
newline
rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
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rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
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bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
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bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
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bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
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bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
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bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
newline
bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
newline
bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
newline
bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
newline
bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
base ad:0x40087000
elif (cpuis("LPC54101*"))
base ad:0x40098000
endif
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54101*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
tree "I2C1"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
newline
bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
newline
bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
newline
bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
newline
bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
newline
bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
newline
rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
newline
rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
newline
bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
newline
rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
newline
bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
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bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
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bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
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bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
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bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
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bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
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bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
endif
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
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bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
sif (cpuis("LPC54101*"))
group.long 0x0++0x1B
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: master  slave  and monitor." "0: Fast-mode plus. The I2C block will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The monitor function will not perform..,1: Enabled. The monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C monitor function is disabled.,1: Enabled. The I2C monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
bitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
bitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
bitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address. It is cleared when another address cycle presents an address that does not match an enabled address on the Slave function .." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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bitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
bitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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bitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 347 for state values and actions." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
bitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
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bitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
bitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
newline
bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
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bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
newline
bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
newline
bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
line.long 0xC "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0xC 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0xC 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
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bitfld.long 0xC 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0xC 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
newline
bitfld.long 0xC 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0xC 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
newline
bitfld.long 0xC 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0xC 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
newline
bitfld.long 0xC 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0xC 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
newline
bitfld.long 0xC 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
line.long 0x10 "TIMEOUT,Time-out value register."
hexmask.long.word 0x10 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I2C function clocks  as defined by the CLKDIV register. To change this value while I 2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x10 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x14 "CLKDIV,Clock pre-divider for the entire I2C block. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x14 0.--15. 1. "DIVVAL,This field controls how the clock (PCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = PCLK is used directly by the I2C. 0x0001 = PCLK is divided by 2 before use. 0x0002 = PCLK is divided by 3 before use."
line.long 0x18 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x18 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x18 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x18 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x18 17. "MONOV,Monitor Overflow flag." "0,1"
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bitfld.long 0x18 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x18 15. "SLVDESEL,Slave Deselected flag." "0,1"
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bitfld.long 0x18 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x18 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x18 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x18 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x18 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x20++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. When a DMA data transfer is complete .." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter tLOW in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x40++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
newline
bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
endif
sif (cpuis("LPC54101*"))
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x48)++0x3
line.long 0x0 "SLVADR[$1],Slave address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x58++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
group.long 0x80++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The monitor function..,1: Repeated start detected. The monitor function.."
newline
bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The monitor function has not..,1: Start detected. The monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
endif
tree.end
endif
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
base ad:0x40088000
elif (cpuis("LPC54101*"))
base ad:0x4009C000
endif
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54101*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
tree "I2C2"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
newline
bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
newline
bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
newline
bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
newline
bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
newline
bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
newline
rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
newline
rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
newline
bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
newline
rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
newline
bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
newline
bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
newline
bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
newline
bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
newline
bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
newline
bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
newline
bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
newline
bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
newline
bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
newline
bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
newline
bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
newline
bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
newline
bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
newline
bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
newline
bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
newline
bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
newline
bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
newline
hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
endif
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
newline
bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
sif (cpuis("LPC54101*"))
group.long 0x0++0x1B
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: master  slave  and monitor." "0: Fast-mode plus. The I2C block will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The monitor function will not perform..,1: Enabled. The monitor function will perform clock.."
newline
bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C monitor function is disabled.,1: Enabled. The I2C monitor function is enabled."
newline
bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
newline
bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
bitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
newline
bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
bitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
bitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address. It is cleared when another address cycle presents an address that does not match an enabled address on the Slave function .." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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bitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
bitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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bitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 347 for state values and actions." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
bitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
newline
bitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
bitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
newline
bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
newline
bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
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bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
line.long 0xC "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0xC 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0xC 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
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bitfld.long 0xC 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0xC 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
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bitfld.long 0xC 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0xC 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
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bitfld.long 0xC 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0xC 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
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bitfld.long 0xC 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0xC 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
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bitfld.long 0xC 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
line.long 0x10 "TIMEOUT,Time-out value register."
hexmask.long.word 0x10 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I2C function clocks  as defined by the CLKDIV register. To change this value while I 2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x10 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x14 "CLKDIV,Clock pre-divider for the entire I2C block. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x14 0.--15. 1. "DIVVAL,This field controls how the clock (PCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = PCLK is used directly by the I2C. 0x0001 = PCLK is divided by 2 before use. 0x0002 = PCLK is divided by 3 before use."
line.long 0x18 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x18 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x18 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x18 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x18 17. "MONOV,Monitor Overflow flag." "0,1"
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bitfld.long 0x18 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x18 15. "SLVDESEL,Slave Deselected flag." "0,1"
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bitfld.long 0x18 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x18 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x18 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x18 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x18 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x20++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. When a DMA data transfer is complete .." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter tLOW in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x40++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
endif
sif (cpuis("LPC54101*"))
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x48)++0x3
line.long 0x0 "SLVADR[$1],Slave address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x58++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
group.long 0x80++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The monitor function..,1: Repeated start detected. The monitor function.."
newline
bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The monitor function has not..,1: Start detected. The monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
endif
tree.end
endif
sif (cpuis("LPC54102*"))
tree "I2C0"
base ad:0x40094000
group.long 0x0++0x1B
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: master  slave  and monitor." "0: Fast-mode plus. The I2C block will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The monitor function will not perform..,1: Enabled. The monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C monitor function is disabled.,1: Enabled. The I2C monitor function is enabled."
newline
bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
newline
bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
bitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
newline
bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
bitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
newline
bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
bitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address. It is cleared when another address cycle presents an address that does not match an enabled address on the Slave function .." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
newline
bitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
bitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
newline
bitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 347 for state values and actions." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
bitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
newline
bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
newline
bitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
bitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
newline
bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
newline
bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
newline
bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
newline
bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
newline
bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
line.long 0xC "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0xC 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0xC 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
newline
bitfld.long 0xC 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0xC 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
newline
bitfld.long 0xC 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0xC 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
newline
bitfld.long 0xC 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0xC 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
newline
bitfld.long 0xC 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0xC 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
newline
bitfld.long 0xC 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
line.long 0x10 "TIMEOUT,Time-out value register."
hexmask.long.word 0x10 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I2C function clocks  as defined by the CLKDIV register. To change this value while I 2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x10 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x14 "CLKDIV,Clock pre-divider for the entire I2C block. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x14 0.--15. 1. "DIVVAL,This field controls how the clock (PCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = PCLK is used directly by the I2C. 0x0001 = PCLK is divided by 2 before use. 0x0002 = PCLK is divided by 3 before use."
line.long 0x18 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x18 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x18 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
newline
bitfld.long 0x18 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x18 17. "MONOV,Monitor Overflow flag." "0,1"
newline
bitfld.long 0x18 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x18 15. "SLVDESEL,Slave Deselected flag." "0,1"
newline
bitfld.long 0x18 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x18 8. "SLVPENDING,Slave Pending." "0,1"
newline
bitfld.long 0x18 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x18 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x18 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x20++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. When a DMA data transfer is complete .." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter tLOW in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x40++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x48)++0x3
line.long 0x0 "SLVADR[$1],Slave address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x58++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
group.long 0x80++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The monitor function..,1: Repeated start detected. The monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The monitor function has not..,1: Start detected. The monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
tree.end
tree "I2C1"
base ad:0x40098000
group.long 0x0++0x1B
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: master  slave  and monitor." "0: Fast-mode plus. The I2C block will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The monitor function will not perform..,1: Enabled. The monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C monitor function is disabled.,1: Enabled. The I2C monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
bitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
bitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
bitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address. It is cleared when another address cycle presents an address that does not match an enabled address on the Slave function .." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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bitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
bitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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bitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 347 for state values and actions." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
bitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
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bitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
bitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
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bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
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bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
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bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
line.long 0xC "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0xC 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0xC 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
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bitfld.long 0xC 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0xC 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
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bitfld.long 0xC 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0xC 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
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bitfld.long 0xC 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0xC 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
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bitfld.long 0xC 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0xC 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
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bitfld.long 0xC 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
line.long 0x10 "TIMEOUT,Time-out value register."
hexmask.long.word 0x10 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I2C function clocks  as defined by the CLKDIV register. To change this value while I 2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x10 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x14 "CLKDIV,Clock pre-divider for the entire I2C block. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x14 0.--15. 1. "DIVVAL,This field controls how the clock (PCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = PCLK is used directly by the I2C. 0x0001 = PCLK is divided by 2 before use. 0x0002 = PCLK is divided by 3 before use."
line.long 0x18 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x18 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x18 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x18 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x18 17. "MONOV,Monitor Overflow flag." "0,1"
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bitfld.long 0x18 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x18 15. "SLVDESEL,Slave Deselected flag." "0,1"
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bitfld.long 0x18 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x18 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x18 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x18 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x18 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x20++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. When a DMA data transfer is complete .." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter tLOW in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x40++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x48)++0x3
line.long 0x0 "SLVADR[$1],Slave address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x58++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
group.long 0x80++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The monitor function..,1: Repeated start detected. The monitor function.."
newline
bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The monitor function has not..,1: Start detected. The monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
tree.end
tree "I2C2"
base ad:0x4009C000
group.long 0x0++0x1B
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: master  slave  and monitor." "0: Fast-mode plus. The I2C block will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The monitor function will not perform..,1: Enabled. The monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C monitor function is disabled.,1: Enabled. The I2C monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
bitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
bitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
bitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address. It is cleared when another address cycle presents an address that does not match an enabled address on the Slave function .." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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bitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
bitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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bitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 347 for state values and actions." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
bitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
newline
bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
newline
bitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
bitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
newline
bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
newline
bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
newline
bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
newline
bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
newline
bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
line.long 0xC "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0xC 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0xC 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
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bitfld.long 0xC 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0xC 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
newline
bitfld.long 0xC 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0xC 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
newline
bitfld.long 0xC 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0xC 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
newline
bitfld.long 0xC 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0xC 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
newline
bitfld.long 0xC 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
line.long 0x10 "TIMEOUT,Time-out value register."
hexmask.long.word 0x10 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I2C function clocks  as defined by the CLKDIV register. To change this value while I 2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x10 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x14 "CLKDIV,Clock pre-divider for the entire I2C block. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x14 0.--15. 1. "DIVVAL,This field controls how the clock (PCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = PCLK is used directly by the I2C. 0x0001 = PCLK is divided by 2 before use. 0x0002 = PCLK is divided by 3 before use."
line.long 0x18 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x18 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x18 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x18 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x18 17. "MONOV,Monitor Overflow flag." "0,1"
newline
bitfld.long 0x18 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x18 15. "SLVDESEL,Slave Deselected flag." "0,1"
newline
bitfld.long 0x18 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x18 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x18 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x18 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
newline
bitfld.long 0x18 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x20++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. When a DMA data transfer is complete .." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
newline
bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter tLOW in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x40++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
newline
bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x48)++0x3
line.long 0x0 "SLVADR[$1],Slave address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x58++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
group.long 0x80++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The monitor function..,1: Repeated start detected. The monitor function.."
newline
bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The monitor function has not..,1: Start detected. The monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
tree.end
endif
sif (cpuis("LPC54113*"))
tree "I2C0"
base ad:0x40086000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
newline
bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
newline
bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
newline
bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
newline
bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
newline
bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
newline
rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
newline
rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
newline
bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
newline
rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
newline
bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
newline
bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
newline
bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
newline
bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
newline
bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
newline
bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
newline
bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
newline
bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
newline
bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
newline
bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
newline
bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
newline
bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
newline
bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
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bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
tree.end
tree "I2C1"
base ad:0x40087000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
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rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
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bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
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bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
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bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
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bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
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bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
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bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
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bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
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bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
tree.end
tree "I2C2"
base ad:0x40088000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
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rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
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bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
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bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
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bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
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bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
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bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
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bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
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bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
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bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
tree.end
tree "I2C3"
base ad:0x40089000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
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rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
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bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
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bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
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bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
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bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
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bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
newline
bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
newline
bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
newline
bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
newline
bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
newline
bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
tree.end
tree "I2C4"
base ad:0x4008A000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
newline
bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
newline
bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
newline
bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
newline
bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
newline
bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
newline
rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
newline
rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
newline
bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
newline
rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
newline
bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
newline
bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
newline
bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
newline
bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
newline
bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
newline
bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
newline
bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
newline
bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
newline
bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
newline
bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
newline
bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
newline
bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
newline
bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
newline
bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
newline
bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
newline
bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
newline
bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
tree.end
tree "I2C5"
base ad:0x40096000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
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rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
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bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
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bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
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bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
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bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
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bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
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bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
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bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
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bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
tree.end
tree "I2C6"
base ad:0x40097000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
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rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
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bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
newline
bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
newline
bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
newline
bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
newline
bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
newline
bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
newline
bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
newline
bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
newline
bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
newline
bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
newline
bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
newline
bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
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bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
tree.end
tree "I2C7"
base ad:0x40098000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
newline
bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
newline
bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
newline
rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
newline
rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
newline
bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
newline
rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
newline
bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
newline
bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
newline
bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
newline
bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
newline
bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
newline
bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
newline
bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
newline
bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
newline
bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
newline
bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
newline
bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
newline
bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
newline
bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
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bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
tree.end
endif
sif (cpuis("LPC54114*"))
tree "I2C0"
base ad:0x40086000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
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rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
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bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
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bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
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bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
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bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
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bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
newline
bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
newline
bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
newline
bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
newline
bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
tree.end
tree "I2C1"
base ad:0x40087000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
newline
bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
newline
bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
newline
bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
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rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
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bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
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bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
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bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
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bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
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bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
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bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
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bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
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bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
tree.end
tree "I2C2"
base ad:0x40088000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
newline
rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
newline
rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
newline
bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
newline
bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
newline
bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
newline
bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
newline
bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
newline
bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
newline
bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
newline
bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
newline
bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
newline
bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
newline
bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
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bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
tree.end
tree "I2C3"
base ad:0x40089000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
newline
rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
newline
rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
newline
bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
newline
bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
newline
bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
newline
bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
newline
bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
newline
bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
newline
bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
newline
bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
newline
bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
newline
bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
newline
bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
newline
bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
newline
bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
newline
bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
newline
bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
tree.end
tree "I2C4"
base ad:0x4008A000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
newline
bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
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rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
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bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
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bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
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bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
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bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
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bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
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bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
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bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
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bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
tree.end
tree "I2C5"
base ad:0x40096000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
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rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
newline
bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
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bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
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bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
newline
bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
newline
bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
newline
bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
newline
bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
newline
bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
newline
bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
newline
bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
newline
bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
newline
bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
newline
bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
newline
bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
newline
bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
tree.end
tree "I2C6"
base ad:0x40097000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
newline
bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
newline
bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
newline
bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
newline
bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
newline
bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
newline
rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
newline
rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
newline
bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
newline
rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
newline
bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
newline
bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
newline
bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
newline
bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
newline
bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
newline
bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
newline
bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
newline
bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
newline
bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
newline
bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
newline
bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
newline
bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
newline
bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
newline
bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
newline
bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
newline
bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
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bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
tree.end
tree "I2C7"
base ad:0x40098000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
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rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
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bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
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bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
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bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
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bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
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bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
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bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
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bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
newline
bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
tree.end
endif
sif (cpuis("LPC54605*"))
tree "I2C0"
base ad:0x40086000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
newline
rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
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rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
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bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
newline
bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
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bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
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bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
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bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
newline
bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
newline
bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
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bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
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bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2C1"
base ad:0x40087000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
newline
rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
newline
bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
newline
bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
newline
bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
newline
bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
newline
bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
newline
bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
newline
bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
newline
bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
newline
bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
newline
bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
newline
bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
newline
bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
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bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2C2"
base ad:0x40088000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
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rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
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bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
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bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
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bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
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bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
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bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
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bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
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bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
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bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2C3"
base ad:0x40089000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
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rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
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bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
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bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
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bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
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bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
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bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
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bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
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bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
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bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2C4"
base ad:0x4008A000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
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rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
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bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
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bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
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bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
newline
bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
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bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
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bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
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bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
newline
bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
newline
bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
newline
bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2C5"
base ad:0x40096000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
newline
rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
newline
rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
newline
bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
newline
rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
newline
bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
newline
bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
newline
bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
newline
bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
newline
bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
newline
bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
newline
bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
newline
bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
newline
bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
newline
bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
newline
bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
newline
bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
newline
bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
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bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2C6"
base ad:0x40097000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
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rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
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bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
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bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
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bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
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bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
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bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
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bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
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bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
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bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2C7"
base ad:0x40098000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
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rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
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bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
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bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
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bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
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bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
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bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
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bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
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bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
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bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2C8"
base ad:0x40099000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
newline
rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
newline
bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
newline
bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
newline
bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
newline
bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
newline
bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
newline
bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
newline
bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
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bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
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bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2C9"
base ad:0x4009A000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
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rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
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bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
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bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
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bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
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bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
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bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
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bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
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bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
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bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
endif
sif (cpuis("LPC54606*"))
tree "I2C0"
base ad:0x40086000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
newline
bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
newline
rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
newline
rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
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bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
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bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
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bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
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bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
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bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
newline
bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
newline
bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
newline
bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
newline
bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
newline
bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2C1"
base ad:0x40087000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
newline
bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
newline
bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
newline
bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
newline
rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
newline
rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
newline
rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
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bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
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bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
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bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
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bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
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bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
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bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
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bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
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bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2C2"
base ad:0x40088000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
newline
rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
newline
bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
newline
bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
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bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
newline
bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
newline
bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
newline
bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
newline
bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
newline
bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
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bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2C3"
base ad:0x40089000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
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rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
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bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
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bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
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bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
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bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
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bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
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bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
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bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
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bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2C4"
base ad:0x4008A000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
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rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
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bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
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bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
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bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
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bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
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bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
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bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
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bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
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bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2C5"
base ad:0x40096000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
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rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
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bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
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bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
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bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
newline
bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
newline
bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
newline
bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
newline
bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
newline
bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
newline
bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2C6"
base ad:0x40097000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
newline
bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
newline
bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
newline
bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
newline
bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
newline
bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
newline
rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
newline
rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
newline
bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
newline
rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
newline
bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
newline
bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
newline
bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
newline
bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
newline
bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
newline
bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
newline
bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
newline
bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
newline
bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
newline
bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
newline
bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
newline
bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
newline
bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
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bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2C7"
base ad:0x40098000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
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rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
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bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
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bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
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bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
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bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
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bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
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bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
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bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
newline
bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
newline
bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2C8"
base ad:0x40099000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
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rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
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bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
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bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
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bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
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bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
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bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
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bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
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bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
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bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2C9"
base ad:0x4009A000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
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rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
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bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
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bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
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bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
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bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
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bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
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bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
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bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
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bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
endif
sif (cpuis("LPC54607*"))
tree "I2C0"
base ad:0x40086000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
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rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
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bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
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bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
newline
bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
newline
bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
newline
bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
newline
bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
newline
bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
newline
bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2C1"
base ad:0x40087000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
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rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
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bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
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bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
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bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
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bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
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bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
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bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
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bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
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bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2C2"
base ad:0x40088000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
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rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
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bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
newline
bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
newline
bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
newline
bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
newline
bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
newline
bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
newline
bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
newline
bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
newline
bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
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bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
newline
bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2C3"
base ad:0x40089000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
newline
bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
newline
bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
newline
bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
newline
rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
newline
rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
newline
bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
newline
rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
newline
bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
newline
bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
newline
bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
newline
bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
newline
bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
newline
bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
newline
bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
newline
bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
newline
bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
newline
bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
newline
bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
newline
bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
newline
bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
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bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2C4"
base ad:0x4008A000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
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rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
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bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
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bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
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bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
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bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
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bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
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bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
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bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
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bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2C5"
base ad:0x40096000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
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rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
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bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
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bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
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bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
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bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
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bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
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bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
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bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
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bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2C6"
base ad:0x40097000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
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rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
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bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
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bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
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bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
newline
bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
newline
bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
newline
bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
newline
bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
newline
bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2C7"
base ad:0x40098000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
newline
bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
newline
bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
newline
bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
newline
bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
newline
rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
newline
rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
newline
bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
newline
rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
newline
bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
newline
bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
newline
bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
newline
bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
newline
bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
newline
bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
newline
bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
newline
bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
newline
bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
newline
bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
newline
bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
newline
bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
newline
bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
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bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2C8"
base ad:0x40099000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
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rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
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bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
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bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
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bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
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bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
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bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
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bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
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bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
newline
bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
newline
bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2C9"
base ad:0x4009A000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
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rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
newline
bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
newline
bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
newline
bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
newline
bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
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bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
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bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
newline
bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
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bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
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bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
newline
bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
newline
bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
endif
sif (cpuis("LPC54608*"))
tree "I2C0"
base ad:0x40086000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
newline
bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
newline
bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
newline
bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
newline
bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
newline
bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
newline
rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
newline
rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
newline
bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
newline
rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
newline
bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
newline
bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
newline
bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
newline
bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
newline
bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
newline
bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
newline
bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
newline
bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
newline
bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
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bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
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bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2C1"
base ad:0x40087000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
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rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
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bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
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bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
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bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
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bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
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bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
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bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
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bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
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bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2C2"
base ad:0x40088000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
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rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
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bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
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bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
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bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
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bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
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bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
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bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
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bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
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bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2C3"
base ad:0x40089000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
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rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
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bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
newline
bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
newline
bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
newline
bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
newline
bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
newline
bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
newline
bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
newline
bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
newline
bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
newline
bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2C4"
base ad:0x4008A000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
newline
bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
newline
rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
newline
rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
newline
bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
newline
rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
newline
bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
newline
bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
newline
bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
newline
bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
newline
bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
newline
bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
newline
bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
newline
bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
newline
bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
newline
bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
newline
bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
newline
bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
newline
bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
newline
bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
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bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2C5"
base ad:0x40096000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
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rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
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bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
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bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
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bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
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bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
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bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
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bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
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bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
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bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2C6"
base ad:0x40097000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
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rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
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bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
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bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
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bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
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bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
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bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
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bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
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bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
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bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2C7"
base ad:0x40098000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
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rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
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bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
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bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
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bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
newline
bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
newline
bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
newline
bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
newline
bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
newline
bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2C8"
base ad:0x40099000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
newline
bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
newline
bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
newline
bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
newline
bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
newline
bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
newline
rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
newline
rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
newline
bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
newline
rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
newline
bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
newline
bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
newline
bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
newline
bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
newline
bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
newline
bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
newline
bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
newline
bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
newline
bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
newline
bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
newline
bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
newline
bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
newline
bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
newline
bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
newline
bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
newline
bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
newline
bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2C9"
base ad:0x4009A000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
newline
bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
newline
bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
newline
bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
newline
rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
newline
bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
newline
rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
newline
bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
newline
bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
newline
bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
newline
bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
newline
bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
newline
bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
newline
bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
newline
bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
newline
bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
newline
bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
newline
bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
newline
bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
newline
bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
newline
bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
newline
bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
newline
bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
newline
bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
newline
bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
newline
hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
endif
sif (cpuis("LPC54616*"))
tree "I2C0"
base ad:0x40086000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
newline
bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
newline
bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
newline
bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
newline
bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
newline
bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
newline
rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
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rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
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bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
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bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
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bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
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bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
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bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
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bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
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bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
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bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2C1"
base ad:0x40087000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
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rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
newline
bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
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bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
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bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
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bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
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bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
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bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
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bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
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bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2C2"
base ad:0x40088000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
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rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
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bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
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bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
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bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
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bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
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bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
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bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
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bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
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bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2C3"
base ad:0x40089000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
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rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
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bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
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bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
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bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
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bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
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bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
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bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
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bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
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bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2C4"
base ad:0x4008A000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
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rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
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bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
newline
bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
newline
bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
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bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
newline
bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
newline
bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
newline
bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
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bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2C5"
base ad:0x40096000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
newline
bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
newline
bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
newline
rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
newline
rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
newline
bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
newline
rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
newline
bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
newline
bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
newline
bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
newline
bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
newline
bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
newline
bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
newline
bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
newline
bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
newline
bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
newline
bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
newline
bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
newline
bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
newline
bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
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bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2C6"
base ad:0x40097000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
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rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
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bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
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bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
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bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
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bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
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bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
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bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
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bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
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bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2C7"
base ad:0x40098000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
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rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
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bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
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bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
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bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
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bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
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bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
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bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
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bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
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bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2C8"
base ad:0x40099000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
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rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
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bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
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bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
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bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
newline
bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
newline
bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
newline
bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
newline
bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
newline
bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
newline
bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
newline
bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2C9"
base ad:0x4009A000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
newline
bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
newline
bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
newline
bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
newline
bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
newline
bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
newline
rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
newline
rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
newline
bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
newline
rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
newline
bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
newline
bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
newline
bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
newline
bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
newline
bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
newline
bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
newline
bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
newline
bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
newline
bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
newline
bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
newline
bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
newline
bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
newline
bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
newline
bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
newline
bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
newline
hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
endif
sif (cpuis("LPC54618*"))
tree "I2C0"
base ad:0x40086000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
newline
bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
newline
bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
newline
bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
newline
bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
newline
bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
newline
rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
newline
rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
newline
bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
newline
rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
newline
bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
newline
bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
newline
bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
newline
bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
newline
bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
newline
bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
newline
bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
newline
bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
newline
bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
newline
bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
newline
bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
newline
bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
newline
bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
newline
bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
newline
bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
newline
bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
newline
bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
newline
bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
newline
hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2C1"
base ad:0x40087000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
newline
bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
newline
bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
newline
bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
newline
bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
newline
bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
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rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
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bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
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bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
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bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
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bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
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bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
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bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
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bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
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bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2C2"
base ad:0x40088000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
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rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
newline
bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
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bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
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bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
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bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
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bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
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bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
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bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
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bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2C3"
base ad:0x40089000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
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rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
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bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
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bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
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bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
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bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
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bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
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bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
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bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
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bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2C4"
base ad:0x4008A000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
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rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
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bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
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bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
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bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
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bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
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bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
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bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
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bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
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bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2C5"
base ad:0x40096000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
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rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
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bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
newline
bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
newline
bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
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bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
newline
bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
newline
bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
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bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2C6"
base ad:0x40097000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
newline
bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
newline
rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
newline
rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
newline
bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
newline
rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
newline
bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
newline
bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
newline
bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
newline
bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
newline
bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
newline
bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
newline
bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
newline
bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
newline
bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
newline
bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
newline
bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
newline
bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
newline
bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
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bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2C7"
base ad:0x40098000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
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rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
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bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
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bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
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bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
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bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
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bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
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bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
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bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
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bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2C8"
base ad:0x40099000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
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rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
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bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
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bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
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bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
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bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
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bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
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bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
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bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
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bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2C9"
base ad:0x4009A000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
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rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
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bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
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bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
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bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
newline
bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
newline
bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
newline
bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
newline
bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
newline
bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
newline
bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
newline
bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
newline
bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
newline
bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
newline
bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
newline
bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
newline
bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
newline
bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
newline
hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
endif
sif (cpuis("LPC54628*"))
tree "I2C0"
base ad:0x40086000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
newline
bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
newline
bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
newline
bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
newline
bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
newline
bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
newline
rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
newline
rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
newline
bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
newline
rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
newline
bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
newline
bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
newline
bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
newline
bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
newline
bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
newline
bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
newline
bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
newline
bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
newline
bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
newline
bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
newline
bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
newline
bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
newline
bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
newline
bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
newline
bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
newline
bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
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bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2C1"
base ad:0x40087000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
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rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
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bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
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bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
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bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
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bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
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bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
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bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
newline
bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
newline
bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2C2"
base ad:0x40088000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
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rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
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bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
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bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
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bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
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bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
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bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
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bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
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bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
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bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2C3"
base ad:0x40089000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
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rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
newline
bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
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bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
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bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
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bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
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bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
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bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
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bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
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bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2C4"
base ad:0x4008A000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
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rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
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bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
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bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
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bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
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bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
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bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
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bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
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bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
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bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2C5"
base ad:0x40096000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
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rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
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bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
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bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
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bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
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bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
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bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
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bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
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bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
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bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2C6"
base ad:0x40097000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
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rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
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bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
newline
bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
newline
bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
newline
bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
newline
bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
newline
bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
newline
bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
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bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2C7"
base ad:0x40098000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
newline
bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
newline
rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
newline
rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
newline
bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
newline
rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
newline
bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
newline
bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
newline
bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
newline
bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
newline
bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
newline
bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
newline
bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
newline
bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
newline
bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
newline
bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
newline
bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
newline
bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
newline
bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
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bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2C8"
base ad:0x40099000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
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rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
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bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
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bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
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bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
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bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
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bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
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bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
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bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
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bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2C9"
base ad:0x4009A000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration for shared functions."
bitfld.long 0x0 5. "HSCAPABLE,High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter  as well as the timing for certain I2C signalling  enabling High-speed mode applies to all functions: Master  Slave  and Monitor." "0: Fast-mode plus. The I 2C interface will support..,1: High-speed. In addition to Standard-mode.."
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching." "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable. When disabled  the time-out function is internally reset." "0: Disabled. Time-out function is disabled.,1: Enabled. Time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable. When disabled  configurations settings for the Monitor function are not changed  but the Monitor function is internally reset." "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable. When disabled  configurations settings for the Slave function are not changed  but the Slave function is internally reset." "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable. When disabled  configurations settings for the Master function are not changed  but the Master function is internally reset." "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status register for Master. Slave. and Monitor functions."
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit." "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start  Stop  and clock edges. The flag is cleared by writing a 1 to this bit. No time-out.." "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when.." "0: Not idle. The I2C bus is not idle or this flag..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop." "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag." "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready. This flag is cleared when the MONRXDAT register is read." "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit." "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address  or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that.." "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers  and provides an identification of the.." "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in.." "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
newline
rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled.." "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (Slave..,2: Slave transmit. Data can be transmitted (Slave..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is.." "0: In progress. The Slave function does not..,1: Pending. The Slave function needs service."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE." "0: No Arbitration Loss has occurred.,1: Arbitration loss. The Master function has.."
newline
rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code. The master state code reflects the master state when the MSTPENDING bit is set  that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All.." "0: Idle. The Master function is available to be..,1: Receive ready. Received data available (Master..,2: Transmit ready. Data can be transmitted (Master..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending  the MSTSTATE bits indicate what type of software service if any the master expects. This flag will.." "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set and read register."
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable." "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable." "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
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bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable." "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable." "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
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bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable." "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable." "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable." "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable." "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable." "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable." "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
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bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable." "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register."
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear." "0,1"
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bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear." "0,1"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear." "0,1"
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bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear." "0,1"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear." "0,1"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear." "0,1"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented." "0,1"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out value register."
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks  as defined by the CLKDIV register. To change this value while I2C is in operation  disable all time-outs  write a new value to TIMEOUT  then re-enable.."
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value  bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks."
line.long 0x4 "CLKDIV,Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register. and controls some timing of the Slave function."
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3.."
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions."
bitfld.long 0x0 25. "SCLTIMEOUT,SCL time-out Interrupt flag." "0,1"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event time-out Interrupt flag." "0,1"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag." "0,1"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag." "0,1"
newline
bitfld.long 0x0 16. "MONRDY,Monitor Ready." "0,1"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag." "0,1"
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bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status." "0,1"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending." "0,1"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag." "0,1"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag." "0,1"
newline
bitfld.long 0x0 0. "MSTPENDING,Master Pending." "0,1"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master control register."
bitfld.long 0x0 3. "MSTDMA,Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start  address  Stop  and address match must always be done with software  typically via an interrupt. Address acknowledgement must also be.." "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control. This bit is write-only." "0: No effect.,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control. This bit is write-only." "0: No effect.,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue. This bit is write-only." "0: No effect.,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master timing configuration."
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus.." "0: 2 clocks. Minimum SCL high time is 2 clock of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clock of..,3: 5 clocks. Minimum SCL high time is 5 clock of..,4: 6 clocks. Minimum SCL high time is 6 clock of..,5: 7 clocks. Minimum SCL high time is 7 clock of..,6: 8 clocks. Minimum SCL high time is 8 clock of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C.." "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Combined Master receiver and transmitter data register."
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function."
group.long 0x840++0x7
line.long 0x0 "SLVCTL,Slave control register."
bitfld.long 0x0 9. "AUTOMATCHREAD,When AUTOACK is set  this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction  the direction needs to be specified." "0: The expected next operation in Automatic Mode is..,1: The expected next operation in Automatic Mode is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge.When this bit is set  it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit.." "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable." "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK." "0: No effect.,1: NACK. Causes the Slave function to NACK the.."
newline
bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue." "0: No effect.,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Combined Slave receiver and transmitter data register."
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x848)++0x3
line.long 0x0 "SLVADR[$1],Slave address register."
bitfld.long 0x0 15. "AUTONACK,Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD  allows software to ignore I2C traffic while handling previous I2C data or other operations." "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x0 1.--7. 1. "SLVADR,Slave Address. Seven bit slave address that is compared to received addresses if enabled."
newline
bitfld.long 0x0 0. "SADISABLE,Slave Address n Disable." "0: Enabled. Slave Address n is enabled.,1: Ignored Slave Address n is ignored."
repeat.end
group.long 0x858++0x3
line.long 0x0 "SLVQUAL0,Slave Qualification for address 0."
hexmask.long.byte 0x0 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is  assuming that it is enabled. If QUALMODE0 = 0  any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of.."
bitfld.long 0x0 0. "QUALMODE0,Qualify mode for slave address 0." "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor receiver data register."
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK." "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start." "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
newline
bitfld.long 0x0 8. "MONSTART,Monitor Received Start." "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
newline
hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
endif
tree.end
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54113*")||cpuis("LPC54114*")||cpuis("LPC54605*")||cpuis("LPC54606*")||cpuis("LPC54607*")||cpuis("LPC54608*")||cpuis("LPC54616*")||cpuis("LPC54618*")||cpuis("LPC54628*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
tree "I2S (Inter-Integrated Sound Bus Controller)"
base ad:0x0
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54113*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
tree "I2S0"
base ad:0x40097000
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
repeat 3. (list 0x0 0x1 0x2)(list ad:0x40097000 ad:0x40097020 ad:0x40097040)
tree "SECCHANNEL[$1]"
base $2
group.long ($2+0xC20)++0xB
line.long 0x0 "PCFG1,Configuration register 1 for channel pair"
bitfld.long 0x0 10. "ONECHANNEL,Single channel mode." "0,1"
bitfld.long 0x0 0. "PAIRENABLE,Enable for this channel pair.." "0,1"
line.long 0x4 "PCFG2,Configuration register 2 for channel pair"
hexmask.long.word 0x4 16.--24. 1. "POSITION,Data Position."
line.long 0x8 "PSTAT,Status register for channel pair"
rbitfld.long 0x8 3. "DATAPAUSED,Data Paused status flag." "0,1"
bitfld.long 0x8 2. "LR,Left/Right indication." "0,1"
bitfld.long 0x8 1. "SLVFRMERR,Save Frame Error flag." "0,1"
bitfld.long 0x8 0. "BUSY,Busy status for this channel pair." "0,1"
tree.end
repeat.end
base ad:0x40097000
rgroup.long 0x1DFC++0x3
line.long 0x0 "ID,I2S Module identification"
hexmask.long.word 0x0 16.--31. 1. "ID,Unique module identifier for this IP block."
hexmask.long.byte 0x0 12.--15. 1. "Major_Rev,Major revision of module implementation  starting at 0."
newline
hexmask.long.byte 0x0 8.--11. 1. "Minor_Rev,Minor revision of module implementation  starting at 0."
hexmask.long.byte 0x0 0.--7. 1. "Aperture,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
endif
group.long 0xC00++0xB
line.long 0x0 "CFG1,Configuration register 1 for the primary channel pair."
hexmask.long.byte 0x0 16.--20. 1. "DATALEN,Data Length  minus 1 encoded  defines the number of data bits to be transmitted or received for all I2S channel pairs in this Flexcomm. Note that data is only driven to or received from SDA for the number of bits defined by DATALEN. DATALEN is.."
bitfld.long 0x0 13. "WS_POL,WS polarity." "0: Data frames begin at a falling edge of WS..,1: WS is inverted resulting in a data frame.."
newline
bitfld.long 0x0 12. "SCK_POL,SCK polarity." "0: Data is launched on SCK falling edges and..,1: Data is launched on SCK rising edges and sampled.."
bitfld.long 0x0 11. "PDMDATA,PDM Data selection. This bit controls the data source for I2S transmit  and cannot be set in Rx mode. This bit only has an effect if the device the Flexcomm resides in includes a D-Mic subsystem. For the LPC5411x  this bit applies only to.." "0: Normal operation data is transferred to or from..,1: The data source is the D-Mic subsystem. When.."
newline
bitfld.long 0x0 10. "ONECHANNEL,Single channel mode. Applies to both transmit and receive. This configuration bit applies only to the first I2S channel pair. Other channel pairs may select this mode independently in their separate CFG1 registers." "0: I2S data for this channel pair is treated as..,1: I2S data for this channel pair is treated as a.."
bitfld.long 0x0 9. "LEFTJUST,Left Justify data." "0: Data is transferred between the FIFO and the I2S..,1: Data is transferred between the FIFO and the I2S.."
newline
bitfld.long 0x0 8. "RIGHTLOW,Right channel data is in the Low portion of FIFO data. Essentially  this swaps left and right channel data as it is transferred to or from the FIFO. This bit is not used if the data width is greater than 24 bits or if PDMDATA = 1. Note that if.." "0: The right channel is taken from the high part of..,1: The right channel is taken from the low part of.."
bitfld.long 0x0 6.--7. "MODE,Selects the basic I2S operating mode. Other configurations modify this to obtain all supported cases. See Formats and modes for examples." "0: I2S mode a.k.a. 'classic' mode. WS has a 50%..,1: DSP mode where WS has a 50% duty cycle. See..,2: DSP mode where WS has a one clock long pulse at..,3: DSP mode where WS has a one data slot long pulse.."
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bitfld.long 0x0 4.--5. "MSTSLVCFG,Master / slave configuration selection  determining how SCK and WS are used by all channel pairs in this Flexcomm." "0: Normal slave mode the default mode. SCK and WS..,1: WS synchronized master. WS is received from..,2: Master using an existing SCK. SCK is received..,3: Normal master mode. SCK and WS are generated so.."
bitfld.long 0x0 2.--3. "PAIRCOUNT,Provides the number of I2S channel pairs in this Flexcomm This is a read-only field whose value may be different in other Flexcomms. 00 = there is 1 I2S channel pair in this Flexcomm. 01 = there are 2 I2S channel pairs in this Flexcomm. 10 =.." "0: there is 1 I2S channel pair in this Flexcomm,1: there are 2 I2S channel pairs in this Flexcomm,2: 3 I2S channel pairs in this flexcomm,3: 4 I2S channel pairs in this flexcomm"
newline
bitfld.long 0x0 1. "DATAPAUSE,Data flow Pause. Allows pausing data flow between the I2S serializer/deserializer and the FIFO. This could be done in order to change streams  or while restarting after a data underflow or overflow. When paused  FIFO operations can be done.." "0: Normal operation or resuming normal operation at..,1: A pause in the data flow is being requested. It.."
bitfld.long 0x0 0. "MAINENABLE,Main enable for I 2S function in this Flexcomm" "0: All I 2S channel pairs in this Flexcomm are..,1: This I 2S channel pair is enabled. Other channel.."
line.long 0x4 "CFG2,Configuration register 2 for the primary channel pair."
hexmask.long.word 0x4 16.--24. 1. "POSITION,Data Position. Defines the location within the frame of the data for this channel pair. POSITION + DATALEN must be less than FRAMELEN. See Frame format. When MODE = 0  POSITION defines the location of data in both the left phase and right phase .."
hexmask.long.word 0x4 0.--8. 1. "FRAMELEN,Frame Length  minus 1 encoded  defines the number of clocks and data bits in the frames that this channel pair participates in. See Frame format. 0x000 to 0x002 = not supported 0x003 = frame is 4 bits in total length 0x004 = frame is 5 bits in.."
line.long 0x8 "STAT,Status register for the primary channel pair."
rbitfld.long 0x8 3. "DATAPAUSED,Data Paused status flag. Applies to all I2S channels" "0: Data is not currently paused. A data pause may..,1: A data pause has been requested and is now in.."
rbitfld.long 0x8 2. "LR,Left/Right indication. This flag is considered to be a debugging aid and is not expected to be used by an I2S driver. Valid when one channel pair is busy. Indicates left or right data being processed for the currently busy channel pair." "0: Left channel.,1: Right channel."
newline
bitfld.long 0x8 1. "SLVFRMERR,Slave Frame Error flag. This applies when at least one channel pair is operating as a slave. An error indicates that the incoming WS signal did not transition as expected due to a mismatch between FRAMELEN and the actual incoming I2S stream." "0: No error has been recorded.,1: An error has been recorded for some channel pair.."
rbitfld.long 0x8 0. "BUSY,Busy status for the primary channel pair. Other BUSY flags may be found in the STAT register for each channel pair." "0: The transmitter/receiver for channel pair is..,1: The transmitter/receiver for channel pair is.."
group.long 0xC1C++0x3
line.long 0x0 "DIV,Clock divider. used by all channel pairs."
hexmask.long.word 0x0 0.--11. 1. "DIV,This field controls how this I2S block uses the Flexcomm function clock. 0x000 = The Flexcomm function clock is used directly. 0x001 = The Flexcomm function clock is divided by 2. 0x002 = The Flexcomm function clock is divided by 3. 0xFFF = The.."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
sif (cpuis("LPC54113*"))
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
endif
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
newline
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
newline
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
newline
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
newline
bitfld.long 0x0 3. "PACK48,Packing format for 48-bit data. This relates to how data is entered into or taken from the FIFO by software or DMA." "0: 48-bit I2S FIFO entries are handled as all..,1: 48-bit I2S FIFO entries are handled as.."
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x0 2. "TXI2SE0,Transmit I2S empty 0. Determines the value sent by the I2S in transmit mode if the TX FIFO becomes empty. This value is sent repeatedly until the I2S is paused  the error is cleared  new data is provided  and the I2S is un-paused." "0: If the TX FIFO becomes empty the last value is..,1: If the TX FIFO becomes empty 0 is sent. Use if.."
newline
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x0 2. "TXI2SSE0,Transmit I2S empty 0. Determines the value sent by the I2S in transmit mode if the TX FIFO becomes empty. This value is sent repeatedly until the I2S is paused  the error is cleared  new data is provided  and the I2S is un-paused." "0: If the TX FIFO becomes empty the last value is..,1: If the TX FIFO becomes empty 0 is sent. Use if.."
endif
newline
bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
newline
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
newline
rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
newline
rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
newline
rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
newline
bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
newline
bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
newline
bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
newline
bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
newline
bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
newline
bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
wgroup.long 0xE20++0x7
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long 0x0 0.--31. 1. "TXDATA,Transmit data to the FIFO. The number of bits used depends on configuration details."
line.long 0x4 "FIFOWR48H,FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA."
hexmask.long.tbyte 0x4 0.--23. 1. "TXDATA,Transmit data to the FIFO. Whether this register is used and the number of bits used depends on configuration details."
rgroup.long 0xE30++0x7
line.long 0x0 "FIFORD,FIFO read data."
hexmask.long 0x0 0.--31. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on configuration details."
line.long 0x4 "FIFORD48H,FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA."
hexmask.long.tbyte 0x4 0.--23. 1. "RXDATA,Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details."
rgroup.long 0xE40++0x7
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
hexmask.long 0x0 0.--31. 1. "RXDATA,Received data from the FIFO."
line.long 0x4 "FIFORD48HNOPOP,FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA."
hexmask.long.tbyte 0x4 0.--23. 1. "RXDATA,Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details."
tree.end
endif
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54113*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
tree "I2S1"
base ad:0x40098000
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
repeat 3. (list 0x0 0x1 0x2)(list ad:0x40098000 ad:0x40098020 ad:0x40098040)
tree "SECCHANNEL[$1]"
base $2
group.long ($2+0xC20)++0xB
line.long 0x0 "PCFG1,Configuration register 1 for channel pair"
bitfld.long 0x0 10. "ONECHANNEL,Single channel mode." "0,1"
bitfld.long 0x0 0. "PAIRENABLE,Enable for this channel pair.." "0,1"
line.long 0x4 "PCFG2,Configuration register 2 for channel pair"
hexmask.long.word 0x4 16.--24. 1. "POSITION,Data Position."
line.long 0x8 "PSTAT,Status register for channel pair"
rbitfld.long 0x8 3. "DATAPAUSED,Data Paused status flag." "0,1"
bitfld.long 0x8 2. "LR,Left/Right indication." "0,1"
bitfld.long 0x8 1. "SLVFRMERR,Save Frame Error flag." "0,1"
bitfld.long 0x8 0. "BUSY,Busy status for this channel pair." "0,1"
tree.end
repeat.end
base ad:0x40098000
rgroup.long 0x1DFC++0x3
line.long 0x0 "ID,I2S Module identification"
hexmask.long.word 0x0 16.--31. 1. "ID,Unique module identifier for this IP block."
hexmask.long.byte 0x0 12.--15. 1. "Major_Rev,Major revision of module implementation  starting at 0."
newline
hexmask.long.byte 0x0 8.--11. 1. "Minor_Rev,Minor revision of module implementation  starting at 0."
hexmask.long.byte 0x0 0.--7. 1. "Aperture,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
endif
group.long 0xC00++0xB
line.long 0x0 "CFG1,Configuration register 1 for the primary channel pair."
hexmask.long.byte 0x0 16.--20. 1. "DATALEN,Data Length  minus 1 encoded  defines the number of data bits to be transmitted or received for all I2S channel pairs in this Flexcomm. Note that data is only driven to or received from SDA for the number of bits defined by DATALEN. DATALEN is.."
bitfld.long 0x0 13. "WS_POL,WS polarity." "0: Data frames begin at a falling edge of WS..,1: WS is inverted resulting in a data frame.."
newline
bitfld.long 0x0 12. "SCK_POL,SCK polarity." "0: Data is launched on SCK falling edges and..,1: Data is launched on SCK rising edges and sampled.."
bitfld.long 0x0 11. "PDMDATA,PDM Data selection. This bit controls the data source for I2S transmit  and cannot be set in Rx mode. This bit only has an effect if the device the Flexcomm resides in includes a D-Mic subsystem. For the LPC5411x  this bit applies only to.." "0: Normal operation data is transferred to or from..,1: The data source is the D-Mic subsystem. When.."
newline
bitfld.long 0x0 10. "ONECHANNEL,Single channel mode. Applies to both transmit and receive. This configuration bit applies only to the first I2S channel pair. Other channel pairs may select this mode independently in their separate CFG1 registers." "0: I2S data for this channel pair is treated as..,1: I2S data for this channel pair is treated as a.."
bitfld.long 0x0 9. "LEFTJUST,Left Justify data." "0: Data is transferred between the FIFO and the I2S..,1: Data is transferred between the FIFO and the I2S.."
newline
bitfld.long 0x0 8. "RIGHTLOW,Right channel data is in the Low portion of FIFO data. Essentially  this swaps left and right channel data as it is transferred to or from the FIFO. This bit is not used if the data width is greater than 24 bits or if PDMDATA = 1. Note that if.." "0: The right channel is taken from the high part of..,1: The right channel is taken from the low part of.."
bitfld.long 0x0 6.--7. "MODE,Selects the basic I2S operating mode. Other configurations modify this to obtain all supported cases. See Formats and modes for examples." "0: I2S mode a.k.a. 'classic' mode. WS has a 50%..,1: DSP mode where WS has a 50% duty cycle. See..,2: DSP mode where WS has a one clock long pulse at..,3: DSP mode where WS has a one data slot long pulse.."
newline
bitfld.long 0x0 4.--5. "MSTSLVCFG,Master / slave configuration selection  determining how SCK and WS are used by all channel pairs in this Flexcomm." "0: Normal slave mode the default mode. SCK and WS..,1: WS synchronized master. WS is received from..,2: Master using an existing SCK. SCK is received..,3: Normal master mode. SCK and WS are generated so.."
bitfld.long 0x0 2.--3. "PAIRCOUNT,Provides the number of I2S channel pairs in this Flexcomm This is a read-only field whose value may be different in other Flexcomms. 00 = there is 1 I2S channel pair in this Flexcomm. 01 = there are 2 I2S channel pairs in this Flexcomm. 10 =.." "0: there is 1 I2S channel pair in this Flexcomm,1: there are 2 I2S channel pairs in this Flexcomm,2: 3 I2S channel pairs in this flexcomm,3: 4 I2S channel pairs in this flexcomm"
newline
bitfld.long 0x0 1. "DATAPAUSE,Data flow Pause. Allows pausing data flow between the I2S serializer/deserializer and the FIFO. This could be done in order to change streams  or while restarting after a data underflow or overflow. When paused  FIFO operations can be done.." "0: Normal operation or resuming normal operation at..,1: A pause in the data flow is being requested. It.."
bitfld.long 0x0 0. "MAINENABLE,Main enable for I 2S function in this Flexcomm" "0: All I 2S channel pairs in this Flexcomm are..,1: This I 2S channel pair is enabled. Other channel.."
line.long 0x4 "CFG2,Configuration register 2 for the primary channel pair."
hexmask.long.word 0x4 16.--24. 1. "POSITION,Data Position. Defines the location within the frame of the data for this channel pair. POSITION + DATALEN must be less than FRAMELEN. See Frame format. When MODE = 0  POSITION defines the location of data in both the left phase and right phase .."
hexmask.long.word 0x4 0.--8. 1. "FRAMELEN,Frame Length  minus 1 encoded  defines the number of clocks and data bits in the frames that this channel pair participates in. See Frame format. 0x000 to 0x002 = not supported 0x003 = frame is 4 bits in total length 0x004 = frame is 5 bits in.."
line.long 0x8 "STAT,Status register for the primary channel pair."
rbitfld.long 0x8 3. "DATAPAUSED,Data Paused status flag. Applies to all I2S channels" "0: Data is not currently paused. A data pause may..,1: A data pause has been requested and is now in.."
rbitfld.long 0x8 2. "LR,Left/Right indication. This flag is considered to be a debugging aid and is not expected to be used by an I2S driver. Valid when one channel pair is busy. Indicates left or right data being processed for the currently busy channel pair." "0: Left channel.,1: Right channel."
newline
bitfld.long 0x8 1. "SLVFRMERR,Slave Frame Error flag. This applies when at least one channel pair is operating as a slave. An error indicates that the incoming WS signal did not transition as expected due to a mismatch between FRAMELEN and the actual incoming I2S stream." "0: No error has been recorded.,1: An error has been recorded for some channel pair.."
rbitfld.long 0x8 0. "BUSY,Busy status for the primary channel pair. Other BUSY flags may be found in the STAT register for each channel pair." "0: The transmitter/receiver for channel pair is..,1: The transmitter/receiver for channel pair is.."
group.long 0xC1C++0x3
line.long 0x0 "DIV,Clock divider. used by all channel pairs."
hexmask.long.word 0x0 0.--11. 1. "DIV,This field controls how this I2S block uses the Flexcomm function clock. 0x000 = The Flexcomm function clock is used directly. 0x001 = The Flexcomm function clock is divided by 2. 0x002 = The Flexcomm function clock is divided by 3. 0xFFF = The.."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
sif (cpuis("LPC54113*"))
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
endif
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
newline
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
newline
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
newline
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
newline
bitfld.long 0x0 3. "PACK48,Packing format for 48-bit data. This relates to how data is entered into or taken from the FIFO by software or DMA." "0: 48-bit I2S FIFO entries are handled as all..,1: 48-bit I2S FIFO entries are handled as.."
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x0 2. "TXI2SE0,Transmit I2S empty 0. Determines the value sent by the I2S in transmit mode if the TX FIFO becomes empty. This value is sent repeatedly until the I2S is paused  the error is cleared  new data is provided  and the I2S is un-paused." "0: If the TX FIFO becomes empty the last value is..,1: If the TX FIFO becomes empty 0 is sent. Use if.."
newline
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x0 2. "TXI2SSE0,Transmit I2S empty 0. Determines the value sent by the I2S in transmit mode if the TX FIFO becomes empty. This value is sent repeatedly until the I2S is paused  the error is cleared  new data is provided  and the I2S is un-paused." "0: If the TX FIFO becomes empty the last value is..,1: If the TX FIFO becomes empty 0 is sent. Use if.."
endif
newline
bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
newline
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
newline
rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
newline
rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
newline
rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
newline
bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
newline
bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
newline
bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
newline
bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
newline
bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
wgroup.long 0xE20++0x7
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long 0x0 0.--31. 1. "TXDATA,Transmit data to the FIFO. The number of bits used depends on configuration details."
line.long 0x4 "FIFOWR48H,FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA."
hexmask.long.tbyte 0x4 0.--23. 1. "TXDATA,Transmit data to the FIFO. Whether this register is used and the number of bits used depends on configuration details."
rgroup.long 0xE30++0x7
line.long 0x0 "FIFORD,FIFO read data."
hexmask.long 0x0 0.--31. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on configuration details."
line.long 0x4 "FIFORD48H,FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA."
hexmask.long.tbyte 0x4 0.--23. 1. "RXDATA,Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details."
rgroup.long 0xE40++0x7
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
hexmask.long 0x0 0.--31. 1. "RXDATA,Received data from the FIFO."
line.long 0x4 "FIFORD48HNOPOP,FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA."
hexmask.long.tbyte 0x4 0.--23. 1. "RXDATA,Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details."
tree.end
endif
sif (cpuis("LPC54114*"))
tree "I2S0"
base ad:0x40097000
group.long 0xC00++0xB
line.long 0x0 "CFG1,Configuration register 1 for the primary channel pair."
hexmask.long.byte 0x0 16.--20. 1. "DATALEN,Data Length  minus 1 encoded  defines the number of data bits to be transmitted or received for all I2S channel pairs in this Flexcomm. Note that data is only driven to or received from SDA for the number of bits defined by DATALEN. DATALEN is.."
bitfld.long 0x0 13. "WS_POL,WS polarity." "0: Data frames begin at a falling edge of WS..,1: WS is inverted resulting in a data frame.."
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bitfld.long 0x0 12. "SCK_POL,SCK polarity." "0: Data is launched on SCK falling edges and..,1: Data is launched on SCK rising edges and sampled.."
bitfld.long 0x0 11. "PDMDATA,PDM Data selection. This bit controls the data source for I2S transmit  and cannot be set in Rx mode. This bit only has an effect if the device the Flexcomm resides in includes a D-Mic subsystem. For the LPC5411x  this bit applies only to.." "0: Normal operation data is transferred to or from..,1: The data source is the D-Mic subsystem. When.."
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bitfld.long 0x0 10. "ONECHANNEL,Single channel mode. Applies to both transmit and receive. This configuration bit applies only to the first I2S channel pair. Other channel pairs may select this mode independently in their separate CFG1 registers." "0: I2S data for this channel pair is treated as..,1: I2S data for this channel pair is treated as a.."
bitfld.long 0x0 9. "LEFTJUST,Left Justify data." "0: Data is transferred between the FIFO and the I2S..,1: Data is transferred between the FIFO and the I2S.."
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bitfld.long 0x0 8. "RIGHTLOW,Right channel data is in the Low portion of FIFO data. Essentially  this swaps left and right channel data as it is transferred to or from the FIFO. This bit is not used if the data width is greater than 24 bits or if PDMDATA = 1. Note that if.." "0: The right channel is taken from the high part of..,1: The right channel is taken from the low part of.."
bitfld.long 0x0 6.--7. "MODE,Selects the basic I2S operating mode. Other configurations modify this to obtain all supported cases. See Formats and modes for examples." "0: I2S mode a.k.a. 'classic' mode. WS has a 50%..,1: DSP mode where WS has a 50% duty cycle. See..,2: DSP mode where WS has a one clock long pulse at..,3: DSP mode where WS has a one data slot long pulse.."
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bitfld.long 0x0 4.--5. "MSTSLVCFG,Master / slave configuration selection  determining how SCK and WS are used by all channel pairs in this Flexcomm." "0: Normal slave mode the default mode. SCK and WS..,1: WS synchronized master. WS is received from..,2: Master using an existing SCK. SCK is received..,3: Normal master mode. SCK and WS are generated so.."
bitfld.long 0x0 2.--3. "PAIRCOUNT,Provides the number of I2S channel pairs in this Flexcomm This is a read-only field whose value may be different in other Flexcomms. 00 = there is 1 I2S channel pair in this Flexcomm. 01 = there are 2 I2S channel pairs in this Flexcomm. 10 =.." "0: there is 1 I2S channel pair in this Flexcomm,1: there are 2 I2S channel pairs in this Flexcomm,2: 3 I2S channel pairs in this flexcomm,3: 4 I2S channel pairs in this flexcomm"
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bitfld.long 0x0 1. "DATAPAUSE,Data flow Pause. Allows pausing data flow between the I2S serializer/deserializer and the FIFO. This could be done in order to change streams  or while restarting after a data underflow or overflow. When paused  FIFO operations can be done.." "0: Normal operation or resuming normal operation at..,1: A pause in the data flow is being requested. It.."
bitfld.long 0x0 0. "MAINENABLE,Main enable for I 2S function in this Flexcomm" "0: All I 2S channel pairs in this Flexcomm are..,1: This I 2S channel pair is enabled. Other channel.."
line.long 0x4 "CFG2,Configuration register 2 for the primary channel pair."
hexmask.long.word 0x4 16.--24. 1. "POSITION,Data Position. Defines the location within the frame of the data for this channel pair. POSITION + DATALEN must be less than FRAMELEN. See Frame format. When MODE = 0  POSITION defines the location of data in both the left phase and right phase .."
hexmask.long.word 0x4 0.--8. 1. "FRAMELEN,Frame Length  minus 1 encoded  defines the number of clocks and data bits in the frames that this channel pair participates in. See Frame format. 0x000 to 0x002 = not supported 0x003 = frame is 4 bits in total length 0x004 = frame is 5 bits in.."
line.long 0x8 "STAT,Status register for the primary channel pair."
rbitfld.long 0x8 3. "DATAPAUSED,Data Paused status flag. Applies to all I2S channels" "0: Data is not currently paused. A data pause may..,1: A data pause has been requested and is now in.."
rbitfld.long 0x8 2. "LR,Left/Right indication. This flag is considered to be a debugging aid and is not expected to be used by an I2S driver. Valid when one channel pair is busy. Indicates left or right data being processed for the currently busy channel pair." "0: Left channel.,1: Right channel."
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bitfld.long 0x8 1. "SLVFRMERR,Slave Frame Error flag. This applies when at least one channel pair is operating as a slave. An error indicates that the incoming WS signal did not transition as expected due to a mismatch between FRAMELEN and the actual incoming I2S stream." "0: No error has been recorded.,1: An error has been recorded for some channel pair.."
rbitfld.long 0x8 0. "BUSY,Busy status for the primary channel pair. Other BUSY flags may be found in the STAT register for each channel pair." "0: The transmitter/receiver for channel pair is..,1: The transmitter/receiver for channel pair is.."
group.long 0xC1C++0x3
line.long 0x0 "DIV,Clock divider. used by all channel pairs."
hexmask.long.word 0x0 0.--11. 1. "DIV,This field controls how this I2S block uses the Flexcomm function clock. 0x000 = The Flexcomm function clock is used directly. 0x001 = The Flexcomm function clock is divided by 2. 0x002 = The Flexcomm function clock is divided by 3. 0xFFF = The.."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
newline
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 3. "PACK48,Packing format for 48-bit data. This relates to how data is entered into or taken from the FIFO by software or DMA." "0: 48-bit I2S FIFO entries are handled as all..,1: 48-bit I2S FIFO entries are handled as.."
bitfld.long 0x0 2. "TXI2SSE0,Transmit I2S empty 0. Determines the value sent by the I2S in transmit mode if the TX FIFO becomes empty. This value is sent repeatedly until the I2S is paused  the error is cleared  new data is provided  and the I2S is un-paused." "0: If the TX FIFO becomes empty the last value is..,1: If the TX FIFO becomes empty 0 is sent. Use if.."
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
wgroup.long 0xE20++0x7
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long 0x0 0.--31. 1. "TXDATA,Transmit data to the FIFO. The number of bits used depends on configuration details."
line.long 0x4 "FIFOWR48H,FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA."
hexmask.long.tbyte 0x4 0.--23. 1. "TXDATA,Transmit data to the FIFO. Whether this register is used and the number of bits used depends on configuration details."
rgroup.long 0xE30++0x7
line.long 0x0 "FIFORD,FIFO read data."
hexmask.long 0x0 0.--31. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on configuration details."
line.long 0x4 "FIFORD48H,FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA."
hexmask.long.tbyte 0x4 0.--23. 1. "RXDATA,Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details."
rgroup.long 0xE40++0x7
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
hexmask.long 0x0 0.--31. 1. "RXDATA,Received data from the FIFO."
line.long 0x4 "FIFORD48HNOPOP,FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA."
hexmask.long.tbyte 0x4 0.--23. 1. "RXDATA,Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details."
tree.end
tree "I2S1"
base ad:0x40098000
group.long 0xC00++0xB
line.long 0x0 "CFG1,Configuration register 1 for the primary channel pair."
hexmask.long.byte 0x0 16.--20. 1. "DATALEN,Data Length  minus 1 encoded  defines the number of data bits to be transmitted or received for all I2S channel pairs in this Flexcomm. Note that data is only driven to or received from SDA for the number of bits defined by DATALEN. DATALEN is.."
bitfld.long 0x0 13. "WS_POL,WS polarity." "0: Data frames begin at a falling edge of WS..,1: WS is inverted resulting in a data frame.."
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bitfld.long 0x0 12. "SCK_POL,SCK polarity." "0: Data is launched on SCK falling edges and..,1: Data is launched on SCK rising edges and sampled.."
bitfld.long 0x0 11. "PDMDATA,PDM Data selection. This bit controls the data source for I2S transmit  and cannot be set in Rx mode. This bit only has an effect if the device the Flexcomm resides in includes a D-Mic subsystem. For the LPC5411x  this bit applies only to.." "0: Normal operation data is transferred to or from..,1: The data source is the D-Mic subsystem. When.."
newline
bitfld.long 0x0 10. "ONECHANNEL,Single channel mode. Applies to both transmit and receive. This configuration bit applies only to the first I2S channel pair. Other channel pairs may select this mode independently in their separate CFG1 registers." "0: I2S data for this channel pair is treated as..,1: I2S data for this channel pair is treated as a.."
bitfld.long 0x0 9. "LEFTJUST,Left Justify data." "0: Data is transferred between the FIFO and the I2S..,1: Data is transferred between the FIFO and the I2S.."
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bitfld.long 0x0 8. "RIGHTLOW,Right channel data is in the Low portion of FIFO data. Essentially  this swaps left and right channel data as it is transferred to or from the FIFO. This bit is not used if the data width is greater than 24 bits or if PDMDATA = 1. Note that if.." "0: The right channel is taken from the high part of..,1: The right channel is taken from the low part of.."
bitfld.long 0x0 6.--7. "MODE,Selects the basic I2S operating mode. Other configurations modify this to obtain all supported cases. See Formats and modes for examples." "0: I2S mode a.k.a. 'classic' mode. WS has a 50%..,1: DSP mode where WS has a 50% duty cycle. See..,2: DSP mode where WS has a one clock long pulse at..,3: DSP mode where WS has a one data slot long pulse.."
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bitfld.long 0x0 4.--5. "MSTSLVCFG,Master / slave configuration selection  determining how SCK and WS are used by all channel pairs in this Flexcomm." "0: Normal slave mode the default mode. SCK and WS..,1: WS synchronized master. WS is received from..,2: Master using an existing SCK. SCK is received..,3: Normal master mode. SCK and WS are generated so.."
bitfld.long 0x0 2.--3. "PAIRCOUNT,Provides the number of I2S channel pairs in this Flexcomm This is a read-only field whose value may be different in other Flexcomms. 00 = there is 1 I2S channel pair in this Flexcomm. 01 = there are 2 I2S channel pairs in this Flexcomm. 10 =.." "0: there is 1 I2S channel pair in this Flexcomm,1: there are 2 I2S channel pairs in this Flexcomm,2: 3 I2S channel pairs in this flexcomm,3: 4 I2S channel pairs in this flexcomm"
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bitfld.long 0x0 1. "DATAPAUSE,Data flow Pause. Allows pausing data flow between the I2S serializer/deserializer and the FIFO. This could be done in order to change streams  or while restarting after a data underflow or overflow. When paused  FIFO operations can be done.." "0: Normal operation or resuming normal operation at..,1: A pause in the data flow is being requested. It.."
bitfld.long 0x0 0. "MAINENABLE,Main enable for I 2S function in this Flexcomm" "0: All I 2S channel pairs in this Flexcomm are..,1: This I 2S channel pair is enabled. Other channel.."
line.long 0x4 "CFG2,Configuration register 2 for the primary channel pair."
hexmask.long.word 0x4 16.--24. 1. "POSITION,Data Position. Defines the location within the frame of the data for this channel pair. POSITION + DATALEN must be less than FRAMELEN. See Frame format. When MODE = 0  POSITION defines the location of data in both the left phase and right phase .."
hexmask.long.word 0x4 0.--8. 1. "FRAMELEN,Frame Length  minus 1 encoded  defines the number of clocks and data bits in the frames that this channel pair participates in. See Frame format. 0x000 to 0x002 = not supported 0x003 = frame is 4 bits in total length 0x004 = frame is 5 bits in.."
line.long 0x8 "STAT,Status register for the primary channel pair."
rbitfld.long 0x8 3. "DATAPAUSED,Data Paused status flag. Applies to all I2S channels" "0: Data is not currently paused. A data pause may..,1: A data pause has been requested and is now in.."
rbitfld.long 0x8 2. "LR,Left/Right indication. This flag is considered to be a debugging aid and is not expected to be used by an I2S driver. Valid when one channel pair is busy. Indicates left or right data being processed for the currently busy channel pair." "0: Left channel.,1: Right channel."
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bitfld.long 0x8 1. "SLVFRMERR,Slave Frame Error flag. This applies when at least one channel pair is operating as a slave. An error indicates that the incoming WS signal did not transition as expected due to a mismatch between FRAMELEN and the actual incoming I2S stream." "0: No error has been recorded.,1: An error has been recorded for some channel pair.."
rbitfld.long 0x8 0. "BUSY,Busy status for the primary channel pair. Other BUSY flags may be found in the STAT register for each channel pair." "0: The transmitter/receiver for channel pair is..,1: The transmitter/receiver for channel pair is.."
group.long 0xC1C++0x3
line.long 0x0 "DIV,Clock divider. used by all channel pairs."
hexmask.long.word 0x0 0.--11. 1. "DIV,This field controls how this I2S block uses the Flexcomm function clock. 0x000 = The Flexcomm function clock is used directly. 0x001 = The Flexcomm function clock is divided by 2. 0x002 = The Flexcomm function clock is divided by 3. 0xFFF = The.."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
newline
bitfld.long 0x0 3. "PACK48,Packing format for 48-bit data. This relates to how data is entered into or taken from the FIFO by software or DMA." "0: 48-bit I2S FIFO entries are handled as all..,1: 48-bit I2S FIFO entries are handled as.."
bitfld.long 0x0 2. "TXI2SSE0,Transmit I2S empty 0. Determines the value sent by the I2S in transmit mode if the TX FIFO becomes empty. This value is sent repeatedly until the I2S is paused  the error is cleared  new data is provided  and the I2S is un-paused." "0: If the TX FIFO becomes empty the last value is..,1: If the TX FIFO becomes empty 0 is sent. Use if.."
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
newline
rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
newline
rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
newline
rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
newline
bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
newline
bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
newline
bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
newline
bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
newline
bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
newline
bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
wgroup.long 0xE20++0x7
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long 0x0 0.--31. 1. "TXDATA,Transmit data to the FIFO. The number of bits used depends on configuration details."
line.long 0x4 "FIFOWR48H,FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA."
hexmask.long.tbyte 0x4 0.--23. 1. "TXDATA,Transmit data to the FIFO. Whether this register is used and the number of bits used depends on configuration details."
rgroup.long 0xE30++0x7
line.long 0x0 "FIFORD,FIFO read data."
hexmask.long 0x0 0.--31. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on configuration details."
line.long 0x4 "FIFORD48H,FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA."
hexmask.long.tbyte 0x4 0.--23. 1. "RXDATA,Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details."
rgroup.long 0xE40++0x7
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
hexmask.long 0x0 0.--31. 1. "RXDATA,Received data from the FIFO."
line.long 0x4 "FIFORD48HNOPOP,FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA."
hexmask.long.tbyte 0x4 0.--23. 1. "RXDATA,Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details."
tree.end
endif
sif (cpuis("LPC54605*"))
tree "I2S0"
base ad:0x40097000
repeat 3. (list 0x0 0x1 0x2)(list ad:0x40097000 ad:0x40097020 ad:0x40097040)
tree "SECCHANNEL[$1]"
base $2
group.long ($2+0xC20)++0xB
line.long 0x0 "PCFG1,Configuration register 1 for channel pair"
bitfld.long 0x0 10. "ONECHANNEL,Single channel mode." "0,1"
bitfld.long 0x0 0. "PAIRENABLE,Enable for this channel pair.." "0,1"
line.long 0x4 "PCFG2,Configuration register 2 for channel pair"
hexmask.long.word 0x4 16.--24. 1. "POSITION,Data Position."
line.long 0x8 "PSTAT,Status register for channel pair"
rbitfld.long 0x8 3. "DATAPAUSED,Data Paused status flag." "0,1"
bitfld.long 0x8 2. "LR,Left/Right indication." "0,1"
bitfld.long 0x8 1. "SLVFRMERR,Save Frame Error flag." "0,1"
bitfld.long 0x8 0. "BUSY,Busy status for this channel pair." "0,1"
tree.end
repeat.end
base ad:0x40097000
group.long 0xC00++0xB
line.long 0x0 "CFG1,Configuration register 1 for the primary channel pair."
hexmask.long.byte 0x0 16.--20. 1. "DATALEN,Data Length  minus 1 encoded  defines the number of data bits to be transmitted or received for all I2S channel pairs in this Flexcomm. Note that data is only driven to or received from SDA for the number of bits defined by DATALEN. DATALEN is.."
bitfld.long 0x0 13. "WS_POL,WS polarity." "0: Data frames begin at a falling edge of WS..,1: WS is inverted resulting in a data frame.."
newline
bitfld.long 0x0 12. "SCK_POL,SCK polarity." "0: Data is launched on SCK falling edges and..,1: Data is launched on SCK rising edges and sampled.."
bitfld.long 0x0 11. "PDMDATA,PDM Data selection. This bit controls the data source for I2S transmit  and cannot be set in Rx mode. This bit only has an effect if the device the Flexcomm resides in includes a D-Mic subsystem. For the LPC5411x  this bit applies only to.." "0: Normal operation data is transferred to or from..,1: The data source is the D-Mic subsystem. When.."
newline
bitfld.long 0x0 10. "ONECHANNEL,Single channel mode. Applies to both transmit and receive. This configuration bit applies only to the first I2S channel pair. Other channel pairs may select this mode independently in their separate CFG1 registers." "0: I2S data for this channel pair is treated as..,1: I2S data for this channel pair is treated as a.."
bitfld.long 0x0 9. "LEFTJUST,Left Justify data." "0: Data is transferred between the FIFO and the I2S..,1: Data is transferred between the FIFO and the I2S.."
newline
bitfld.long 0x0 8. "RIGHTLOW,Right channel data is in the Low portion of FIFO data. Essentially  this swaps left and right channel data as it is transferred to or from the FIFO. This bit is not used if the data width is greater than 24 bits or if PDMDATA = 1. Note that if.." "0: The right channel is taken from the high part of..,1: The right channel is taken from the low part of.."
bitfld.long 0x0 6.--7. "MODE,Selects the basic I2S operating mode. Other configurations modify this to obtain all supported cases. See Formats and modes for examples." "0: I2S mode a.k.a. 'classic' mode. WS has a 50%..,1: DSP mode where WS has a 50% duty cycle. See..,2: DSP mode where WS has a one clock long pulse at..,3: DSP mode where WS has a one data slot long pulse.."
newline
bitfld.long 0x0 4.--5. "MSTSLVCFG,Master / slave configuration selection  determining how SCK and WS are used by all channel pairs in this Flexcomm." "0: Normal slave mode the default mode. SCK and WS..,1: WS synchronized master. WS is received from..,2: Master using an existing SCK. SCK is received..,3: Normal master mode. SCK and WS are generated so.."
bitfld.long 0x0 2.--3. "PAIRCOUNT,Provides the number of I2S channel pairs in this Flexcomm This is a read-only field whose value may be different in other Flexcomms. 00 = there is 1 I2S channel pair in this Flexcomm. 01 = there are 2 I2S channel pairs in this Flexcomm. 10 =.." "0: there is 1 I2S channel pair in this Flexcomm,1: there are 2 I2S channel pairs in this Flexcomm,2: 3 I2S channel pairs in this flexcomm,3: 4 I2S channel pairs in this flexcomm"
newline
bitfld.long 0x0 1. "DATAPAUSE,Data flow Pause. Allows pausing data flow between the I2S serializer/deserializer and the FIFO. This could be done in order to change streams  or while restarting after a data underflow or overflow. When paused  FIFO operations can be done.." "0: Normal operation or resuming normal operation at..,1: A pause in the data flow is being requested. It.."
bitfld.long 0x0 0. "MAINENABLE,Main enable for I 2S function in this Flexcomm" "0: All I 2S channel pairs in this Flexcomm are..,1: This I 2S channel pair is enabled. Other channel.."
line.long 0x4 "CFG2,Configuration register 2 for the primary channel pair."
hexmask.long.word 0x4 16.--24. 1. "POSITION,Data Position. Defines the location within the frame of the data for this channel pair. POSITION + DATALEN must be less than FRAMELEN. See Frame format. When MODE = 0  POSITION defines the location of data in both the left phase and right phase .."
hexmask.long.word 0x4 0.--8. 1. "FRAMELEN,Frame Length  minus 1 encoded  defines the number of clocks and data bits in the frames that this channel pair participates in. See Frame format. 0x000 to 0x002 = not supported 0x003 = frame is 4 bits in total length 0x004 = frame is 5 bits in.."
line.long 0x8 "STAT,Status register for the primary channel pair."
rbitfld.long 0x8 3. "DATAPAUSED,Data Paused status flag. Applies to all I2S channels" "0: Data is not currently paused. A data pause may..,1: A data pause has been requested and is now in.."
rbitfld.long 0x8 2. "LR,Left/Right indication. This flag is considered to be a debugging aid and is not expected to be used by an I2S driver. Valid when one channel pair is busy. Indicates left or right data being processed for the currently busy channel pair." "0: Left channel.,1: Right channel."
newline
bitfld.long 0x8 1. "SLVFRMERR,Slave Frame Error flag. This applies when at least one channel pair is operating as a slave. An error indicates that the incoming WS signal did not transition as expected due to a mismatch between FRAMELEN and the actual incoming I2S stream." "0: No error has been recorded.,1: An error has been recorded for some channel pair.."
rbitfld.long 0x8 0. "BUSY,Busy status for the primary channel pair. Other BUSY flags may be found in the STAT register for each channel pair." "0: The transmitter/receiver for channel pair is..,1: The transmitter/receiver for channel pair is.."
group.long 0xC1C++0x3
line.long 0x0 "DIV,Clock divider. used by all channel pairs."
hexmask.long.word 0x0 0.--11. 1. "DIV,This field controls how this I2S block uses the Flexcomm function clock. 0x000 = The Flexcomm function clock is used directly. 0x001 = The Flexcomm function clock is divided by 2. 0x002 = The Flexcomm function clock is divided by 3. 0xFFF = The.."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
newline
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
newline
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
newline
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
newline
bitfld.long 0x0 3. "PACK48,Packing format for 48-bit data. This relates to how data is entered into or taken from the FIFO by software or DMA." "0: 48-bit I2S FIFO entries are handled as all..,1: 48-bit I2S FIFO entries are handled as.."
bitfld.long 0x0 2. "TXI2SE0,Transmit I2S empty 0. Determines the value sent by the I2S in transmit mode if the TX FIFO becomes empty. This value is sent repeatedly until the I2S is paused  the error is cleared  new data is provided  and the I2S is un-paused." "0: If the TX FIFO becomes empty the last value is..,1: If the TX FIFO becomes empty 0 is sent. Use if.."
newline
bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
newline
rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
newline
rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
newline
rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
newline
bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
newline
bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
newline
bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
newline
bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
newline
bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
newline
bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
wgroup.long 0xE20++0x7
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long 0x0 0.--31. 1. "TXDATA,Transmit data to the FIFO. The number of bits used depends on configuration details."
line.long 0x4 "FIFOWR48H,FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA."
hexmask.long.tbyte 0x4 0.--23. 1. "TXDATA,Transmit data to the FIFO. Whether this register is used and the number of bits used depends on configuration details."
rgroup.long 0xE30++0x7
line.long 0x0 "FIFORD,FIFO read data."
hexmask.long 0x0 0.--31. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on configuration details."
line.long 0x4 "FIFORD48H,FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA."
hexmask.long.tbyte 0x4 0.--23. 1. "RXDATA,Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details."
rgroup.long 0xE40++0x7
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
hexmask.long 0x0 0.--31. 1. "RXDATA,Received data from the FIFO."
line.long 0x4 "FIFORD48HNOPOP,FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA."
hexmask.long.tbyte 0x4 0.--23. 1. "RXDATA,Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details."
rgroup.long 0x1DFC++0x3
line.long 0x0 "ID,I2S Module identification"
hexmask.long.word 0x0 16.--31. 1. "ID,Unique module identifier for this IP block."
hexmask.long.byte 0x0 12.--15. 1. "Major_Rev,Major revision of module implementation  starting at 0."
newline
hexmask.long.byte 0x0 8.--11. 1. "Minor_Rev,Minor revision of module implementation  starting at 0."
hexmask.long.byte 0x0 0.--7. 1. "Aperture,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2S1"
base ad:0x40098000
repeat 3. (list 0x0 0x1 0x2)(list ad:0x40098000 ad:0x40098020 ad:0x40098040)
tree "SECCHANNEL[$1]"
base $2
group.long ($2+0xC20)++0xB
line.long 0x0 "PCFG1,Configuration register 1 for channel pair"
bitfld.long 0x0 10. "ONECHANNEL,Single channel mode." "0,1"
bitfld.long 0x0 0. "PAIRENABLE,Enable for this channel pair.." "0,1"
line.long 0x4 "PCFG2,Configuration register 2 for channel pair"
hexmask.long.word 0x4 16.--24. 1. "POSITION,Data Position."
line.long 0x8 "PSTAT,Status register for channel pair"
rbitfld.long 0x8 3. "DATAPAUSED,Data Paused status flag." "0,1"
bitfld.long 0x8 2. "LR,Left/Right indication." "0,1"
bitfld.long 0x8 1. "SLVFRMERR,Save Frame Error flag." "0,1"
bitfld.long 0x8 0. "BUSY,Busy status for this channel pair." "0,1"
tree.end
repeat.end
base ad:0x40098000
group.long 0xC00++0xB
line.long 0x0 "CFG1,Configuration register 1 for the primary channel pair."
hexmask.long.byte 0x0 16.--20. 1. "DATALEN,Data Length  minus 1 encoded  defines the number of data bits to be transmitted or received for all I2S channel pairs in this Flexcomm. Note that data is only driven to or received from SDA for the number of bits defined by DATALEN. DATALEN is.."
bitfld.long 0x0 13. "WS_POL,WS polarity." "0: Data frames begin at a falling edge of WS..,1: WS is inverted resulting in a data frame.."
newline
bitfld.long 0x0 12. "SCK_POL,SCK polarity." "0: Data is launched on SCK falling edges and..,1: Data is launched on SCK rising edges and sampled.."
bitfld.long 0x0 11. "PDMDATA,PDM Data selection. This bit controls the data source for I2S transmit  and cannot be set in Rx mode. This bit only has an effect if the device the Flexcomm resides in includes a D-Mic subsystem. For the LPC5411x  this bit applies only to.." "0: Normal operation data is transferred to or from..,1: The data source is the D-Mic subsystem. When.."
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bitfld.long 0x0 10. "ONECHANNEL,Single channel mode. Applies to both transmit and receive. This configuration bit applies only to the first I2S channel pair. Other channel pairs may select this mode independently in their separate CFG1 registers." "0: I2S data for this channel pair is treated as..,1: I2S data for this channel pair is treated as a.."
bitfld.long 0x0 9. "LEFTJUST,Left Justify data." "0: Data is transferred between the FIFO and the I2S..,1: Data is transferred between the FIFO and the I2S.."
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bitfld.long 0x0 8. "RIGHTLOW,Right channel data is in the Low portion of FIFO data. Essentially  this swaps left and right channel data as it is transferred to or from the FIFO. This bit is not used if the data width is greater than 24 bits or if PDMDATA = 1. Note that if.." "0: The right channel is taken from the high part of..,1: The right channel is taken from the low part of.."
bitfld.long 0x0 6.--7. "MODE,Selects the basic I2S operating mode. Other configurations modify this to obtain all supported cases. See Formats and modes for examples." "0: I2S mode a.k.a. 'classic' mode. WS has a 50%..,1: DSP mode where WS has a 50% duty cycle. See..,2: DSP mode where WS has a one clock long pulse at..,3: DSP mode where WS has a one data slot long pulse.."
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bitfld.long 0x0 4.--5. "MSTSLVCFG,Master / slave configuration selection  determining how SCK and WS are used by all channel pairs in this Flexcomm." "0: Normal slave mode the default mode. SCK and WS..,1: WS synchronized master. WS is received from..,2: Master using an existing SCK. SCK is received..,3: Normal master mode. SCK and WS are generated so.."
bitfld.long 0x0 2.--3. "PAIRCOUNT,Provides the number of I2S channel pairs in this Flexcomm This is a read-only field whose value may be different in other Flexcomms. 00 = there is 1 I2S channel pair in this Flexcomm. 01 = there are 2 I2S channel pairs in this Flexcomm. 10 =.." "0: there is 1 I2S channel pair in this Flexcomm,1: there are 2 I2S channel pairs in this Flexcomm,2: 3 I2S channel pairs in this flexcomm,3: 4 I2S channel pairs in this flexcomm"
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bitfld.long 0x0 1. "DATAPAUSE,Data flow Pause. Allows pausing data flow between the I2S serializer/deserializer and the FIFO. This could be done in order to change streams  or while restarting after a data underflow or overflow. When paused  FIFO operations can be done.." "0: Normal operation or resuming normal operation at..,1: A pause in the data flow is being requested. It.."
bitfld.long 0x0 0. "MAINENABLE,Main enable for I 2S function in this Flexcomm" "0: All I 2S channel pairs in this Flexcomm are..,1: This I 2S channel pair is enabled. Other channel.."
line.long 0x4 "CFG2,Configuration register 2 for the primary channel pair."
hexmask.long.word 0x4 16.--24. 1. "POSITION,Data Position. Defines the location within the frame of the data for this channel pair. POSITION + DATALEN must be less than FRAMELEN. See Frame format. When MODE = 0  POSITION defines the location of data in both the left phase and right phase .."
hexmask.long.word 0x4 0.--8. 1. "FRAMELEN,Frame Length  minus 1 encoded  defines the number of clocks and data bits in the frames that this channel pair participates in. See Frame format. 0x000 to 0x002 = not supported 0x003 = frame is 4 bits in total length 0x004 = frame is 5 bits in.."
line.long 0x8 "STAT,Status register for the primary channel pair."
rbitfld.long 0x8 3. "DATAPAUSED,Data Paused status flag. Applies to all I2S channels" "0: Data is not currently paused. A data pause may..,1: A data pause has been requested and is now in.."
rbitfld.long 0x8 2. "LR,Left/Right indication. This flag is considered to be a debugging aid and is not expected to be used by an I2S driver. Valid when one channel pair is busy. Indicates left or right data being processed for the currently busy channel pair." "0: Left channel.,1: Right channel."
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bitfld.long 0x8 1. "SLVFRMERR,Slave Frame Error flag. This applies when at least one channel pair is operating as a slave. An error indicates that the incoming WS signal did not transition as expected due to a mismatch between FRAMELEN and the actual incoming I2S stream." "0: No error has been recorded.,1: An error has been recorded for some channel pair.."
rbitfld.long 0x8 0. "BUSY,Busy status for the primary channel pair. Other BUSY flags may be found in the STAT register for each channel pair." "0: The transmitter/receiver for channel pair is..,1: The transmitter/receiver for channel pair is.."
group.long 0xC1C++0x3
line.long 0x0 "DIV,Clock divider. used by all channel pairs."
hexmask.long.word 0x0 0.--11. 1. "DIV,This field controls how this I2S block uses the Flexcomm function clock. 0x000 = The Flexcomm function clock is used directly. 0x001 = The Flexcomm function clock is divided by 2. 0x002 = The Flexcomm function clock is divided by 3. 0xFFF = The.."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 3. "PACK48,Packing format for 48-bit data. This relates to how data is entered into or taken from the FIFO by software or DMA." "0: 48-bit I2S FIFO entries are handled as all..,1: 48-bit I2S FIFO entries are handled as.."
bitfld.long 0x0 2. "TXI2SE0,Transmit I2S empty 0. Determines the value sent by the I2S in transmit mode if the TX FIFO becomes empty. This value is sent repeatedly until the I2S is paused  the error is cleared  new data is provided  and the I2S is un-paused." "0: If the TX FIFO becomes empty the last value is..,1: If the TX FIFO becomes empty 0 is sent. Use if.."
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
wgroup.long 0xE20++0x7
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long 0x0 0.--31. 1. "TXDATA,Transmit data to the FIFO. The number of bits used depends on configuration details."
line.long 0x4 "FIFOWR48H,FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA."
hexmask.long.tbyte 0x4 0.--23. 1. "TXDATA,Transmit data to the FIFO. Whether this register is used and the number of bits used depends on configuration details."
rgroup.long 0xE30++0x7
line.long 0x0 "FIFORD,FIFO read data."
hexmask.long 0x0 0.--31. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on configuration details."
line.long 0x4 "FIFORD48H,FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA."
hexmask.long.tbyte 0x4 0.--23. 1. "RXDATA,Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details."
rgroup.long 0xE40++0x7
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
hexmask.long 0x0 0.--31. 1. "RXDATA,Received data from the FIFO."
line.long 0x4 "FIFORD48HNOPOP,FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA."
hexmask.long.tbyte 0x4 0.--23. 1. "RXDATA,Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details."
rgroup.long 0x1DFC++0x3
line.long 0x0 "ID,I2S Module identification"
hexmask.long.word 0x0 16.--31. 1. "ID,Unique module identifier for this IP block."
hexmask.long.byte 0x0 12.--15. 1. "Major_Rev,Major revision of module implementation  starting at 0."
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hexmask.long.byte 0x0 8.--11. 1. "Minor_Rev,Minor revision of module implementation  starting at 0."
hexmask.long.byte 0x0 0.--7. 1. "Aperture,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
endif
sif (cpuis("LPC54606*"))
tree "I2S0"
base ad:0x40097000
repeat 3. (list 0x0 0x1 0x2)(list ad:0x40097000 ad:0x40097020 ad:0x40097040)
tree "SECCHANNEL[$1]"
base $2
group.long ($2+0xC20)++0xB
line.long 0x0 "PCFG1,Configuration register 1 for channel pair"
bitfld.long 0x0 10. "ONECHANNEL,Single channel mode." "0,1"
bitfld.long 0x0 0. "PAIRENABLE,Enable for this channel pair.." "0,1"
line.long 0x4 "PCFG2,Configuration register 2 for channel pair"
hexmask.long.word 0x4 16.--24. 1. "POSITION,Data Position."
line.long 0x8 "PSTAT,Status register for channel pair"
rbitfld.long 0x8 3. "DATAPAUSED,Data Paused status flag." "0,1"
bitfld.long 0x8 2. "LR,Left/Right indication." "0,1"
bitfld.long 0x8 1. "SLVFRMERR,Save Frame Error flag." "0,1"
bitfld.long 0x8 0. "BUSY,Busy status for this channel pair." "0,1"
tree.end
repeat.end
base ad:0x40097000
group.long 0xC00++0xB
line.long 0x0 "CFG1,Configuration register 1 for the primary channel pair."
hexmask.long.byte 0x0 16.--20. 1. "DATALEN,Data Length  minus 1 encoded  defines the number of data bits to be transmitted or received for all I2S channel pairs in this Flexcomm. Note that data is only driven to or received from SDA for the number of bits defined by DATALEN. DATALEN is.."
bitfld.long 0x0 13. "WS_POL,WS polarity." "0: Data frames begin at a falling edge of WS..,1: WS is inverted resulting in a data frame.."
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bitfld.long 0x0 12. "SCK_POL,SCK polarity." "0: Data is launched on SCK falling edges and..,1: Data is launched on SCK rising edges and sampled.."
bitfld.long 0x0 11. "PDMDATA,PDM Data selection. This bit controls the data source for I2S transmit  and cannot be set in Rx mode. This bit only has an effect if the device the Flexcomm resides in includes a D-Mic subsystem. For the LPC5411x  this bit applies only to.." "0: Normal operation data is transferred to or from..,1: The data source is the D-Mic subsystem. When.."
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bitfld.long 0x0 10. "ONECHANNEL,Single channel mode. Applies to both transmit and receive. This configuration bit applies only to the first I2S channel pair. Other channel pairs may select this mode independently in their separate CFG1 registers." "0: I2S data for this channel pair is treated as..,1: I2S data for this channel pair is treated as a.."
bitfld.long 0x0 9. "LEFTJUST,Left Justify data." "0: Data is transferred between the FIFO and the I2S..,1: Data is transferred between the FIFO and the I2S.."
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bitfld.long 0x0 8. "RIGHTLOW,Right channel data is in the Low portion of FIFO data. Essentially  this swaps left and right channel data as it is transferred to or from the FIFO. This bit is not used if the data width is greater than 24 bits or if PDMDATA = 1. Note that if.." "0: The right channel is taken from the high part of..,1: The right channel is taken from the low part of.."
bitfld.long 0x0 6.--7. "MODE,Selects the basic I2S operating mode. Other configurations modify this to obtain all supported cases. See Formats and modes for examples." "0: I2S mode a.k.a. 'classic' mode. WS has a 50%..,1: DSP mode where WS has a 50% duty cycle. See..,2: DSP mode where WS has a one clock long pulse at..,3: DSP mode where WS has a one data slot long pulse.."
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bitfld.long 0x0 4.--5. "MSTSLVCFG,Master / slave configuration selection  determining how SCK and WS are used by all channel pairs in this Flexcomm." "0: Normal slave mode the default mode. SCK and WS..,1: WS synchronized master. WS is received from..,2: Master using an existing SCK. SCK is received..,3: Normal master mode. SCK and WS are generated so.."
bitfld.long 0x0 2.--3. "PAIRCOUNT,Provides the number of I2S channel pairs in this Flexcomm This is a read-only field whose value may be different in other Flexcomms. 00 = there is 1 I2S channel pair in this Flexcomm. 01 = there are 2 I2S channel pairs in this Flexcomm. 10 =.." "0: there is 1 I2S channel pair in this Flexcomm,1: there are 2 I2S channel pairs in this Flexcomm,2: 3 I2S channel pairs in this flexcomm,3: 4 I2S channel pairs in this flexcomm"
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bitfld.long 0x0 1. "DATAPAUSE,Data flow Pause. Allows pausing data flow between the I2S serializer/deserializer and the FIFO. This could be done in order to change streams  or while restarting after a data underflow or overflow. When paused  FIFO operations can be done.." "0: Normal operation or resuming normal operation at..,1: A pause in the data flow is being requested. It.."
bitfld.long 0x0 0. "MAINENABLE,Main enable for I 2S function in this Flexcomm" "0: All I 2S channel pairs in this Flexcomm are..,1: This I 2S channel pair is enabled. Other channel.."
line.long 0x4 "CFG2,Configuration register 2 for the primary channel pair."
hexmask.long.word 0x4 16.--24. 1. "POSITION,Data Position. Defines the location within the frame of the data for this channel pair. POSITION + DATALEN must be less than FRAMELEN. See Frame format. When MODE = 0  POSITION defines the location of data in both the left phase and right phase .."
hexmask.long.word 0x4 0.--8. 1. "FRAMELEN,Frame Length  minus 1 encoded  defines the number of clocks and data bits in the frames that this channel pair participates in. See Frame format. 0x000 to 0x002 = not supported 0x003 = frame is 4 bits in total length 0x004 = frame is 5 bits in.."
line.long 0x8 "STAT,Status register for the primary channel pair."
rbitfld.long 0x8 3. "DATAPAUSED,Data Paused status flag. Applies to all I2S channels" "0: Data is not currently paused. A data pause may..,1: A data pause has been requested and is now in.."
rbitfld.long 0x8 2. "LR,Left/Right indication. This flag is considered to be a debugging aid and is not expected to be used by an I2S driver. Valid when one channel pair is busy. Indicates left or right data being processed for the currently busy channel pair." "0: Left channel.,1: Right channel."
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bitfld.long 0x8 1. "SLVFRMERR,Slave Frame Error flag. This applies when at least one channel pair is operating as a slave. An error indicates that the incoming WS signal did not transition as expected due to a mismatch between FRAMELEN and the actual incoming I2S stream." "0: No error has been recorded.,1: An error has been recorded for some channel pair.."
rbitfld.long 0x8 0. "BUSY,Busy status for the primary channel pair. Other BUSY flags may be found in the STAT register for each channel pair." "0: The transmitter/receiver for channel pair is..,1: The transmitter/receiver for channel pair is.."
group.long 0xC1C++0x3
line.long 0x0 "DIV,Clock divider. used by all channel pairs."
hexmask.long.word 0x0 0.--11. 1. "DIV,This field controls how this I2S block uses the Flexcomm function clock. 0x000 = The Flexcomm function clock is used directly. 0x001 = The Flexcomm function clock is divided by 2. 0x002 = The Flexcomm function clock is divided by 3. 0xFFF = The.."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 3. "PACK48,Packing format for 48-bit data. This relates to how data is entered into or taken from the FIFO by software or DMA." "0: 48-bit I2S FIFO entries are handled as all..,1: 48-bit I2S FIFO entries are handled as.."
bitfld.long 0x0 2. "TXI2SE0,Transmit I2S empty 0. Determines the value sent by the I2S in transmit mode if the TX FIFO becomes empty. This value is sent repeatedly until the I2S is paused  the error is cleared  new data is provided  and the I2S is un-paused." "0: If the TX FIFO becomes empty the last value is..,1: If the TX FIFO becomes empty 0 is sent. Use if.."
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
newline
bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
newline
bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
newline
bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
newline
bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
newline
bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
newline
bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
wgroup.long 0xE20++0x7
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long 0x0 0.--31. 1. "TXDATA,Transmit data to the FIFO. The number of bits used depends on configuration details."
line.long 0x4 "FIFOWR48H,FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA."
hexmask.long.tbyte 0x4 0.--23. 1. "TXDATA,Transmit data to the FIFO. Whether this register is used and the number of bits used depends on configuration details."
rgroup.long 0xE30++0x7
line.long 0x0 "FIFORD,FIFO read data."
hexmask.long 0x0 0.--31. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on configuration details."
line.long 0x4 "FIFORD48H,FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA."
hexmask.long.tbyte 0x4 0.--23. 1. "RXDATA,Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details."
rgroup.long 0xE40++0x7
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
hexmask.long 0x0 0.--31. 1. "RXDATA,Received data from the FIFO."
line.long 0x4 "FIFORD48HNOPOP,FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA."
hexmask.long.tbyte 0x4 0.--23. 1. "RXDATA,Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details."
rgroup.long 0x1DFC++0x3
line.long 0x0 "ID,I2S Module identification"
hexmask.long.word 0x0 16.--31. 1. "ID,Unique module identifier for this IP block."
hexmask.long.byte 0x0 12.--15. 1. "Major_Rev,Major revision of module implementation  starting at 0."
newline
hexmask.long.byte 0x0 8.--11. 1. "Minor_Rev,Minor revision of module implementation  starting at 0."
hexmask.long.byte 0x0 0.--7. 1. "Aperture,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2S1"
base ad:0x40098000
repeat 3. (list 0x0 0x1 0x2)(list ad:0x40098000 ad:0x40098020 ad:0x40098040)
tree "SECCHANNEL[$1]"
base $2
group.long ($2+0xC20)++0xB
line.long 0x0 "PCFG1,Configuration register 1 for channel pair"
bitfld.long 0x0 10. "ONECHANNEL,Single channel mode." "0,1"
bitfld.long 0x0 0. "PAIRENABLE,Enable for this channel pair.." "0,1"
line.long 0x4 "PCFG2,Configuration register 2 for channel pair"
hexmask.long.word 0x4 16.--24. 1. "POSITION,Data Position."
line.long 0x8 "PSTAT,Status register for channel pair"
rbitfld.long 0x8 3. "DATAPAUSED,Data Paused status flag." "0,1"
bitfld.long 0x8 2. "LR,Left/Right indication." "0,1"
bitfld.long 0x8 1. "SLVFRMERR,Save Frame Error flag." "0,1"
bitfld.long 0x8 0. "BUSY,Busy status for this channel pair." "0,1"
tree.end
repeat.end
base ad:0x40098000
group.long 0xC00++0xB
line.long 0x0 "CFG1,Configuration register 1 for the primary channel pair."
hexmask.long.byte 0x0 16.--20. 1. "DATALEN,Data Length  minus 1 encoded  defines the number of data bits to be transmitted or received for all I2S channel pairs in this Flexcomm. Note that data is only driven to or received from SDA for the number of bits defined by DATALEN. DATALEN is.."
bitfld.long 0x0 13. "WS_POL,WS polarity." "0: Data frames begin at a falling edge of WS..,1: WS is inverted resulting in a data frame.."
newline
bitfld.long 0x0 12. "SCK_POL,SCK polarity." "0: Data is launched on SCK falling edges and..,1: Data is launched on SCK rising edges and sampled.."
bitfld.long 0x0 11. "PDMDATA,PDM Data selection. This bit controls the data source for I2S transmit  and cannot be set in Rx mode. This bit only has an effect if the device the Flexcomm resides in includes a D-Mic subsystem. For the LPC5411x  this bit applies only to.." "0: Normal operation data is transferred to or from..,1: The data source is the D-Mic subsystem. When.."
newline
bitfld.long 0x0 10. "ONECHANNEL,Single channel mode. Applies to both transmit and receive. This configuration bit applies only to the first I2S channel pair. Other channel pairs may select this mode independently in their separate CFG1 registers." "0: I2S data for this channel pair is treated as..,1: I2S data for this channel pair is treated as a.."
bitfld.long 0x0 9. "LEFTJUST,Left Justify data." "0: Data is transferred between the FIFO and the I2S..,1: Data is transferred between the FIFO and the I2S.."
newline
bitfld.long 0x0 8. "RIGHTLOW,Right channel data is in the Low portion of FIFO data. Essentially  this swaps left and right channel data as it is transferred to or from the FIFO. This bit is not used if the data width is greater than 24 bits or if PDMDATA = 1. Note that if.." "0: The right channel is taken from the high part of..,1: The right channel is taken from the low part of.."
bitfld.long 0x0 6.--7. "MODE,Selects the basic I2S operating mode. Other configurations modify this to obtain all supported cases. See Formats and modes for examples." "0: I2S mode a.k.a. 'classic' mode. WS has a 50%..,1: DSP mode where WS has a 50% duty cycle. See..,2: DSP mode where WS has a one clock long pulse at..,3: DSP mode where WS has a one data slot long pulse.."
newline
bitfld.long 0x0 4.--5. "MSTSLVCFG,Master / slave configuration selection  determining how SCK and WS are used by all channel pairs in this Flexcomm." "0: Normal slave mode the default mode. SCK and WS..,1: WS synchronized master. WS is received from..,2: Master using an existing SCK. SCK is received..,3: Normal master mode. SCK and WS are generated so.."
bitfld.long 0x0 2.--3. "PAIRCOUNT,Provides the number of I2S channel pairs in this Flexcomm This is a read-only field whose value may be different in other Flexcomms. 00 = there is 1 I2S channel pair in this Flexcomm. 01 = there are 2 I2S channel pairs in this Flexcomm. 10 =.." "0: there is 1 I2S channel pair in this Flexcomm,1: there are 2 I2S channel pairs in this Flexcomm,2: 3 I2S channel pairs in this flexcomm,3: 4 I2S channel pairs in this flexcomm"
newline
bitfld.long 0x0 1. "DATAPAUSE,Data flow Pause. Allows pausing data flow between the I2S serializer/deserializer and the FIFO. This could be done in order to change streams  or while restarting after a data underflow or overflow. When paused  FIFO operations can be done.." "0: Normal operation or resuming normal operation at..,1: A pause in the data flow is being requested. It.."
bitfld.long 0x0 0. "MAINENABLE,Main enable for I 2S function in this Flexcomm" "0: All I 2S channel pairs in this Flexcomm are..,1: This I 2S channel pair is enabled. Other channel.."
line.long 0x4 "CFG2,Configuration register 2 for the primary channel pair."
hexmask.long.word 0x4 16.--24. 1. "POSITION,Data Position. Defines the location within the frame of the data for this channel pair. POSITION + DATALEN must be less than FRAMELEN. See Frame format. When MODE = 0  POSITION defines the location of data in both the left phase and right phase .."
hexmask.long.word 0x4 0.--8. 1. "FRAMELEN,Frame Length  minus 1 encoded  defines the number of clocks and data bits in the frames that this channel pair participates in. See Frame format. 0x000 to 0x002 = not supported 0x003 = frame is 4 bits in total length 0x004 = frame is 5 bits in.."
line.long 0x8 "STAT,Status register for the primary channel pair."
rbitfld.long 0x8 3. "DATAPAUSED,Data Paused status flag. Applies to all I2S channels" "0: Data is not currently paused. A data pause may..,1: A data pause has been requested and is now in.."
rbitfld.long 0x8 2. "LR,Left/Right indication. This flag is considered to be a debugging aid and is not expected to be used by an I2S driver. Valid when one channel pair is busy. Indicates left or right data being processed for the currently busy channel pair." "0: Left channel.,1: Right channel."
newline
bitfld.long 0x8 1. "SLVFRMERR,Slave Frame Error flag. This applies when at least one channel pair is operating as a slave. An error indicates that the incoming WS signal did not transition as expected due to a mismatch between FRAMELEN and the actual incoming I2S stream." "0: No error has been recorded.,1: An error has been recorded for some channel pair.."
rbitfld.long 0x8 0. "BUSY,Busy status for the primary channel pair. Other BUSY flags may be found in the STAT register for each channel pair." "0: The transmitter/receiver for channel pair is..,1: The transmitter/receiver for channel pair is.."
group.long 0xC1C++0x3
line.long 0x0 "DIV,Clock divider. used by all channel pairs."
hexmask.long.word 0x0 0.--11. 1. "DIV,This field controls how this I2S block uses the Flexcomm function clock. 0x000 = The Flexcomm function clock is used directly. 0x001 = The Flexcomm function clock is divided by 2. 0x002 = The Flexcomm function clock is divided by 3. 0xFFF = The.."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
newline
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
newline
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
newline
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
newline
bitfld.long 0x0 3. "PACK48,Packing format for 48-bit data. This relates to how data is entered into or taken from the FIFO by software or DMA." "0: 48-bit I2S FIFO entries are handled as all..,1: 48-bit I2S FIFO entries are handled as.."
bitfld.long 0x0 2. "TXI2SE0,Transmit I2S empty 0. Determines the value sent by the I2S in transmit mode if the TX FIFO becomes empty. This value is sent repeatedly until the I2S is paused  the error is cleared  new data is provided  and the I2S is un-paused." "0: If the TX FIFO becomes empty the last value is..,1: If the TX FIFO becomes empty 0 is sent. Use if.."
newline
bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
newline
rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
newline
rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
newline
rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
newline
bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
newline
bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
newline
bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
newline
bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
newline
bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
newline
bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
wgroup.long 0xE20++0x7
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long 0x0 0.--31. 1. "TXDATA,Transmit data to the FIFO. The number of bits used depends on configuration details."
line.long 0x4 "FIFOWR48H,FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA."
hexmask.long.tbyte 0x4 0.--23. 1. "TXDATA,Transmit data to the FIFO. Whether this register is used and the number of bits used depends on configuration details."
rgroup.long 0xE30++0x7
line.long 0x0 "FIFORD,FIFO read data."
hexmask.long 0x0 0.--31. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on configuration details."
line.long 0x4 "FIFORD48H,FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA."
hexmask.long.tbyte 0x4 0.--23. 1. "RXDATA,Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details."
rgroup.long 0xE40++0x7
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
hexmask.long 0x0 0.--31. 1. "RXDATA,Received data from the FIFO."
line.long 0x4 "FIFORD48HNOPOP,FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA."
hexmask.long.tbyte 0x4 0.--23. 1. "RXDATA,Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details."
rgroup.long 0x1DFC++0x3
line.long 0x0 "ID,I2S Module identification"
hexmask.long.word 0x0 16.--31. 1. "ID,Unique module identifier for this IP block."
hexmask.long.byte 0x0 12.--15. 1. "Major_Rev,Major revision of module implementation  starting at 0."
newline
hexmask.long.byte 0x0 8.--11. 1. "Minor_Rev,Minor revision of module implementation  starting at 0."
hexmask.long.byte 0x0 0.--7. 1. "Aperture,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
endif
sif (cpuis("LPC54607*"))
tree "I2S0"
base ad:0x40097000
repeat 3. (list 0x0 0x1 0x2)(list ad:0x40097000 ad:0x40097020 ad:0x40097040)
tree "SECCHANNEL[$1]"
base $2
group.long ($2+0xC20)++0xB
line.long 0x0 "PCFG1,Configuration register 1 for channel pair"
bitfld.long 0x0 10. "ONECHANNEL,Single channel mode." "0,1"
bitfld.long 0x0 0. "PAIRENABLE,Enable for this channel pair.." "0,1"
line.long 0x4 "PCFG2,Configuration register 2 for channel pair"
hexmask.long.word 0x4 16.--24. 1. "POSITION,Data Position."
line.long 0x8 "PSTAT,Status register for channel pair"
rbitfld.long 0x8 3. "DATAPAUSED,Data Paused status flag." "0,1"
bitfld.long 0x8 2. "LR,Left/Right indication." "0,1"
bitfld.long 0x8 1. "SLVFRMERR,Save Frame Error flag." "0,1"
bitfld.long 0x8 0. "BUSY,Busy status for this channel pair." "0,1"
tree.end
repeat.end
base ad:0x40097000
group.long 0xC00++0xB
line.long 0x0 "CFG1,Configuration register 1 for the primary channel pair."
hexmask.long.byte 0x0 16.--20. 1. "DATALEN,Data Length  minus 1 encoded  defines the number of data bits to be transmitted or received for all I2S channel pairs in this Flexcomm. Note that data is only driven to or received from SDA for the number of bits defined by DATALEN. DATALEN is.."
bitfld.long 0x0 13. "WS_POL,WS polarity." "0: Data frames begin at a falling edge of WS..,1: WS is inverted resulting in a data frame.."
newline
bitfld.long 0x0 12. "SCK_POL,SCK polarity." "0: Data is launched on SCK falling edges and..,1: Data is launched on SCK rising edges and sampled.."
bitfld.long 0x0 11. "PDMDATA,PDM Data selection. This bit controls the data source for I2S transmit  and cannot be set in Rx mode. This bit only has an effect if the device the Flexcomm resides in includes a D-Mic subsystem. For the LPC5411x  this bit applies only to.." "0: Normal operation data is transferred to or from..,1: The data source is the D-Mic subsystem. When.."
newline
bitfld.long 0x0 10. "ONECHANNEL,Single channel mode. Applies to both transmit and receive. This configuration bit applies only to the first I2S channel pair. Other channel pairs may select this mode independently in their separate CFG1 registers." "0: I2S data for this channel pair is treated as..,1: I2S data for this channel pair is treated as a.."
bitfld.long 0x0 9. "LEFTJUST,Left Justify data." "0: Data is transferred between the FIFO and the I2S..,1: Data is transferred between the FIFO and the I2S.."
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bitfld.long 0x0 8. "RIGHTLOW,Right channel data is in the Low portion of FIFO data. Essentially  this swaps left and right channel data as it is transferred to or from the FIFO. This bit is not used if the data width is greater than 24 bits or if PDMDATA = 1. Note that if.." "0: The right channel is taken from the high part of..,1: The right channel is taken from the low part of.."
bitfld.long 0x0 6.--7. "MODE,Selects the basic I2S operating mode. Other configurations modify this to obtain all supported cases. See Formats and modes for examples." "0: I2S mode a.k.a. 'classic' mode. WS has a 50%..,1: DSP mode where WS has a 50% duty cycle. See..,2: DSP mode where WS has a one clock long pulse at..,3: DSP mode where WS has a one data slot long pulse.."
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bitfld.long 0x0 4.--5. "MSTSLVCFG,Master / slave configuration selection  determining how SCK and WS are used by all channel pairs in this Flexcomm." "0: Normal slave mode the default mode. SCK and WS..,1: WS synchronized master. WS is received from..,2: Master using an existing SCK. SCK is received..,3: Normal master mode. SCK and WS are generated so.."
bitfld.long 0x0 2.--3. "PAIRCOUNT,Provides the number of I2S channel pairs in this Flexcomm This is a read-only field whose value may be different in other Flexcomms. 00 = there is 1 I2S channel pair in this Flexcomm. 01 = there are 2 I2S channel pairs in this Flexcomm. 10 =.." "0: there is 1 I2S channel pair in this Flexcomm,1: there are 2 I2S channel pairs in this Flexcomm,2: 3 I2S channel pairs in this flexcomm,3: 4 I2S channel pairs in this flexcomm"
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bitfld.long 0x0 1. "DATAPAUSE,Data flow Pause. Allows pausing data flow between the I2S serializer/deserializer and the FIFO. This could be done in order to change streams  or while restarting after a data underflow or overflow. When paused  FIFO operations can be done.." "0: Normal operation or resuming normal operation at..,1: A pause in the data flow is being requested. It.."
bitfld.long 0x0 0. "MAINENABLE,Main enable for I 2S function in this Flexcomm" "0: All I 2S channel pairs in this Flexcomm are..,1: This I 2S channel pair is enabled. Other channel.."
line.long 0x4 "CFG2,Configuration register 2 for the primary channel pair."
hexmask.long.word 0x4 16.--24. 1. "POSITION,Data Position. Defines the location within the frame of the data for this channel pair. POSITION + DATALEN must be less than FRAMELEN. See Frame format. When MODE = 0  POSITION defines the location of data in both the left phase and right phase .."
hexmask.long.word 0x4 0.--8. 1. "FRAMELEN,Frame Length  minus 1 encoded  defines the number of clocks and data bits in the frames that this channel pair participates in. See Frame format. 0x000 to 0x002 = not supported 0x003 = frame is 4 bits in total length 0x004 = frame is 5 bits in.."
line.long 0x8 "STAT,Status register for the primary channel pair."
rbitfld.long 0x8 3. "DATAPAUSED,Data Paused status flag. Applies to all I2S channels" "0: Data is not currently paused. A data pause may..,1: A data pause has been requested and is now in.."
rbitfld.long 0x8 2. "LR,Left/Right indication. This flag is considered to be a debugging aid and is not expected to be used by an I2S driver. Valid when one channel pair is busy. Indicates left or right data being processed for the currently busy channel pair." "0: Left channel.,1: Right channel."
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bitfld.long 0x8 1. "SLVFRMERR,Slave Frame Error flag. This applies when at least one channel pair is operating as a slave. An error indicates that the incoming WS signal did not transition as expected due to a mismatch between FRAMELEN and the actual incoming I2S stream." "0: No error has been recorded.,1: An error has been recorded for some channel pair.."
rbitfld.long 0x8 0. "BUSY,Busy status for the primary channel pair. Other BUSY flags may be found in the STAT register for each channel pair." "0: The transmitter/receiver for channel pair is..,1: The transmitter/receiver for channel pair is.."
group.long 0xC1C++0x3
line.long 0x0 "DIV,Clock divider. used by all channel pairs."
hexmask.long.word 0x0 0.--11. 1. "DIV,This field controls how this I2S block uses the Flexcomm function clock. 0x000 = The Flexcomm function clock is used directly. 0x001 = The Flexcomm function clock is divided by 2. 0x002 = The Flexcomm function clock is divided by 3. 0xFFF = The.."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 3. "PACK48,Packing format for 48-bit data. This relates to how data is entered into or taken from the FIFO by software or DMA." "0: 48-bit I2S FIFO entries are handled as all..,1: 48-bit I2S FIFO entries are handled as.."
bitfld.long 0x0 2. "TXI2SE0,Transmit I2S empty 0. Determines the value sent by the I2S in transmit mode if the TX FIFO becomes empty. This value is sent repeatedly until the I2S is paused  the error is cleared  new data is provided  and the I2S is un-paused." "0: If the TX FIFO becomes empty the last value is..,1: If the TX FIFO becomes empty 0 is sent. Use if.."
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
wgroup.long 0xE20++0x7
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long 0x0 0.--31. 1. "TXDATA,Transmit data to the FIFO. The number of bits used depends on configuration details."
line.long 0x4 "FIFOWR48H,FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA."
hexmask.long.tbyte 0x4 0.--23. 1. "TXDATA,Transmit data to the FIFO. Whether this register is used and the number of bits used depends on configuration details."
rgroup.long 0xE30++0x7
line.long 0x0 "FIFORD,FIFO read data."
hexmask.long 0x0 0.--31. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on configuration details."
line.long 0x4 "FIFORD48H,FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA."
hexmask.long.tbyte 0x4 0.--23. 1. "RXDATA,Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details."
rgroup.long 0xE40++0x7
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
hexmask.long 0x0 0.--31. 1. "RXDATA,Received data from the FIFO."
line.long 0x4 "FIFORD48HNOPOP,FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA."
hexmask.long.tbyte 0x4 0.--23. 1. "RXDATA,Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details."
rgroup.long 0x1DFC++0x3
line.long 0x0 "ID,I2S Module identification"
hexmask.long.word 0x0 16.--31. 1. "ID,Unique module identifier for this IP block."
hexmask.long.byte 0x0 12.--15. 1. "Major_Rev,Major revision of module implementation  starting at 0."
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hexmask.long.byte 0x0 8.--11. 1. "Minor_Rev,Minor revision of module implementation  starting at 0."
hexmask.long.byte 0x0 0.--7. 1. "Aperture,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2S1"
base ad:0x40098000
repeat 3. (list 0x0 0x1 0x2)(list ad:0x40098000 ad:0x40098020 ad:0x40098040)
tree "SECCHANNEL[$1]"
base $2
group.long ($2+0xC20)++0xB
line.long 0x0 "PCFG1,Configuration register 1 for channel pair"
bitfld.long 0x0 10. "ONECHANNEL,Single channel mode." "0,1"
bitfld.long 0x0 0. "PAIRENABLE,Enable for this channel pair.." "0,1"
line.long 0x4 "PCFG2,Configuration register 2 for channel pair"
hexmask.long.word 0x4 16.--24. 1. "POSITION,Data Position."
line.long 0x8 "PSTAT,Status register for channel pair"
rbitfld.long 0x8 3. "DATAPAUSED,Data Paused status flag." "0,1"
bitfld.long 0x8 2. "LR,Left/Right indication." "0,1"
bitfld.long 0x8 1. "SLVFRMERR,Save Frame Error flag." "0,1"
bitfld.long 0x8 0. "BUSY,Busy status for this channel pair." "0,1"
tree.end
repeat.end
base ad:0x40098000
group.long 0xC00++0xB
line.long 0x0 "CFG1,Configuration register 1 for the primary channel pair."
hexmask.long.byte 0x0 16.--20. 1. "DATALEN,Data Length  minus 1 encoded  defines the number of data bits to be transmitted or received for all I2S channel pairs in this Flexcomm. Note that data is only driven to or received from SDA for the number of bits defined by DATALEN. DATALEN is.."
bitfld.long 0x0 13. "WS_POL,WS polarity." "0: Data frames begin at a falling edge of WS..,1: WS is inverted resulting in a data frame.."
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bitfld.long 0x0 12. "SCK_POL,SCK polarity." "0: Data is launched on SCK falling edges and..,1: Data is launched on SCK rising edges and sampled.."
bitfld.long 0x0 11. "PDMDATA,PDM Data selection. This bit controls the data source for I2S transmit  and cannot be set in Rx mode. This bit only has an effect if the device the Flexcomm resides in includes a D-Mic subsystem. For the LPC5411x  this bit applies only to.." "0: Normal operation data is transferred to or from..,1: The data source is the D-Mic subsystem. When.."
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bitfld.long 0x0 10. "ONECHANNEL,Single channel mode. Applies to both transmit and receive. This configuration bit applies only to the first I2S channel pair. Other channel pairs may select this mode independently in their separate CFG1 registers." "0: I2S data for this channel pair is treated as..,1: I2S data for this channel pair is treated as a.."
bitfld.long 0x0 9. "LEFTJUST,Left Justify data." "0: Data is transferred between the FIFO and the I2S..,1: Data is transferred between the FIFO and the I2S.."
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bitfld.long 0x0 8. "RIGHTLOW,Right channel data is in the Low portion of FIFO data. Essentially  this swaps left and right channel data as it is transferred to or from the FIFO. This bit is not used if the data width is greater than 24 bits or if PDMDATA = 1. Note that if.." "0: The right channel is taken from the high part of..,1: The right channel is taken from the low part of.."
bitfld.long 0x0 6.--7. "MODE,Selects the basic I2S operating mode. Other configurations modify this to obtain all supported cases. See Formats and modes for examples." "0: I2S mode a.k.a. 'classic' mode. WS has a 50%..,1: DSP mode where WS has a 50% duty cycle. See..,2: DSP mode where WS has a one clock long pulse at..,3: DSP mode where WS has a one data slot long pulse.."
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bitfld.long 0x0 4.--5. "MSTSLVCFG,Master / slave configuration selection  determining how SCK and WS are used by all channel pairs in this Flexcomm." "0: Normal slave mode the default mode. SCK and WS..,1: WS synchronized master. WS is received from..,2: Master using an existing SCK. SCK is received..,3: Normal master mode. SCK and WS are generated so.."
bitfld.long 0x0 2.--3. "PAIRCOUNT,Provides the number of I2S channel pairs in this Flexcomm This is a read-only field whose value may be different in other Flexcomms. 00 = there is 1 I2S channel pair in this Flexcomm. 01 = there are 2 I2S channel pairs in this Flexcomm. 10 =.." "0: there is 1 I2S channel pair in this Flexcomm,1: there are 2 I2S channel pairs in this Flexcomm,2: 3 I2S channel pairs in this flexcomm,3: 4 I2S channel pairs in this flexcomm"
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bitfld.long 0x0 1. "DATAPAUSE,Data flow Pause. Allows pausing data flow between the I2S serializer/deserializer and the FIFO. This could be done in order to change streams  or while restarting after a data underflow or overflow. When paused  FIFO operations can be done.." "0: Normal operation or resuming normal operation at..,1: A pause in the data flow is being requested. It.."
bitfld.long 0x0 0. "MAINENABLE,Main enable for I 2S function in this Flexcomm" "0: All I 2S channel pairs in this Flexcomm are..,1: This I 2S channel pair is enabled. Other channel.."
line.long 0x4 "CFG2,Configuration register 2 for the primary channel pair."
hexmask.long.word 0x4 16.--24. 1. "POSITION,Data Position. Defines the location within the frame of the data for this channel pair. POSITION + DATALEN must be less than FRAMELEN. See Frame format. When MODE = 0  POSITION defines the location of data in both the left phase and right phase .."
hexmask.long.word 0x4 0.--8. 1. "FRAMELEN,Frame Length  minus 1 encoded  defines the number of clocks and data bits in the frames that this channel pair participates in. See Frame format. 0x000 to 0x002 = not supported 0x003 = frame is 4 bits in total length 0x004 = frame is 5 bits in.."
line.long 0x8 "STAT,Status register for the primary channel pair."
rbitfld.long 0x8 3. "DATAPAUSED,Data Paused status flag. Applies to all I2S channels" "0: Data is not currently paused. A data pause may..,1: A data pause has been requested and is now in.."
rbitfld.long 0x8 2. "LR,Left/Right indication. This flag is considered to be a debugging aid and is not expected to be used by an I2S driver. Valid when one channel pair is busy. Indicates left or right data being processed for the currently busy channel pair." "0: Left channel.,1: Right channel."
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bitfld.long 0x8 1. "SLVFRMERR,Slave Frame Error flag. This applies when at least one channel pair is operating as a slave. An error indicates that the incoming WS signal did not transition as expected due to a mismatch between FRAMELEN and the actual incoming I2S stream." "0: No error has been recorded.,1: An error has been recorded for some channel pair.."
rbitfld.long 0x8 0. "BUSY,Busy status for the primary channel pair. Other BUSY flags may be found in the STAT register for each channel pair." "0: The transmitter/receiver for channel pair is..,1: The transmitter/receiver for channel pair is.."
group.long 0xC1C++0x3
line.long 0x0 "DIV,Clock divider. used by all channel pairs."
hexmask.long.word 0x0 0.--11. 1. "DIV,This field controls how this I2S block uses the Flexcomm function clock. 0x000 = The Flexcomm function clock is used directly. 0x001 = The Flexcomm function clock is divided by 2. 0x002 = The Flexcomm function clock is divided by 3. 0xFFF = The.."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 3. "PACK48,Packing format for 48-bit data. This relates to how data is entered into or taken from the FIFO by software or DMA." "0: 48-bit I2S FIFO entries are handled as all..,1: 48-bit I2S FIFO entries are handled as.."
bitfld.long 0x0 2. "TXI2SE0,Transmit I2S empty 0. Determines the value sent by the I2S in transmit mode if the TX FIFO becomes empty. This value is sent repeatedly until the I2S is paused  the error is cleared  new data is provided  and the I2S is un-paused." "0: If the TX FIFO becomes empty the last value is..,1: If the TX FIFO becomes empty 0 is sent. Use if.."
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
wgroup.long 0xE20++0x7
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long 0x0 0.--31. 1. "TXDATA,Transmit data to the FIFO. The number of bits used depends on configuration details."
line.long 0x4 "FIFOWR48H,FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA."
hexmask.long.tbyte 0x4 0.--23. 1. "TXDATA,Transmit data to the FIFO. Whether this register is used and the number of bits used depends on configuration details."
rgroup.long 0xE30++0x7
line.long 0x0 "FIFORD,FIFO read data."
hexmask.long 0x0 0.--31. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on configuration details."
line.long 0x4 "FIFORD48H,FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA."
hexmask.long.tbyte 0x4 0.--23. 1. "RXDATA,Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details."
rgroup.long 0xE40++0x7
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
hexmask.long 0x0 0.--31. 1. "RXDATA,Received data from the FIFO."
line.long 0x4 "FIFORD48HNOPOP,FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA."
hexmask.long.tbyte 0x4 0.--23. 1. "RXDATA,Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details."
rgroup.long 0x1DFC++0x3
line.long 0x0 "ID,I2S Module identification"
hexmask.long.word 0x0 16.--31. 1. "ID,Unique module identifier for this IP block."
hexmask.long.byte 0x0 12.--15. 1. "Major_Rev,Major revision of module implementation  starting at 0."
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hexmask.long.byte 0x0 8.--11. 1. "Minor_Rev,Minor revision of module implementation  starting at 0."
hexmask.long.byte 0x0 0.--7. 1. "Aperture,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
endif
sif (cpuis("LPC54608*"))
tree "I2S0"
base ad:0x40097000
repeat 3. (list 0x0 0x1 0x2)(list ad:0x40097000 ad:0x40097020 ad:0x40097040)
tree "SECCHANNEL[$1]"
base $2
group.long ($2+0xC20)++0xB
line.long 0x0 "PCFG1,Configuration register 1 for channel pair"
bitfld.long 0x0 10. "ONECHANNEL,Single channel mode." "0,1"
bitfld.long 0x0 0. "PAIRENABLE,Enable for this channel pair.." "0,1"
line.long 0x4 "PCFG2,Configuration register 2 for channel pair"
hexmask.long.word 0x4 16.--24. 1. "POSITION,Data Position."
line.long 0x8 "PSTAT,Status register for channel pair"
rbitfld.long 0x8 3. "DATAPAUSED,Data Paused status flag." "0,1"
bitfld.long 0x8 2. "LR,Left/Right indication." "0,1"
bitfld.long 0x8 1. "SLVFRMERR,Save Frame Error flag." "0,1"
bitfld.long 0x8 0. "BUSY,Busy status for this channel pair." "0,1"
tree.end
repeat.end
base ad:0x40097000
group.long 0xC00++0xB
line.long 0x0 "CFG1,Configuration register 1 for the primary channel pair."
hexmask.long.byte 0x0 16.--20. 1. "DATALEN,Data Length  minus 1 encoded  defines the number of data bits to be transmitted or received for all I2S channel pairs in this Flexcomm. Note that data is only driven to or received from SDA for the number of bits defined by DATALEN. DATALEN is.."
bitfld.long 0x0 13. "WS_POL,WS polarity." "0: Data frames begin at a falling edge of WS..,1: WS is inverted resulting in a data frame.."
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bitfld.long 0x0 12. "SCK_POL,SCK polarity." "0: Data is launched on SCK falling edges and..,1: Data is launched on SCK rising edges and sampled.."
bitfld.long 0x0 11. "PDMDATA,PDM Data selection. This bit controls the data source for I2S transmit  and cannot be set in Rx mode. This bit only has an effect if the device the Flexcomm resides in includes a D-Mic subsystem. For the LPC5411x  this bit applies only to.." "0: Normal operation data is transferred to or from..,1: The data source is the D-Mic subsystem. When.."
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bitfld.long 0x0 10. "ONECHANNEL,Single channel mode. Applies to both transmit and receive. This configuration bit applies only to the first I2S channel pair. Other channel pairs may select this mode independently in their separate CFG1 registers." "0: I2S data for this channel pair is treated as..,1: I2S data for this channel pair is treated as a.."
bitfld.long 0x0 9. "LEFTJUST,Left Justify data." "0: Data is transferred between the FIFO and the I2S..,1: Data is transferred between the FIFO and the I2S.."
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bitfld.long 0x0 8. "RIGHTLOW,Right channel data is in the Low portion of FIFO data. Essentially  this swaps left and right channel data as it is transferred to or from the FIFO. This bit is not used if the data width is greater than 24 bits or if PDMDATA = 1. Note that if.." "0: The right channel is taken from the high part of..,1: The right channel is taken from the low part of.."
bitfld.long 0x0 6.--7. "MODE,Selects the basic I2S operating mode. Other configurations modify this to obtain all supported cases. See Formats and modes for examples." "0: I2S mode a.k.a. 'classic' mode. WS has a 50%..,1: DSP mode where WS has a 50% duty cycle. See..,2: DSP mode where WS has a one clock long pulse at..,3: DSP mode where WS has a one data slot long pulse.."
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bitfld.long 0x0 4.--5. "MSTSLVCFG,Master / slave configuration selection  determining how SCK and WS are used by all channel pairs in this Flexcomm." "0: Normal slave mode the default mode. SCK and WS..,1: WS synchronized master. WS is received from..,2: Master using an existing SCK. SCK is received..,3: Normal master mode. SCK and WS are generated so.."
bitfld.long 0x0 2.--3. "PAIRCOUNT,Provides the number of I2S channel pairs in this Flexcomm This is a read-only field whose value may be different in other Flexcomms. 00 = there is 1 I2S channel pair in this Flexcomm. 01 = there are 2 I2S channel pairs in this Flexcomm. 10 =.." "0: there is 1 I2S channel pair in this Flexcomm,1: there are 2 I2S channel pairs in this Flexcomm,2: 3 I2S channel pairs in this flexcomm,3: 4 I2S channel pairs in this flexcomm"
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bitfld.long 0x0 1. "DATAPAUSE,Data flow Pause. Allows pausing data flow between the I2S serializer/deserializer and the FIFO. This could be done in order to change streams  or while restarting after a data underflow or overflow. When paused  FIFO operations can be done.." "0: Normal operation or resuming normal operation at..,1: A pause in the data flow is being requested. It.."
bitfld.long 0x0 0. "MAINENABLE,Main enable for I 2S function in this Flexcomm" "0: All I 2S channel pairs in this Flexcomm are..,1: This I 2S channel pair is enabled. Other channel.."
line.long 0x4 "CFG2,Configuration register 2 for the primary channel pair."
hexmask.long.word 0x4 16.--24. 1. "POSITION,Data Position. Defines the location within the frame of the data for this channel pair. POSITION + DATALEN must be less than FRAMELEN. See Frame format. When MODE = 0  POSITION defines the location of data in both the left phase and right phase .."
hexmask.long.word 0x4 0.--8. 1. "FRAMELEN,Frame Length  minus 1 encoded  defines the number of clocks and data bits in the frames that this channel pair participates in. See Frame format. 0x000 to 0x002 = not supported 0x003 = frame is 4 bits in total length 0x004 = frame is 5 bits in.."
line.long 0x8 "STAT,Status register for the primary channel pair."
rbitfld.long 0x8 3. "DATAPAUSED,Data Paused status flag. Applies to all I2S channels" "0: Data is not currently paused. A data pause may..,1: A data pause has been requested and is now in.."
rbitfld.long 0x8 2. "LR,Left/Right indication. This flag is considered to be a debugging aid and is not expected to be used by an I2S driver. Valid when one channel pair is busy. Indicates left or right data being processed for the currently busy channel pair." "0: Left channel.,1: Right channel."
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bitfld.long 0x8 1. "SLVFRMERR,Slave Frame Error flag. This applies when at least one channel pair is operating as a slave. An error indicates that the incoming WS signal did not transition as expected due to a mismatch between FRAMELEN and the actual incoming I2S stream." "0: No error has been recorded.,1: An error has been recorded for some channel pair.."
rbitfld.long 0x8 0. "BUSY,Busy status for the primary channel pair. Other BUSY flags may be found in the STAT register for each channel pair." "0: The transmitter/receiver for channel pair is..,1: The transmitter/receiver for channel pair is.."
group.long 0xC1C++0x3
line.long 0x0 "DIV,Clock divider. used by all channel pairs."
hexmask.long.word 0x0 0.--11. 1. "DIV,This field controls how this I2S block uses the Flexcomm function clock. 0x000 = The Flexcomm function clock is used directly. 0x001 = The Flexcomm function clock is divided by 2. 0x002 = The Flexcomm function clock is divided by 3. 0xFFF = The.."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
newline
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 3. "PACK48,Packing format for 48-bit data. This relates to how data is entered into or taken from the FIFO by software or DMA." "0: 48-bit I2S FIFO entries are handled as all..,1: 48-bit I2S FIFO entries are handled as.."
bitfld.long 0x0 2. "TXI2SE0,Transmit I2S empty 0. Determines the value sent by the I2S in transmit mode if the TX FIFO becomes empty. This value is sent repeatedly until the I2S is paused  the error is cleared  new data is provided  and the I2S is un-paused." "0: If the TX FIFO becomes empty the last value is..,1: If the TX FIFO becomes empty 0 is sent. Use if.."
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
newline
bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
wgroup.long 0xE20++0x7
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long 0x0 0.--31. 1. "TXDATA,Transmit data to the FIFO. The number of bits used depends on configuration details."
line.long 0x4 "FIFOWR48H,FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA."
hexmask.long.tbyte 0x4 0.--23. 1. "TXDATA,Transmit data to the FIFO. Whether this register is used and the number of bits used depends on configuration details."
rgroup.long 0xE30++0x7
line.long 0x0 "FIFORD,FIFO read data."
hexmask.long 0x0 0.--31. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on configuration details."
line.long 0x4 "FIFORD48H,FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA."
hexmask.long.tbyte 0x4 0.--23. 1. "RXDATA,Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details."
rgroup.long 0xE40++0x7
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
hexmask.long 0x0 0.--31. 1. "RXDATA,Received data from the FIFO."
line.long 0x4 "FIFORD48HNOPOP,FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA."
hexmask.long.tbyte 0x4 0.--23. 1. "RXDATA,Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details."
rgroup.long 0x1DFC++0x3
line.long 0x0 "ID,I2S Module identification"
hexmask.long.word 0x0 16.--31. 1. "ID,Unique module identifier for this IP block."
hexmask.long.byte 0x0 12.--15. 1. "Major_Rev,Major revision of module implementation  starting at 0."
newline
hexmask.long.byte 0x0 8.--11. 1. "Minor_Rev,Minor revision of module implementation  starting at 0."
hexmask.long.byte 0x0 0.--7. 1. "Aperture,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2S1"
base ad:0x40098000
repeat 3. (list 0x0 0x1 0x2)(list ad:0x40098000 ad:0x40098020 ad:0x40098040)
tree "SECCHANNEL[$1]"
base $2
group.long ($2+0xC20)++0xB
line.long 0x0 "PCFG1,Configuration register 1 for channel pair"
bitfld.long 0x0 10. "ONECHANNEL,Single channel mode." "0,1"
bitfld.long 0x0 0. "PAIRENABLE,Enable for this channel pair.." "0,1"
line.long 0x4 "PCFG2,Configuration register 2 for channel pair"
hexmask.long.word 0x4 16.--24. 1. "POSITION,Data Position."
line.long 0x8 "PSTAT,Status register for channel pair"
rbitfld.long 0x8 3. "DATAPAUSED,Data Paused status flag." "0,1"
bitfld.long 0x8 2. "LR,Left/Right indication." "0,1"
bitfld.long 0x8 1. "SLVFRMERR,Save Frame Error flag." "0,1"
bitfld.long 0x8 0. "BUSY,Busy status for this channel pair." "0,1"
tree.end
repeat.end
base ad:0x40098000
group.long 0xC00++0xB
line.long 0x0 "CFG1,Configuration register 1 for the primary channel pair."
hexmask.long.byte 0x0 16.--20. 1. "DATALEN,Data Length  minus 1 encoded  defines the number of data bits to be transmitted or received for all I2S channel pairs in this Flexcomm. Note that data is only driven to or received from SDA for the number of bits defined by DATALEN. DATALEN is.."
bitfld.long 0x0 13. "WS_POL,WS polarity." "0: Data frames begin at a falling edge of WS..,1: WS is inverted resulting in a data frame.."
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bitfld.long 0x0 12. "SCK_POL,SCK polarity." "0: Data is launched on SCK falling edges and..,1: Data is launched on SCK rising edges and sampled.."
bitfld.long 0x0 11. "PDMDATA,PDM Data selection. This bit controls the data source for I2S transmit  and cannot be set in Rx mode. This bit only has an effect if the device the Flexcomm resides in includes a D-Mic subsystem. For the LPC5411x  this bit applies only to.." "0: Normal operation data is transferred to or from..,1: The data source is the D-Mic subsystem. When.."
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bitfld.long 0x0 10. "ONECHANNEL,Single channel mode. Applies to both transmit and receive. This configuration bit applies only to the first I2S channel pair. Other channel pairs may select this mode independently in their separate CFG1 registers." "0: I2S data for this channel pair is treated as..,1: I2S data for this channel pair is treated as a.."
bitfld.long 0x0 9. "LEFTJUST,Left Justify data." "0: Data is transferred between the FIFO and the I2S..,1: Data is transferred between the FIFO and the I2S.."
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bitfld.long 0x0 8. "RIGHTLOW,Right channel data is in the Low portion of FIFO data. Essentially  this swaps left and right channel data as it is transferred to or from the FIFO. This bit is not used if the data width is greater than 24 bits or if PDMDATA = 1. Note that if.." "0: The right channel is taken from the high part of..,1: The right channel is taken from the low part of.."
bitfld.long 0x0 6.--7. "MODE,Selects the basic I2S operating mode. Other configurations modify this to obtain all supported cases. See Formats and modes for examples." "0: I2S mode a.k.a. 'classic' mode. WS has a 50%..,1: DSP mode where WS has a 50% duty cycle. See..,2: DSP mode where WS has a one clock long pulse at..,3: DSP mode where WS has a one data slot long pulse.."
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bitfld.long 0x0 4.--5. "MSTSLVCFG,Master / slave configuration selection  determining how SCK and WS are used by all channel pairs in this Flexcomm." "0: Normal slave mode the default mode. SCK and WS..,1: WS synchronized master. WS is received from..,2: Master using an existing SCK. SCK is received..,3: Normal master mode. SCK and WS are generated so.."
bitfld.long 0x0 2.--3. "PAIRCOUNT,Provides the number of I2S channel pairs in this Flexcomm This is a read-only field whose value may be different in other Flexcomms. 00 = there is 1 I2S channel pair in this Flexcomm. 01 = there are 2 I2S channel pairs in this Flexcomm. 10 =.." "0: there is 1 I2S channel pair in this Flexcomm,1: there are 2 I2S channel pairs in this Flexcomm,2: 3 I2S channel pairs in this flexcomm,3: 4 I2S channel pairs in this flexcomm"
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bitfld.long 0x0 1. "DATAPAUSE,Data flow Pause. Allows pausing data flow between the I2S serializer/deserializer and the FIFO. This could be done in order to change streams  or while restarting after a data underflow or overflow. When paused  FIFO operations can be done.." "0: Normal operation or resuming normal operation at..,1: A pause in the data flow is being requested. It.."
bitfld.long 0x0 0. "MAINENABLE,Main enable for I 2S function in this Flexcomm" "0: All I 2S channel pairs in this Flexcomm are..,1: This I 2S channel pair is enabled. Other channel.."
line.long 0x4 "CFG2,Configuration register 2 for the primary channel pair."
hexmask.long.word 0x4 16.--24. 1. "POSITION,Data Position. Defines the location within the frame of the data for this channel pair. POSITION + DATALEN must be less than FRAMELEN. See Frame format. When MODE = 0  POSITION defines the location of data in both the left phase and right phase .."
hexmask.long.word 0x4 0.--8. 1. "FRAMELEN,Frame Length  minus 1 encoded  defines the number of clocks and data bits in the frames that this channel pair participates in. See Frame format. 0x000 to 0x002 = not supported 0x003 = frame is 4 bits in total length 0x004 = frame is 5 bits in.."
line.long 0x8 "STAT,Status register for the primary channel pair."
rbitfld.long 0x8 3. "DATAPAUSED,Data Paused status flag. Applies to all I2S channels" "0: Data is not currently paused. A data pause may..,1: A data pause has been requested and is now in.."
rbitfld.long 0x8 2. "LR,Left/Right indication. This flag is considered to be a debugging aid and is not expected to be used by an I2S driver. Valid when one channel pair is busy. Indicates left or right data being processed for the currently busy channel pair." "0: Left channel.,1: Right channel."
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bitfld.long 0x8 1. "SLVFRMERR,Slave Frame Error flag. This applies when at least one channel pair is operating as a slave. An error indicates that the incoming WS signal did not transition as expected due to a mismatch between FRAMELEN and the actual incoming I2S stream." "0: No error has been recorded.,1: An error has been recorded for some channel pair.."
rbitfld.long 0x8 0. "BUSY,Busy status for the primary channel pair. Other BUSY flags may be found in the STAT register for each channel pair." "0: The transmitter/receiver for channel pair is..,1: The transmitter/receiver for channel pair is.."
group.long 0xC1C++0x3
line.long 0x0 "DIV,Clock divider. used by all channel pairs."
hexmask.long.word 0x0 0.--11. 1. "DIV,This field controls how this I2S block uses the Flexcomm function clock. 0x000 = The Flexcomm function clock is used directly. 0x001 = The Flexcomm function clock is divided by 2. 0x002 = The Flexcomm function clock is divided by 3. 0xFFF = The.."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 3. "PACK48,Packing format for 48-bit data. This relates to how data is entered into or taken from the FIFO by software or DMA." "0: 48-bit I2S FIFO entries are handled as all..,1: 48-bit I2S FIFO entries are handled as.."
bitfld.long 0x0 2. "TXI2SE0,Transmit I2S empty 0. Determines the value sent by the I2S in transmit mode if the TX FIFO becomes empty. This value is sent repeatedly until the I2S is paused  the error is cleared  new data is provided  and the I2S is un-paused." "0: If the TX FIFO becomes empty the last value is..,1: If the TX FIFO becomes empty 0 is sent. Use if.."
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
wgroup.long 0xE20++0x7
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long 0x0 0.--31. 1. "TXDATA,Transmit data to the FIFO. The number of bits used depends on configuration details."
line.long 0x4 "FIFOWR48H,FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA."
hexmask.long.tbyte 0x4 0.--23. 1. "TXDATA,Transmit data to the FIFO. Whether this register is used and the number of bits used depends on configuration details."
rgroup.long 0xE30++0x7
line.long 0x0 "FIFORD,FIFO read data."
hexmask.long 0x0 0.--31. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on configuration details."
line.long 0x4 "FIFORD48H,FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA."
hexmask.long.tbyte 0x4 0.--23. 1. "RXDATA,Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details."
rgroup.long 0xE40++0x7
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
hexmask.long 0x0 0.--31. 1. "RXDATA,Received data from the FIFO."
line.long 0x4 "FIFORD48HNOPOP,FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA."
hexmask.long.tbyte 0x4 0.--23. 1. "RXDATA,Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details."
rgroup.long 0x1DFC++0x3
line.long 0x0 "ID,I2S Module identification"
hexmask.long.word 0x0 16.--31. 1. "ID,Unique module identifier for this IP block."
hexmask.long.byte 0x0 12.--15. 1. "Major_Rev,Major revision of module implementation  starting at 0."
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hexmask.long.byte 0x0 8.--11. 1. "Minor_Rev,Minor revision of module implementation  starting at 0."
hexmask.long.byte 0x0 0.--7. 1. "Aperture,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
endif
sif (cpuis("LPC54616*"))
tree "I2S0"
base ad:0x40097000
repeat 3. (list 0x0 0x1 0x2)(list ad:0x40097000 ad:0x40097020 ad:0x40097040)
tree "SECCHANNEL[$1]"
base $2
group.long ($2+0xC20)++0xB
line.long 0x0 "PCFG1,Configuration register 1 for channel pair"
bitfld.long 0x0 10. "ONECHANNEL,Single channel mode." "0,1"
bitfld.long 0x0 0. "PAIRENABLE,Enable for this channel pair.." "0,1"
line.long 0x4 "PCFG2,Configuration register 2 for channel pair"
hexmask.long.word 0x4 16.--24. 1. "POSITION,Data Position."
line.long 0x8 "PSTAT,Status register for channel pair"
rbitfld.long 0x8 3. "DATAPAUSED,Data Paused status flag." "0,1"
bitfld.long 0x8 2. "LR,Left/Right indication." "0,1"
bitfld.long 0x8 1. "SLVFRMERR,Save Frame Error flag." "0,1"
bitfld.long 0x8 0. "BUSY,Busy status for this channel pair." "0,1"
tree.end
repeat.end
base ad:0x40097000
group.long 0xC00++0xB
line.long 0x0 "CFG1,Configuration register 1 for the primary channel pair."
hexmask.long.byte 0x0 16.--20. 1. "DATALEN,Data Length  minus 1 encoded  defines the number of data bits to be transmitted or received for all I2S channel pairs in this Flexcomm. Note that data is only driven to or received from SDA for the number of bits defined by DATALEN. DATALEN is.."
bitfld.long 0x0 13. "WS_POL,WS polarity." "0: Data frames begin at a falling edge of WS..,1: WS is inverted resulting in a data frame.."
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bitfld.long 0x0 12. "SCK_POL,SCK polarity." "0: Data is launched on SCK falling edges and..,1: Data is launched on SCK rising edges and sampled.."
bitfld.long 0x0 11. "PDMDATA,PDM Data selection. This bit controls the data source for I2S transmit  and cannot be set in Rx mode. This bit only has an effect if the device the Flexcomm resides in includes a D-Mic subsystem. For the LPC5411x  this bit applies only to.." "0: Normal operation data is transferred to or from..,1: The data source is the D-Mic subsystem. When.."
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bitfld.long 0x0 10. "ONECHANNEL,Single channel mode. Applies to both transmit and receive. This configuration bit applies only to the first I2S channel pair. Other channel pairs may select this mode independently in their separate CFG1 registers." "0: I2S data for this channel pair is treated as..,1: I2S data for this channel pair is treated as a.."
bitfld.long 0x0 9. "LEFTJUST,Left Justify data." "0: Data is transferred between the FIFO and the I2S..,1: Data is transferred between the FIFO and the I2S.."
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bitfld.long 0x0 8. "RIGHTLOW,Right channel data is in the Low portion of FIFO data. Essentially  this swaps left and right channel data as it is transferred to or from the FIFO. This bit is not used if the data width is greater than 24 bits or if PDMDATA = 1. Note that if.." "0: The right channel is taken from the high part of..,1: The right channel is taken from the low part of.."
bitfld.long 0x0 6.--7. "MODE,Selects the basic I2S operating mode. Other configurations modify this to obtain all supported cases. See Formats and modes for examples." "0: I2S mode a.k.a. 'classic' mode. WS has a 50%..,1: DSP mode where WS has a 50% duty cycle. See..,2: DSP mode where WS has a one clock long pulse at..,3: DSP mode where WS has a one data slot long pulse.."
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bitfld.long 0x0 4.--5. "MSTSLVCFG,Master / slave configuration selection  determining how SCK and WS are used by all channel pairs in this Flexcomm." "0: Normal slave mode the default mode. SCK and WS..,1: WS synchronized master. WS is received from..,2: Master using an existing SCK. SCK is received..,3: Normal master mode. SCK and WS are generated so.."
bitfld.long 0x0 2.--3. "PAIRCOUNT,Provides the number of I2S channel pairs in this Flexcomm This is a read-only field whose value may be different in other Flexcomms. 00 = there is 1 I2S channel pair in this Flexcomm. 01 = there are 2 I2S channel pairs in this Flexcomm. 10 =.." "0: there is 1 I2S channel pair in this Flexcomm,1: there are 2 I2S channel pairs in this Flexcomm,2: 3 I2S channel pairs in this flexcomm,3: 4 I2S channel pairs in this flexcomm"
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bitfld.long 0x0 1. "DATAPAUSE,Data flow Pause. Allows pausing data flow between the I2S serializer/deserializer and the FIFO. This could be done in order to change streams  or while restarting after a data underflow or overflow. When paused  FIFO operations can be done.." "0: Normal operation or resuming normal operation at..,1: A pause in the data flow is being requested. It.."
bitfld.long 0x0 0. "MAINENABLE,Main enable for I 2S function in this Flexcomm" "0: All I 2S channel pairs in this Flexcomm are..,1: This I 2S channel pair is enabled. Other channel.."
line.long 0x4 "CFG2,Configuration register 2 for the primary channel pair."
hexmask.long.word 0x4 16.--24. 1. "POSITION,Data Position. Defines the location within the frame of the data for this channel pair. POSITION + DATALEN must be less than FRAMELEN. See Frame format. When MODE = 0  POSITION defines the location of data in both the left phase and right phase .."
hexmask.long.word 0x4 0.--8. 1. "FRAMELEN,Frame Length  minus 1 encoded  defines the number of clocks and data bits in the frames that this channel pair participates in. See Frame format. 0x000 to 0x002 = not supported 0x003 = frame is 4 bits in total length 0x004 = frame is 5 bits in.."
line.long 0x8 "STAT,Status register for the primary channel pair."
rbitfld.long 0x8 3. "DATAPAUSED,Data Paused status flag. Applies to all I2S channels" "0: Data is not currently paused. A data pause may..,1: A data pause has been requested and is now in.."
rbitfld.long 0x8 2. "LR,Left/Right indication. This flag is considered to be a debugging aid and is not expected to be used by an I2S driver. Valid when one channel pair is busy. Indicates left or right data being processed for the currently busy channel pair." "0: Left channel.,1: Right channel."
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bitfld.long 0x8 1. "SLVFRMERR,Slave Frame Error flag. This applies when at least one channel pair is operating as a slave. An error indicates that the incoming WS signal did not transition as expected due to a mismatch between FRAMELEN and the actual incoming I2S stream." "0: No error has been recorded.,1: An error has been recorded for some channel pair.."
rbitfld.long 0x8 0. "BUSY,Busy status for the primary channel pair. Other BUSY flags may be found in the STAT register for each channel pair." "0: The transmitter/receiver for channel pair is..,1: The transmitter/receiver for channel pair is.."
group.long 0xC1C++0x3
line.long 0x0 "DIV,Clock divider. used by all channel pairs."
hexmask.long.word 0x0 0.--11. 1. "DIV,This field controls how this I2S block uses the Flexcomm function clock. 0x000 = The Flexcomm function clock is used directly. 0x001 = The Flexcomm function clock is divided by 2. 0x002 = The Flexcomm function clock is divided by 3. 0xFFF = The.."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 3. "PACK48,Packing format for 48-bit data. This relates to how data is entered into or taken from the FIFO by software or DMA." "0: 48-bit I2S FIFO entries are handled as all..,1: 48-bit I2S FIFO entries are handled as.."
bitfld.long 0x0 2. "TXI2SE0,Transmit I2S empty 0. Determines the value sent by the I2S in transmit mode if the TX FIFO becomes empty. This value is sent repeatedly until the I2S is paused  the error is cleared  new data is provided  and the I2S is un-paused." "0: If the TX FIFO becomes empty the last value is..,1: If the TX FIFO becomes empty 0 is sent. Use if.."
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
newline
bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
newline
bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
newline
bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
newline
bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
wgroup.long 0xE20++0x7
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long 0x0 0.--31. 1. "TXDATA,Transmit data to the FIFO. The number of bits used depends on configuration details."
line.long 0x4 "FIFOWR48H,FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA."
hexmask.long.tbyte 0x4 0.--23. 1. "TXDATA,Transmit data to the FIFO. Whether this register is used and the number of bits used depends on configuration details."
rgroup.long 0xE30++0x7
line.long 0x0 "FIFORD,FIFO read data."
hexmask.long 0x0 0.--31. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on configuration details."
line.long 0x4 "FIFORD48H,FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA."
hexmask.long.tbyte 0x4 0.--23. 1. "RXDATA,Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details."
rgroup.long 0xE40++0x7
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
hexmask.long 0x0 0.--31. 1. "RXDATA,Received data from the FIFO."
line.long 0x4 "FIFORD48HNOPOP,FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA."
hexmask.long.tbyte 0x4 0.--23. 1. "RXDATA,Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details."
rgroup.long 0x1DFC++0x3
line.long 0x0 "ID,I2S Module identification"
hexmask.long.word 0x0 16.--31. 1. "ID,Unique module identifier for this IP block."
hexmask.long.byte 0x0 12.--15. 1. "Major_Rev,Major revision of module implementation  starting at 0."
newline
hexmask.long.byte 0x0 8.--11. 1. "Minor_Rev,Minor revision of module implementation  starting at 0."
hexmask.long.byte 0x0 0.--7. 1. "Aperture,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2S1"
base ad:0x40098000
repeat 3. (list 0x0 0x1 0x2)(list ad:0x40098000 ad:0x40098020 ad:0x40098040)
tree "SECCHANNEL[$1]"
base $2
group.long ($2+0xC20)++0xB
line.long 0x0 "PCFG1,Configuration register 1 for channel pair"
bitfld.long 0x0 10. "ONECHANNEL,Single channel mode." "0,1"
bitfld.long 0x0 0. "PAIRENABLE,Enable for this channel pair.." "0,1"
line.long 0x4 "PCFG2,Configuration register 2 for channel pair"
hexmask.long.word 0x4 16.--24. 1. "POSITION,Data Position."
line.long 0x8 "PSTAT,Status register for channel pair"
rbitfld.long 0x8 3. "DATAPAUSED,Data Paused status flag." "0,1"
bitfld.long 0x8 2. "LR,Left/Right indication." "0,1"
bitfld.long 0x8 1. "SLVFRMERR,Save Frame Error flag." "0,1"
bitfld.long 0x8 0. "BUSY,Busy status for this channel pair." "0,1"
tree.end
repeat.end
base ad:0x40098000
group.long 0xC00++0xB
line.long 0x0 "CFG1,Configuration register 1 for the primary channel pair."
hexmask.long.byte 0x0 16.--20. 1. "DATALEN,Data Length  minus 1 encoded  defines the number of data bits to be transmitted or received for all I2S channel pairs in this Flexcomm. Note that data is only driven to or received from SDA for the number of bits defined by DATALEN. DATALEN is.."
bitfld.long 0x0 13. "WS_POL,WS polarity." "0: Data frames begin at a falling edge of WS..,1: WS is inverted resulting in a data frame.."
newline
bitfld.long 0x0 12. "SCK_POL,SCK polarity." "0: Data is launched on SCK falling edges and..,1: Data is launched on SCK rising edges and sampled.."
bitfld.long 0x0 11. "PDMDATA,PDM Data selection. This bit controls the data source for I2S transmit  and cannot be set in Rx mode. This bit only has an effect if the device the Flexcomm resides in includes a D-Mic subsystem. For the LPC5411x  this bit applies only to.." "0: Normal operation data is transferred to or from..,1: The data source is the D-Mic subsystem. When.."
newline
bitfld.long 0x0 10. "ONECHANNEL,Single channel mode. Applies to both transmit and receive. This configuration bit applies only to the first I2S channel pair. Other channel pairs may select this mode independently in their separate CFG1 registers." "0: I2S data for this channel pair is treated as..,1: I2S data for this channel pair is treated as a.."
bitfld.long 0x0 9. "LEFTJUST,Left Justify data." "0: Data is transferred between the FIFO and the I2S..,1: Data is transferred between the FIFO and the I2S.."
newline
bitfld.long 0x0 8. "RIGHTLOW,Right channel data is in the Low portion of FIFO data. Essentially  this swaps left and right channel data as it is transferred to or from the FIFO. This bit is not used if the data width is greater than 24 bits or if PDMDATA = 1. Note that if.." "0: The right channel is taken from the high part of..,1: The right channel is taken from the low part of.."
bitfld.long 0x0 6.--7. "MODE,Selects the basic I2S operating mode. Other configurations modify this to obtain all supported cases. See Formats and modes for examples." "0: I2S mode a.k.a. 'classic' mode. WS has a 50%..,1: DSP mode where WS has a 50% duty cycle. See..,2: DSP mode where WS has a one clock long pulse at..,3: DSP mode where WS has a one data slot long pulse.."
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bitfld.long 0x0 4.--5. "MSTSLVCFG,Master / slave configuration selection  determining how SCK and WS are used by all channel pairs in this Flexcomm." "0: Normal slave mode the default mode. SCK and WS..,1: WS synchronized master. WS is received from..,2: Master using an existing SCK. SCK is received..,3: Normal master mode. SCK and WS are generated so.."
bitfld.long 0x0 2.--3. "PAIRCOUNT,Provides the number of I2S channel pairs in this Flexcomm This is a read-only field whose value may be different in other Flexcomms. 00 = there is 1 I2S channel pair in this Flexcomm. 01 = there are 2 I2S channel pairs in this Flexcomm. 10 =.." "0: there is 1 I2S channel pair in this Flexcomm,1: there are 2 I2S channel pairs in this Flexcomm,2: 3 I2S channel pairs in this flexcomm,3: 4 I2S channel pairs in this flexcomm"
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bitfld.long 0x0 1. "DATAPAUSE,Data flow Pause. Allows pausing data flow between the I2S serializer/deserializer and the FIFO. This could be done in order to change streams  or while restarting after a data underflow or overflow. When paused  FIFO operations can be done.." "0: Normal operation or resuming normal operation at..,1: A pause in the data flow is being requested. It.."
bitfld.long 0x0 0. "MAINENABLE,Main enable for I 2S function in this Flexcomm" "0: All I 2S channel pairs in this Flexcomm are..,1: This I 2S channel pair is enabled. Other channel.."
line.long 0x4 "CFG2,Configuration register 2 for the primary channel pair."
hexmask.long.word 0x4 16.--24. 1. "POSITION,Data Position. Defines the location within the frame of the data for this channel pair. POSITION + DATALEN must be less than FRAMELEN. See Frame format. When MODE = 0  POSITION defines the location of data in both the left phase and right phase .."
hexmask.long.word 0x4 0.--8. 1. "FRAMELEN,Frame Length  minus 1 encoded  defines the number of clocks and data bits in the frames that this channel pair participates in. See Frame format. 0x000 to 0x002 = not supported 0x003 = frame is 4 bits in total length 0x004 = frame is 5 bits in.."
line.long 0x8 "STAT,Status register for the primary channel pair."
rbitfld.long 0x8 3. "DATAPAUSED,Data Paused status flag. Applies to all I2S channels" "0: Data is not currently paused. A data pause may..,1: A data pause has been requested and is now in.."
rbitfld.long 0x8 2. "LR,Left/Right indication. This flag is considered to be a debugging aid and is not expected to be used by an I2S driver. Valid when one channel pair is busy. Indicates left or right data being processed for the currently busy channel pair." "0: Left channel.,1: Right channel."
newline
bitfld.long 0x8 1. "SLVFRMERR,Slave Frame Error flag. This applies when at least one channel pair is operating as a slave. An error indicates that the incoming WS signal did not transition as expected due to a mismatch between FRAMELEN and the actual incoming I2S stream." "0: No error has been recorded.,1: An error has been recorded for some channel pair.."
rbitfld.long 0x8 0. "BUSY,Busy status for the primary channel pair. Other BUSY flags may be found in the STAT register for each channel pair." "0: The transmitter/receiver for channel pair is..,1: The transmitter/receiver for channel pair is.."
group.long 0xC1C++0x3
line.long 0x0 "DIV,Clock divider. used by all channel pairs."
hexmask.long.word 0x0 0.--11. 1. "DIV,This field controls how this I2S block uses the Flexcomm function clock. 0x000 = The Flexcomm function clock is used directly. 0x001 = The Flexcomm function clock is divided by 2. 0x002 = The Flexcomm function clock is divided by 3. 0xFFF = The.."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
newline
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
newline
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
newline
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
newline
bitfld.long 0x0 3. "PACK48,Packing format for 48-bit data. This relates to how data is entered into or taken from the FIFO by software or DMA." "0: 48-bit I2S FIFO entries are handled as all..,1: 48-bit I2S FIFO entries are handled as.."
bitfld.long 0x0 2. "TXI2SE0,Transmit I2S empty 0. Determines the value sent by the I2S in transmit mode if the TX FIFO becomes empty. This value is sent repeatedly until the I2S is paused  the error is cleared  new data is provided  and the I2S is un-paused." "0: If the TX FIFO becomes empty the last value is..,1: If the TX FIFO becomes empty 0 is sent. Use if.."
newline
bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
newline
rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
newline
rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
newline
rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
newline
bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
newline
bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
newline
bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
newline
bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
newline
bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
newline
bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
wgroup.long 0xE20++0x7
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long 0x0 0.--31. 1. "TXDATA,Transmit data to the FIFO. The number of bits used depends on configuration details."
line.long 0x4 "FIFOWR48H,FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA."
hexmask.long.tbyte 0x4 0.--23. 1. "TXDATA,Transmit data to the FIFO. Whether this register is used and the number of bits used depends on configuration details."
rgroup.long 0xE30++0x7
line.long 0x0 "FIFORD,FIFO read data."
hexmask.long 0x0 0.--31. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on configuration details."
line.long 0x4 "FIFORD48H,FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA."
hexmask.long.tbyte 0x4 0.--23. 1. "RXDATA,Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details."
rgroup.long 0xE40++0x7
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
hexmask.long 0x0 0.--31. 1. "RXDATA,Received data from the FIFO."
line.long 0x4 "FIFORD48HNOPOP,FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA."
hexmask.long.tbyte 0x4 0.--23. 1. "RXDATA,Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details."
rgroup.long 0x1DFC++0x3
line.long 0x0 "ID,I2S Module identification"
hexmask.long.word 0x0 16.--31. 1. "ID,Unique module identifier for this IP block."
hexmask.long.byte 0x0 12.--15. 1. "Major_Rev,Major revision of module implementation  starting at 0."
newline
hexmask.long.byte 0x0 8.--11. 1. "Minor_Rev,Minor revision of module implementation  starting at 0."
hexmask.long.byte 0x0 0.--7. 1. "Aperture,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
endif
sif (cpuis("LPC54618*"))
tree "I2S0"
base ad:0x40097000
repeat 3. (list 0x0 0x1 0x2)(list ad:0x40097000 ad:0x40097020 ad:0x40097040)
tree "SECCHANNEL[$1]"
base $2
group.long ($2+0xC20)++0xB
line.long 0x0 "PCFG1,Configuration register 1 for channel pair"
bitfld.long 0x0 10. "ONECHANNEL,Single channel mode." "0,1"
bitfld.long 0x0 0. "PAIRENABLE,Enable for this channel pair.." "0,1"
line.long 0x4 "PCFG2,Configuration register 2 for channel pair"
hexmask.long.word 0x4 16.--24. 1. "POSITION,Data Position."
line.long 0x8 "PSTAT,Status register for channel pair"
rbitfld.long 0x8 3. "DATAPAUSED,Data Paused status flag." "0,1"
bitfld.long 0x8 2. "LR,Left/Right indication." "0,1"
bitfld.long 0x8 1. "SLVFRMERR,Save Frame Error flag." "0,1"
bitfld.long 0x8 0. "BUSY,Busy status for this channel pair." "0,1"
tree.end
repeat.end
base ad:0x40097000
group.long 0xC00++0xB
line.long 0x0 "CFG1,Configuration register 1 for the primary channel pair."
hexmask.long.byte 0x0 16.--20. 1. "DATALEN,Data Length  minus 1 encoded  defines the number of data bits to be transmitted or received for all I2S channel pairs in this Flexcomm. Note that data is only driven to or received from SDA for the number of bits defined by DATALEN. DATALEN is.."
bitfld.long 0x0 13. "WS_POL,WS polarity." "0: Data frames begin at a falling edge of WS..,1: WS is inverted resulting in a data frame.."
newline
bitfld.long 0x0 12. "SCK_POL,SCK polarity." "0: Data is launched on SCK falling edges and..,1: Data is launched on SCK rising edges and sampled.."
bitfld.long 0x0 11. "PDMDATA,PDM Data selection. This bit controls the data source for I2S transmit  and cannot be set in Rx mode. This bit only has an effect if the device the Flexcomm resides in includes a D-Mic subsystem. For the LPC5411x  this bit applies only to.." "0: Normal operation data is transferred to or from..,1: The data source is the D-Mic subsystem. When.."
newline
bitfld.long 0x0 10. "ONECHANNEL,Single channel mode. Applies to both transmit and receive. This configuration bit applies only to the first I2S channel pair. Other channel pairs may select this mode independently in their separate CFG1 registers." "0: I2S data for this channel pair is treated as..,1: I2S data for this channel pair is treated as a.."
bitfld.long 0x0 9. "LEFTJUST,Left Justify data." "0: Data is transferred between the FIFO and the I2S..,1: Data is transferred between the FIFO and the I2S.."
newline
bitfld.long 0x0 8. "RIGHTLOW,Right channel data is in the Low portion of FIFO data. Essentially  this swaps left and right channel data as it is transferred to or from the FIFO. This bit is not used if the data width is greater than 24 bits or if PDMDATA = 1. Note that if.." "0: The right channel is taken from the high part of..,1: The right channel is taken from the low part of.."
bitfld.long 0x0 6.--7. "MODE,Selects the basic I2S operating mode. Other configurations modify this to obtain all supported cases. See Formats and modes for examples." "0: I2S mode a.k.a. 'classic' mode. WS has a 50%..,1: DSP mode where WS has a 50% duty cycle. See..,2: DSP mode where WS has a one clock long pulse at..,3: DSP mode where WS has a one data slot long pulse.."
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bitfld.long 0x0 4.--5. "MSTSLVCFG,Master / slave configuration selection  determining how SCK and WS are used by all channel pairs in this Flexcomm." "0: Normal slave mode the default mode. SCK and WS..,1: WS synchronized master. WS is received from..,2: Master using an existing SCK. SCK is received..,3: Normal master mode. SCK and WS are generated so.."
bitfld.long 0x0 2.--3. "PAIRCOUNT,Provides the number of I2S channel pairs in this Flexcomm This is a read-only field whose value may be different in other Flexcomms. 00 = there is 1 I2S channel pair in this Flexcomm. 01 = there are 2 I2S channel pairs in this Flexcomm. 10 =.." "0: there is 1 I2S channel pair in this Flexcomm,1: there are 2 I2S channel pairs in this Flexcomm,2: 3 I2S channel pairs in this flexcomm,3: 4 I2S channel pairs in this flexcomm"
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bitfld.long 0x0 1. "DATAPAUSE,Data flow Pause. Allows pausing data flow between the I2S serializer/deserializer and the FIFO. This could be done in order to change streams  or while restarting after a data underflow or overflow. When paused  FIFO operations can be done.." "0: Normal operation or resuming normal operation at..,1: A pause in the data flow is being requested. It.."
bitfld.long 0x0 0. "MAINENABLE,Main enable for I 2S function in this Flexcomm" "0: All I 2S channel pairs in this Flexcomm are..,1: This I 2S channel pair is enabled. Other channel.."
line.long 0x4 "CFG2,Configuration register 2 for the primary channel pair."
hexmask.long.word 0x4 16.--24. 1. "POSITION,Data Position. Defines the location within the frame of the data for this channel pair. POSITION + DATALEN must be less than FRAMELEN. See Frame format. When MODE = 0  POSITION defines the location of data in both the left phase and right phase .."
hexmask.long.word 0x4 0.--8. 1. "FRAMELEN,Frame Length  minus 1 encoded  defines the number of clocks and data bits in the frames that this channel pair participates in. See Frame format. 0x000 to 0x002 = not supported 0x003 = frame is 4 bits in total length 0x004 = frame is 5 bits in.."
line.long 0x8 "STAT,Status register for the primary channel pair."
rbitfld.long 0x8 3. "DATAPAUSED,Data Paused status flag. Applies to all I2S channels" "0: Data is not currently paused. A data pause may..,1: A data pause has been requested and is now in.."
rbitfld.long 0x8 2. "LR,Left/Right indication. This flag is considered to be a debugging aid and is not expected to be used by an I2S driver. Valid when one channel pair is busy. Indicates left or right data being processed for the currently busy channel pair." "0: Left channel.,1: Right channel."
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bitfld.long 0x8 1. "SLVFRMERR,Slave Frame Error flag. This applies when at least one channel pair is operating as a slave. An error indicates that the incoming WS signal did not transition as expected due to a mismatch between FRAMELEN and the actual incoming I2S stream." "0: No error has been recorded.,1: An error has been recorded for some channel pair.."
rbitfld.long 0x8 0. "BUSY,Busy status for the primary channel pair. Other BUSY flags may be found in the STAT register for each channel pair." "0: The transmitter/receiver for channel pair is..,1: The transmitter/receiver for channel pair is.."
group.long 0xC1C++0x3
line.long 0x0 "DIV,Clock divider. used by all channel pairs."
hexmask.long.word 0x0 0.--11. 1. "DIV,This field controls how this I2S block uses the Flexcomm function clock. 0x000 = The Flexcomm function clock is used directly. 0x001 = The Flexcomm function clock is divided by 2. 0x002 = The Flexcomm function clock is divided by 3. 0xFFF = The.."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 3. "PACK48,Packing format for 48-bit data. This relates to how data is entered into or taken from the FIFO by software or DMA." "0: 48-bit I2S FIFO entries are handled as all..,1: 48-bit I2S FIFO entries are handled as.."
bitfld.long 0x0 2. "TXI2SE0,Transmit I2S empty 0. Determines the value sent by the I2S in transmit mode if the TX FIFO becomes empty. This value is sent repeatedly until the I2S is paused  the error is cleared  new data is provided  and the I2S is un-paused." "0: If the TX FIFO becomes empty the last value is..,1: If the TX FIFO becomes empty 0 is sent. Use if.."
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
wgroup.long 0xE20++0x7
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long 0x0 0.--31. 1. "TXDATA,Transmit data to the FIFO. The number of bits used depends on configuration details."
line.long 0x4 "FIFOWR48H,FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA."
hexmask.long.tbyte 0x4 0.--23. 1. "TXDATA,Transmit data to the FIFO. Whether this register is used and the number of bits used depends on configuration details."
rgroup.long 0xE30++0x7
line.long 0x0 "FIFORD,FIFO read data."
hexmask.long 0x0 0.--31. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on configuration details."
line.long 0x4 "FIFORD48H,FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA."
hexmask.long.tbyte 0x4 0.--23. 1. "RXDATA,Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details."
rgroup.long 0xE40++0x7
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
hexmask.long 0x0 0.--31. 1. "RXDATA,Received data from the FIFO."
line.long 0x4 "FIFORD48HNOPOP,FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA."
hexmask.long.tbyte 0x4 0.--23. 1. "RXDATA,Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details."
rgroup.long 0x1DFC++0x3
line.long 0x0 "ID,I2S Module identification"
hexmask.long.word 0x0 16.--31. 1. "ID,Unique module identifier for this IP block."
hexmask.long.byte 0x0 12.--15. 1. "Major_Rev,Major revision of module implementation  starting at 0."
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hexmask.long.byte 0x0 8.--11. 1. "Minor_Rev,Minor revision of module implementation  starting at 0."
hexmask.long.byte 0x0 0.--7. 1. "Aperture,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2S1"
base ad:0x40098000
repeat 3. (list 0x0 0x1 0x2)(list ad:0x40098000 ad:0x40098020 ad:0x40098040)
tree "SECCHANNEL[$1]"
base $2
group.long ($2+0xC20)++0xB
line.long 0x0 "PCFG1,Configuration register 1 for channel pair"
bitfld.long 0x0 10. "ONECHANNEL,Single channel mode." "0,1"
bitfld.long 0x0 0. "PAIRENABLE,Enable for this channel pair.." "0,1"
line.long 0x4 "PCFG2,Configuration register 2 for channel pair"
hexmask.long.word 0x4 16.--24. 1. "POSITION,Data Position."
line.long 0x8 "PSTAT,Status register for channel pair"
rbitfld.long 0x8 3. "DATAPAUSED,Data Paused status flag." "0,1"
bitfld.long 0x8 2. "LR,Left/Right indication." "0,1"
bitfld.long 0x8 1. "SLVFRMERR,Save Frame Error flag." "0,1"
bitfld.long 0x8 0. "BUSY,Busy status for this channel pair." "0,1"
tree.end
repeat.end
base ad:0x40098000
group.long 0xC00++0xB
line.long 0x0 "CFG1,Configuration register 1 for the primary channel pair."
hexmask.long.byte 0x0 16.--20. 1. "DATALEN,Data Length  minus 1 encoded  defines the number of data bits to be transmitted or received for all I2S channel pairs in this Flexcomm. Note that data is only driven to or received from SDA for the number of bits defined by DATALEN. DATALEN is.."
bitfld.long 0x0 13. "WS_POL,WS polarity." "0: Data frames begin at a falling edge of WS..,1: WS is inverted resulting in a data frame.."
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bitfld.long 0x0 12. "SCK_POL,SCK polarity." "0: Data is launched on SCK falling edges and..,1: Data is launched on SCK rising edges and sampled.."
bitfld.long 0x0 11. "PDMDATA,PDM Data selection. This bit controls the data source for I2S transmit  and cannot be set in Rx mode. This bit only has an effect if the device the Flexcomm resides in includes a D-Mic subsystem. For the LPC5411x  this bit applies only to.." "0: Normal operation data is transferred to or from..,1: The data source is the D-Mic subsystem. When.."
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bitfld.long 0x0 10. "ONECHANNEL,Single channel mode. Applies to both transmit and receive. This configuration bit applies only to the first I2S channel pair. Other channel pairs may select this mode independently in their separate CFG1 registers." "0: I2S data for this channel pair is treated as..,1: I2S data for this channel pair is treated as a.."
bitfld.long 0x0 9. "LEFTJUST,Left Justify data." "0: Data is transferred between the FIFO and the I2S..,1: Data is transferred between the FIFO and the I2S.."
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bitfld.long 0x0 8. "RIGHTLOW,Right channel data is in the Low portion of FIFO data. Essentially  this swaps left and right channel data as it is transferred to or from the FIFO. This bit is not used if the data width is greater than 24 bits or if PDMDATA = 1. Note that if.." "0: The right channel is taken from the high part of..,1: The right channel is taken from the low part of.."
bitfld.long 0x0 6.--7. "MODE,Selects the basic I2S operating mode. Other configurations modify this to obtain all supported cases. See Formats and modes for examples." "0: I2S mode a.k.a. 'classic' mode. WS has a 50%..,1: DSP mode where WS has a 50% duty cycle. See..,2: DSP mode where WS has a one clock long pulse at..,3: DSP mode where WS has a one data slot long pulse.."
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bitfld.long 0x0 4.--5. "MSTSLVCFG,Master / slave configuration selection  determining how SCK and WS are used by all channel pairs in this Flexcomm." "0: Normal slave mode the default mode. SCK and WS..,1: WS synchronized master. WS is received from..,2: Master using an existing SCK. SCK is received..,3: Normal master mode. SCK and WS are generated so.."
bitfld.long 0x0 2.--3. "PAIRCOUNT,Provides the number of I2S channel pairs in this Flexcomm This is a read-only field whose value may be different in other Flexcomms. 00 = there is 1 I2S channel pair in this Flexcomm. 01 = there are 2 I2S channel pairs in this Flexcomm. 10 =.." "0: there is 1 I2S channel pair in this Flexcomm,1: there are 2 I2S channel pairs in this Flexcomm,2: 3 I2S channel pairs in this flexcomm,3: 4 I2S channel pairs in this flexcomm"
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bitfld.long 0x0 1. "DATAPAUSE,Data flow Pause. Allows pausing data flow between the I2S serializer/deserializer and the FIFO. This could be done in order to change streams  or while restarting after a data underflow or overflow. When paused  FIFO operations can be done.." "0: Normal operation or resuming normal operation at..,1: A pause in the data flow is being requested. It.."
bitfld.long 0x0 0. "MAINENABLE,Main enable for I 2S function in this Flexcomm" "0: All I 2S channel pairs in this Flexcomm are..,1: This I 2S channel pair is enabled. Other channel.."
line.long 0x4 "CFG2,Configuration register 2 for the primary channel pair."
hexmask.long.word 0x4 16.--24. 1. "POSITION,Data Position. Defines the location within the frame of the data for this channel pair. POSITION + DATALEN must be less than FRAMELEN. See Frame format. When MODE = 0  POSITION defines the location of data in both the left phase and right phase .."
hexmask.long.word 0x4 0.--8. 1. "FRAMELEN,Frame Length  minus 1 encoded  defines the number of clocks and data bits in the frames that this channel pair participates in. See Frame format. 0x000 to 0x002 = not supported 0x003 = frame is 4 bits in total length 0x004 = frame is 5 bits in.."
line.long 0x8 "STAT,Status register for the primary channel pair."
rbitfld.long 0x8 3. "DATAPAUSED,Data Paused status flag. Applies to all I2S channels" "0: Data is not currently paused. A data pause may..,1: A data pause has been requested and is now in.."
rbitfld.long 0x8 2. "LR,Left/Right indication. This flag is considered to be a debugging aid and is not expected to be used by an I2S driver. Valid when one channel pair is busy. Indicates left or right data being processed for the currently busy channel pair." "0: Left channel.,1: Right channel."
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bitfld.long 0x8 1. "SLVFRMERR,Slave Frame Error flag. This applies when at least one channel pair is operating as a slave. An error indicates that the incoming WS signal did not transition as expected due to a mismatch between FRAMELEN and the actual incoming I2S stream." "0: No error has been recorded.,1: An error has been recorded for some channel pair.."
rbitfld.long 0x8 0. "BUSY,Busy status for the primary channel pair. Other BUSY flags may be found in the STAT register for each channel pair." "0: The transmitter/receiver for channel pair is..,1: The transmitter/receiver for channel pair is.."
group.long 0xC1C++0x3
line.long 0x0 "DIV,Clock divider. used by all channel pairs."
hexmask.long.word 0x0 0.--11. 1. "DIV,This field controls how this I2S block uses the Flexcomm function clock. 0x000 = The Flexcomm function clock is used directly. 0x001 = The Flexcomm function clock is divided by 2. 0x002 = The Flexcomm function clock is divided by 3. 0xFFF = The.."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 3. "PACK48,Packing format for 48-bit data. This relates to how data is entered into or taken from the FIFO by software or DMA." "0: 48-bit I2S FIFO entries are handled as all..,1: 48-bit I2S FIFO entries are handled as.."
bitfld.long 0x0 2. "TXI2SE0,Transmit I2S empty 0. Determines the value sent by the I2S in transmit mode if the TX FIFO becomes empty. This value is sent repeatedly until the I2S is paused  the error is cleared  new data is provided  and the I2S is un-paused." "0: If the TX FIFO becomes empty the last value is..,1: If the TX FIFO becomes empty 0 is sent. Use if.."
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
wgroup.long 0xE20++0x7
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long 0x0 0.--31. 1. "TXDATA,Transmit data to the FIFO. The number of bits used depends on configuration details."
line.long 0x4 "FIFOWR48H,FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA."
hexmask.long.tbyte 0x4 0.--23. 1. "TXDATA,Transmit data to the FIFO. Whether this register is used and the number of bits used depends on configuration details."
rgroup.long 0xE30++0x7
line.long 0x0 "FIFORD,FIFO read data."
hexmask.long 0x0 0.--31. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on configuration details."
line.long 0x4 "FIFORD48H,FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA."
hexmask.long.tbyte 0x4 0.--23. 1. "RXDATA,Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details."
rgroup.long 0xE40++0x7
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
hexmask.long 0x0 0.--31. 1. "RXDATA,Received data from the FIFO."
line.long 0x4 "FIFORD48HNOPOP,FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA."
hexmask.long.tbyte 0x4 0.--23. 1. "RXDATA,Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details."
rgroup.long 0x1DFC++0x3
line.long 0x0 "ID,I2S Module identification"
hexmask.long.word 0x0 16.--31. 1. "ID,Unique module identifier for this IP block."
hexmask.long.byte 0x0 12.--15. 1. "Major_Rev,Major revision of module implementation  starting at 0."
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hexmask.long.byte 0x0 8.--11. 1. "Minor_Rev,Minor revision of module implementation  starting at 0."
hexmask.long.byte 0x0 0.--7. 1. "Aperture,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
endif
sif (cpuis("LPC54628*"))
tree "I2S0"
base ad:0x40097000
repeat 3. (list 0x0 0x1 0x2)(list ad:0x40097000 ad:0x40097020 ad:0x40097040)
tree "SECCHANNEL[$1]"
base $2
group.long ($2+0xC20)++0xB
line.long 0x0 "PCFG1,Configuration register 1 for channel pair"
bitfld.long 0x0 10. "ONECHANNEL,Single channel mode." "0,1"
bitfld.long 0x0 0. "PAIRENABLE,Enable for this channel pair.." "0,1"
line.long 0x4 "PCFG2,Configuration register 2 for channel pair"
hexmask.long.word 0x4 16.--24. 1. "POSITION,Data Position."
line.long 0x8 "PSTAT,Status register for channel pair"
rbitfld.long 0x8 3. "DATAPAUSED,Data Paused status flag." "0,1"
bitfld.long 0x8 2. "LR,Left/Right indication." "0,1"
bitfld.long 0x8 1. "SLVFRMERR,Save Frame Error flag." "0,1"
bitfld.long 0x8 0. "BUSY,Busy status for this channel pair." "0,1"
tree.end
repeat.end
base ad:0x40097000
group.long 0xC00++0xB
line.long 0x0 "CFG1,Configuration register 1 for the primary channel pair."
hexmask.long.byte 0x0 16.--20. 1. "DATALEN,Data Length  minus 1 encoded  defines the number of data bits to be transmitted or received for all I2S channel pairs in this Flexcomm. Note that data is only driven to or received from SDA for the number of bits defined by DATALEN. DATALEN is.."
bitfld.long 0x0 13. "WS_POL,WS polarity." "0: Data frames begin at a falling edge of WS..,1: WS is inverted resulting in a data frame.."
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bitfld.long 0x0 12. "SCK_POL,SCK polarity." "0: Data is launched on SCK falling edges and..,1: Data is launched on SCK rising edges and sampled.."
bitfld.long 0x0 11. "PDMDATA,PDM Data selection. This bit controls the data source for I2S transmit  and cannot be set in Rx mode. This bit only has an effect if the device the Flexcomm resides in includes a D-Mic subsystem. For the LPC5411x  this bit applies only to.." "0: Normal operation data is transferred to or from..,1: The data source is the D-Mic subsystem. When.."
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bitfld.long 0x0 10. "ONECHANNEL,Single channel mode. Applies to both transmit and receive. This configuration bit applies only to the first I2S channel pair. Other channel pairs may select this mode independently in their separate CFG1 registers." "0: I2S data for this channel pair is treated as..,1: I2S data for this channel pair is treated as a.."
bitfld.long 0x0 9. "LEFTJUST,Left Justify data." "0: Data is transferred between the FIFO and the I2S..,1: Data is transferred between the FIFO and the I2S.."
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bitfld.long 0x0 8. "RIGHTLOW,Right channel data is in the Low portion of FIFO data. Essentially  this swaps left and right channel data as it is transferred to or from the FIFO. This bit is not used if the data width is greater than 24 bits or if PDMDATA = 1. Note that if.." "0: The right channel is taken from the high part of..,1: The right channel is taken from the low part of.."
bitfld.long 0x0 6.--7. "MODE,Selects the basic I2S operating mode. Other configurations modify this to obtain all supported cases. See Formats and modes for examples." "0: I2S mode a.k.a. 'classic' mode. WS has a 50%..,1: DSP mode where WS has a 50% duty cycle. See..,2: DSP mode where WS has a one clock long pulse at..,3: DSP mode where WS has a one data slot long pulse.."
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bitfld.long 0x0 4.--5. "MSTSLVCFG,Master / slave configuration selection  determining how SCK and WS are used by all channel pairs in this Flexcomm." "0: Normal slave mode the default mode. SCK and WS..,1: WS synchronized master. WS is received from..,2: Master using an existing SCK. SCK is received..,3: Normal master mode. SCK and WS are generated so.."
bitfld.long 0x0 2.--3. "PAIRCOUNT,Provides the number of I2S channel pairs in this Flexcomm This is a read-only field whose value may be different in other Flexcomms. 00 = there is 1 I2S channel pair in this Flexcomm. 01 = there are 2 I2S channel pairs in this Flexcomm. 10 =.." "0: there is 1 I2S channel pair in this Flexcomm,1: there are 2 I2S channel pairs in this Flexcomm,2: 3 I2S channel pairs in this flexcomm,3: 4 I2S channel pairs in this flexcomm"
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bitfld.long 0x0 1. "DATAPAUSE,Data flow Pause. Allows pausing data flow between the I2S serializer/deserializer and the FIFO. This could be done in order to change streams  or while restarting after a data underflow or overflow. When paused  FIFO operations can be done.." "0: Normal operation or resuming normal operation at..,1: A pause in the data flow is being requested. It.."
bitfld.long 0x0 0. "MAINENABLE,Main enable for I 2S function in this Flexcomm" "0: All I 2S channel pairs in this Flexcomm are..,1: This I 2S channel pair is enabled. Other channel.."
line.long 0x4 "CFG2,Configuration register 2 for the primary channel pair."
hexmask.long.word 0x4 16.--24. 1. "POSITION,Data Position. Defines the location within the frame of the data for this channel pair. POSITION + DATALEN must be less than FRAMELEN. See Frame format. When MODE = 0  POSITION defines the location of data in both the left phase and right phase .."
hexmask.long.word 0x4 0.--8. 1. "FRAMELEN,Frame Length  minus 1 encoded  defines the number of clocks and data bits in the frames that this channel pair participates in. See Frame format. 0x000 to 0x002 = not supported 0x003 = frame is 4 bits in total length 0x004 = frame is 5 bits in.."
line.long 0x8 "STAT,Status register for the primary channel pair."
rbitfld.long 0x8 3. "DATAPAUSED,Data Paused status flag. Applies to all I2S channels" "0: Data is not currently paused. A data pause may..,1: A data pause has been requested and is now in.."
rbitfld.long 0x8 2. "LR,Left/Right indication. This flag is considered to be a debugging aid and is not expected to be used by an I2S driver. Valid when one channel pair is busy. Indicates left or right data being processed for the currently busy channel pair." "0: Left channel.,1: Right channel."
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bitfld.long 0x8 1. "SLVFRMERR,Slave Frame Error flag. This applies when at least one channel pair is operating as a slave. An error indicates that the incoming WS signal did not transition as expected due to a mismatch between FRAMELEN and the actual incoming I2S stream." "0: No error has been recorded.,1: An error has been recorded for some channel pair.."
rbitfld.long 0x8 0. "BUSY,Busy status for the primary channel pair. Other BUSY flags may be found in the STAT register for each channel pair." "0: The transmitter/receiver for channel pair is..,1: The transmitter/receiver for channel pair is.."
group.long 0xC1C++0x3
line.long 0x0 "DIV,Clock divider. used by all channel pairs."
hexmask.long.word 0x0 0.--11. 1. "DIV,This field controls how this I2S block uses the Flexcomm function clock. 0x000 = The Flexcomm function clock is used directly. 0x001 = The Flexcomm function clock is divided by 2. 0x002 = The Flexcomm function clock is divided by 3. 0xFFF = The.."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
newline
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 3. "PACK48,Packing format for 48-bit data. This relates to how data is entered into or taken from the FIFO by software or DMA." "0: 48-bit I2S FIFO entries are handled as all..,1: 48-bit I2S FIFO entries are handled as.."
bitfld.long 0x0 2. "TXI2SE0,Transmit I2S empty 0. Determines the value sent by the I2S in transmit mode if the TX FIFO becomes empty. This value is sent repeatedly until the I2S is paused  the error is cleared  new data is provided  and the I2S is un-paused." "0: If the TX FIFO becomes empty the last value is..,1: If the TX FIFO becomes empty 0 is sent. Use if.."
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
newline
bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
newline
bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
newline
bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
newline
bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
wgroup.long 0xE20++0x7
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long 0x0 0.--31. 1. "TXDATA,Transmit data to the FIFO. The number of bits used depends on configuration details."
line.long 0x4 "FIFOWR48H,FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA."
hexmask.long.tbyte 0x4 0.--23. 1. "TXDATA,Transmit data to the FIFO. Whether this register is used and the number of bits used depends on configuration details."
rgroup.long 0xE30++0x7
line.long 0x0 "FIFORD,FIFO read data."
hexmask.long 0x0 0.--31. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on configuration details."
line.long 0x4 "FIFORD48H,FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA."
hexmask.long.tbyte 0x4 0.--23. 1. "RXDATA,Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details."
rgroup.long 0xE40++0x7
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
hexmask.long 0x0 0.--31. 1. "RXDATA,Received data from the FIFO."
line.long 0x4 "FIFORD48HNOPOP,FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA."
hexmask.long.tbyte 0x4 0.--23. 1. "RXDATA,Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details."
rgroup.long 0x1DFC++0x3
line.long 0x0 "ID,I2S Module identification"
hexmask.long.word 0x0 16.--31. 1. "ID,Unique module identifier for this IP block."
hexmask.long.byte 0x0 12.--15. 1. "Major_Rev,Major revision of module implementation  starting at 0."
newline
hexmask.long.byte 0x0 8.--11. 1. "Minor_Rev,Minor revision of module implementation  starting at 0."
hexmask.long.byte 0x0 0.--7. 1. "Aperture,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "I2S1"
base ad:0x40098000
repeat 3. (list 0x0 0x1 0x2)(list ad:0x40098000 ad:0x40098020 ad:0x40098040)
tree "SECCHANNEL[$1]"
base $2
group.long ($2+0xC20)++0xB
line.long 0x0 "PCFG1,Configuration register 1 for channel pair"
bitfld.long 0x0 10. "ONECHANNEL,Single channel mode." "0,1"
bitfld.long 0x0 0. "PAIRENABLE,Enable for this channel pair.." "0,1"
line.long 0x4 "PCFG2,Configuration register 2 for channel pair"
hexmask.long.word 0x4 16.--24. 1. "POSITION,Data Position."
line.long 0x8 "PSTAT,Status register for channel pair"
rbitfld.long 0x8 3. "DATAPAUSED,Data Paused status flag." "0,1"
bitfld.long 0x8 2. "LR,Left/Right indication." "0,1"
bitfld.long 0x8 1. "SLVFRMERR,Save Frame Error flag." "0,1"
bitfld.long 0x8 0. "BUSY,Busy status for this channel pair." "0,1"
tree.end
repeat.end
base ad:0x40098000
group.long 0xC00++0xB
line.long 0x0 "CFG1,Configuration register 1 for the primary channel pair."
hexmask.long.byte 0x0 16.--20. 1. "DATALEN,Data Length  minus 1 encoded  defines the number of data bits to be transmitted or received for all I2S channel pairs in this Flexcomm. Note that data is only driven to or received from SDA for the number of bits defined by DATALEN. DATALEN is.."
bitfld.long 0x0 13. "WS_POL,WS polarity." "0: Data frames begin at a falling edge of WS..,1: WS is inverted resulting in a data frame.."
newline
bitfld.long 0x0 12. "SCK_POL,SCK polarity." "0: Data is launched on SCK falling edges and..,1: Data is launched on SCK rising edges and sampled.."
bitfld.long 0x0 11. "PDMDATA,PDM Data selection. This bit controls the data source for I2S transmit  and cannot be set in Rx mode. This bit only has an effect if the device the Flexcomm resides in includes a D-Mic subsystem. For the LPC5411x  this bit applies only to.." "0: Normal operation data is transferred to or from..,1: The data source is the D-Mic subsystem. When.."
newline
bitfld.long 0x0 10. "ONECHANNEL,Single channel mode. Applies to both transmit and receive. This configuration bit applies only to the first I2S channel pair. Other channel pairs may select this mode independently in their separate CFG1 registers." "0: I2S data for this channel pair is treated as..,1: I2S data for this channel pair is treated as a.."
bitfld.long 0x0 9. "LEFTJUST,Left Justify data." "0: Data is transferred between the FIFO and the I2S..,1: Data is transferred between the FIFO and the I2S.."
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bitfld.long 0x0 8. "RIGHTLOW,Right channel data is in the Low portion of FIFO data. Essentially  this swaps left and right channel data as it is transferred to or from the FIFO. This bit is not used if the data width is greater than 24 bits or if PDMDATA = 1. Note that if.." "0: The right channel is taken from the high part of..,1: The right channel is taken from the low part of.."
bitfld.long 0x0 6.--7. "MODE,Selects the basic I2S operating mode. Other configurations modify this to obtain all supported cases. See Formats and modes for examples." "0: I2S mode a.k.a. 'classic' mode. WS has a 50%..,1: DSP mode where WS has a 50% duty cycle. See..,2: DSP mode where WS has a one clock long pulse at..,3: DSP mode where WS has a one data slot long pulse.."
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bitfld.long 0x0 4.--5. "MSTSLVCFG,Master / slave configuration selection  determining how SCK and WS are used by all channel pairs in this Flexcomm." "0: Normal slave mode the default mode. SCK and WS..,1: WS synchronized master. WS is received from..,2: Master using an existing SCK. SCK is received..,3: Normal master mode. SCK and WS are generated so.."
bitfld.long 0x0 2.--3. "PAIRCOUNT,Provides the number of I2S channel pairs in this Flexcomm This is a read-only field whose value may be different in other Flexcomms. 00 = there is 1 I2S channel pair in this Flexcomm. 01 = there are 2 I2S channel pairs in this Flexcomm. 10 =.." "0: there is 1 I2S channel pair in this Flexcomm,1: there are 2 I2S channel pairs in this Flexcomm,2: 3 I2S channel pairs in this flexcomm,3: 4 I2S channel pairs in this flexcomm"
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bitfld.long 0x0 1. "DATAPAUSE,Data flow Pause. Allows pausing data flow between the I2S serializer/deserializer and the FIFO. This could be done in order to change streams  or while restarting after a data underflow or overflow. When paused  FIFO operations can be done.." "0: Normal operation or resuming normal operation at..,1: A pause in the data flow is being requested. It.."
bitfld.long 0x0 0. "MAINENABLE,Main enable for I 2S function in this Flexcomm" "0: All I 2S channel pairs in this Flexcomm are..,1: This I 2S channel pair is enabled. Other channel.."
line.long 0x4 "CFG2,Configuration register 2 for the primary channel pair."
hexmask.long.word 0x4 16.--24. 1. "POSITION,Data Position. Defines the location within the frame of the data for this channel pair. POSITION + DATALEN must be less than FRAMELEN. See Frame format. When MODE = 0  POSITION defines the location of data in both the left phase and right phase .."
hexmask.long.word 0x4 0.--8. 1. "FRAMELEN,Frame Length  minus 1 encoded  defines the number of clocks and data bits in the frames that this channel pair participates in. See Frame format. 0x000 to 0x002 = not supported 0x003 = frame is 4 bits in total length 0x004 = frame is 5 bits in.."
line.long 0x8 "STAT,Status register for the primary channel pair."
rbitfld.long 0x8 3. "DATAPAUSED,Data Paused status flag. Applies to all I2S channels" "0: Data is not currently paused. A data pause may..,1: A data pause has been requested and is now in.."
rbitfld.long 0x8 2. "LR,Left/Right indication. This flag is considered to be a debugging aid and is not expected to be used by an I2S driver. Valid when one channel pair is busy. Indicates left or right data being processed for the currently busy channel pair." "0: Left channel.,1: Right channel."
newline
bitfld.long 0x8 1. "SLVFRMERR,Slave Frame Error flag. This applies when at least one channel pair is operating as a slave. An error indicates that the incoming WS signal did not transition as expected due to a mismatch between FRAMELEN and the actual incoming I2S stream." "0: No error has been recorded.,1: An error has been recorded for some channel pair.."
rbitfld.long 0x8 0. "BUSY,Busy status for the primary channel pair. Other BUSY flags may be found in the STAT register for each channel pair." "0: The transmitter/receiver for channel pair is..,1: The transmitter/receiver for channel pair is.."
group.long 0xC1C++0x3
line.long 0x0 "DIV,Clock divider. used by all channel pairs."
hexmask.long.word 0x0 0.--11. 1. "DIV,This field controls how this I2S block uses the Flexcomm function clock. 0x000 = The Flexcomm function clock is used directly. 0x001 = The Flexcomm function clock is divided by 2. 0x002 = The Flexcomm function clock is divided by 3. 0xFFF = The.."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
newline
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
newline
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
newline
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
newline
bitfld.long 0x0 3. "PACK48,Packing format for 48-bit data. This relates to how data is entered into or taken from the FIFO by software or DMA." "0: 48-bit I2S FIFO entries are handled as all..,1: 48-bit I2S FIFO entries are handled as.."
bitfld.long 0x0 2. "TXI2SE0,Transmit I2S empty 0. Determines the value sent by the I2S in transmit mode if the TX FIFO becomes empty. This value is sent repeatedly until the I2S is paused  the error is cleared  new data is provided  and the I2S is un-paused." "0: If the TX FIFO becomes empty the last value is..,1: If the TX FIFO becomes empty 0 is sent. Use if.."
newline
bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
newline
rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
newline
rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
newline
rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
newline
bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
newline
bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
newline
bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
newline
bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
newline
bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
newline
bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
wgroup.long 0xE20++0x7
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long 0x0 0.--31. 1. "TXDATA,Transmit data to the FIFO. The number of bits used depends on configuration details."
line.long 0x4 "FIFOWR48H,FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA."
hexmask.long.tbyte 0x4 0.--23. 1. "TXDATA,Transmit data to the FIFO. Whether this register is used and the number of bits used depends on configuration details."
rgroup.long 0xE30++0x7
line.long 0x0 "FIFORD,FIFO read data."
hexmask.long 0x0 0.--31. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on configuration details."
line.long 0x4 "FIFORD48H,FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA."
hexmask.long.tbyte 0x4 0.--23. 1. "RXDATA,Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details."
rgroup.long 0xE40++0x7
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
hexmask.long 0x0 0.--31. 1. "RXDATA,Received data from the FIFO."
line.long 0x4 "FIFORD48HNOPOP,FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA."
hexmask.long.tbyte 0x4 0.--23. 1. "RXDATA,Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details."
rgroup.long 0x1DFC++0x3
line.long 0x0 "ID,I2S Module identification"
hexmask.long.word 0x0 16.--31. 1. "ID,Unique module identifier for this IP block."
hexmask.long.byte 0x0 12.--15. 1. "Major_Rev,Major revision of module implementation  starting at 0."
newline
hexmask.long.byte 0x0 8.--11. 1. "Minor_Rev,Minor revision of module implementation  starting at 0."
hexmask.long.byte 0x0 0.--7. 1. "Aperture,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
endif
tree.end
endif
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54113*")||cpuis("LPC54114*")||cpuis("LPC54605*")||cpuis("LPC54606*")||cpuis("LPC54607*")||cpuis("LPC54608*")||cpuis("LPC54616*")||cpuis("LPC54618*")||cpuis("LPC54628*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
base ad:0x40005000
elif (cpuis("LPC54101*")||cpuis("LPC54102*"))
base ad:0x40050000
endif
tree "INPUTMUX (Input Multiplexing)"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
repeat 7. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2)++0x3
line.long 0x0 "SCT0_INMUX[$1],Trigger select register for DMA channel"
hexmask.long.byte 0x0 0.--4. 1. "INP_N,Input number to SCT0 inputs 0 to 6.."
repeat.end
repeat 32. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0xE0)++0x3
line.long 0x0 "DMA_ITRIG_INMUX[$1],Trigger select register for DMA channel"
hexmask.long.byte 0x0 0.--4. 1. "INP,Trigger input number (decimal value) for DMA channel n (n = 0 to 31). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 = Timer CTIMER0 Match 0 5 = Timer CTIMER0 Match 1 6 = Timer CTIMER1.."
repeat.end
group.long 0x180++0x7
line.long 0x0 "FREQMEAS_REF,Selection for frequency measurement reference clock"
hexmask.long.byte 0x0 0.--4. 1. "CLKIN,Clock source number (decimal value) for frequency measure function target clock: 0 = CLK_IN 1 = FRO 12 MHz oscillator 2 = Watchdog oscillator 3 = 32 kHz RTC oscillator 4 = Main clock (see Section 4.5.23) 5 = PIO0_4 6 = PIO0_20 7 = PIO0_24 8 = PIO1_4"
line.long 0x4 "FREQMEAS_TARGET,Selection for frequency measurement target clock"
hexmask.long.byte 0x4 0.--4. 1. "CLKIN,Clock source number (decimal value) for frequency measure function target clock: 0 = CLK_IN 1 = FRO 12 MHz oscillator 2 = Watchdog oscillator 3 = 32 kHz RTC oscillator 4 = Main clock (see Section 4.5.23) 5 = PIO0_4 6 = PIO0_20 7 = PIO0_24 8 = PIO1_4"
endif
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0xC0)++0x3
line.long 0x0 "PINTSEL[$1],Pin interrupt select register"
hexmask.long.byte 0x0 0.--7. 1. "INTPIN,Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO1_31 correspond to numbers 0 to 63)."
repeat.end
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x160)++0x3
line.long 0x0 "DMA_OTRIG_INMUX[$1],DMA output trigger selection to become DMA trigger"
hexmask.long.byte 0x0 0.--4. 1. "INP,DMA trigger output number (decimal value) for DMA channel n (n = 0 to 19)."
repeat.end
sif (cpuis("LPC54101*"))
repeat 22. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0xE0)++0x3
line.long 0x0 "DMA_ITRIG_INMUX[$1],Trigger select register for DMA channel"
hexmask.long.byte 0x0 0.--4. 1. "INP,Trigger input number (decimal value) for DMA channel n (n = 0 to 21). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 = Timer CTIMER0 Match 0 5 = Timer CTIMER0 Match 1 6 = Timer CTIMER1.."
repeat.end
endif
sif (cpuis("LPC54101*"))
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x140)++0x3
line.long 0x0 "DMA_OTRIG_INMUX[$1],DMA output trigger selection to become DMA trigger"
hexmask.long.byte 0x0 0.--4. 1. "INP,DMA trigger output number (decimal value) for DMA channel n (n = 0 to 19)."
repeat.end
group.long 0x160++0x7
line.long 0x0 "FREQMEAS_REF,Selection for frequency measurement reference clock"
hexmask.long.byte 0x0 0.--4. 1. "CLKIN,Clock source number (decimal value) for frequency measure function target clock: 0 = CLK_IN 1 = FRO 12 MHz oscillator 2 = Watchdog oscillator 3 = 32 kHz RTC oscillator 4 = Main clock (see Section 4.5.23) 5 = PIO0_4 6 = PIO0_20 7 = PIO0_24 8 = PIO1_4"
line.long 0x4 "FREQMEAS_TARGET,Selection for frequency measurement target clock"
hexmask.long.byte 0x4 0.--4. 1. "CLKIN,Clock source number (decimal value) for frequency measure function target clock: 0 = CLK_IN 1 = FRO 12 MHz oscillator 2 = Watchdog oscillator 3 = 32 kHz RTC oscillator 4 = Main clock (see Section 4.5.23) 5 = PIO0_4 6 = PIO0_20 7 = PIO0_24 8 = PIO1_4"
endif
sif (cpuis("LPC54102*"))
repeat 22. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0xE0)++0x3
line.long 0x0 "DMA_ITRIG_INMUX[$1],Trigger select register for DMA channel"
hexmask.long.byte 0x0 0.--4. 1. "INP,Trigger input number (decimal value) for DMA channel n (n = 0 to 21). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 = Timer CTIMER0 Match 0 5 = Timer CTIMER0 Match 1 6 = Timer CTIMER1.."
repeat.end
endif
sif (cpuis("LPC54102*"))
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x140)++0x3
line.long 0x0 "DMA_OTRIG_INMUX[$1],DMA output trigger selection to become DMA trigger"
hexmask.long.byte 0x0 0.--4. 1. "INP,DMA trigger output number (decimal value) for DMA channel n (n = 0 to 19)."
repeat.end
group.long 0x160++0x7
line.long 0x0 "FREQMEAS_REF,Selection for frequency measurement reference clock"
hexmask.long.byte 0x0 0.--4. 1. "CLKIN,Clock source number (decimal value) for frequency measure function target clock: 0 = CLK_IN 1 = FRO 12 MHz oscillator 2 = Watchdog oscillator 3 = 32 kHz RTC oscillator 4 = Main clock (see Section 4.5.23) 5 = PIO0_4 6 = PIO0_20 7 = PIO0_24 8 = PIO1_4"
line.long 0x4 "FREQMEAS_TARGET,Selection for frequency measurement target clock"
hexmask.long.byte 0x4 0.--4. 1. "CLKIN,Clock source number (decimal value) for frequency measure function target clock: 0 = CLK_IN 1 = FRO 12 MHz oscillator 2 = Watchdog oscillator 3 = 32 kHz RTC oscillator 4 = Main clock (see Section 4.5.23) 5 = PIO0_4 6 = PIO0_20 7 = PIO0_24 8 = PIO1_4"
endif
sif (cpuis("LPC54113*"))
repeat 22. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0xE0)++0x3
line.long 0x0 "DMA_ITRIG_INMUX[$1],Trigger select register for DMA channel"
hexmask.long.byte 0x0 0.--4. 1. "INP,Trigger input number (decimal value) for DMA channel n (n = 0 to 21). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 = Timer CTIMER0 Match 0 5 = Timer CTIMER0 Match 1 6 = Timer CTIMER1.."
repeat.end
group.long 0x180++0x7
line.long 0x0 "FREQMEAS_REF,Selection for frequency measurement reference clock"
hexmask.long.byte 0x0 0.--4. 1. "CLKIN,Clock source number (decimal value) for frequency measure function target clock: 0 = CLK_IN 1 = FRO 12 MHz oscillator 2 = Watchdog oscillator 3 = 32 kHz RTC oscillator 4 = Main clock (see Section 4.5.23) 5 = PIO0_4 6 = PIO0_20 7 = PIO0_24 8 = PIO1_4"
line.long 0x4 "FREQMEAS_TARGET,Selection for frequency measurement target clock"
hexmask.long.byte 0x4 0.--4. 1. "CLKIN,Clock source number (decimal value) for frequency measure function target clock: 0 = CLK_IN 1 = FRO 12 MHz oscillator 2 = Watchdog oscillator 3 = 32 kHz RTC oscillator 4 = Main clock (see Section 4.5.23) 5 = PIO0_4 6 = PIO0_20 7 = PIO0_24 8 = PIO1_4"
endif
sif (cpuis("LPC54114*"))
repeat 22. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0xE0)++0x3
line.long 0x0 "DMA_ITRIG_INMUX[$1],Trigger select register for DMA channel"
hexmask.long.byte 0x0 0.--4. 1. "INP,Trigger input number (decimal value) for DMA channel n (n = 0 to 21). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 = Timer CTIMER0 Match 0 5 = Timer CTIMER0 Match 1 6 = Timer CTIMER1.."
repeat.end
group.long 0x180++0x7
line.long 0x0 "FREQMEAS_REF,Selection for frequency measurement reference clock"
hexmask.long.byte 0x0 0.--4. 1. "CLKIN,Clock source number (decimal value) for frequency measure function target clock: 0 = CLK_IN 1 = FRO 12 MHz oscillator 2 = Watchdog oscillator 3 = 32 kHz RTC oscillator 4 = Main clock (see Section 4.5.23) 5 = PIO0_4 6 = PIO0_20 7 = PIO0_24 8 = PIO1_4"
line.long 0x4 "FREQMEAS_TARGET,Selection for frequency measurement target clock"
hexmask.long.byte 0x4 0.--4. 1. "CLKIN,Clock source number (decimal value) for frequency measure function target clock: 0 = CLK_IN 1 = FRO 12 MHz oscillator 2 = Watchdog oscillator 3 = 32 kHz RTC oscillator 4 = Main clock (see Section 4.5.23) 5 = PIO0_4 6 = PIO0_20 7 = PIO0_24 8 = PIO1_4"
endif
sif (cpuis("LPC54605*"))
repeat 7. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2)++0x3
line.long 0x0 "SCT0_INMUX[$1],Trigger select register for DMA channel"
hexmask.long.byte 0x0 0.--4. 1. "INP_N,Input number to SCT0 inputs 0 to 6.."
repeat.end
endif
sif (cpuis("LPC54605*"))
repeat 30. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0xE0)++0x3
line.long 0x0 "DMA_ITRIG_INMUX[$1],Trigger select register for DMA channel"
hexmask.long.byte 0x0 0.--4. 1. "INP,Trigger input number (decimal value) for DMA channel n (n = 0 to 21). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 = Timer CTIMER0 Match 0 5 = Timer CTIMER0 Match 1 6 = Timer CTIMER1.."
repeat.end
group.long 0x180++0x7
line.long 0x0 "FREQMEAS_REF,Selection for frequency measurement reference clock"
hexmask.long.byte 0x0 0.--4. 1. "CLKIN,Clock source number (decimal value) for frequency measure function target clock: 0 = CLK_IN 1 = FRO 12 MHz oscillator 2 = Watchdog oscillator 3 = 32 kHz RTC oscillator 4 = Main clock (see Section 4.5.23) 5 = PIO0_4 6 = PIO0_20 7 = PIO0_24 8 = PIO1_4"
line.long 0x4 "FREQMEAS_TARGET,Selection for frequency measurement target clock"
hexmask.long.byte 0x4 0.--4. 1. "CLKIN,Clock source number (decimal value) for frequency measure function target clock: 0 = CLK_IN 1 = FRO 12 MHz oscillator 2 = Watchdog oscillator 3 = 32 kHz RTC oscillator 4 = Main clock (see Section 4.5.23) 5 = PIO0_4 6 = PIO0_20 7 = PIO0_24 8 = PIO1_4"
endif
sif (cpuis("LPC54606*"))
repeat 7. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2)++0x3
line.long 0x0 "SCT0_INMUX[$1],Trigger select register for DMA channel"
hexmask.long.byte 0x0 0.--4. 1. "INP_N,Input number to SCT0 inputs 0 to 6.."
repeat.end
endif
sif (cpuis("LPC54606*"))
repeat 30. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0xE0)++0x3
line.long 0x0 "DMA_ITRIG_INMUX[$1],Trigger select register for DMA channel"
hexmask.long.byte 0x0 0.--4. 1. "INP,Trigger input number (decimal value) for DMA channel n (n = 0 to 21). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 = Timer CTIMER0 Match 0 5 = Timer CTIMER0 Match 1 6 = Timer CTIMER1.."
repeat.end
group.long 0x180++0x7
line.long 0x0 "FREQMEAS_REF,Selection for frequency measurement reference clock"
hexmask.long.byte 0x0 0.--4. 1. "CLKIN,Clock source number (decimal value) for frequency measure function target clock: 0 = CLK_IN 1 = FRO 12 MHz oscillator 2 = Watchdog oscillator 3 = 32 kHz RTC oscillator 4 = Main clock (see Section 4.5.23) 5 = PIO0_4 6 = PIO0_20 7 = PIO0_24 8 = PIO1_4"
line.long 0x4 "FREQMEAS_TARGET,Selection for frequency measurement target clock"
hexmask.long.byte 0x4 0.--4. 1. "CLKIN,Clock source number (decimal value) for frequency measure function target clock: 0 = CLK_IN 1 = FRO 12 MHz oscillator 2 = Watchdog oscillator 3 = 32 kHz RTC oscillator 4 = Main clock (see Section 4.5.23) 5 = PIO0_4 6 = PIO0_20 7 = PIO0_24 8 = PIO1_4"
endif
sif (cpuis("LPC54607*"))
repeat 7. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2)++0x3
line.long 0x0 "SCT0_INMUX[$1],Trigger select register for DMA channel"
hexmask.long.byte 0x0 0.--4. 1. "INP_N,Input number to SCT0 inputs 0 to 6.."
repeat.end
endif
sif (cpuis("LPC54607*"))
repeat 30. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0xE0)++0x3
line.long 0x0 "DMA_ITRIG_INMUX[$1],Trigger select register for DMA channel"
hexmask.long.byte 0x0 0.--4. 1. "INP,Trigger input number (decimal value) for DMA channel n (n = 0 to 21). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 = Timer CTIMER0 Match 0 5 = Timer CTIMER0 Match 1 6 = Timer CTIMER1.."
repeat.end
group.long 0x180++0x7
line.long 0x0 "FREQMEAS_REF,Selection for frequency measurement reference clock"
hexmask.long.byte 0x0 0.--4. 1. "CLKIN,Clock source number (decimal value) for frequency measure function target clock: 0 = CLK_IN 1 = FRO 12 MHz oscillator 2 = Watchdog oscillator 3 = 32 kHz RTC oscillator 4 = Main clock (see Section 4.5.23) 5 = PIO0_4 6 = PIO0_20 7 = PIO0_24 8 = PIO1_4"
line.long 0x4 "FREQMEAS_TARGET,Selection for frequency measurement target clock"
hexmask.long.byte 0x4 0.--4. 1. "CLKIN,Clock source number (decimal value) for frequency measure function target clock: 0 = CLK_IN 1 = FRO 12 MHz oscillator 2 = Watchdog oscillator 3 = 32 kHz RTC oscillator 4 = Main clock (see Section 4.5.23) 5 = PIO0_4 6 = PIO0_20 7 = PIO0_24 8 = PIO1_4"
endif
sif (cpuis("LPC54608*"))
repeat 7. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2)++0x3
line.long 0x0 "SCT0_INMUX[$1],Trigger select register for DMA channel"
hexmask.long.byte 0x0 0.--4. 1. "INP_N,Input number to SCT0 inputs 0 to 6.."
repeat.end
endif
sif (cpuis("LPC54608*"))
repeat 30. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0xE0)++0x3
line.long 0x0 "DMA_ITRIG_INMUX[$1],Trigger select register for DMA channel"
hexmask.long.byte 0x0 0.--4. 1. "INP,Trigger input number (decimal value) for DMA channel n (n = 0 to 21). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 = Timer CTIMER0 Match 0 5 = Timer CTIMER0 Match 1 6 = Timer CTIMER1.."
repeat.end
group.long 0x180++0x7
line.long 0x0 "FREQMEAS_REF,Selection for frequency measurement reference clock"
hexmask.long.byte 0x0 0.--4. 1. "CLKIN,Clock source number (decimal value) for frequency measure function target clock: 0 = CLK_IN 1 = FRO 12 MHz oscillator 2 = Watchdog oscillator 3 = 32 kHz RTC oscillator 4 = Main clock (see Section 4.5.23) 5 = PIO0_4 6 = PIO0_20 7 = PIO0_24 8 = PIO1_4"
line.long 0x4 "FREQMEAS_TARGET,Selection for frequency measurement target clock"
hexmask.long.byte 0x4 0.--4. 1. "CLKIN,Clock source number (decimal value) for frequency measure function target clock: 0 = CLK_IN 1 = FRO 12 MHz oscillator 2 = Watchdog oscillator 3 = 32 kHz RTC oscillator 4 = Main clock (see Section 4.5.23) 5 = PIO0_4 6 = PIO0_20 7 = PIO0_24 8 = PIO1_4"
endif
sif (cpuis("LPC54616*"))
repeat 7. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2)++0x3
line.long 0x0 "SCT0_INMUX[$1],Trigger select register for DMA channel"
hexmask.long.byte 0x0 0.--4. 1. "INP_N,Input number to SCT0 inputs 0 to 6.."
repeat.end
endif
sif (cpuis("LPC54616*"))
repeat 30. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0xE0)++0x3
line.long 0x0 "DMA_ITRIG_INMUX[$1],Trigger select register for DMA channel"
hexmask.long.byte 0x0 0.--4. 1. "INP,Trigger input number (decimal value) for DMA channel n (n = 0 to 21). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 = Timer CTIMER0 Match 0 5 = Timer CTIMER0 Match 1 6 = Timer CTIMER1.."
repeat.end
group.long 0x180++0x7
line.long 0x0 "FREQMEAS_REF,Selection for frequency measurement reference clock"
hexmask.long.byte 0x0 0.--4. 1. "CLKIN,Clock source number (decimal value) for frequency measure function target clock: 0 = CLK_IN 1 = FRO 12 MHz oscillator 2 = Watchdog oscillator 3 = 32 kHz RTC oscillator 4 = Main clock (see Section 4.5.23) 5 = PIO0_4 6 = PIO0_20 7 = PIO0_24 8 = PIO1_4"
line.long 0x4 "FREQMEAS_TARGET,Selection for frequency measurement target clock"
hexmask.long.byte 0x4 0.--4. 1. "CLKIN,Clock source number (decimal value) for frequency measure function target clock: 0 = CLK_IN 1 = FRO 12 MHz oscillator 2 = Watchdog oscillator 3 = 32 kHz RTC oscillator 4 = Main clock (see Section 4.5.23) 5 = PIO0_4 6 = PIO0_20 7 = PIO0_24 8 = PIO1_4"
endif
sif (cpuis("LPC54618*"))
repeat 7. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2)++0x3
line.long 0x0 "SCT0_INMUX[$1],Trigger select register for DMA channel"
hexmask.long.byte 0x0 0.--4. 1. "INP_N,Input number to SCT0 inputs 0 to 6.."
repeat.end
endif
sif (cpuis("LPC54618*"))
repeat 30. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0xE0)++0x3
line.long 0x0 "DMA_ITRIG_INMUX[$1],Trigger select register for DMA channel"
hexmask.long.byte 0x0 0.--4. 1. "INP,Trigger input number (decimal value) for DMA channel n (n = 0 to 21). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 = Timer CTIMER0 Match 0 5 = Timer CTIMER0 Match 1 6 = Timer CTIMER1.."
repeat.end
group.long 0x180++0x7
line.long 0x0 "FREQMEAS_REF,Selection for frequency measurement reference clock"
hexmask.long.byte 0x0 0.--4. 1. "CLKIN,Clock source number (decimal value) for frequency measure function target clock: 0 = CLK_IN 1 = FRO 12 MHz oscillator 2 = Watchdog oscillator 3 = 32 kHz RTC oscillator 4 = Main clock (see Section 4.5.23) 5 = PIO0_4 6 = PIO0_20 7 = PIO0_24 8 = PIO1_4"
line.long 0x4 "FREQMEAS_TARGET,Selection for frequency measurement target clock"
hexmask.long.byte 0x4 0.--4. 1. "CLKIN,Clock source number (decimal value) for frequency measure function target clock: 0 = CLK_IN 1 = FRO 12 MHz oscillator 2 = Watchdog oscillator 3 = 32 kHz RTC oscillator 4 = Main clock (see Section 4.5.23) 5 = PIO0_4 6 = PIO0_20 7 = PIO0_24 8 = PIO1_4"
endif
sif (cpuis("LPC54628*"))
repeat 7. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2)++0x3
line.long 0x0 "SCT0_INMUX[$1],Trigger select register for DMA channel"
hexmask.long.byte 0x0 0.--4. 1. "INP_N,Input number to SCT0 inputs 0 to 6.."
repeat.end
endif
sif (cpuis("LPC54628*"))
repeat 30. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0xE0)++0x3
line.long 0x0 "DMA_ITRIG_INMUX[$1],Trigger select register for DMA channel"
hexmask.long.byte 0x0 0.--4. 1. "INP,Trigger input number (decimal value) for DMA channel n (n = 0 to 21). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 = Timer CTIMER0 Match 0 5 = Timer CTIMER0 Match 1 6 = Timer CTIMER1.."
repeat.end
group.long 0x180++0x7
line.long 0x0 "FREQMEAS_REF,Selection for frequency measurement reference clock"
hexmask.long.byte 0x0 0.--4. 1. "CLKIN,Clock source number (decimal value) for frequency measure function target clock: 0 = CLK_IN 1 = FRO 12 MHz oscillator 2 = Watchdog oscillator 3 = 32 kHz RTC oscillator 4 = Main clock (see Section 4.5.23) 5 = PIO0_4 6 = PIO0_20 7 = PIO0_24 8 = PIO1_4"
line.long 0x4 "FREQMEAS_TARGET,Selection for frequency measurement target clock"
hexmask.long.byte 0x4 0.--4. 1. "CLKIN,Clock source number (decimal value) for frequency measure function target clock: 0 = CLK_IN 1 = FRO 12 MHz oscillator 2 = Watchdog oscillator 3 = 32 kHz RTC oscillator 4 = Main clock (see Section 4.5.23) 5 = PIO0_4 6 = PIO0_20 7 = PIO0_24 8 = PIO1_4"
endif
tree.end
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54113*")||cpuis("LPC54114*")||cpuis("LPC54605*")||cpuis("LPC54606*")||cpuis("LPC54607*")||cpuis("LPC54608*")||cpuis("LPC54616*")||cpuis("LPC54618*")||cpuis("LPC54628*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
base ad:0x40001000
elif (cpuis("LPC54101*")||cpuis("LPC54102*"))
base ad:0x4001C000
endif
tree "IOCON (I/O Pin Configuration)"
group.long 0x0++0xFF
line.long 0x0 "PIO00,Digital I/O control for port 0 pins PIO0_0"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x0 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x0 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x0 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x0 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x0 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x0 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x0 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x0 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x0 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x0 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x0 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x0 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x0 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x0 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x0 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x0 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x0 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x0 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x0 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x0 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x0 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x0 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x0 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x0 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x0 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x0 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x0 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x0 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x0 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x0 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x0 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x0 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x0 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x0 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x0 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x0 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
line.long 0x4 "PIO01,Digital I/O control for port 0 pins PIO0_1"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x4 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x4 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x4 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x4 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x4 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x4 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x4 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x4 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x4 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x4 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x4 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x4 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x4 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x4 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x4 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x4 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x4 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x4 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x4 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x4 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x4 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x4 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x4 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x4 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x4 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x4 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x4 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x4 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x4 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x4 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x4 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x4 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x4 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x4 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x4 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x4 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
line.long 0x8 "PIO02,Digital I/O control for port 0 pins PIO0_2"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x8 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x8 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x8 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x8 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x8 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x8 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x8 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x8 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x8 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x8 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x8 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x8 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x8 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x8 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x8 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x8 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x8 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x8 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x8 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x8 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x8 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x8 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x8 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x8 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x8 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x8 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x8 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x8 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x8 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x8 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x8 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x8 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x8 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x8 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x8 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x8 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
line.long 0xC "PIO03,Digital I/O control for port 0 pins PIO0_3"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0xC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xC 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0xC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0xC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0xC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0xC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0xC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0xC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0xC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0xC 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xC 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xC 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xC 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xC 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0xC 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xC 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xC 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xC 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xC 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0xC 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xC 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xC 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xC 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xC 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0xC 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xC 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xC 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xC 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xC 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0xC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xC 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0xC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xC 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0xC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xC 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0xC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xC 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0xC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xC 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0xC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xC 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0xC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xC 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0xC 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xC 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0xC 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xC 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0xC 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xC 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0xC 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xC 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
line.long 0x10 "PIO04,Digital I/O control for port 0 pins PIO0_4"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x10 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x10 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x10 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x10 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x10 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x10 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x10 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x10 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x10 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x10 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x10 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x10 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x10 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x10 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x10 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x10 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x10 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x10 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x10 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x10 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x10 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x10 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x10 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x10 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x10 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x10 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x10 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x10 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x10 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x10 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x10 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x10 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x10 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x10 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x10 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x10 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x10 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x10 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x10 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x10 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x10 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x10 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x10 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x10 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x10 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x10 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x10 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x10 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x10 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x10 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x10 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x10 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x10 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x10 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x10 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x10 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x10 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x10 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x10 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x10 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x10 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x10 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x10 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x10 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x10 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x10 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x10 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x10 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x10 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x10 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x10 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x10 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x10 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x10 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x10 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x10 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x10 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x10 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x10 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x10 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x10 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x10 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x10 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x10 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
line.long 0x14 "PIO05,Digital I/O control for port 0 pins PIO0_5"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x14 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x14 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x14 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x14 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x14 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x14 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x14 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x14 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x14 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x14 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x14 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x14 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x14 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x14 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x14 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x14 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x14 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x14 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x14 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x14 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x14 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x14 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x14 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x14 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x14 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x14 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x14 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x14 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x14 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x14 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x14 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x14 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x14 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x14 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x14 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x14 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x14 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x14 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x14 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x14 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x14 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x14 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x14 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x14 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x14 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x14 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x14 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x14 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x14 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x14 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x14 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x14 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x14 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x14 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x14 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x14 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x14 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x14 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x14 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x14 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x14 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x14 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x14 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x14 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x14 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x14 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x14 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x14 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x14 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x14 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x14 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x14 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x14 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x14 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x14 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x14 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x14 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x14 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x14 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x14 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x14 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x14 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x14 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x14 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
line.long 0x18 "PIO06,Digital I/O control for port 0 pins PIO0_6"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x18 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x18 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x18 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x18 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x18 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x18 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x18 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x18 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x18 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x18 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x18 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x18 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x18 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x18 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x18 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x18 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x18 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x18 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x18 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x18 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x18 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x18 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x18 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x18 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x18 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x18 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x18 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x18 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x18 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x18 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x18 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x18 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x18 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x18 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x18 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x18 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x18 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x18 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x18 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x18 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x18 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x18 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x18 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x18 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x18 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x18 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x18 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x18 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x18 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x18 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x18 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x18 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x18 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x18 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x18 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x18 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x18 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x18 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x18 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x18 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x18 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x18 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x18 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x18 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x18 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x18 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x18 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x18 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x18 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x18 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x18 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x18 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x18 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x18 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x18 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x18 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x18 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x18 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x18 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x18 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x18 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x18 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x18 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x18 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
line.long 0x1C "PIO07,Digital I/O control for port 0 pins PIO0_7"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x1C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x1C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x1C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x1C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x1C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x1C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x1C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x1C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x1C 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1C 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1C 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1C 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1C 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x1C 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1C 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1C 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1C 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1C 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x1C 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1C 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1C 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1C 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1C 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x1C 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1C 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1C 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1C 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1C 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x1C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x1C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x1C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x1C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x1C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x1C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x1C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x1C 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x1C 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x1C 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x1C 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x1C 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x1C 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x1C 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x1C 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
line.long 0x20 "PIO08,Digital I/O control for port 0 pins PIO0_8"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x20 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x20 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x20 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x20 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x20 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x20 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x20 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x20 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x20 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x20 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x20 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x20 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x20 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x20 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x20 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x20 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x20 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x20 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x20 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x20 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x20 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x20 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x20 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x20 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x20 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x20 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x20 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x20 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x20 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x20 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x20 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x20 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x20 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x20 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x20 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x20 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x20 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x20 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x20 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x20 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x20 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x20 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x20 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x20 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x20 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x20 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x20 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x20 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x20 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x20 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x20 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x20 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x20 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x20 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x20 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x20 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x20 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x20 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x20 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x20 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x20 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x20 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x20 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x20 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x20 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x20 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x20 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x20 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x20 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x20 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x20 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x20 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x20 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x20 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x20 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x20 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x20 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x20 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x20 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x20 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x20 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x20 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x20 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x20 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
line.long 0x24 "PIO09,Digital I/O control for port 0 pins PIO0_9"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x24 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x24 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x24 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x24 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x24 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x24 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x24 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x24 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x24 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x24 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x24 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x24 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x24 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x24 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x24 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x24 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x24 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x24 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x24 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x24 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x24 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x24 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x24 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x24 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x24 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x24 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x24 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x24 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x24 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x24 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x24 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x24 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x24 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x24 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x24 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x24 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x24 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x24 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x24 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x24 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x24 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x24 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x24 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x24 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x24 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x24 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x24 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x24 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x24 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x24 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x24 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x24 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x24 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x24 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x24 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x24 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x24 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x24 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x24 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x24 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x24 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x24 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x24 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x24 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x24 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x24 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x24 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x24 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x24 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x24 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x24 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x24 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x24 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x24 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x24 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x24 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x24 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x24 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x24 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x24 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x24 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x24 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x24 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x24 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
line.long 0x28 "PIO010,Digital I/O control for port 0 pins PIO0_10"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x28 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x28 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x28 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x28 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x28 6. "ANAMODE,Enables or disables analog mode." "0: Enable analog Mode.,1: Disable analog Mode."
newline
bitfld.long 0x28 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x28 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x28 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x28 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x28 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x28 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x28 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x28 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x28 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x28 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x28 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x28 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x28 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x28 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x28 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x28 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x28 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x28 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x28 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x28 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x28 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x28 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x28 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x28 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x28 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x28 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x28 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x28 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x28 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x28 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x28 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x28 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x28 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x28 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x28 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x28 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x28 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x28 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x28 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x28 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x28 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x28 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x28 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x28 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x28 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x28 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x28 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x28 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x28 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x28 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x28 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x28 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x28 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x28 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x28 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x28 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x28 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x28 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x28 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x28 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x28 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x28 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x28 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x28 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x28 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x28 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x28 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x28 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x28 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x28 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x28 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x28 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
line.long 0x2C "PIO011,Digital I/O control for port 0 pins PIO0_11"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x2C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x2C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x2C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x2C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x2C 6. "ANAMODE,Enables or disables analog mode." "0: Enable analog Mode.,1: Disable analog Mode."
newline
bitfld.long 0x2C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x2C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x2C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x2C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x2C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x2C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x2C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x2C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x2C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x2C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x2C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x2C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x2C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x2C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x2C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x2C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x2C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x2C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x2C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x2C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x2C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x2C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x2C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x2C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x2C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x2C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x2C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x2C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x2C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x2C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x2C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x2C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x2C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x2C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x2C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x2C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x2C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x2C 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x2C 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x2C 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x2C 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x2C 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x2C 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x2C 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x2C 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x2C 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x2C 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x2C 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x2C 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x2C 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x2C 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x2C 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x2C 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x2C 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x2C 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x2C 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x2C 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x2C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x2C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x2C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x2C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x2C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x2C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x2C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x2C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x2C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x2C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x2C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x2C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x2C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x2C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x2C 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x2C 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x2C 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x2C 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x2C 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x2C 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x2C 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x2C 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
line.long 0x30 "PIO012,Digital I/O control for port 0 pins PIO0_12"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x30 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x30 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x30 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x30 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x30 6. "ANAMODE,Enables or disables analog mode." "0: Enable analog Mode.,1: Disable analog Mode."
newline
bitfld.long 0x30 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x30 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x30 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x30 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x30 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x30 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x30 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x30 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x30 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x30 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x30 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x30 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x30 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x30 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x30 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x30 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x30 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x30 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x30 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x30 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x30 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x30 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x30 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x30 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x30 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x30 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x30 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x30 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x30 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x30 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x30 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x30 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x30 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x30 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x30 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x30 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x30 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x30 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x30 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x30 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x30 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x30 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x30 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x30 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x30 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x30 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x30 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x30 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x30 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x30 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x30 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x30 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x30 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x30 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x30 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x30 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x30 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x30 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x30 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x30 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x30 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x30 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x30 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x30 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x30 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x30 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x30 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x30 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x30 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x30 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x30 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x30 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x30 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x30 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x30 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x30 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x30 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x30 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x30 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
line.long 0x34 "PIO013,Digital I/O control for port 0 pins PIO0_13"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x34 11. "I2CFILTEROFF,Configures I2C features for standard mode  fast mode  and Fast Mode Plus operation." "0: Enabled. I2C 50 ns glitch filter enabled.,1: Disabled. I2C 50 ns glitch filter disabled."
newline
bitfld.long 0x34 10. "I2CDRIVE,Controls the current sink capability of the pin." "0: Low drive. Output drive sink is 4 mA. This is..,1: High drive. Output drive sink is 20 mA. This is.."
newline
bitfld.long 0x34 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x34 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x34 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x34 6. "I2CSLEW,Controls slew rate of I2C pad." "0: I2C mode.,1: GPIO mode."
newline
hexmask.long.byte 0x34 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x34 11. "I2CFILTER,Configures I2C features for standard mode  fast mode  and Fast Mode Plus operation." "0: Enabled. I2C 50 ns glitch filter enabled.,1: Disabled. I2C 50 ns glitch filter disabled."
newline
bitfld.long 0x34 10. "I2CDRIVE,Controls the current sink capability of the pin." "0: Low drive. Output drive sink is 4 mA. This is..,1: High drive. Output drive sink is 20 mA. This is.."
newline
bitfld.long 0x34 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x34 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x34 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x34 6. "I2CSLEW,Controls slew rate of I2C pad." "0: I2C mode.,1: GPIO mode."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x34 11. "I2CFILTER,Configures I2C features for standard mode  fast mode  and Fast Mode Plus operation." "0: Enabled. I2C 50 ns glitch filter enabled.,1: Disabled. I2C 50 ns glitch filter disabled."
newline
bitfld.long 0x34 10. "I2CDRIVE,Controls the current sink capability of the pin." "0: Low drive. Output drive sink is 4 mA. This is..,1: High drive. Output drive sink is 20 mA. This is.."
newline
bitfld.long 0x34 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x34 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x34 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x34 6. "I2CSLEW,Controls slew rate of I2C pad." "0: I2C mode.,1: GPIO mode."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x34 11. "I2CFILTER,Configures I2C features for standard mode  fast mode  and Fast Mode Plus operation." "0: Enabled. I2C 50 ns glitch filter enabled.,1: Disabled. I2C 50 ns glitch filter disabled."
newline
bitfld.long 0x34 10. "I2CDRIVE,Controls the current sink capability of the pin." "0: Low drive. Output drive sink is 4 mA. This is..,1: High drive. Output drive sink is 20 mA. This is.."
newline
bitfld.long 0x34 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x34 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x34 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x34 6. "I2CSLEW,Controls slew rate of I2C pad." "0: I2C mode.,1: GPIO mode."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x34 11. "I2CFILTER,Configures I2C features for standard mode  fast mode  and Fast Mode Plus operation." "0: Enabled. I2C 50 ns glitch filter enabled.,1: Disabled. I2C 50 ns glitch filter disabled."
newline
bitfld.long 0x34 10. "I2CDRIVE,Controls the current sink capability of the pin." "0: Low drive. Output drive sink is 4 mA. This is..,1: High drive. Output drive sink is 20 mA. This is.."
newline
bitfld.long 0x34 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x34 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x34 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x34 6. "I2CSLEW,Controls slew rate of I2C pad." "0: I2C mode.,1: GPIO mode."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x34 11. "I2CFILTER,Configures I2C features for standard mode  fast mode  and Fast Mode Plus operation." "0: Enabled. I2C 50 ns glitch filter enabled.,1: Disabled. I2C 50 ns glitch filter disabled."
newline
bitfld.long 0x34 10. "I2CDRIVE,Controls the current sink capability of the pin." "0: Low drive. Output drive sink is 4 mA. This is..,1: High drive. Output drive sink is 20 mA. This is.."
newline
bitfld.long 0x34 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x34 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x34 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x34 6. "I2CSLEW,Controls slew rate of I2C pad." "0: I2C mode.,1: GPIO mode."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x34 11. "I2CFILTER,Configures I2C features for standard mode  fast mode  and Fast Mode Plus operation." "0: Enabled. I2C 50 ns glitch filter enabled.,1: Disabled. I2C 50 ns glitch filter disabled."
newline
bitfld.long 0x34 10. "I2CDRIVE,Controls the current sink capability of the pin." "0: Low drive. Output drive sink is 4 mA. This is..,1: High drive. Output drive sink is 20 mA. This is.."
newline
bitfld.long 0x34 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x34 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x34 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x34 6. "I2CSLEW,Controls slew rate of I2C pad." "0: I2C mode.,1: GPIO mode."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x34 11. "I2CFILTER,Configures I2C features for standard mode  fast mode  and Fast Mode Plus operation." "0: Enabled. I2C 50 ns glitch filter enabled.,1: Disabled. I2C 50 ns glitch filter disabled."
newline
bitfld.long 0x34 10. "I2CDRIVE,Controls the current sink capability of the pin." "0: Low drive. Output drive sink is 4 mA. This is..,1: High drive. Output drive sink is 20 mA. This is.."
newline
bitfld.long 0x34 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x34 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x34 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x34 6. "I2CSLEW,Controls slew rate of I2C pad." "0: I2C mode.,1: GPIO mode."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x34 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x34 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x34 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x34 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x34 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x34 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x34 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x34 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x34 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x34 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x34 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x34 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x34 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x34 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x34 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x34 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x34 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x34 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x34 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x34 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x34 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x34 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x34 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x34 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x34 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x34 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x34 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x34 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54605*"))
hexmask.long.byte 0x34 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54606*"))
hexmask.long.byte 0x34 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54607*"))
hexmask.long.byte 0x34 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54608*"))
hexmask.long.byte 0x34 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54616*"))
hexmask.long.byte 0x34 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54618*"))
hexmask.long.byte 0x34 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54628*"))
hexmask.long.byte 0x34 0.--3. 1. "FUNC,Selects pin function."
endif
line.long 0x38 "PIO014,Digital I/O control for port 0 pins PIO0_14"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x38 11. "I2CFILTEROFF,Configures I2C features for standard mode  fast mode  and Fast Mode Plus operation." "0: Enabled. I2C 50 ns glitch filter enabled.,1: Disabled. I2C 50 ns glitch filter disabled."
newline
bitfld.long 0x38 10. "I2CDRIVE,Controls the current sink capability of the pin." "0: Low drive. Output drive sink is 4 mA. This is..,1: High drive. Output drive sink is 20 mA. This is.."
newline
bitfld.long 0x38 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x38 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x38 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x38 6. "I2CSLEW,Controls slew rate of I2C pad." "0: I2C mode.,1: GPIO mode."
newline
hexmask.long.byte 0x38 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x38 11. "I2CFILTER,Configures I2C features for standard mode  fast mode  and Fast Mode Plus operation." "0: Enabled. I2C 50 ns glitch filter enabled.,1: Disabled. I2C 50 ns glitch filter disabled."
newline
bitfld.long 0x38 10. "I2CDRIVE,Controls the current sink capability of the pin." "0: Low drive. Output drive sink is 4 mA. This is..,1: High drive. Output drive sink is 20 mA. This is.."
newline
bitfld.long 0x38 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x38 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x38 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x38 6. "I2CSLEW,Controls slew rate of I2C pad." "0: I2C mode.,1: GPIO mode."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x38 11. "I2CFILTER,Configures I2C features for standard mode  fast mode  and Fast Mode Plus operation." "0: Enabled. I2C 50 ns glitch filter enabled.,1: Disabled. I2C 50 ns glitch filter disabled."
newline
bitfld.long 0x38 10. "I2CDRIVE,Controls the current sink capability of the pin." "0: Low drive. Output drive sink is 4 mA. This is..,1: High drive. Output drive sink is 20 mA. This is.."
newline
bitfld.long 0x38 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x38 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x38 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x38 6. "I2CSLEW,Controls slew rate of I2C pad." "0: I2C mode.,1: GPIO mode."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x38 11. "I2CFILTER,Configures I2C features for standard mode  fast mode  and Fast Mode Plus operation." "0: Enabled. I2C 50 ns glitch filter enabled.,1: Disabled. I2C 50 ns glitch filter disabled."
newline
bitfld.long 0x38 10. "I2CDRIVE,Controls the current sink capability of the pin." "0: Low drive. Output drive sink is 4 mA. This is..,1: High drive. Output drive sink is 20 mA. This is.."
newline
bitfld.long 0x38 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x38 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x38 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x38 6. "I2CSLEW,Controls slew rate of I2C pad." "0: I2C mode.,1: GPIO mode."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x38 11. "I2CFILTER,Configures I2C features for standard mode  fast mode  and Fast Mode Plus operation." "0: Enabled. I2C 50 ns glitch filter enabled.,1: Disabled. I2C 50 ns glitch filter disabled."
newline
bitfld.long 0x38 10. "I2CDRIVE,Controls the current sink capability of the pin." "0: Low drive. Output drive sink is 4 mA. This is..,1: High drive. Output drive sink is 20 mA. This is.."
newline
bitfld.long 0x38 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x38 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x38 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x38 6. "I2CSLEW,Controls slew rate of I2C pad." "0: I2C mode.,1: GPIO mode."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x38 11. "I2CFILTER,Configures I2C features for standard mode  fast mode  and Fast Mode Plus operation." "0: Enabled. I2C 50 ns glitch filter enabled.,1: Disabled. I2C 50 ns glitch filter disabled."
newline
bitfld.long 0x38 10. "I2CDRIVE,Controls the current sink capability of the pin." "0: Low drive. Output drive sink is 4 mA. This is..,1: High drive. Output drive sink is 20 mA. This is.."
newline
bitfld.long 0x38 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x38 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x38 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x38 6. "I2CSLEW,Controls slew rate of I2C pad." "0: I2C mode.,1: GPIO mode."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x38 11. "I2CFILTER,Configures I2C features for standard mode  fast mode  and Fast Mode Plus operation." "0: Enabled. I2C 50 ns glitch filter enabled.,1: Disabled. I2C 50 ns glitch filter disabled."
newline
bitfld.long 0x38 10. "I2CDRIVE,Controls the current sink capability of the pin." "0: Low drive. Output drive sink is 4 mA. This is..,1: High drive. Output drive sink is 20 mA. This is.."
newline
bitfld.long 0x38 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x38 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x38 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x38 6. "I2CSLEW,Controls slew rate of I2C pad." "0: I2C mode.,1: GPIO mode."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x38 11. "I2CFILTER,Configures I2C features for standard mode  fast mode  and Fast Mode Plus operation." "0: Enabled. I2C 50 ns glitch filter enabled.,1: Disabled. I2C 50 ns glitch filter disabled."
newline
bitfld.long 0x38 10. "I2CDRIVE,Controls the current sink capability of the pin." "0: Low drive. Output drive sink is 4 mA. This is..,1: High drive. Output drive sink is 20 mA. This is.."
newline
bitfld.long 0x38 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x38 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x38 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x38 6. "I2CSLEW,Controls slew rate of I2C pad." "0: I2C mode.,1: GPIO mode."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x38 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x38 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x38 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x38 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x38 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x38 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x38 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x38 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x38 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x38 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x38 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x38 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x38 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x38 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x38 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x38 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x38 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x38 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x38 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x38 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x38 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x38 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x38 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x38 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x38 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x38 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x38 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x38 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54605*"))
hexmask.long.byte 0x38 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54606*"))
hexmask.long.byte 0x38 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54607*"))
hexmask.long.byte 0x38 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54608*"))
hexmask.long.byte 0x38 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54616*"))
hexmask.long.byte 0x38 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54618*"))
hexmask.long.byte 0x38 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54628*"))
hexmask.long.byte 0x38 0.--3. 1. "FUNC,Selects pin function."
endif
line.long 0x3C "PIO015,Digital I/O control for port 0 pins PIO0_15"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x3C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x3C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x3C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x3C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x3C 6. "ANAMODE,Enables or disables analog mode." "0: Enable analog Mode.,1: Disable analog Mode."
newline
bitfld.long 0x3C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x3C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x3C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x3C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x3C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x3C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x3C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x3C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x3C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x3C 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x3C 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x3C 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x3C 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x3C 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x3C 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x3C 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x3C 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x3C 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x3C 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x3C 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x3C 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x3C 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x3C 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x3C 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x3C 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x3C 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x3C 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x3C 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x3C 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x3C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x3C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x3C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x3C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x3C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x3C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x3C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x3C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x3C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x3C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x3C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x3C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x3C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x3C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x3C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x3C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x3C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x3C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x3C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x3C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x3C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x3C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x3C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x3C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x3C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x3C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x3C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x3C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x3C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x3C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x3C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x3C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x3C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x3C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x3C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x3C 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x3C 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x3C 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x3C 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x3C 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x3C 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x3C 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x3C 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
line.long 0x40 "PIO016,Digital I/O control for port 0 pins PIO0_16"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x40 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x40 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x40 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x40 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x40 6. "ANAMODE,Enables or disables analog mode." "0: Enable analog Mode.,1: Disable analog Mode."
newline
bitfld.long 0x40 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x40 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x40 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x40 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x40 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x40 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x40 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x40 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x40 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x40 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x40 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x40 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x40 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x40 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x40 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x40 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x40 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x40 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x40 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x40 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x40 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x40 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x40 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x40 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x40 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x40 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x40 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x40 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x40 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x40 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x40 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x40 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x40 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x40 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x40 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x40 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x40 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x40 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x40 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x40 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x40 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x40 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x40 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x40 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x40 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x40 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x40 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x40 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x40 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x40 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x40 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x40 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x40 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x40 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x40 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x40 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x40 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x40 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x40 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x40 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x40 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x40 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x40 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x40 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x40 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x40 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x40 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x40 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x40 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x40 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x40 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x40 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
line.long 0x44 "PIO017,Digital I/O control for port 0 pins PIO0_17"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x44 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x44 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x44 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x44 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x44 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x44 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x44 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x44 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x44 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x44 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x44 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x44 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x44 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x44 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x44 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x44 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x44 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x44 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x44 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x44 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x44 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x44 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x44 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x44 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x44 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x44 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x44 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x44 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x44 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x44 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x44 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x44 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x44 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x44 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x44 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x44 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x44 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x44 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x44 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x44 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x44 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x44 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x44 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x44 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x44 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x44 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x44 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x44 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x44 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x44 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x44 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x44 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x44 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x44 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x44 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x44 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x44 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x44 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x44 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x44 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x44 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x44 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x44 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x44 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x44 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x44 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x44 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x44 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x44 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x44 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x44 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x44 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x44 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x44 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x44 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x44 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x44 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x44 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x44 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x44 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x44 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x44 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x44 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x44 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
line.long 0x48 "PIO018,Digital I/O control for port 0 pins PIO0_18"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x48 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x48 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x48 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x48 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x48 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x48 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x48 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x48 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x48 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x48 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x48 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x48 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x48 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x48 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x48 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x48 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x48 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x48 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x48 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x48 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x48 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x48 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x48 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x48 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x48 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x48 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x48 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x48 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x48 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x48 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x48 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x48 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x48 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x48 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x48 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x48 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x48 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x48 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x48 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x48 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x48 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x48 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x48 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x48 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x48 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x48 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x48 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x48 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x48 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x48 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x48 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x48 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x48 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x48 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x48 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x48 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x48 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x48 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x48 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x48 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x48 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x48 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x48 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x48 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x48 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x48 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x48 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x48 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x48 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x48 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x48 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x48 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x48 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x48 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x48 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x48 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x48 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x48 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x48 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x48 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x48 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x48 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x48 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x48 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
line.long 0x4C "PIO019,Digital I/O control for port 0 pins PIO0_19"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x4C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x4C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x4C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x4C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x4C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x4C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x4C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x4C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x4C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x4C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x4C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x4C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x4C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x4C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x4C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x4C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x4C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x4C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x4C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x4C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x4C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x4C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x4C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x4C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x4C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x4C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x4C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x4C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x4C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x4C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x4C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x4C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x4C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x4C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x4C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x4C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x4C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x4C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x4C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x4C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x4C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x4C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x4C 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x4C 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x4C 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x4C 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x4C 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x4C 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x4C 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x4C 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x4C 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x4C 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x4C 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x4C 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x4C 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x4C 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x4C 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x4C 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x4C 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x4C 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x4C 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x4C 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x4C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x4C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x4C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x4C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x4C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x4C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x4C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x4C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x4C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x4C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x4C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x4C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x4C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x4C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x4C 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x4C 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x4C 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x4C 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x4C 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x4C 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x4C 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x4C 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
line.long 0x50 "PIO020,Digital I/O control for port 0 pins PIO0_20"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x50 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x50 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x50 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x50 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x50 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x50 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x50 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x50 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x50 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x50 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x50 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x50 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x50 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x50 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x50 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x50 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x50 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x50 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x50 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x50 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x50 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x50 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x50 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x50 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x50 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x50 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x50 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x50 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x50 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x50 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x50 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x50 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x50 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x50 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x50 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x50 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x50 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x50 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x50 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x50 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x50 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x50 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x50 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x50 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x50 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x50 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x50 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x50 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x50 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x50 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x50 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x50 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x50 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x50 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x50 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x50 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x50 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x50 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x50 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x50 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x50 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x50 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x50 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x50 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x50 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x50 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x50 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x50 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x50 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x50 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x50 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x50 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x50 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x50 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x50 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x50 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x50 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x50 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x50 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x50 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x50 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x50 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x50 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x50 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
line.long 0x54 "PIO021,Digital I/O control for port 0 pins PIO0_21"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x54 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x54 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x54 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x54 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x54 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x54 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x54 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x54 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x54 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x54 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x54 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x54 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x54 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x54 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x54 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x54 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x54 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x54 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x54 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x54 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x54 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x54 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x54 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x54 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x54 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x54 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x54 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x54 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x54 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x54 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x54 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x54 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x54 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x54 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x54 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x54 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x54 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x54 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x54 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x54 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x54 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x54 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x54 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x54 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x54 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x54 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x54 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x54 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x54 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x54 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x54 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x54 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x54 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x54 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x54 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x54 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x54 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x54 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x54 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x54 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x54 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x54 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x54 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x54 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x54 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x54 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x54 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x54 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x54 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x54 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x54 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x54 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x54 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x54 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x54 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x54 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x54 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x54 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x54 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x54 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x54 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x54 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x54 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x54 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
line.long 0x58 "PIO022,Digital I/O control for port 0 pins PIO0_22"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x58 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x58 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x58 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x58 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x58 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x58 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x58 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x58 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x58 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x58 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x58 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x58 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x58 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x58 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x58 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x58 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x58 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x58 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x58 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x58 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x58 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x58 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x58 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x58 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x58 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x58 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x58 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x58 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x58 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x58 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x58 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x58 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x58 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x58 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x58 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x58 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x58 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x58 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x58 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x58 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x58 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x58 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x58 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x58 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x58 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x58 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x58 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x58 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x58 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x58 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x58 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x58 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x58 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x58 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x58 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x58 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x58 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x58 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x58 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x58 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x58 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x58 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x58 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x58 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x58 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x58 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x58 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x58 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x58 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x58 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x58 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x58 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x58 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x58 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x58 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x58 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x58 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x58 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x58 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x58 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x58 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x58 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x58 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x58 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
line.long 0x5C "PIO023,Digital I/O control for port 0 pins PIO0_23"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x5C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x5C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x5C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x5C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x5C 6. "ANAMODE,Enables or disables analog mode." "0: Enable analog Mode.,1: Disable analog Mode."
newline
bitfld.long 0x5C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x5C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x5C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x5C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x5C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x5C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x5C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x5C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x5C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x5C 10. "I2CFILTER,Configures I2C features for standard mode  fast mode  and Fast Mode Plus operation." "0: Enabled. I2C 50 ns glitch filter enabled.,1: Disabled. I2C 50 ns glitch filter disabled."
newline
bitfld.long 0x5C 9. "I2CDRIVE,Controls the current sink capability of the pin." "0: Low drive. Output drive sink is 4 mA. This is..,1: High drive. Output drive sink is 20 mA. This is.."
newline
bitfld.long 0x5C 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x5C 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x5C 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x5C 5. "I2CSLEW,Controls slew rate of I2C pad." "0: I2C mode.,1: GPIO mode."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x5C 10. "I2CFILTER,Configures I2C features for standard mode  fast mode  and Fast Mode Plus operation." "0: Enabled. I2C 50 ns glitch filter enabled.,1: Disabled. I2C 50 ns glitch filter disabled."
newline
bitfld.long 0x5C 9. "I2CDRIVE,Controls the current sink capability of the pin." "0: Low drive. Output drive sink is 4 mA. This is..,1: High drive. Output drive sink is 20 mA. This is.."
newline
bitfld.long 0x5C 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x5C 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x5C 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x5C 5. "I2CSLEW,Controls slew rate of I2C pad." "0: I2C mode.,1: GPIO mode."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x5C 10. "I2CFILTER,Configures I2C features for standard mode  fast mode  and Fast Mode Plus operation." "0: Enabled. I2C 50 ns glitch filter enabled.,1: Disabled. I2C 50 ns glitch filter disabled."
newline
bitfld.long 0x5C 9. "I2CDRIVE,Controls the current sink capability of the pin." "0: Low drive. Output drive sink is 4 mA. This is..,1: High drive. Output drive sink is 20 mA. This is.."
newline
bitfld.long 0x5C 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x5C 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x5C 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x5C 5. "I2CSLEW,Controls slew rate of I2C pad." "0: I2C mode.,1: GPIO mode."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x5C 10. "I2CFILTER,Configures I2C features for standard mode  fast mode  and Fast Mode Plus operation." "0: Enabled. I2C 50 ns glitch filter enabled.,1: Disabled. I2C 50 ns glitch filter disabled."
newline
bitfld.long 0x5C 9. "I2CDRIVE,Controls the current sink capability of the pin." "0: Low drive. Output drive sink is 4 mA. This is..,1: High drive. Output drive sink is 20 mA. This is.."
newline
bitfld.long 0x5C 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x5C 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x5C 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x5C 5. "I2CSLEW,Controls slew rate of I2C pad." "0: I2C mode.,1: GPIO mode."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x5C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x5C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x5C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x5C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x5C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x5C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x5C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x5C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x5C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x5C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x5C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x5C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x5C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x5C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x5C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x5C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x5C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x5C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x5C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x5C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x5C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x5C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x5C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x5C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x5C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x5C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x5C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x5C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x5C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x5C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x5C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x5C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x5C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x5C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x5C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x5C 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x5C 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x5C 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x5C 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
line.long 0x60 "PIO024,Digital I/O control for port 0 pins PIO0_24"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x60 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x60 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x60 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x60 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x60 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x60 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x60 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x60 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x60 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x60 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x60 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x60 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x60 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x60 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x60 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x60 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x60 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x60 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x60 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x60 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x60 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x60 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x60 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x60 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x60 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x60 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x60 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x60 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x60 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x60 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x60 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x60 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x60 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x60 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x60 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x60 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x60 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x60 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x60 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x60 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x60 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x60 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x60 10. "I2CFILTER,Configures I2C features for standard mode  fast mode  and Fast Mode Plus operation." "0: Enabled. I2C 50 ns glitch filter enabled.,1: Disabled. I2C 50 ns glitch filter disabled."
newline
bitfld.long 0x60 9. "I2CDRIVE,Controls the current sink capability of the pin." "0: Low drive. Output drive sink is 4 mA. This is..,1: High drive. Output drive sink is 20 mA. This is.."
newline
bitfld.long 0x60 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x60 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x60 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x60 5. "I2CSLEW,Controls slew rate of I2C pad." "0: I2C mode.,1: GPIO mode."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x60 10. "I2CFILTER,Configures I2C features for standard mode  fast mode  and Fast Mode Plus operation." "0: Enabled. I2C 50 ns glitch filter enabled.,1: Disabled. I2C 50 ns glitch filter disabled."
newline
bitfld.long 0x60 9. "I2CDRIVE,Controls the current sink capability of the pin." "0: Low drive. Output drive sink is 4 mA. This is..,1: High drive. Output drive sink is 20 mA. This is.."
newline
bitfld.long 0x60 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x60 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x60 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x60 5. "I2CSLEW,Controls slew rate of I2C pad." "0: I2C mode.,1: GPIO mode."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x60 10. "I2CFILTER,Configures I2C features for standard mode  fast mode  and Fast Mode Plus operation." "0: Enabled. I2C 50 ns glitch filter enabled.,1: Disabled. I2C 50 ns glitch filter disabled."
newline
bitfld.long 0x60 9. "I2CDRIVE,Controls the current sink capability of the pin." "0: Low drive. Output drive sink is 4 mA. This is..,1: High drive. Output drive sink is 20 mA. This is.."
newline
bitfld.long 0x60 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x60 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x60 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x60 5. "I2CSLEW,Controls slew rate of I2C pad." "0: I2C mode.,1: GPIO mode."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x60 10. "I2CFILTER,Configures I2C features for standard mode  fast mode  and Fast Mode Plus operation." "0: Enabled. I2C 50 ns glitch filter enabled.,1: Disabled. I2C 50 ns glitch filter disabled."
newline
bitfld.long 0x60 9. "I2CDRIVE,Controls the current sink capability of the pin." "0: Low drive. Output drive sink is 4 mA. This is..,1: High drive. Output drive sink is 20 mA. This is.."
newline
bitfld.long 0x60 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x60 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x60 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x60 5. "I2CSLEW,Controls slew rate of I2C pad." "0: I2C mode.,1: GPIO mode."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x60 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x60 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x60 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x60 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x60 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x60 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x60 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x60 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x60 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x60 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x60 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x60 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x60 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x60 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x60 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x60 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x60 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x60 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
line.long 0x64 "PIO025,Digital I/O control for port 0 pins PIO0_25"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x64 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x64 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x64 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x64 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x64 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x64 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x64 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x64 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x64 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x64 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x64 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x64 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x64 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x64 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x64 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x64 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x64 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x64 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x64 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x64 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x64 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x64 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x64 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x64 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x64 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x64 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x64 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x64 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x64 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x64 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x64 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x64 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x64 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x64 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x64 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x64 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x64 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x64 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x64 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x64 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x64 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x64 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x64 10. "I2CFILTER,Configures I2C features for standard mode  fast mode  and Fast Mode Plus operation." "0: Enabled. I2C 50 ns glitch filter enabled.,1: Disabled. I2C 50 ns glitch filter disabled."
newline
bitfld.long 0x64 9. "I2CDRIVE,Controls the current sink capability of the pin." "0: Low drive. Output drive sink is 4 mA. This is..,1: High drive. Output drive sink is 20 mA. This is.."
newline
bitfld.long 0x64 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x64 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x64 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x64 5. "I2CSLEW,Controls slew rate of I2C pad." "0: I2C mode.,1: GPIO mode."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x64 10. "I2CFILTER,Configures I2C features for standard mode  fast mode  and Fast Mode Plus operation." "0: Enabled. I2C 50 ns glitch filter enabled.,1: Disabled. I2C 50 ns glitch filter disabled."
newline
bitfld.long 0x64 9. "I2CDRIVE,Controls the current sink capability of the pin." "0: Low drive. Output drive sink is 4 mA. This is..,1: High drive. Output drive sink is 20 mA. This is.."
newline
bitfld.long 0x64 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x64 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x64 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x64 5. "I2CSLEW,Controls slew rate of I2C pad." "0: I2C mode.,1: GPIO mode."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x64 10. "I2CFILTER,Configures I2C features for standard mode  fast mode  and Fast Mode Plus operation." "0: Enabled. I2C 50 ns glitch filter enabled.,1: Disabled. I2C 50 ns glitch filter disabled."
newline
bitfld.long 0x64 9. "I2CDRIVE,Controls the current sink capability of the pin." "0: Low drive. Output drive sink is 4 mA. This is..,1: High drive. Output drive sink is 20 mA. This is.."
newline
bitfld.long 0x64 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x64 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x64 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x64 5. "I2CSLEW,Controls slew rate of I2C pad." "0: I2C mode.,1: GPIO mode."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x64 10. "I2CFILTER,Configures I2C features for standard mode  fast mode  and Fast Mode Plus operation." "0: Enabled. I2C 50 ns glitch filter enabled.,1: Disabled. I2C 50 ns glitch filter disabled."
newline
bitfld.long 0x64 9. "I2CDRIVE,Controls the current sink capability of the pin." "0: Low drive. Output drive sink is 4 mA. This is..,1: High drive. Output drive sink is 20 mA. This is.."
newline
bitfld.long 0x64 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x64 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x64 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x64 5. "I2CSLEW,Controls slew rate of I2C pad." "0: I2C mode.,1: GPIO mode."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x64 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x64 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x64 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x64 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x64 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x64 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x64 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x64 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x64 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x64 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x64 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x64 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x64 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x64 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x64 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x64 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x64 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x64 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
line.long 0x68 "PIO026,Digital I/O control for port 0 pins PIO0_26"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x68 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x68 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x68 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x68 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x68 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x68 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x68 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x68 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x68 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x68 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x68 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x68 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x68 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x68 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x68 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x68 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x68 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x68 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x68 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x68 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x68 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x68 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x68 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x68 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x68 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x68 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x68 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x68 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x68 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x68 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x68 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x68 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x68 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x68 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x68 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x68 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x68 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x68 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x68 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x68 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x68 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x68 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x68 10. "I2CFILTER,Configures I2C features for standard mode  fast mode  and Fast Mode Plus operation." "0: Enabled. I2C 50 ns glitch filter enabled.,1: Disabled. I2C 50 ns glitch filter disabled."
newline
bitfld.long 0x68 9. "I2CDRIVE,Controls the current sink capability of the pin." "0: Low drive. Output drive sink is 4 mA. This is..,1: High drive. Output drive sink is 20 mA. This is.."
newline
bitfld.long 0x68 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x68 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x68 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x68 5. "I2CSLEW,Controls slew rate of I2C pad." "0: I2C mode.,1: GPIO mode."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x68 10. "I2CFILTER,Configures I2C features for standard mode  fast mode  and Fast Mode Plus operation." "0: Enabled. I2C 50 ns glitch filter enabled.,1: Disabled. I2C 50 ns glitch filter disabled."
newline
bitfld.long 0x68 9. "I2CDRIVE,Controls the current sink capability of the pin." "0: Low drive. Output drive sink is 4 mA. This is..,1: High drive. Output drive sink is 20 mA. This is.."
newline
bitfld.long 0x68 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x68 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x68 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x68 5. "I2CSLEW,Controls slew rate of I2C pad." "0: I2C mode.,1: GPIO mode."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x68 10. "I2CFILTER,Configures I2C features for standard mode  fast mode  and Fast Mode Plus operation." "0: Enabled. I2C 50 ns glitch filter enabled.,1: Disabled. I2C 50 ns glitch filter disabled."
newline
bitfld.long 0x68 9. "I2CDRIVE,Controls the current sink capability of the pin." "0: Low drive. Output drive sink is 4 mA. This is..,1: High drive. Output drive sink is 20 mA. This is.."
newline
bitfld.long 0x68 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x68 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x68 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x68 5. "I2CSLEW,Controls slew rate of I2C pad." "0: I2C mode.,1: GPIO mode."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x68 10. "I2CFILTER,Configures I2C features for standard mode  fast mode  and Fast Mode Plus operation." "0: Enabled. I2C 50 ns glitch filter enabled.,1: Disabled. I2C 50 ns glitch filter disabled."
newline
bitfld.long 0x68 9. "I2CDRIVE,Controls the current sink capability of the pin." "0: Low drive. Output drive sink is 4 mA. This is..,1: High drive. Output drive sink is 20 mA. This is.."
newline
bitfld.long 0x68 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x68 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x68 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x68 5. "I2CSLEW,Controls slew rate of I2C pad." "0: I2C mode.,1: GPIO mode."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x68 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x68 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x68 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x68 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x68 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x68 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x68 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x68 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x68 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x68 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x68 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x68 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x68 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x68 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x68 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x68 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x68 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x68 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
line.long 0x6C "PIO027,Digital I/O control for port 0 pins PIO0_27"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x6C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x6C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x6C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x6C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x6C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x6C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x6C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x6C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x6C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x6C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x6C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x6C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x6C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x6C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x6C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x6C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x6C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x6C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x6C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x6C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x6C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x6C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x6C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x6C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x6C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x6C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x6C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x6C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x6C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x6C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x6C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x6C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x6C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x6C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x6C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x6C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x6C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x6C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x6C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x6C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x6C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x6C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x6C 10. "I2CFILTER,Configures I2C features for standard mode  fast mode  and Fast Mode Plus operation." "0: Enabled. I2C 50 ns glitch filter enabled.,1: Disabled. I2C 50 ns glitch filter disabled."
newline
bitfld.long 0x6C 9. "I2CDRIVE,Controls the current sink capability of the pin." "0: Low drive. Output drive sink is 4 mA. This is..,1: High drive. Output drive sink is 20 mA. This is.."
newline
bitfld.long 0x6C 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x6C 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x6C 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x6C 5. "I2CSLEW,Controls slew rate of I2C pad." "0: I2C mode.,1: GPIO mode."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x6C 10. "I2CFILTER,Configures I2C features for standard mode  fast mode  and Fast Mode Plus operation." "0: Enabled. I2C 50 ns glitch filter enabled.,1: Disabled. I2C 50 ns glitch filter disabled."
newline
bitfld.long 0x6C 9. "I2CDRIVE,Controls the current sink capability of the pin." "0: Low drive. Output drive sink is 4 mA. This is..,1: High drive. Output drive sink is 20 mA. This is.."
newline
bitfld.long 0x6C 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x6C 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x6C 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x6C 5. "I2CSLEW,Controls slew rate of I2C pad." "0: I2C mode.,1: GPIO mode."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x6C 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x6C 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x6C 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x6C 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x6C 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x6C 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x6C 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x6C 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x6C 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x6C 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x6C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x6C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x6C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x6C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x6C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x6C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x6C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x6C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x6C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x6C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x6C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x6C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x6C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x6C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x6C 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x6C 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x6C 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x6C 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x6C 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x6C 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
line.long 0x70 "PIO028,Digital I/O control for port 0 pins PIO0_28"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x70 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x70 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x70 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x70 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x70 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x70 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x70 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x70 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x70 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x70 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x70 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x70 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x70 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x70 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x70 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x70 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x70 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x70 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x70 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x70 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x70 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x70 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x70 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x70 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x70 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x70 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x70 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x70 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x70 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x70 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x70 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x70 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x70 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x70 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x70 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x70 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x70 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x70 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x70 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x70 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x70 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x70 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x70 10. "I2CFILTER,Configures I2C features for standard mode  fast mode  and Fast Mode Plus operation." "0: Enabled. I2C 50 ns glitch filter enabled.,1: Disabled. I2C 50 ns glitch filter disabled."
newline
bitfld.long 0x70 9. "I2CDRIVE,Controls the current sink capability of the pin." "0: Low drive. Output drive sink is 4 mA. This is..,1: High drive. Output drive sink is 20 mA. This is.."
newline
bitfld.long 0x70 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x70 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x70 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x70 5. "I2CSLEW,Controls slew rate of I2C pad." "0: I2C mode.,1: GPIO mode."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x70 10. "I2CFILTER,Configures I2C features for standard mode  fast mode  and Fast Mode Plus operation." "0: Enabled. I2C 50 ns glitch filter enabled.,1: Disabled. I2C 50 ns glitch filter disabled."
newline
bitfld.long 0x70 9. "I2CDRIVE,Controls the current sink capability of the pin." "0: Low drive. Output drive sink is 4 mA. This is..,1: High drive. Output drive sink is 20 mA. This is.."
newline
bitfld.long 0x70 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x70 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x70 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x70 5. "I2CSLEW,Controls slew rate of I2C pad." "0: I2C mode.,1: GPIO mode."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x70 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x70 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x70 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x70 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x70 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x70 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x70 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x70 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x70 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x70 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x70 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x70 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x70 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x70 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x70 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x70 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x70 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x70 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x70 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x70 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x70 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x70 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x70 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x70 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x70 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x70 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x70 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x70 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x70 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x70 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
line.long 0x74 "PIO029,Digital I/O control for port 0 pins PIO0_29"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x74 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x74 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x74 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x74 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x74 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x74 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x74 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x74 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x74 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x74 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x74 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x74 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x74 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x74 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x74 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x74 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x74 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x74 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x74 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x74 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x74 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x74 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x74 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x74 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x74 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x74 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x74 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x74 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x74 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x74 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x74 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x74 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x74 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x74 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x74 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x74 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x74 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x74 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x74 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x74 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x74 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x74 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x74 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x74 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x74 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x74 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x74 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x74 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x74 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x74 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x74 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x74 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x74 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x74 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x74 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x74 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x74 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x74 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x74 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x74 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x74 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x74 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x74 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x74 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x74 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x74 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x74 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x74 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x74 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x74 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x74 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x74 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x74 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x74 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x74 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x74 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x74 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x74 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x74 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x74 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
line.long 0x78 "PIO030,Digital I/O control for port 0 pins PIO0_30"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x78 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x78 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x78 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x78 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x78 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x78 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x78 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x78 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x78 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x78 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x78 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x78 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x78 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x78 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x78 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x78 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x78 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x78 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x78 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x78 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x78 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x78 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x78 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x78 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x78 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x78 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x78 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x78 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x78 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x78 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x78 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x78 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x78 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x78 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x78 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x78 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x78 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x78 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x78 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x78 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x78 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x78 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x78 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x78 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x78 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x78 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x78 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x78 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x78 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x78 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x78 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x78 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x78 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x78 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x78 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x78 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x78 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x78 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x78 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x78 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x78 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x78 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x78 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x78 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x78 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x78 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x78 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x78 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x78 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x78 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x78 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x78 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x78 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x78 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x78 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x78 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x78 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x78 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x78 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x78 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
line.long 0x7C "PIO031,Digital I/O control for port 0 pins PIO0_31"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x7C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x7C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x7C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x7C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x7C 6. "ANAMODE,Enables or disables analog mode." "0: Enable analog Mode.,1: Disable analog Mode."
newline
bitfld.long 0x7C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x7C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x7C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x7C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x7C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x7C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x7C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x7C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x7C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x7C 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x7C 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x7C 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x7C 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x7C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x7C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x7C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x7C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x7C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x7C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x7C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x7C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x7C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x7C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x7C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x7C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x7C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x7C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x7C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x7C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x7C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x7C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x7C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x7C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x7C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x7C 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x7C 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x7C 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x7C 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x7C 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x7C 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x7C 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x7C 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x7C 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x7C 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x7C 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x7C 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x7C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x7C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x7C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x7C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x7C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x7C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x7C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x7C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x7C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x7C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x7C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x7C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x7C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x7C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x7C 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x7C 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x7C 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x7C 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x7C 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x7C 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x7C 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x7C 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
line.long 0x80 "PIO10,Digital I/O control for port 1 pins PIO1_0"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x80 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x80 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x80 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x80 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x80 6. "ANAMODE,Enables or disables analog mode." "0: Enable analog Mode.,1: Disable analog Mode."
newline
bitfld.long 0x80 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x80 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x80 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x80 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x80 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x80 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x80 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x80 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x80 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x80 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x80 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x80 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x80 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x80 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x80 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x80 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x80 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x80 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x80 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x80 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x80 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x80 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x80 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x80 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x80 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x80 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x80 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x80 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x80 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x80 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x80 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x80 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x80 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x80 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x80 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x80 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x80 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x80 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x80 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x80 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x80 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x80 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x80 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x80 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x80 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x80 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x80 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x80 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x80 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x80 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x80 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x80 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x80 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x80 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x80 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x80 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x80 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x80 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x80 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x80 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x80 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x80 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x80 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x80 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x80 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x80 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x80 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x80 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
line.long 0x84 "PIO11,Digital I/O control for port 1 pins PIO1_1"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x84 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x84 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x84 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x84 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x84 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x84 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x84 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x84 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x84 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x84 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x84 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x84 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x84 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x84 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x84 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x84 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x84 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x84 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x84 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x84 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x84 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x84 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x84 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x84 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x84 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x84 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x84 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x84 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x84 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x84 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x84 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x84 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x84 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x84 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x84 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x84 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x84 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x84 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x84 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x84 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x84 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x84 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x84 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x84 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x84 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x84 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x84 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x84 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x84 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x84 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x84 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x84 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x84 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x84 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x84 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x84 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x84 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x84 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x84 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x84 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x84 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x84 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x84 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x84 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x84 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x84 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x84 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x84 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x84 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x84 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x84 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x84 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x84 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x84 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x84 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x84 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x84 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x84 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x84 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x84 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
line.long 0x88 "PIO12,Digital I/O control for port 1 pins PIO1_2"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x88 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x88 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x88 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x88 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x88 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x88 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x88 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x88 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x88 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x88 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x88 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x88 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x88 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x88 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x88 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x88 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x88 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x88 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x88 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x88 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x88 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x88 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x88 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x88 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x88 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x88 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x88 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x88 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x88 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x88 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x88 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x88 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x88 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x88 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x88 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x88 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x88 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x88 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x88 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x88 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x88 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x88 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x88 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x88 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x88 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x88 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x88 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x88 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x88 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x88 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x88 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x88 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x88 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x88 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x88 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x88 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x88 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x88 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x88 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x88 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x88 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x88 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x88 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x88 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x88 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x88 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x88 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x88 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x88 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x88 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x88 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x88 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x88 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x88 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x88 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x88 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x88 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x88 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x88 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x88 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
line.long 0x8C "PIO13,Digital I/O control for port 1 pins PIO1_3"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x8C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x8C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x8C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x8C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x8C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x8C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x8C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x8C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x8C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x8C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x8C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x8C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x8C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x8C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x8C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x8C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x8C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x8C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x8C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x8C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x8C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x8C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x8C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x8C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x8C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x8C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x8C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x8C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x8C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x8C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x8C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x8C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x8C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x8C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x8C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x8C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x8C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x8C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x8C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x8C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x8C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x8C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x8C 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x8C 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x8C 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x8C 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x8C 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x8C 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x8C 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x8C 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x8C 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x8C 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x8C 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x8C 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x8C 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x8C 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x8C 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x8C 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x8C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x8C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x8C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x8C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x8C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x8C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x8C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x8C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x8C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x8C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x8C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x8C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x8C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x8C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x8C 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x8C 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x8C 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x8C 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x8C 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x8C 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x8C 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x8C 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
line.long 0x90 "PIO14,Digital I/O control for port 1 pins PIO1_4"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x90 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x90 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x90 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x90 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x90 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x90 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x90 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x90 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x90 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x90 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x90 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x90 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x90 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x90 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x90 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x90 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x90 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x90 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x90 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x90 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x90 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x90 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x90 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x90 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x90 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x90 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x90 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x90 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x90 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x90 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x90 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x90 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x90 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x90 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x90 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x90 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x90 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x90 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x90 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x90 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x90 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x90 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x90 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x90 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x90 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x90 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x90 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x90 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x90 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x90 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x90 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x90 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x90 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x90 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x90 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x90 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x90 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x90 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x90 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x90 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x90 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x90 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x90 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x90 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x90 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x90 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x90 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x90 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x90 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x90 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x90 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x90 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x90 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x90 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x90 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x90 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x90 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x90 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x90 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x90 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
line.long 0x94 "PIO15,Digital I/O control for port 1 pins PIO1_5"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x94 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x94 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x94 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x94 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x94 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x94 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x94 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x94 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x94 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x94 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x94 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x94 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x94 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x94 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x94 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x94 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x94 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x94 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x94 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x94 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x94 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x94 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x94 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x94 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x94 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x94 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x94 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x94 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x94 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x94 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x94 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x94 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x94 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x94 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x94 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x94 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x94 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x94 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x94 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x94 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x94 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x94 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x94 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x94 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x94 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x94 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x94 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x94 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x94 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x94 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x94 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x94 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x94 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x94 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x94 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x94 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x94 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x94 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x94 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x94 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x94 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x94 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x94 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x94 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x94 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x94 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x94 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x94 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x94 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x94 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x94 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x94 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x94 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x94 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x94 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x94 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x94 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x94 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x94 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x94 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
line.long 0x98 "PIO16,Digital I/O control for port 1 pins PIO1_6"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x98 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x98 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x98 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x98 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x98 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x98 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x98 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x98 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x98 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x98 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x98 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x98 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x98 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x98 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x98 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x98 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x98 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x98 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x98 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x98 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x98 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x98 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x98 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x98 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x98 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x98 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x98 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x98 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x98 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x98 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x98 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x98 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x98 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x98 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x98 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x98 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x98 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x98 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x98 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x98 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x98 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x98 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x98 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x98 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x98 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x98 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x98 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x98 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x98 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x98 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x98 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x98 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x98 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x98 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x98 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x98 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x98 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x98 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x98 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x98 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x98 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x98 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x98 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x98 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x98 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x98 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x98 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x98 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x98 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x98 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x98 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x98 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x98 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x98 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x98 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x98 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x98 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x98 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x98 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x98 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
line.long 0x9C "PIO17,Digital I/O control for port 1 pins PIO1_7"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x9C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x9C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x9C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x9C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x9C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x9C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x9C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x9C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x9C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x9C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x9C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x9C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x9C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x9C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x9C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x9C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x9C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x9C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x9C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x9C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x9C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x9C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x9C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x9C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x9C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x9C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x9C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x9C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x9C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x9C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x9C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x9C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x9C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x9C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x9C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x9C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x9C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x9C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x9C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x9C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x9C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x9C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x9C 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x9C 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x9C 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x9C 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x9C 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x9C 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x9C 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x9C 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x9C 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x9C 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x9C 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x9C 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x9C 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x9C 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x9C 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x9C 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x9C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x9C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x9C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x9C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x9C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x9C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x9C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x9C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x9C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x9C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x9C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x9C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x9C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x9C 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x9C 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x9C 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x9C 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x9C 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x9C 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x9C 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x9C 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0x9C 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
line.long 0xA0 "PIO18,Digital I/O control for port 1 pins PIO1_8"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0xA0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xA0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xA0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xA0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xA0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xA0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xA0 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0xA0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xA0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xA0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xA0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xA0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0xA0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xA0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xA0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xA0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xA0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0xA0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xA0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xA0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xA0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xA0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0xA0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xA0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xA0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xA0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xA0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0xA0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xA0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xA0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xA0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xA0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0xA0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xA0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xA0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xA0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xA0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0xA0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xA0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xA0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xA0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xA0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0xA0 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0xA0 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0xA0 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0xA0 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0xA0 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xA0 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xA0 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0xA0 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xA0 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xA0 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0xA0 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xA0 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xA0 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0xA0 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xA0 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xA0 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0xA0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xA0 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0xA0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xA0 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0xA0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xA0 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0xA0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xA0 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0xA0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xA0 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0xA0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xA0 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0xA0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xA0 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0xA0 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xA0 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0xA0 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xA0 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0xA0 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xA0 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0xA0 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xA0 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
line.long 0xA4 "PIO19,Digital I/O control for port 1 pins PIO1_9"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0xA4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xA4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xA4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xA4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xA4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xA4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xA4 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0xA4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xA4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xA4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xA4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xA4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0xA4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xA4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xA4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xA4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xA4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0xA4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xA4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xA4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xA4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xA4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0xA4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xA4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xA4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xA4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xA4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0xA4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xA4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xA4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xA4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xA4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0xA4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xA4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xA4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xA4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xA4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0xA4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xA4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xA4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xA4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xA4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0xA4 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xA4 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xA4 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xA4 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xA4 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0xA4 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xA4 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xA4 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xA4 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xA4 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0xA4 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xA4 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xA4 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xA4 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xA4 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0xA4 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xA4 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xA4 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xA4 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xA4 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0xA4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xA4 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0xA4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xA4 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0xA4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xA4 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0xA4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xA4 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0xA4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xA4 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0xA4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xA4 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0xA4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xA4 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0xA4 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xA4 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0xA4 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xA4 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0xA4 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xA4 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0xA4 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xA4 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
line.long 0xA8 "PIO110,Digital I/O control for port 1 pins PIO1_10"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0xA8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xA8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xA8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xA8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xA8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xA8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xA8 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0xA8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xA8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xA8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xA8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xA8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0xA8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xA8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xA8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xA8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xA8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0xA8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xA8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xA8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xA8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xA8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0xA8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xA8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xA8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xA8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xA8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0xA8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xA8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xA8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xA8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xA8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0xA8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xA8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xA8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xA8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xA8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0xA8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xA8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xA8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xA8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xA8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0xA8 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xA8 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xA8 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xA8 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xA8 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0xA8 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xA8 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xA8 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xA8 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xA8 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0xA8 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xA8 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xA8 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xA8 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xA8 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0xA8 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xA8 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xA8 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xA8 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xA8 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0xA8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xA8 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0xA8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xA8 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0xA8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xA8 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0xA8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xA8 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0xA8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xA8 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0xA8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xA8 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0xA8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xA8 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0xA8 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xA8 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0xA8 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xA8 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0xA8 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xA8 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0xA8 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xA8 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
line.long 0xAC "PIO111,Digital I/O control for port 1 pins PIO1_11"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0xAC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xAC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xAC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xAC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xAC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xAC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xAC 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0xAC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xAC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xAC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xAC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xAC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0xAC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xAC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xAC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xAC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xAC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0xAC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xAC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xAC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xAC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xAC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0xAC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xAC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xAC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xAC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xAC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0xAC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xAC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xAC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xAC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xAC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0xAC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xAC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xAC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xAC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xAC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0xAC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xAC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xAC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xAC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xAC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0xAC 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xAC 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xAC 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xAC 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xAC 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0xAC 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xAC 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xAC 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xAC 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xAC 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0xAC 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xAC 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xAC 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xAC 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xAC 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0xAC 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xAC 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xAC 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xAC 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xAC 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0xAC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xAC 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0xAC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xAC 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0xAC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xAC 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0xAC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xAC 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0xAC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xAC 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0xAC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xAC 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0xAC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xAC 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0xAC 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xAC 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0xAC 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xAC 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0xAC 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xAC 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0xAC 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xAC 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
line.long 0xB0 "PIO112,Digital I/O control for port 1 pins PIO1_12"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0xB0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xB0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xB0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xB0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xB0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xB0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xB0 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0xB0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xB0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xB0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xB0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xB0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0xB0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xB0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xB0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xB0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xB0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0xB0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xB0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xB0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xB0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xB0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0xB0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xB0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xB0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xB0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xB0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0xB0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xB0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xB0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xB0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xB0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0xB0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xB0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xB0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xB0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xB0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0xB0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xB0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xB0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xB0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xB0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0xB0 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xB0 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xB0 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xB0 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xB0 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0xB0 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xB0 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xB0 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xB0 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xB0 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0xB0 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xB0 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xB0 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xB0 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xB0 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0xB0 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xB0 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xB0 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xB0 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xB0 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0xB0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xB0 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0xB0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xB0 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0xB0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xB0 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0xB0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xB0 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0xB0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xB0 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0xB0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xB0 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0xB0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xB0 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0xB0 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xB0 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0xB0 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xB0 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0xB0 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xB0 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0xB0 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xB0 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
line.long 0xB4 "PIO113,Digital I/O control for port 1 pins PIO1_13"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0xB4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xB4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xB4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xB4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xB4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xB4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xB4 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0xB4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xB4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xB4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xB4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xB4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0xB4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xB4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xB4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xB4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xB4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0xB4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xB4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xB4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xB4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xB4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0xB4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xB4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xB4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xB4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xB4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0xB4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xB4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xB4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xB4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xB4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0xB4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xB4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xB4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xB4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xB4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0xB4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xB4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xB4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xB4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xB4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0xB4 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xB4 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xB4 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xB4 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xB4 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0xB4 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xB4 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xB4 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xB4 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xB4 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0xB4 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xB4 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xB4 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xB4 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xB4 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0xB4 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xB4 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xB4 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xB4 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xB4 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0xB4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xB4 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0xB4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xB4 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0xB4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xB4 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0xB4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xB4 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0xB4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xB4 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0xB4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xB4 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0xB4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xB4 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0xB4 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xB4 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0xB4 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xB4 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0xB4 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xB4 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0xB4 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xB4 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
line.long 0xB8 "PIO114,Digital I/O control for port 1 pins PIO1_14"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0xB8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xB8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xB8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xB8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xB8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xB8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xB8 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0xB8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xB8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xB8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xB8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xB8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0xB8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xB8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xB8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xB8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xB8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0xB8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xB8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xB8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xB8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xB8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0xB8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xB8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xB8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xB8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xB8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0xB8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xB8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xB8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xB8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xB8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0xB8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xB8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xB8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xB8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xB8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0xB8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xB8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xB8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xB8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xB8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0xB8 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xB8 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xB8 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xB8 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xB8 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0xB8 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xB8 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xB8 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xB8 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xB8 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0xB8 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xB8 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xB8 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xB8 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xB8 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0xB8 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xB8 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xB8 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xB8 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xB8 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0xB8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xB8 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0xB8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xB8 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0xB8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xB8 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0xB8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xB8 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0xB8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xB8 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0xB8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xB8 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0xB8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xB8 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0xB8 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xB8 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0xB8 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xB8 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0xB8 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xB8 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0xB8 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xB8 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
line.long 0xBC "PIO115,Digital I/O control for port 1 pins PIO1_15"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0xBC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xBC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xBC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xBC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xBC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xBC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xBC 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0xBC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xBC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xBC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xBC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xBC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0xBC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xBC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xBC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xBC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xBC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0xBC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xBC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xBC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xBC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xBC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0xBC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xBC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xBC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xBC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xBC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0xBC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xBC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xBC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xBC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xBC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0xBC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xBC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xBC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xBC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xBC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0xBC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xBC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xBC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xBC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xBC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0xBC 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xBC 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xBC 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xBC 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xBC 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0xBC 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xBC 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xBC 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xBC 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xBC 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0xBC 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xBC 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xBC 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xBC 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xBC 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0xBC 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xBC 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xBC 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xBC 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xBC 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0xBC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xBC 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0xBC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xBC 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0xBC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xBC 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0xBC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xBC 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0xBC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xBC 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0xBC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xBC 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0xBC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xBC 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0xBC 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xBC 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0xBC 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xBC 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0xBC 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xBC 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0xBC 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xBC 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
line.long 0xC0 "PIO116,Digital I/O control for port 1 pins PIO1_16"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0xC0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xC0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xC0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xC0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xC0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xC0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xC0 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0xC0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xC0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xC0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xC0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xC0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0xC0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xC0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xC0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xC0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xC0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0xC0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xC0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xC0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xC0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xC0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0xC0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xC0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xC0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xC0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xC0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0xC0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xC0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xC0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xC0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xC0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0xC0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xC0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xC0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xC0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xC0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0xC0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xC0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xC0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xC0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xC0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0xC0 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xC0 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xC0 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xC0 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xC0 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0xC0 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xC0 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xC0 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xC0 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xC0 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0xC0 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xC0 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xC0 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xC0 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xC0 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0xC0 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xC0 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xC0 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xC0 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xC0 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0xC0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xC0 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0xC0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xC0 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0xC0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xC0 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0xC0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xC0 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0xC0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xC0 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0xC0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xC0 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0xC0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xC0 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0xC0 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xC0 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0xC0 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xC0 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0xC0 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xC0 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0xC0 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xC0 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
line.long 0xC4 "PIO117,Digital I/O control for port 1 pins PIO1_17"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0xC4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xC4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xC4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xC4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xC4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xC4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xC4 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0xC4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xC4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xC4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xC4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xC4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0xC4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xC4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xC4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xC4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xC4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0xC4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xC4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xC4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xC4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xC4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0xC4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xC4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xC4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xC4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xC4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0xC4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xC4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xC4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xC4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xC4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0xC4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xC4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xC4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xC4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xC4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0xC4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xC4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xC4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xC4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xC4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0xC4 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xC4 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xC4 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xC4 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xC4 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0xC4 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xC4 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xC4 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xC4 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xC4 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0xC4 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xC4 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xC4 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xC4 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xC4 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0xC4 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xC4 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xC4 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xC4 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xC4 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0xC4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xC4 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0xC4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xC4 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0xC4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xC4 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0xC4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xC4 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0xC4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xC4 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0xC4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xC4 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0xC4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xC4 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0xC4 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xC4 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0xC4 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xC4 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0xC4 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xC4 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0xC4 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xC4 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
line.long 0xC8 "PIO118,Digital I/O control for port 1 pins PIO1_18"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0xC8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xC8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xC8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xC8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xC8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xC8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xC8 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0xC8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xC8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xC8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xC8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xC8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0xC8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xC8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xC8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xC8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xC8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0xC8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xC8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xC8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xC8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xC8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0xC8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xC8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xC8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xC8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xC8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0xC8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xC8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xC8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xC8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xC8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0xC8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xC8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xC8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xC8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xC8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0xC8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xC8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xC8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xC8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xC8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0xC8 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xC8 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xC8 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xC8 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xC8 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0xC8 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xC8 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xC8 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xC8 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xC8 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0xC8 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xC8 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xC8 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xC8 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xC8 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0xC8 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xC8 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xC8 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xC8 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xC8 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0xC8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xC8 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0xC8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xC8 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0xC8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xC8 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0xC8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xC8 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0xC8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xC8 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0xC8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xC8 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0xC8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xC8 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0xC8 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xC8 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0xC8 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xC8 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0xC8 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xC8 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0xC8 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xC8 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
line.long 0xCC "PIO119,Digital I/O control for port 1 pins PIO1_19"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0xCC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xCC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xCC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xCC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xCC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xCC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xCC 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0xCC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xCC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xCC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xCC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xCC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0xCC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xCC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xCC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xCC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xCC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0xCC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xCC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xCC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xCC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xCC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0xCC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xCC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xCC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xCC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xCC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0xCC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xCC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xCC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xCC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xCC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0xCC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xCC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xCC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xCC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xCC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0xCC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xCC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xCC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xCC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xCC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0xCC 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xCC 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xCC 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xCC 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xCC 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0xCC 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xCC 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xCC 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xCC 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xCC 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0xCC 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xCC 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xCC 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xCC 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xCC 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0xCC 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xCC 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xCC 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xCC 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xCC 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0xCC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xCC 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0xCC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xCC 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0xCC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xCC 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0xCC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xCC 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0xCC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xCC 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0xCC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xCC 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0xCC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xCC 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0xCC 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xCC 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0xCC 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xCC 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0xCC 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xCC 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0xCC 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xCC 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
line.long 0xD0 "PIO120,Digital I/O control for port 1 pins PIO1_20"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0xD0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xD0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xD0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xD0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xD0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xD0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xD0 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0xD0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xD0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xD0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xD0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xD0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0xD0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xD0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xD0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xD0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xD0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0xD0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xD0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xD0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xD0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xD0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0xD0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xD0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xD0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xD0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xD0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0xD0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xD0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xD0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xD0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xD0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0xD0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xD0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xD0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xD0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xD0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0xD0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xD0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xD0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xD0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xD0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0xD0 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xD0 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xD0 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xD0 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xD0 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0xD0 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xD0 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xD0 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xD0 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xD0 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0xD0 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xD0 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xD0 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xD0 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xD0 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0xD0 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xD0 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xD0 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xD0 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xD0 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0xD0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xD0 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0xD0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xD0 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0xD0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xD0 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0xD0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xD0 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0xD0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xD0 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0xD0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xD0 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0xD0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xD0 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0xD0 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xD0 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0xD0 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xD0 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0xD0 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xD0 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0xD0 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xD0 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
line.long 0xD4 "PIO121,Digital I/O control for port 1 pins PIO1_21"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0xD4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xD4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xD4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xD4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xD4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xD4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xD4 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0xD4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xD4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xD4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xD4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xD4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0xD4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xD4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xD4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xD4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xD4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0xD4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xD4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xD4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xD4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xD4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0xD4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xD4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xD4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xD4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xD4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0xD4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xD4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xD4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xD4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xD4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0xD4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xD4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xD4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xD4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xD4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0xD4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xD4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xD4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xD4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xD4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0xD4 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xD4 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xD4 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xD4 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xD4 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0xD4 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xD4 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xD4 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xD4 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xD4 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0xD4 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xD4 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xD4 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xD4 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xD4 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0xD4 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xD4 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xD4 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xD4 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xD4 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0xD4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xD4 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0xD4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xD4 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0xD4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xD4 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0xD4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xD4 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0xD4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xD4 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0xD4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xD4 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0xD4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xD4 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0xD4 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xD4 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0xD4 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xD4 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0xD4 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xD4 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0xD4 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xD4 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
line.long 0xD8 "PIO122,Digital I/O control for port 1 pins PIO1_22"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0xD8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xD8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xD8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xD8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xD8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xD8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xD8 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0xD8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xD8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xD8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xD8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xD8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0xD8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xD8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xD8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xD8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xD8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0xD8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xD8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xD8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xD8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xD8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0xD8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xD8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xD8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xD8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xD8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0xD8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xD8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xD8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xD8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xD8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0xD8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xD8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xD8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xD8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xD8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0xD8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xD8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xD8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xD8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xD8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0xD8 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xD8 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xD8 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xD8 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xD8 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0xD8 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xD8 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xD8 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xD8 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xD8 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0xD8 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xD8 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xD8 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xD8 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xD8 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0xD8 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xD8 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xD8 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xD8 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xD8 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0xD8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xD8 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0xD8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xD8 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0xD8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xD8 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0xD8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xD8 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0xD8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xD8 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0xD8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xD8 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0xD8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xD8 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0xD8 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xD8 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0xD8 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xD8 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0xD8 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xD8 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0xD8 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xD8 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
line.long 0xDC "PIO123,Digital I/O control for port 1 pins PIO1_23"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0xDC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xDC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xDC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xDC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xDC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xDC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xDC 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0xDC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xDC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xDC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xDC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xDC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0xDC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xDC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xDC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xDC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xDC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0xDC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xDC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xDC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xDC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xDC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0xDC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xDC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xDC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xDC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xDC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0xDC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xDC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xDC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xDC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xDC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0xDC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xDC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xDC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xDC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xDC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0xDC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xDC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xDC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xDC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xDC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0xDC 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xDC 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xDC 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xDC 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xDC 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0xDC 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xDC 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xDC 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xDC 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xDC 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0xDC 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xDC 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xDC 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xDC 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xDC 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0xDC 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xDC 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xDC 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xDC 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xDC 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0xDC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xDC 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0xDC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xDC 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0xDC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xDC 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0xDC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xDC 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0xDC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xDC 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0xDC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xDC 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0xDC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xDC 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0xDC 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xDC 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0xDC 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xDC 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0xDC 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xDC 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0xDC 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xDC 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
line.long 0xE0 "PIO124,Digital I/O control for port 1 pins PIO1_24"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0xE0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xE0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xE0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xE0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xE0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xE0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xE0 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0xE0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xE0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xE0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xE0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xE0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0xE0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xE0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xE0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xE0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xE0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0xE0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xE0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xE0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xE0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xE0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0xE0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xE0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xE0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xE0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xE0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0xE0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xE0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xE0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xE0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xE0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0xE0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xE0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xE0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xE0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xE0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0xE0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xE0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xE0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xE0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xE0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0xE0 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xE0 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xE0 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xE0 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xE0 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0xE0 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xE0 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xE0 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xE0 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xE0 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0xE0 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xE0 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xE0 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xE0 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xE0 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0xE0 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xE0 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xE0 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xE0 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xE0 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0xE0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xE0 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0xE0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xE0 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0xE0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xE0 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0xE0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xE0 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0xE0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xE0 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0xE0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xE0 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0xE0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xE0 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0xE0 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xE0 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0xE0 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xE0 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0xE0 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xE0 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0xE0 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xE0 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
line.long 0xE4 "PIO125,Digital I/O control for port 1 pins PIO1_25"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0xE4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xE4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xE4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xE4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xE4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xE4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xE4 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0xE4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xE4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xE4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xE4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xE4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0xE4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xE4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xE4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xE4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xE4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0xE4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xE4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xE4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xE4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xE4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0xE4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xE4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xE4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xE4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xE4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0xE4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xE4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xE4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xE4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xE4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0xE4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xE4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xE4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xE4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xE4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0xE4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xE4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xE4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xE4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xE4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0xE4 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xE4 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xE4 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xE4 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xE4 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0xE4 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xE4 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xE4 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xE4 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xE4 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0xE4 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xE4 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xE4 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xE4 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xE4 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0xE4 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xE4 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xE4 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xE4 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xE4 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0xE4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xE4 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0xE4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xE4 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0xE4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xE4 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0xE4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xE4 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0xE4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xE4 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0xE4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xE4 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0xE4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xE4 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0xE4 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xE4 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0xE4 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xE4 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0xE4 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xE4 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0xE4 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xE4 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
line.long 0xE8 "PIO126,Digital I/O control for port 1 pins PIO1_26"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0xE8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xE8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xE8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xE8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xE8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xE8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xE8 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0xE8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xE8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xE8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xE8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xE8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0xE8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xE8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xE8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xE8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xE8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0xE8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xE8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xE8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xE8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xE8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0xE8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xE8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xE8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xE8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xE8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0xE8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xE8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xE8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xE8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xE8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0xE8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xE8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xE8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xE8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xE8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0xE8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xE8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xE8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xE8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xE8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0xE8 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xE8 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xE8 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xE8 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xE8 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0xE8 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xE8 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xE8 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xE8 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xE8 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0xE8 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xE8 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xE8 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xE8 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xE8 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0xE8 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xE8 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xE8 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xE8 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xE8 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0xE8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xE8 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0xE8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xE8 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0xE8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xE8 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0xE8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xE8 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0xE8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xE8 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0xE8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xE8 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0xE8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xE8 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0xE8 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xE8 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0xE8 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xE8 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0xE8 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xE8 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0xE8 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xE8 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
line.long 0xEC "PIO127,Digital I/O control for port 1 pins PIO1_27"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0xEC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xEC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xEC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xEC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xEC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xEC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xEC 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0xEC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xEC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xEC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xEC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xEC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0xEC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xEC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xEC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xEC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xEC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0xEC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xEC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xEC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xEC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xEC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0xEC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xEC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xEC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xEC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xEC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0xEC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xEC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xEC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xEC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xEC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0xEC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xEC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xEC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xEC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xEC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0xEC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xEC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xEC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xEC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xEC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0xEC 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xEC 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xEC 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xEC 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xEC 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0xEC 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xEC 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xEC 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xEC 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xEC 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0xEC 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xEC 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xEC 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xEC 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xEC 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0xEC 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xEC 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xEC 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xEC 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xEC 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0xEC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xEC 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0xEC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xEC 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0xEC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xEC 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0xEC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xEC 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0xEC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xEC 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0xEC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xEC 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0xEC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xEC 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0xEC 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xEC 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0xEC 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xEC 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0xEC 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xEC 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0xEC 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xEC 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
line.long 0xF0 "PIO128,Digital I/O control for port 1 pins PIO1_28"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0xF0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xF0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xF0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xF0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xF0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xF0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xF0 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0xF0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xF0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xF0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xF0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xF0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0xF0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xF0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xF0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xF0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xF0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0xF0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xF0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xF0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xF0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xF0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0xF0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xF0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xF0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xF0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xF0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0xF0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xF0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xF0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xF0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xF0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0xF0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xF0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xF0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xF0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xF0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0xF0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xF0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xF0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xF0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xF0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0xF0 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xF0 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xF0 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xF0 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xF0 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0xF0 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xF0 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xF0 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xF0 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xF0 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0xF0 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xF0 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xF0 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xF0 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xF0 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0xF0 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xF0 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xF0 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xF0 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xF0 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0xF0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xF0 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0xF0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xF0 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0xF0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xF0 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0xF0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xF0 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0xF0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xF0 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0xF0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xF0 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0xF0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xF0 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0xF0 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xF0 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0xF0 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xF0 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0xF0 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xF0 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0xF0 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xF0 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
line.long 0xF4 "PIO129,Digital I/O control for port 1 pins PIO1_29"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0xF4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xF4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xF4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xF4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xF4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xF4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xF4 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0xF4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xF4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xF4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xF4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xF4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0xF4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xF4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xF4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xF4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xF4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0xF4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xF4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xF4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xF4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xF4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0xF4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xF4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xF4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xF4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xF4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0xF4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xF4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xF4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xF4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xF4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0xF4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xF4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xF4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xF4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xF4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0xF4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xF4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xF4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xF4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xF4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0xF4 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xF4 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xF4 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xF4 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xF4 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0xF4 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xF4 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xF4 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xF4 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xF4 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0xF4 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xF4 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xF4 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xF4 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xF4 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0xF4 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xF4 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xF4 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xF4 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xF4 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0xF4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xF4 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0xF4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xF4 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0xF4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xF4 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0xF4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xF4 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0xF4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xF4 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0xF4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xF4 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0xF4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xF4 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0xF4 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xF4 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0xF4 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xF4 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0xF4 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xF4 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0xF4 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xF4 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
line.long 0xF8 "PIO130,Digital I/O control for port 1 pins PIO1_30"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0xF8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xF8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xF8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xF8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xF8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xF8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xF8 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0xF8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xF8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xF8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xF8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xF8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0xF8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xF8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xF8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xF8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xF8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0xF8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xF8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xF8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xF8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xF8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0xF8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xF8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xF8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xF8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xF8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0xF8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xF8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xF8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xF8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xF8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0xF8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xF8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xF8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xF8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xF8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0xF8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xF8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xF8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xF8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xF8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0xF8 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xF8 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xF8 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xF8 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xF8 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0xF8 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xF8 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xF8 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xF8 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xF8 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0xF8 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xF8 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xF8 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xF8 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xF8 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0xF8 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xF8 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xF8 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xF8 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xF8 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0xF8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xF8 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0xF8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xF8 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0xF8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xF8 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0xF8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xF8 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0xF8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xF8 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0xF8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xF8 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0xF8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xF8 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0xF8 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xF8 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0xF8 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xF8 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0xF8 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xF8 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0xF8 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xF8 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
line.long 0xFC "PIO131,Digital I/O control for port 1 pins PIO1_31"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0xFC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xFC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xFC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xFC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xFC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xFC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xFC 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0xFC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xFC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xFC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xFC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xFC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0xFC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xFC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xFC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xFC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xFC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0xFC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xFC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xFC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xFC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xFC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0xFC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xFC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xFC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xFC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xFC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0xFC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xFC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xFC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xFC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xFC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0xFC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xFC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xFC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xFC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xFC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0xFC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xFC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xFC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xFC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xFC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0xFC 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xFC 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xFC 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xFC 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xFC 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0xFC 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xFC 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xFC 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xFC 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xFC 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0xFC 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xFC 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xFC 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xFC 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xFC 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0xFC 10. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xFC 9. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xFC 8. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xFC 7. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xFC 6. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0xFC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xFC 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0xFC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xFC 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0xFC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xFC 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0xFC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xFC 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0xFC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xFC 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0xFC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xFC 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0xFC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xFC 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0xFC 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xFC 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0xFC 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xFC 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0xFC 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xFC 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54114*"))
bitfld.long 0xFC 3.--4. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
bitfld.long 0xFC 0.--2. "FUNC,Selects pin function." "0: Alternative connection 0.,1: Alternative connection 1.,2: Alternative connection 2.,3: Alternative connection 3.,4: Alternative connection 4.,5: Alternative connection 5.,6: Alternative connection 6.,7: Alternative connection 7."
endif
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
group.long 0x100++0x1FF
line.long 0x0 "PIO20,Digital I/O control for port 2 pins PIO2_0"
bitfld.long 0x0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x0 6. "ANAMODE,Enables or disables analog mode." "0: Enable analog Mode.,1: Disable analog Mode."
newline
bitfld.long 0x0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x0 0.--3. 1. "FUNC,Selects pin function."
line.long 0x4 "PIO21,Digital I/O control for port 2 pins PIO2_1"
bitfld.long 0x4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x4 6. "ANAMODE,Enables or disables analog mode." "0: Enable analog Mode.,1: Disable analog Mode."
newline
bitfld.long 0x4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x4 0.--3. 1. "FUNC,Selects pin function."
line.long 0x8 "PIO22,Digital I/O control for port 2 pins PIO2_2"
bitfld.long 0x8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x8 0.--3. 1. "FUNC,Selects pin function."
line.long 0xC "PIO23,Digital I/O control for port 2 pins PIO2_3"
bitfld.long 0xC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xC 0.--3. 1. "FUNC,Selects pin function."
line.long 0x10 "PIO24,Digital I/O control for port 2 pins PIO2_4"
bitfld.long 0x10 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x10 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x10 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x10 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x10 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x10 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x10 0.--3. 1. "FUNC,Selects pin function."
line.long 0x14 "PIO25,Digital I/O control for port 2 pins PIO2_5"
bitfld.long 0x14 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x14 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x14 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x14 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x14 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x14 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x14 0.--3. 1. "FUNC,Selects pin function."
line.long 0x18 "PIO26,Digital I/O control for port 2 pins PIO2_6"
bitfld.long 0x18 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x18 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x18 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x18 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x18 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x18 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x18 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1C "PIO27,Digital I/O control for port 2 pins PIO2_7"
bitfld.long 0x1C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x20 "PIO28,Digital I/O control for port 2 pins PIO2_8"
bitfld.long 0x20 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x20 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x20 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x20 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x20 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x20 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x20 0.--3. 1. "FUNC,Selects pin function."
line.long 0x24 "PIO29,Digital I/O control for port 2 pins PIO2_9"
bitfld.long 0x24 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x24 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x24 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x24 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x24 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x24 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x24 0.--3. 1. "FUNC,Selects pin function."
line.long 0x28 "PIO210,Digital I/O control for port 2 pins PIO2_10"
bitfld.long 0x28 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x28 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x28 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x28 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x28 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x28 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x28 0.--3. 1. "FUNC,Selects pin function."
line.long 0x2C "PIO211,Digital I/O control for port 2 pins PIO2_11"
bitfld.long 0x2C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x2C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x2C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x2C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x2C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x2C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x2C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x30 "PIO212,Digital I/O control for port 2 pins PIO2_12"
bitfld.long 0x30 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x30 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x30 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x30 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x30 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x30 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x30 0.--3. 1. "FUNC,Selects pin function."
line.long 0x34 "PIO213,Digital I/O control for port 2 pins PIO2_13"
bitfld.long 0x34 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x34 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x34 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x34 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x34 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x34 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x34 0.--3. 1. "FUNC,Selects pin function."
line.long 0x38 "PIO214,Digital I/O control for port 2 pins PIO2_14"
bitfld.long 0x38 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x38 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x38 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x38 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x38 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x38 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x38 0.--3. 1. "FUNC,Selects pin function."
line.long 0x3C "PIO215,Digital I/O control for port 2 pins PIO2_15"
bitfld.long 0x3C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x3C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x3C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x3C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x3C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x3C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x3C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x40 "PIO216,Digital I/O control for port 2 pins PIO2_16"
bitfld.long 0x40 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x40 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x40 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x40 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x40 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x40 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x40 0.--3. 1. "FUNC,Selects pin function."
line.long 0x44 "PIO217,Digital I/O control for port 2 pins PIO2_17"
bitfld.long 0x44 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x44 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x44 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x44 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x44 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x44 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x44 0.--3. 1. "FUNC,Selects pin function."
line.long 0x48 "PIO218,Digital I/O control for port 2 pins PIO2_18"
bitfld.long 0x48 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x48 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x48 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x48 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x48 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x48 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x48 0.--3. 1. "FUNC,Selects pin function."
line.long 0x4C "PIO219,Digital I/O control for port 2 pins PIO2_19"
bitfld.long 0x4C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x4C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x4C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x4C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x4C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x4C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x4C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x50 "PIO220,Digital I/O control for port 2 pins PIO2_20"
bitfld.long 0x50 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x50 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x50 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x50 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x50 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x50 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x50 0.--3. 1. "FUNC,Selects pin function."
line.long 0x54 "PIO221,Digital I/O control for port 2 pins PIO2_21"
bitfld.long 0x54 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x54 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x54 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x54 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x54 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x54 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x54 0.--3. 1. "FUNC,Selects pin function."
line.long 0x58 "PIO222,Digital I/O control for port 2 pins PIO2_22"
bitfld.long 0x58 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x58 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x58 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x58 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x58 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x58 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x58 0.--3. 1. "FUNC,Selects pin function."
line.long 0x5C "PIO223,Digital I/O control for port 2 pins PIO2_23"
bitfld.long 0x5C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x5C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x5C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x5C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x5C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x5C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x5C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x60 "PIO224,Digital I/O control for port 2 pins PIO2_24"
bitfld.long 0x60 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x60 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x60 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x60 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x60 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x60 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x60 0.--3. 1. "FUNC,Selects pin function."
line.long 0x64 "PIO225,Digital I/O control for port 2 pins PIO2_25"
bitfld.long 0x64 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x64 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x64 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x64 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x64 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x64 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x64 0.--3. 1. "FUNC,Selects pin function."
line.long 0x68 "PIO226,Digital I/O control for port 2 pins PIO2_26"
bitfld.long 0x68 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x68 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x68 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x68 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x68 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x68 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x68 0.--3. 1. "FUNC,Selects pin function."
line.long 0x6C "PIO227,Digital I/O control for port 2 pins PIO2_27"
bitfld.long 0x6C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x6C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x6C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x6C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x6C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x6C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x6C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x70 "PIO228,Digital I/O control for port 2 pins PIO2_28"
bitfld.long 0x70 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x70 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x70 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x70 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x70 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x70 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x70 0.--3. 1. "FUNC,Selects pin function."
line.long 0x74 "PIO229,Digital I/O control for port 2 pins PIO2_29"
bitfld.long 0x74 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x74 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x74 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x74 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x74 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x74 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x74 0.--3. 1. "FUNC,Selects pin function."
line.long 0x78 "PIO230,Digital I/O control for port 2 pins PIO2_30"
bitfld.long 0x78 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x78 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x78 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x78 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x78 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x78 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x78 0.--3. 1. "FUNC,Selects pin function."
line.long 0x7C "PIO231,Digital I/O control for port 2 pins PIO2_31"
bitfld.long 0x7C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x7C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x7C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x7C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x7C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x7C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x7C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x80 "PIO30,Digital I/O control for port 3 pins PIO3_0"
bitfld.long 0x80 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x80 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x80 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x80 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x80 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x80 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x80 0.--3. 1. "FUNC,Selects pin function."
line.long 0x84 "PIO31,Digital I/O control for port 3 pins PIO3_1"
bitfld.long 0x84 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x84 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x84 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x84 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x84 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x84 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x84 0.--3. 1. "FUNC,Selects pin function."
line.long 0x88 "PIO32,Digital I/O control for port 3 pins PIO3_2"
bitfld.long 0x88 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x88 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x88 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x88 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x88 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x88 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x88 0.--3. 1. "FUNC,Selects pin function."
line.long 0x8C "PIO33,Digital I/O control for port 3 pins PIO3_3"
bitfld.long 0x8C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x8C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x8C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x8C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x8C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x8C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x8C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x90 "PIO34,Digital I/O control for port 3 pins PIO3_4"
bitfld.long 0x90 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x90 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x90 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x90 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x90 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x90 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x90 0.--3. 1. "FUNC,Selects pin function."
line.long 0x94 "PIO35,Digital I/O control for port 3 pins PIO3_5"
bitfld.long 0x94 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x94 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x94 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x94 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x94 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x94 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x94 0.--3. 1. "FUNC,Selects pin function."
line.long 0x98 "PIO36,Digital I/O control for port 3 pins PIO3_6"
bitfld.long 0x98 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x98 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x98 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x98 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x98 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x98 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x98 0.--3. 1. "FUNC,Selects pin function."
line.long 0x9C "PIO37,Digital I/O control for port 3 pins PIO3_7"
bitfld.long 0x9C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x9C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x9C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x9C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x9C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x9C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x9C 0.--3. 1. "FUNC,Selects pin function."
line.long 0xA0 "PIO38,Digital I/O control for port 3 pins PIO3_8"
bitfld.long 0xA0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xA0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xA0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xA0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xA0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xA0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xA0 0.--3. 1. "FUNC,Selects pin function."
line.long 0xA4 "PIO39,Digital I/O control for port 3 pins PIO3_9"
bitfld.long 0xA4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xA4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xA4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xA4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xA4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xA4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xA4 0.--3. 1. "FUNC,Selects pin function."
line.long 0xA8 "PIO310,Digital I/O control for port 3 pins PIO3_10"
bitfld.long 0xA8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xA8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xA8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xA8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xA8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xA8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xA8 0.--3. 1. "FUNC,Selects pin function."
line.long 0xAC "PIO311,Digital I/O control for port 3 pins PIO3_11"
bitfld.long 0xAC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xAC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xAC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xAC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xAC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xAC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xAC 0.--3. 1. "FUNC,Selects pin function."
line.long 0xB0 "PIO312,Digital I/O control for port 3 pins PIO3_12"
bitfld.long 0xB0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xB0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xB0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xB0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xB0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xB0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xB0 0.--3. 1. "FUNC,Selects pin function."
line.long 0xB4 "PIO313,Digital I/O control for port 3 pins PIO3_13"
bitfld.long 0xB4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xB4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xB4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xB4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xB4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xB4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xB4 0.--3. 1. "FUNC,Selects pin function."
line.long 0xB8 "PIO314,Digital I/O control for port 3 pins PIO3_14"
bitfld.long 0xB8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xB8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xB8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xB8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xB8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xB8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xB8 0.--3. 1. "FUNC,Selects pin function."
line.long 0xBC "PIO315,Digital I/O control for port 3 pins PIO3_15"
bitfld.long 0xBC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xBC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xBC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xBC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xBC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xBC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xBC 0.--3. 1. "FUNC,Selects pin function."
line.long 0xC0 "PIO316,Digital I/O control for port 3 pins PIO3_16"
bitfld.long 0xC0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xC0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xC0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xC0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xC0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xC0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xC0 0.--3. 1. "FUNC,Selects pin function."
line.long 0xC4 "PIO317,Digital I/O control for port 3 pins PIO3_17"
bitfld.long 0xC4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xC4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xC4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xC4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xC4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xC4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xC4 0.--3. 1. "FUNC,Selects pin function."
line.long 0xC8 "PIO318,Digital I/O control for port 3 pins PIO3_18"
bitfld.long 0xC8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xC8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xC8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xC8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xC8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xC8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xC8 0.--3. 1. "FUNC,Selects pin function."
line.long 0xCC "PIO319,Digital I/O control for port 3 pins PIO3_19"
bitfld.long 0xCC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xCC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xCC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xCC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xCC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xCC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xCC 0.--3. 1. "FUNC,Selects pin function."
line.long 0xD0 "PIO320,Digital I/O control for port 3 pins PIO3_20"
bitfld.long 0xD0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xD0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xD0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xD0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xD0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xD0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xD0 0.--3. 1. "FUNC,Selects pin function."
line.long 0xD4 "PIO321,Digital I/O control for port 3 pins PIO3_21"
bitfld.long 0xD4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xD4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xD4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xD4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xD4 6. "ANAMODE,Enables or disables analog mode." "0: Enable analog Mode.,1: Disable analog Mode."
newline
bitfld.long 0xD4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xD4 0.--3. 1. "FUNC,Selects pin function."
line.long 0xD8 "PIO322,Digital I/O control for port 3 pins PIO3_22"
bitfld.long 0xD8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xD8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xD8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xD8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xD8 6. "ANAMODE,Enables or disables analog mode." "0: Enable analog Mode.,1: Disable analog Mode."
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bitfld.long 0xD8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xD8 0.--3. 1. "FUNC,Selects pin function."
line.long 0xDC "PIO323,Digital I/O control for port 3 pins PIO3_23"
bitfld.long 0xDC 11. "I2CFILTEROFF,Configures I2C features for standard mode  fast mode  and Fast Mode Plus operation." "0: Enabled. I2C 50 ns glitch filter enabled.,1: Disabled. I2C 50 ns glitch filter disabled."
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bitfld.long 0xDC 10. "I2CDRIVE,Controls the current sink capability of the pin." "0: Low drive. Output drive sink is 4 mA. This is..,1: High drive. Output drive sink is 20 mA. This is.."
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bitfld.long 0xDC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xDC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xDC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xDC 6. "I2CSLEW,Controls slew rate of I2C pad." "0: I2C mode.,1: GPIO mode."
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hexmask.long.byte 0xDC 0.--3. 1. "FUNC,Selects pin function."
line.long 0xE0 "PIO324,Digital I/O control for port 3 pins PIO3_24"
bitfld.long 0xE0 11. "I2CFILTEROFF,Configures I2C features for standard mode  fast mode  and Fast Mode Plus operation." "0: Enabled. I2C 50 ns glitch filter enabled.,1: Disabled. I2C 50 ns glitch filter disabled."
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bitfld.long 0xE0 10. "I2CDRIVE,Controls the current sink capability of the pin." "0: Low drive. Output drive sink is 4 mA. This is..,1: High drive. Output drive sink is 20 mA. This is.."
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bitfld.long 0xE0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xE0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xE0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xE0 6. "I2CSLEW,Controls slew rate of I2C pad." "0: I2C mode.,1: GPIO mode."
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hexmask.long.byte 0xE0 0.--3. 1. "FUNC,Selects pin function."
line.long 0xE4 "PIO325,Digital I/O control for port 3 pins PIO3_25"
bitfld.long 0xE4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xE4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xE4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xE4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xE4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xE4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xE4 0.--3. 1. "FUNC,Selects pin function."
line.long 0xE8 "PIO326,Digital I/O control for port 3 pins PIO3_26"
bitfld.long 0xE8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xE8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xE8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xE8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xE8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xE8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xE8 0.--3. 1. "FUNC,Selects pin function."
line.long 0xEC "PIO327,Digital I/O control for port 3 pins PIO3_27"
bitfld.long 0xEC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xEC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xEC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xEC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xEC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xEC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xEC 0.--3. 1. "FUNC,Selects pin function."
line.long 0xF0 "PIO328,Digital I/O control for port 3 pins PIO3_28"
bitfld.long 0xF0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xF0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xF0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xF0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xF0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xF0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xF0 0.--3. 1. "FUNC,Selects pin function."
line.long 0xF4 "PIO329,Digital I/O control for port 3 pins PIO3_29"
bitfld.long 0xF4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xF4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xF4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xF4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xF4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xF4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xF4 0.--3. 1. "FUNC,Selects pin function."
line.long 0xF8 "PIO330,Digital I/O control for port 3 pins PIO3_30"
bitfld.long 0xF8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xF8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xF8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xF8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xF8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xF8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xF8 0.--3. 1. "FUNC,Selects pin function."
line.long 0xFC "PIO331,Digital I/O control for port 3 pins PIO3_31"
bitfld.long 0xFC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xFC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xFC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xFC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xFC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xFC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xFC 0.--3. 1. "FUNC,Selects pin function."
line.long 0x100 "PIO40,Digital I/O control for port 4 pins PIO4_0"
bitfld.long 0x100 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x100 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x100 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x100 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x100 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x100 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x100 0.--3. 1. "FUNC,Selects pin function."
line.long 0x104 "PIO41,Digital I/O control for port 4 pins PIO4_1"
bitfld.long 0x104 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x104 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x104 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x104 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x104 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x104 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x104 0.--3. 1. "FUNC,Selects pin function."
line.long 0x108 "PIO42,Digital I/O control for port 4 pins PIO4_2"
bitfld.long 0x108 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x108 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x108 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x108 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x108 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x108 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x108 0.--3. 1. "FUNC,Selects pin function."
line.long 0x10C "PIO43,Digital I/O control for port 4 pins PIO4_3"
bitfld.long 0x10C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x10C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x10C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x10C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x10C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x10C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x10C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x110 "PIO44,Digital I/O control for port 4 pins PIO4_4"
bitfld.long 0x110 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x110 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x110 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x110 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x110 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x110 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x110 0.--3. 1. "FUNC,Selects pin function."
line.long 0x114 "PIO45,Digital I/O control for port 4 pins PIO4_5"
bitfld.long 0x114 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x114 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x114 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x114 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x114 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x114 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x114 0.--3. 1. "FUNC,Selects pin function."
line.long 0x118 "PIO46,Digital I/O control for port 4 pins PIO4_6"
bitfld.long 0x118 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x118 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x118 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x118 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x118 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x118 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x118 0.--3. 1. "FUNC,Selects pin function."
line.long 0x11C "PIO47,Digital I/O control for port 4 pins PIO4_7"
bitfld.long 0x11C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x11C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x11C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x11C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x11C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x11C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x11C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x120 "PIO48,Digital I/O control for port 4 pins PIO4_8"
bitfld.long 0x120 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x120 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x120 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x120 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x120 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x120 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x120 0.--3. 1. "FUNC,Selects pin function."
line.long 0x124 "PIO49,Digital I/O control for port 4 pins PIO4_9"
bitfld.long 0x124 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x124 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x124 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x124 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x124 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x124 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x124 0.--3. 1. "FUNC,Selects pin function."
line.long 0x128 "PIO410,Digital I/O control for port 4 pins PIO4_10"
bitfld.long 0x128 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x128 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x128 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x128 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x128 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x128 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x128 0.--3. 1. "FUNC,Selects pin function."
line.long 0x12C "PIO411,Digital I/O control for port 4 pins PIO4_11"
bitfld.long 0x12C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x12C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x12C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x12C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x12C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x12C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x12C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x130 "PIO412,Digital I/O control for port 4 pins PIO4_12"
bitfld.long 0x130 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x130 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x130 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x130 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x130 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x130 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x130 0.--3. 1. "FUNC,Selects pin function."
line.long 0x134 "PIO413,Digital I/O control for port 4 pins PIO4_13"
bitfld.long 0x134 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x134 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x134 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x134 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x134 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x134 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x134 0.--3. 1. "FUNC,Selects pin function."
line.long 0x138 "PIO414,Digital I/O control for port 4 pins PIO4_14"
bitfld.long 0x138 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x138 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x138 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x138 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x138 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x138 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x138 0.--3. 1. "FUNC,Selects pin function."
line.long 0x13C "PIO415,Digital I/O control for port 4 pins PIO4_15"
bitfld.long 0x13C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x13C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x13C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x13C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x13C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x13C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x13C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x140 "PIO416,Digital I/O control for port 4 pins PIO4_16"
bitfld.long 0x140 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x140 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x140 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x140 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x140 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x140 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x140 0.--3. 1. "FUNC,Selects pin function."
line.long 0x144 "PIO417,Digital I/O control for port 4 pins PIO4_17"
bitfld.long 0x144 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x144 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x144 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x144 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x144 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x144 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x144 0.--3. 1. "FUNC,Selects pin function."
line.long 0x148 "PIO418,Digital I/O control for port 4 pins PIO4_18"
bitfld.long 0x148 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x148 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x148 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x148 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x148 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x148 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x148 0.--3. 1. "FUNC,Selects pin function."
line.long 0x14C "PIO419,Digital I/O control for port 4 pins PIO4_19"
bitfld.long 0x14C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x14C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x14C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x14C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x14C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x14C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x14C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x150 "PIO420,Digital I/O control for port 4 pins PIO4_20"
bitfld.long 0x150 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x150 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x150 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x150 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x150 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x150 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x150 0.--3. 1. "FUNC,Selects pin function."
line.long 0x154 "PIO421,Digital I/O control for port 4 pins PIO4_21"
bitfld.long 0x154 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x154 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x154 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x154 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x154 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x154 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x154 0.--3. 1. "FUNC,Selects pin function."
line.long 0x158 "PIO422,Digital I/O control for port 4 pins PIO4_22"
bitfld.long 0x158 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x158 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x158 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x158 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x158 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x158 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x158 0.--3. 1. "FUNC,Selects pin function."
line.long 0x15C "PIO423,Digital I/O control for port 4 pins PIO4_23"
bitfld.long 0x15C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x15C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x15C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x15C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x15C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x15C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x15C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x160 "PIO424,Digital I/O control for port 4 pins PIO4_24"
bitfld.long 0x160 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x160 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x160 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x160 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x160 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x160 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x160 0.--3. 1. "FUNC,Selects pin function."
line.long 0x164 "PIO425,Digital I/O control for port 4 pins PIO4_25"
bitfld.long 0x164 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x164 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x164 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x164 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x164 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x164 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x164 0.--3. 1. "FUNC,Selects pin function."
line.long 0x168 "PIO426,Digital I/O control for port 4 pins PIO4_26"
bitfld.long 0x168 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x168 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x168 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x168 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x168 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x168 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x168 0.--3. 1. "FUNC,Selects pin function."
line.long 0x16C "PIO427,Digital I/O control for port 4 pins PIO4_27"
bitfld.long 0x16C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x16C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x16C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x16C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x16C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x16C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x16C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x170 "PIO428,Digital I/O control for port 4 pins PIO4_28"
bitfld.long 0x170 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x170 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x170 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x170 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x170 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x170 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x170 0.--3. 1. "FUNC,Selects pin function."
line.long 0x174 "PIO429,Digital I/O control for port 4 pins PIO4_29"
bitfld.long 0x174 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x174 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x174 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x174 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x174 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x174 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x174 0.--3. 1. "FUNC,Selects pin function."
line.long 0x178 "PIO430,Digital I/O control for port 4 pins PIO4_30"
bitfld.long 0x178 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x178 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x178 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x178 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x178 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x178 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x178 0.--3. 1. "FUNC,Selects pin function."
line.long 0x17C "PIO431,Digital I/O control for port 4 pins PIO4_31"
bitfld.long 0x17C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x17C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x17C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x17C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x17C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x17C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x17C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x180 "PIO50,Digital I/O control for port 5 pins PIO5_0"
bitfld.long 0x180 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x180 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x180 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x180 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x180 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x180 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x180 0.--3. 1. "FUNC,Selects pin function."
line.long 0x184 "PIO51,Digital I/O control for port 5 pins PIO5_1"
bitfld.long 0x184 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x184 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x184 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x184 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x184 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x184 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x184 0.--3. 1. "FUNC,Selects pin function."
line.long 0x188 "PIO52,Digital I/O control for port 5 pins PIO5_2"
bitfld.long 0x188 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x188 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x188 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x188 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x188 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x188 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x188 0.--3. 1. "FUNC,Selects pin function."
line.long 0x18C "PIO53,Digital I/O control for port 5 pins PIO5_3"
bitfld.long 0x18C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x18C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x18C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x18C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x18C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x18C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x18C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x190 "PIO54,Digital I/O control for port 5 pins PIO5_4"
bitfld.long 0x190 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x190 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x190 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x190 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x190 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x190 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x190 0.--3. 1. "FUNC,Selects pin function."
line.long 0x194 "PIO55,Digital I/O control for port 5 pins PIO5_5"
bitfld.long 0x194 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x194 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x194 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x194 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x194 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x194 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x194 0.--3. 1. "FUNC,Selects pin function."
line.long 0x198 "PIO56,Digital I/O control for port 5 pins PIO5_6"
bitfld.long 0x198 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x198 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x198 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x198 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x198 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x198 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x198 0.--3. 1. "FUNC,Selects pin function."
line.long 0x19C "PIO57,Digital I/O control for port 5 pins PIO5_7"
bitfld.long 0x19C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x19C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x19C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x19C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x19C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x19C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x19C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1A0 "PIO58,Digital I/O control for port 5 pins PIO5_8"
bitfld.long 0x1A0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x1A0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x1A0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x1A0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x1A0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x1A0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x1A0 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1A4 "PIO59,Digital I/O control for port 5 pins PIO5_9"
bitfld.long 0x1A4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x1A4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x1A4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x1A4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x1A4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x1A4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x1A4 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1A8 "PIO510,Digital I/O control for port 5 pins PIO5_10"
bitfld.long 0x1A8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1A8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1A8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1A8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x1A8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x1A8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x1A8 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1AC "PIO511,Digital I/O control for port 5 pins PIO5_11"
bitfld.long 0x1AC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x1AC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x1AC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x1AC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x1AC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x1AC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x1AC 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1B0 "PIO512,Digital I/O control for port 5 pins PIO5_12"
bitfld.long 0x1B0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1B0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1B0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1B0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1B0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x1B0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x1B0 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1B4 "PIO513,Digital I/O control for port 5 pins PIO5_13"
bitfld.long 0x1B4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1B4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1B4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1B4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x1B4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x1B4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x1B4 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1B8 "PIO514,Digital I/O control for port 5 pins PIO5_14"
bitfld.long 0x1B8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1B8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1B8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1B8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1B8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x1B8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x1B8 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1BC "PIO515,Digital I/O control for port 5 pins PIO5_15"
bitfld.long 0x1BC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1BC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1BC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1BC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1BC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1BC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x1BC 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1C0 "PIO516,Digital I/O control for port 5 pins PIO5_16"
bitfld.long 0x1C0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1C0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1C0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1C0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1C0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1C0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x1C0 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1C4 "PIO517,Digital I/O control for port 5 pins PIO5_17"
bitfld.long 0x1C4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1C4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1C4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1C4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1C4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1C4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1C4 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1C8 "PIO518,Digital I/O control for port 5 pins PIO5_18"
bitfld.long 0x1C8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1C8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1C8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1C8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1C8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1C8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1C8 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1CC "PIO519,Digital I/O control for port 5 pins PIO5_19"
bitfld.long 0x1CC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1CC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1CC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1CC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1CC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1CC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1CC 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1D0 "PIO520,Digital I/O control for port 5 pins PIO5_20"
bitfld.long 0x1D0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1D0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1D0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1D0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1D0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1D0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1D0 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1D4 "PIO521,Digital I/O control for port 5 pins PIO5_21"
bitfld.long 0x1D4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1D4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1D4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1D4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1D4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1D4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1D4 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1D8 "PIO522,Digital I/O control for port 5 pins PIO5_22"
bitfld.long 0x1D8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1D8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1D8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1D8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1D8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1D8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1D8 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1DC "PIO523,Digital I/O control for port 5 pins PIO5_23"
bitfld.long 0x1DC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1DC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1DC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1DC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1DC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1DC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1DC 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1E0 "PIO524,Digital I/O control for port 5 pins PIO5_24"
bitfld.long 0x1E0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1E0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1E0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1E0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1E0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1E0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1E0 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1E4 "PIO525,Digital I/O control for port 5 pins PIO5_25"
bitfld.long 0x1E4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1E4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1E4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1E4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1E4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1E4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1E4 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1E8 "PIO526,Digital I/O control for port 5 pins PIO5_26"
bitfld.long 0x1E8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1E8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1E8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1E8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1E8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1E8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1E8 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1EC "PIO527,Digital I/O control for port 5 pins PIO5_27"
bitfld.long 0x1EC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1EC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1EC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1EC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1EC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1EC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1EC 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1F0 "PIO528,Digital I/O control for port 5 pins PIO5_28"
bitfld.long 0x1F0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1F0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1F0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1F0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1F0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1F0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1F0 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1F4 "PIO529,Digital I/O control for port 5 pins PIO5_29"
bitfld.long 0x1F4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1F4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1F4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1F4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1F4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1F4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1F4 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1F8 "PIO530,Digital I/O control for port 5 pins PIO5_30"
bitfld.long 0x1F8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1F8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1F8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1F8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1F8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1F8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1F8 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1FC "PIO531,Digital I/O control for port 5 pins PIO5_31"
bitfld.long 0x1FC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1FC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1FC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1FC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1FC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1FC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1FC 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54605*"))
group.long 0x100++0x1FF
line.long 0x0 "PIO20,Digital I/O control for port 2 pins PIO2_0"
bitfld.long 0x0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x0 0.--3. 1. "FUNC,Selects pin function."
line.long 0x4 "PIO21,Digital I/O control for port 2 pins PIO2_1"
bitfld.long 0x4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x4 0.--3. 1. "FUNC,Selects pin function."
line.long 0x8 "PIO22,Digital I/O control for port 2 pins PIO2_2"
bitfld.long 0x8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x8 0.--3. 1. "FUNC,Selects pin function."
line.long 0xC "PIO23,Digital I/O control for port 2 pins PIO2_3"
bitfld.long 0xC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xC 0.--3. 1. "FUNC,Selects pin function."
line.long 0x10 "PIO24,Digital I/O control for port 2 pins PIO2_4"
bitfld.long 0x10 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x10 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x10 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x10 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x10 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x10 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x10 0.--3. 1. "FUNC,Selects pin function."
line.long 0x14 "PIO25,Digital I/O control for port 2 pins PIO2_5"
bitfld.long 0x14 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x14 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x14 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x14 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x14 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x14 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x14 0.--3. 1. "FUNC,Selects pin function."
line.long 0x18 "PIO26,Digital I/O control for port 2 pins PIO2_6"
bitfld.long 0x18 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x18 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x18 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x18 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x18 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x18 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x18 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1C "PIO27,Digital I/O control for port 2 pins PIO2_7"
bitfld.long 0x1C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x20 "PIO28,Digital I/O control for port 2 pins PIO2_8"
bitfld.long 0x20 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x20 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x20 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x20 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x20 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x20 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x20 0.--3. 1. "FUNC,Selects pin function."
line.long 0x24 "PIO29,Digital I/O control for port 2 pins PIO2_9"
bitfld.long 0x24 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x24 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x24 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x24 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x24 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x24 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x24 0.--3. 1. "FUNC,Selects pin function."
line.long 0x28 "PIO210,Digital I/O control for port 2 pins PIO2_10"
bitfld.long 0x28 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x28 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x28 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x28 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x28 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x28 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x28 0.--3. 1. "FUNC,Selects pin function."
line.long 0x2C "PIO211,Digital I/O control for port 2 pins PIO2_11"
bitfld.long 0x2C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x2C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x2C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x2C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x2C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x2C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x2C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x30 "PIO212,Digital I/O control for port 2 pins PIO2_12"
bitfld.long 0x30 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x30 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x30 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x30 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x30 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x30 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x30 0.--3. 1. "FUNC,Selects pin function."
line.long 0x34 "PIO213,Digital I/O control for port 2 pins PIO2_13"
bitfld.long 0x34 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x34 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x34 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x34 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x34 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x34 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x34 0.--3. 1. "FUNC,Selects pin function."
line.long 0x38 "PIO214,Digital I/O control for port 2 pins PIO2_14"
bitfld.long 0x38 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x38 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x38 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x38 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x38 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x38 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x38 0.--3. 1. "FUNC,Selects pin function."
line.long 0x3C "PIO215,Digital I/O control for port 2 pins PIO2_15"
bitfld.long 0x3C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x3C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x3C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x3C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x3C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x3C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x3C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x40 "PIO216,Digital I/O control for port 2 pins PIO2_16"
bitfld.long 0x40 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x40 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x40 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x40 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x40 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x40 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x40 0.--3. 1. "FUNC,Selects pin function."
line.long 0x44 "PIO217,Digital I/O control for port 2 pins PIO2_17"
bitfld.long 0x44 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x44 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x44 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x44 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x44 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x44 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x44 0.--3. 1. "FUNC,Selects pin function."
line.long 0x48 "PIO218,Digital I/O control for port 2 pins PIO2_18"
bitfld.long 0x48 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x48 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x48 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x48 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x48 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x48 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x48 0.--3. 1. "FUNC,Selects pin function."
line.long 0x4C "PIO219,Digital I/O control for port 2 pins PIO2_19"
bitfld.long 0x4C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x4C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x4C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x4C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x4C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x4C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x4C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x50 "PIO220,Digital I/O control for port 2 pins PIO2_20"
bitfld.long 0x50 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x50 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x50 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x50 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x50 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x50 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x50 0.--3. 1. "FUNC,Selects pin function."
line.long 0x54 "PIO221,Digital I/O control for port 2 pins PIO2_21"
bitfld.long 0x54 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x54 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x54 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x54 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x54 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x54 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x54 0.--3. 1. "FUNC,Selects pin function."
line.long 0x58 "PIO222,Digital I/O control for port 2 pins PIO2_22"
bitfld.long 0x58 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x58 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x58 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x58 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x58 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x58 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x58 0.--3. 1. "FUNC,Selects pin function."
line.long 0x5C "PIO223,Digital I/O control for port 2 pins PIO2_23"
bitfld.long 0x5C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x5C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x5C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x5C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x5C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x5C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x5C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x60 "PIO224,Digital I/O control for port 2 pins PIO2_24"
bitfld.long 0x60 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x60 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x60 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x60 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x60 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x60 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x60 0.--3. 1. "FUNC,Selects pin function."
line.long 0x64 "PIO225,Digital I/O control for port 2 pins PIO2_25"
bitfld.long 0x64 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x64 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x64 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x64 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x64 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x64 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x64 0.--3. 1. "FUNC,Selects pin function."
line.long 0x68 "PIO226,Digital I/O control for port 2 pins PIO2_26"
bitfld.long 0x68 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x68 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x68 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x68 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x68 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x68 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x68 0.--3. 1. "FUNC,Selects pin function."
line.long 0x6C "PIO227,Digital I/O control for port 2 pins PIO2_27"
bitfld.long 0x6C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x6C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x6C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x6C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x6C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x6C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x6C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x70 "PIO228,Digital I/O control for port 2 pins PIO2_28"
bitfld.long 0x70 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x70 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x70 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x70 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x70 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x70 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x70 0.--3. 1. "FUNC,Selects pin function."
line.long 0x74 "PIO229,Digital I/O control for port 2 pins PIO2_29"
bitfld.long 0x74 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x74 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x74 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x74 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x74 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x74 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x74 0.--3. 1. "FUNC,Selects pin function."
line.long 0x78 "PIO230,Digital I/O control for port 2 pins PIO2_30"
bitfld.long 0x78 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x78 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x78 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x78 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x78 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x78 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x78 0.--3. 1. "FUNC,Selects pin function."
line.long 0x7C "PIO231,Digital I/O control for port 2 pins PIO2_31"
bitfld.long 0x7C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x7C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x7C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x7C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x7C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x7C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x7C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x80 "PIO30,Digital I/O control for port 3 pins PIO3_0"
bitfld.long 0x80 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x80 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x80 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x80 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x80 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x80 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x80 0.--3. 1. "FUNC,Selects pin function."
line.long 0x84 "PIO31,Digital I/O control for port 3 pins PIO3_1"
bitfld.long 0x84 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x84 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x84 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x84 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x84 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x84 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x84 0.--3. 1. "FUNC,Selects pin function."
line.long 0x88 "PIO32,Digital I/O control for port 3 pins PIO3_2"
bitfld.long 0x88 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x88 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x88 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x88 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x88 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x88 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x88 0.--3. 1. "FUNC,Selects pin function."
line.long 0x8C "PIO33,Digital I/O control for port 3 pins PIO3_3"
bitfld.long 0x8C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x8C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x8C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x8C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x8C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x8C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x8C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x90 "PIO34,Digital I/O control for port 3 pins PIO3_4"
bitfld.long 0x90 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x90 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x90 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x90 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x90 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x90 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x90 0.--3. 1. "FUNC,Selects pin function."
line.long 0x94 "PIO35,Digital I/O control for port 3 pins PIO3_5"
bitfld.long 0x94 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x94 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x94 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x94 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x94 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x94 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x94 0.--3. 1. "FUNC,Selects pin function."
line.long 0x98 "PIO36,Digital I/O control for port 3 pins PIO3_6"
bitfld.long 0x98 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x98 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x98 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x98 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x98 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x98 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x98 0.--3. 1. "FUNC,Selects pin function."
line.long 0x9C "PIO37,Digital I/O control for port 3 pins PIO3_7"
bitfld.long 0x9C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x9C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x9C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x9C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x9C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x9C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x9C 0.--3. 1. "FUNC,Selects pin function."
line.long 0xA0 "PIO38,Digital I/O control for port 3 pins PIO3_8"
bitfld.long 0xA0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xA0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xA0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xA0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xA0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xA0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xA0 0.--3. 1. "FUNC,Selects pin function."
line.long 0xA4 "PIO39,Digital I/O control for port 3 pins PIO3_9"
bitfld.long 0xA4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xA4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xA4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xA4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xA4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xA4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xA4 0.--3. 1. "FUNC,Selects pin function."
line.long 0xA8 "PIO310,Digital I/O control for port 3 pins PIO3_10"
bitfld.long 0xA8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xA8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xA8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xA8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xA8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xA8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xA8 0.--3. 1. "FUNC,Selects pin function."
line.long 0xAC "PIO311,Digital I/O control for port 3 pins PIO3_11"
bitfld.long 0xAC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xAC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xAC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xAC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xAC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xAC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xAC 0.--3. 1. "FUNC,Selects pin function."
line.long 0xB0 "PIO312,Digital I/O control for port 3 pins PIO3_12"
bitfld.long 0xB0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xB0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xB0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xB0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xB0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xB0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xB0 0.--3. 1. "FUNC,Selects pin function."
line.long 0xB4 "PIO313,Digital I/O control for port 3 pins PIO3_13"
bitfld.long 0xB4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xB4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xB4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xB4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xB4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xB4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xB4 0.--3. 1. "FUNC,Selects pin function."
line.long 0xB8 "PIO314,Digital I/O control for port 3 pins PIO3_14"
bitfld.long 0xB8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xB8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xB8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xB8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xB8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xB8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xB8 0.--3. 1. "FUNC,Selects pin function."
line.long 0xBC "PIO315,Digital I/O control for port 3 pins PIO3_15"
bitfld.long 0xBC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xBC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xBC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xBC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xBC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xBC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xBC 0.--3. 1. "FUNC,Selects pin function."
line.long 0xC0 "PIO316,Digital I/O control for port 3 pins PIO3_16"
bitfld.long 0xC0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xC0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xC0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xC0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xC0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xC0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xC0 0.--3. 1. "FUNC,Selects pin function."
line.long 0xC4 "PIO317,Digital I/O control for port 3 pins PIO3_17"
bitfld.long 0xC4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xC4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xC4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xC4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xC4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xC4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xC4 0.--3. 1. "FUNC,Selects pin function."
line.long 0xC8 "PIO318,Digital I/O control for port 3 pins PIO3_18"
bitfld.long 0xC8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xC8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xC8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xC8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xC8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xC8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xC8 0.--3. 1. "FUNC,Selects pin function."
line.long 0xCC "PIO319,Digital I/O control for port 3 pins PIO3_19"
bitfld.long 0xCC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xCC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xCC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xCC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xCC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xCC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xCC 0.--3. 1. "FUNC,Selects pin function."
line.long 0xD0 "PIO320,Digital I/O control for port 3 pins PIO3_20"
bitfld.long 0xD0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xD0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xD0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xD0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xD0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xD0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xD0 0.--3. 1. "FUNC,Selects pin function."
line.long 0xD4 "PIO321,Digital I/O control for port 3 pins PIO3_21"
bitfld.long 0xD4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xD4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xD4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xD4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xD4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xD4 0.--3. 1. "FUNC,Selects pin function."
line.long 0xD8 "PIO322,Digital I/O control for port 3 pins PIO3_22"
bitfld.long 0xD8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xD8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xD8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xD8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xD8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xD8 0.--3. 1. "FUNC,Selects pin function."
line.long 0xDC "PIO323,Digital I/O control for port 3 pins PIO3_23"
bitfld.long 0xDC 11. "I2CFILTER,Configures I2C features for standard mode  fast mode  and Fast Mode Plus operation." "0: Enabled. I2C 50 ns glitch filter enabled.,1: Disabled. I2C 50 ns glitch filter disabled."
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bitfld.long 0xDC 10. "I2CDRIVE,Controls the current sink capability of the pin." "0: Low drive. Output drive sink is 4 mA. This is..,1: High drive. Output drive sink is 20 mA. This is.."
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bitfld.long 0xDC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xDC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xDC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xDC 6. "I2CSLEW,Controls slew rate of I2C pad." "0: I2C mode.,1: GPIO mode."
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hexmask.long.byte 0xDC 0.--3. 1. "FUNC,Selects pin function."
line.long 0xE0 "PIO324,Digital I/O control for port 3 pins PIO3_24"
bitfld.long 0xE0 11. "I2CFILTER,Configures I2C features for standard mode  fast mode  and Fast Mode Plus operation." "0: Enabled. I2C 50 ns glitch filter enabled.,1: Disabled. I2C 50 ns glitch filter disabled."
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bitfld.long 0xE0 10. "I2CDRIVE,Controls the current sink capability of the pin." "0: Low drive. Output drive sink is 4 mA. This is..,1: High drive. Output drive sink is 20 mA. This is.."
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bitfld.long 0xE0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xE0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xE0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xE0 6. "I2CSLEW,Controls slew rate of I2C pad." "0: I2C mode.,1: GPIO mode."
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hexmask.long.byte 0xE0 0.--3. 1. "FUNC,Selects pin function."
line.long 0xE4 "PIO325,Digital I/O control for port 3 pins PIO3_25"
bitfld.long 0xE4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xE4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xE4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xE4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xE4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xE4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xE4 0.--3. 1. "FUNC,Selects pin function."
line.long 0xE8 "PIO326,Digital I/O control for port 3 pins PIO3_26"
bitfld.long 0xE8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xE8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xE8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xE8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xE8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xE8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xE8 0.--3. 1. "FUNC,Selects pin function."
line.long 0xEC "PIO327,Digital I/O control for port 3 pins PIO3_27"
bitfld.long 0xEC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xEC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xEC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xEC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xEC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xEC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xEC 0.--3. 1. "FUNC,Selects pin function."
line.long 0xF0 "PIO328,Digital I/O control for port 3 pins PIO3_28"
bitfld.long 0xF0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xF0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xF0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xF0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xF0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xF0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xF0 0.--3. 1. "FUNC,Selects pin function."
line.long 0xF4 "PIO329,Digital I/O control for port 3 pins PIO3_29"
bitfld.long 0xF4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xF4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xF4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xF4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xF4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xF4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xF4 0.--3. 1. "FUNC,Selects pin function."
line.long 0xF8 "PIO330,Digital I/O control for port 3 pins PIO3_30"
bitfld.long 0xF8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xF8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xF8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xF8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xF8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xF8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xF8 0.--3. 1. "FUNC,Selects pin function."
line.long 0xFC "PIO331,Digital I/O control for port 3 pins PIO3_31"
bitfld.long 0xFC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xFC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xFC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xFC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xFC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xFC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xFC 0.--3. 1. "FUNC,Selects pin function."
line.long 0x100 "PIO40,Digital I/O control for port 4 pins PIO4_0"
bitfld.long 0x100 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x100 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x100 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x100 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x100 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x100 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x100 0.--3. 1. "FUNC,Selects pin function."
line.long 0x104 "PIO41,Digital I/O control for port 4 pins PIO4_1"
bitfld.long 0x104 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x104 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x104 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x104 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x104 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x104 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x104 0.--3. 1. "FUNC,Selects pin function."
line.long 0x108 "PIO42,Digital I/O control for port 4 pins PIO4_2"
bitfld.long 0x108 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x108 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x108 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x108 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x108 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x108 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x108 0.--3. 1. "FUNC,Selects pin function."
line.long 0x10C "PIO43,Digital I/O control for port 4 pins PIO4_3"
bitfld.long 0x10C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x10C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x10C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x10C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x10C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x10C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x10C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x110 "PIO44,Digital I/O control for port 4 pins PIO4_4"
bitfld.long 0x110 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x110 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x110 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x110 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x110 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x110 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x110 0.--3. 1. "FUNC,Selects pin function."
line.long 0x114 "PIO45,Digital I/O control for port 4 pins PIO4_5"
bitfld.long 0x114 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x114 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x114 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x114 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x114 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x114 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x114 0.--3. 1. "FUNC,Selects pin function."
line.long 0x118 "PIO46,Digital I/O control for port 4 pins PIO4_6"
bitfld.long 0x118 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x118 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x118 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x118 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x118 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x118 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x118 0.--3. 1. "FUNC,Selects pin function."
line.long 0x11C "PIO47,Digital I/O control for port 4 pins PIO4_7"
bitfld.long 0x11C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x11C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x11C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x11C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x11C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x11C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x11C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x120 "PIO48,Digital I/O control for port 4 pins PIO4_8"
bitfld.long 0x120 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x120 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x120 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x120 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x120 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x120 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x120 0.--3. 1. "FUNC,Selects pin function."
line.long 0x124 "PIO49,Digital I/O control for port 4 pins PIO4_9"
bitfld.long 0x124 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x124 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x124 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x124 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x124 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x124 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x124 0.--3. 1. "FUNC,Selects pin function."
line.long 0x128 "PIO410,Digital I/O control for port 4 pins PIO4_10"
bitfld.long 0x128 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x128 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x128 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x128 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x128 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x128 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x128 0.--3. 1. "FUNC,Selects pin function."
line.long 0x12C "PIO411,Digital I/O control for port 4 pins PIO4_11"
bitfld.long 0x12C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x12C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x12C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x12C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x12C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x12C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x12C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x130 "PIO412,Digital I/O control for port 4 pins PIO4_12"
bitfld.long 0x130 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x130 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x130 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x130 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x130 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x130 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x130 0.--3. 1. "FUNC,Selects pin function."
line.long 0x134 "PIO413,Digital I/O control for port 4 pins PIO4_13"
bitfld.long 0x134 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x134 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x134 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x134 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x134 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x134 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x134 0.--3. 1. "FUNC,Selects pin function."
line.long 0x138 "PIO414,Digital I/O control for port 4 pins PIO4_14"
bitfld.long 0x138 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x138 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x138 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x138 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x138 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x138 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x138 0.--3. 1. "FUNC,Selects pin function."
line.long 0x13C "PIO415,Digital I/O control for port 4 pins PIO4_15"
bitfld.long 0x13C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x13C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x13C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x13C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x13C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x13C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x13C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x140 "PIO416,Digital I/O control for port 4 pins PIO4_16"
bitfld.long 0x140 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x140 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x140 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x140 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x140 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x140 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x140 0.--3. 1. "FUNC,Selects pin function."
line.long 0x144 "PIO417,Digital I/O control for port 4 pins PIO4_17"
bitfld.long 0x144 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x144 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x144 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x144 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x144 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x144 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x144 0.--3. 1. "FUNC,Selects pin function."
line.long 0x148 "PIO418,Digital I/O control for port 4 pins PIO4_18"
bitfld.long 0x148 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x148 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x148 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x148 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x148 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x148 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x148 0.--3. 1. "FUNC,Selects pin function."
line.long 0x14C "PIO419,Digital I/O control for port 4 pins PIO4_19"
bitfld.long 0x14C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x14C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x14C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x14C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x14C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x14C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x14C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x150 "PIO420,Digital I/O control for port 4 pins PIO4_20"
bitfld.long 0x150 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x150 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x150 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x150 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x150 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x150 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x150 0.--3. 1. "FUNC,Selects pin function."
line.long 0x154 "PIO421,Digital I/O control for port 4 pins PIO4_21"
bitfld.long 0x154 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x154 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x154 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x154 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x154 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x154 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x154 0.--3. 1. "FUNC,Selects pin function."
line.long 0x158 "PIO422,Digital I/O control for port 4 pins PIO4_22"
bitfld.long 0x158 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x158 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x158 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x158 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x158 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x158 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x158 0.--3. 1. "FUNC,Selects pin function."
line.long 0x15C "PIO423,Digital I/O control for port 4 pins PIO4_23"
bitfld.long 0x15C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x15C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x15C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x15C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x15C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x15C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x15C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x160 "PIO424,Digital I/O control for port 4 pins PIO4_24"
bitfld.long 0x160 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x160 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x160 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x160 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x160 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x160 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x160 0.--3. 1. "FUNC,Selects pin function."
line.long 0x164 "PIO425,Digital I/O control for port 4 pins PIO4_25"
bitfld.long 0x164 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x164 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x164 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x164 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x164 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x164 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x164 0.--3. 1. "FUNC,Selects pin function."
line.long 0x168 "PIO426,Digital I/O control for port 4 pins PIO4_26"
bitfld.long 0x168 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x168 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x168 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x168 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x168 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x168 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x168 0.--3. 1. "FUNC,Selects pin function."
line.long 0x16C "PIO427,Digital I/O control for port 4 pins PIO4_27"
bitfld.long 0x16C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x16C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x16C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x16C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x16C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x16C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x16C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x170 "PIO428,Digital I/O control for port 4 pins PIO4_28"
bitfld.long 0x170 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x170 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x170 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x170 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x170 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x170 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x170 0.--3. 1. "FUNC,Selects pin function."
line.long 0x174 "PIO429,Digital I/O control for port 4 pins PIO4_29"
bitfld.long 0x174 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x174 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x174 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x174 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x174 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x174 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x174 0.--3. 1. "FUNC,Selects pin function."
line.long 0x178 "PIO430,Digital I/O control for port 4 pins PIO4_30"
bitfld.long 0x178 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x178 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x178 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x178 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x178 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x178 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x178 0.--3. 1. "FUNC,Selects pin function."
line.long 0x17C "PIO431,Digital I/O control for port 4 pins PIO4_31"
bitfld.long 0x17C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x17C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x17C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x17C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x17C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x17C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x17C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x180 "PIO50,Digital I/O control for port 5 pins PIO5_0"
bitfld.long 0x180 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x180 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x180 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x180 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x180 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x180 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x180 0.--3. 1. "FUNC,Selects pin function."
line.long 0x184 "PIO51,Digital I/O control for port 5 pins PIO5_1"
bitfld.long 0x184 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x184 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x184 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x184 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x184 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x184 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x184 0.--3. 1. "FUNC,Selects pin function."
line.long 0x188 "PIO52,Digital I/O control for port 5 pins PIO5_2"
bitfld.long 0x188 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x188 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x188 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x188 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x188 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x188 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x188 0.--3. 1. "FUNC,Selects pin function."
line.long 0x18C "PIO53,Digital I/O control for port 5 pins PIO5_3"
bitfld.long 0x18C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x18C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x18C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x18C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x18C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x18C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x18C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x190 "PIO54,Digital I/O control for port 5 pins PIO5_4"
bitfld.long 0x190 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x190 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x190 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x190 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x190 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x190 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x190 0.--3. 1. "FUNC,Selects pin function."
line.long 0x194 "PIO55,Digital I/O control for port 5 pins PIO5_5"
bitfld.long 0x194 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x194 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x194 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x194 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x194 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x194 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x194 0.--3. 1. "FUNC,Selects pin function."
line.long 0x198 "PIO56,Digital I/O control for port 5 pins PIO5_6"
bitfld.long 0x198 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x198 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x198 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x198 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x198 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x198 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x198 0.--3. 1. "FUNC,Selects pin function."
line.long 0x19C "PIO57,Digital I/O control for port 5 pins PIO5_7"
bitfld.long 0x19C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x19C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x19C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x19C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x19C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x19C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x19C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1A0 "PIO58,Digital I/O control for port 5 pins PIO5_8"
bitfld.long 0x1A0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x1A0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x1A0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x1A0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x1A0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x1A0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x1A0 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1A4 "PIO59,Digital I/O control for port 5 pins PIO5_9"
bitfld.long 0x1A4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1A4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x1A4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x1A4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x1A4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x1A4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x1A4 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1A8 "PIO510,Digital I/O control for port 5 pins PIO5_10"
bitfld.long 0x1A8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1A8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x1A8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1A8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x1A8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x1A8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x1A8 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1AC "PIO511,Digital I/O control for port 5 pins PIO5_11"
bitfld.long 0x1AC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x1AC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x1AC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x1AC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x1AC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x1AC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x1AC 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1B0 "PIO512,Digital I/O control for port 5 pins PIO5_12"
bitfld.long 0x1B0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1B0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x1B0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1B0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x1B0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x1B0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x1B0 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1B4 "PIO513,Digital I/O control for port 5 pins PIO5_13"
bitfld.long 0x1B4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1B4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x1B4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x1B4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x1B4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x1B4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x1B4 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1B8 "PIO514,Digital I/O control for port 5 pins PIO5_14"
bitfld.long 0x1B8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1B8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1B8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1B8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x1B8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x1B8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x1B8 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1BC "PIO515,Digital I/O control for port 5 pins PIO5_15"
bitfld.long 0x1BC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1BC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1BC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1BC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1BC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x1BC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x1BC 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1C0 "PIO516,Digital I/O control for port 5 pins PIO5_16"
bitfld.long 0x1C0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1C0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1C0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1C0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1C0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x1C0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x1C0 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1C4 "PIO517,Digital I/O control for port 5 pins PIO5_17"
bitfld.long 0x1C4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1C4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1C4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1C4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1C4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1C4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x1C4 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1C8 "PIO518,Digital I/O control for port 5 pins PIO5_18"
bitfld.long 0x1C8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1C8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1C8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1C8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1C8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1C8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x1C8 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1CC "PIO519,Digital I/O control for port 5 pins PIO5_19"
bitfld.long 0x1CC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1CC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1CC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1CC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1CC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1CC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1CC 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1D0 "PIO520,Digital I/O control for port 5 pins PIO5_20"
bitfld.long 0x1D0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1D0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1D0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1D0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1D0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1D0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1D0 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1D4 "PIO521,Digital I/O control for port 5 pins PIO5_21"
bitfld.long 0x1D4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1D4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1D4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1D4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1D4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1D4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1D4 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1D8 "PIO522,Digital I/O control for port 5 pins PIO5_22"
bitfld.long 0x1D8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1D8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1D8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1D8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1D8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1D8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1D8 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1DC "PIO523,Digital I/O control for port 5 pins PIO5_23"
bitfld.long 0x1DC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1DC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1DC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1DC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1DC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1DC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1DC 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1E0 "PIO524,Digital I/O control for port 5 pins PIO5_24"
bitfld.long 0x1E0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1E0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1E0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1E0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1E0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1E0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1E0 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1E4 "PIO525,Digital I/O control for port 5 pins PIO5_25"
bitfld.long 0x1E4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1E4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1E4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1E4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1E4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1E4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1E4 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1E8 "PIO526,Digital I/O control for port 5 pins PIO5_26"
bitfld.long 0x1E8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1E8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1E8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1E8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1E8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1E8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1E8 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1EC "PIO527,Digital I/O control for port 5 pins PIO5_27"
bitfld.long 0x1EC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1EC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1EC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1EC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1EC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1EC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1EC 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1F0 "PIO528,Digital I/O control for port 5 pins PIO5_28"
bitfld.long 0x1F0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1F0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1F0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1F0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1F0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1F0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1F0 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1F4 "PIO529,Digital I/O control for port 5 pins PIO5_29"
bitfld.long 0x1F4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1F4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1F4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1F4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1F4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1F4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1F4 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1F8 "PIO530,Digital I/O control for port 5 pins PIO5_30"
bitfld.long 0x1F8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1F8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1F8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1F8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1F8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1F8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1F8 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1FC "PIO531,Digital I/O control for port 5 pins PIO5_31"
bitfld.long 0x1FC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1FC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1FC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1FC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1FC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1FC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1FC 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54606*"))
group.long 0x100++0x1FF
line.long 0x0 "PIO20,Digital I/O control for port 2 pins PIO2_0"
bitfld.long 0x0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x0 0.--3. 1. "FUNC,Selects pin function."
line.long 0x4 "PIO21,Digital I/O control for port 2 pins PIO2_1"
bitfld.long 0x4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x4 0.--3. 1. "FUNC,Selects pin function."
line.long 0x8 "PIO22,Digital I/O control for port 2 pins PIO2_2"
bitfld.long 0x8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x8 0.--3. 1. "FUNC,Selects pin function."
line.long 0xC "PIO23,Digital I/O control for port 2 pins PIO2_3"
bitfld.long 0xC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xC 0.--3. 1. "FUNC,Selects pin function."
line.long 0x10 "PIO24,Digital I/O control for port 2 pins PIO2_4"
bitfld.long 0x10 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x10 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x10 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x10 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x10 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x10 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x10 0.--3. 1. "FUNC,Selects pin function."
line.long 0x14 "PIO25,Digital I/O control for port 2 pins PIO2_5"
bitfld.long 0x14 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x14 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x14 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x14 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x14 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x14 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x14 0.--3. 1. "FUNC,Selects pin function."
line.long 0x18 "PIO26,Digital I/O control for port 2 pins PIO2_6"
bitfld.long 0x18 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x18 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x18 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x18 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x18 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x18 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x18 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1C "PIO27,Digital I/O control for port 2 pins PIO2_7"
bitfld.long 0x1C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x20 "PIO28,Digital I/O control for port 2 pins PIO2_8"
bitfld.long 0x20 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x20 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x20 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x20 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x20 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x20 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x20 0.--3. 1. "FUNC,Selects pin function."
line.long 0x24 "PIO29,Digital I/O control for port 2 pins PIO2_9"
bitfld.long 0x24 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x24 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x24 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x24 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x24 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x24 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x24 0.--3. 1. "FUNC,Selects pin function."
line.long 0x28 "PIO210,Digital I/O control for port 2 pins PIO2_10"
bitfld.long 0x28 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x28 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x28 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x28 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x28 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x28 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x28 0.--3. 1. "FUNC,Selects pin function."
line.long 0x2C "PIO211,Digital I/O control for port 2 pins PIO2_11"
bitfld.long 0x2C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x2C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x2C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x2C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x2C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x2C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x2C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x30 "PIO212,Digital I/O control for port 2 pins PIO2_12"
bitfld.long 0x30 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x30 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x30 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x30 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x30 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x30 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x30 0.--3. 1. "FUNC,Selects pin function."
line.long 0x34 "PIO213,Digital I/O control for port 2 pins PIO2_13"
bitfld.long 0x34 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x34 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x34 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x34 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x34 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x34 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x34 0.--3. 1. "FUNC,Selects pin function."
line.long 0x38 "PIO214,Digital I/O control for port 2 pins PIO2_14"
bitfld.long 0x38 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x38 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x38 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x38 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x38 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x38 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x38 0.--3. 1. "FUNC,Selects pin function."
line.long 0x3C "PIO215,Digital I/O control for port 2 pins PIO2_15"
bitfld.long 0x3C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x3C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x3C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x3C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x3C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x3C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x3C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x40 "PIO216,Digital I/O control for port 2 pins PIO2_16"
bitfld.long 0x40 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x40 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x40 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x40 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x40 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x40 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x40 0.--3. 1. "FUNC,Selects pin function."
line.long 0x44 "PIO217,Digital I/O control for port 2 pins PIO2_17"
bitfld.long 0x44 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x44 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x44 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x44 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x44 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x44 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x44 0.--3. 1. "FUNC,Selects pin function."
line.long 0x48 "PIO218,Digital I/O control for port 2 pins PIO2_18"
bitfld.long 0x48 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x48 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x48 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x48 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x48 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x48 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x48 0.--3. 1. "FUNC,Selects pin function."
line.long 0x4C "PIO219,Digital I/O control for port 2 pins PIO2_19"
bitfld.long 0x4C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x4C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x4C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x4C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x4C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x4C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x4C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x50 "PIO220,Digital I/O control for port 2 pins PIO2_20"
bitfld.long 0x50 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x50 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x50 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x50 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x50 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x50 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x50 0.--3. 1. "FUNC,Selects pin function."
line.long 0x54 "PIO221,Digital I/O control for port 2 pins PIO2_21"
bitfld.long 0x54 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x54 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x54 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x54 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x54 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x54 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x54 0.--3. 1. "FUNC,Selects pin function."
line.long 0x58 "PIO222,Digital I/O control for port 2 pins PIO2_22"
bitfld.long 0x58 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x58 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x58 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x58 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x58 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x58 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x58 0.--3. 1. "FUNC,Selects pin function."
line.long 0x5C "PIO223,Digital I/O control for port 2 pins PIO2_23"
bitfld.long 0x5C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x5C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x5C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x5C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x5C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x5C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x5C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x60 "PIO224,Digital I/O control for port 2 pins PIO2_24"
bitfld.long 0x60 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x60 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x60 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x60 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x60 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x60 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x60 0.--3. 1. "FUNC,Selects pin function."
line.long 0x64 "PIO225,Digital I/O control for port 2 pins PIO2_25"
bitfld.long 0x64 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x64 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x64 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x64 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x64 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x64 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x64 0.--3. 1. "FUNC,Selects pin function."
line.long 0x68 "PIO226,Digital I/O control for port 2 pins PIO2_26"
bitfld.long 0x68 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x68 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x68 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x68 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x68 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x68 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x68 0.--3. 1. "FUNC,Selects pin function."
line.long 0x6C "PIO227,Digital I/O control for port 2 pins PIO2_27"
bitfld.long 0x6C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x6C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x6C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x6C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x6C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x6C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x6C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x70 "PIO228,Digital I/O control for port 2 pins PIO2_28"
bitfld.long 0x70 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x70 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x70 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x70 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x70 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x70 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x70 0.--3. 1. "FUNC,Selects pin function."
line.long 0x74 "PIO229,Digital I/O control for port 2 pins PIO2_29"
bitfld.long 0x74 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x74 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x74 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x74 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x74 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x74 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x74 0.--3. 1. "FUNC,Selects pin function."
line.long 0x78 "PIO230,Digital I/O control for port 2 pins PIO2_30"
bitfld.long 0x78 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x78 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x78 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x78 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x78 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x78 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x78 0.--3. 1. "FUNC,Selects pin function."
line.long 0x7C "PIO231,Digital I/O control for port 2 pins PIO2_31"
bitfld.long 0x7C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x7C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x7C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x7C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x7C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x7C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x7C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x80 "PIO30,Digital I/O control for port 3 pins PIO3_0"
bitfld.long 0x80 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x80 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x80 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x80 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x80 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x80 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x80 0.--3. 1. "FUNC,Selects pin function."
line.long 0x84 "PIO31,Digital I/O control for port 3 pins PIO3_1"
bitfld.long 0x84 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x84 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x84 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x84 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x84 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x84 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x84 0.--3. 1. "FUNC,Selects pin function."
line.long 0x88 "PIO32,Digital I/O control for port 3 pins PIO3_2"
bitfld.long 0x88 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x88 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x88 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x88 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x88 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x88 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x88 0.--3. 1. "FUNC,Selects pin function."
line.long 0x8C "PIO33,Digital I/O control for port 3 pins PIO3_3"
bitfld.long 0x8C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x8C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x8C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x8C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x8C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x8C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x8C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x90 "PIO34,Digital I/O control for port 3 pins PIO3_4"
bitfld.long 0x90 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x90 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x90 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x90 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x90 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x90 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x90 0.--3. 1. "FUNC,Selects pin function."
line.long 0x94 "PIO35,Digital I/O control for port 3 pins PIO3_5"
bitfld.long 0x94 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x94 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x94 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x94 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x94 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x94 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x94 0.--3. 1. "FUNC,Selects pin function."
line.long 0x98 "PIO36,Digital I/O control for port 3 pins PIO3_6"
bitfld.long 0x98 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x98 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x98 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x98 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x98 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x98 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x98 0.--3. 1. "FUNC,Selects pin function."
line.long 0x9C "PIO37,Digital I/O control for port 3 pins PIO3_7"
bitfld.long 0x9C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x9C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x9C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x9C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x9C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x9C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x9C 0.--3. 1. "FUNC,Selects pin function."
line.long 0xA0 "PIO38,Digital I/O control for port 3 pins PIO3_8"
bitfld.long 0xA0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xA0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xA0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xA0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xA0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xA0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xA0 0.--3. 1. "FUNC,Selects pin function."
line.long 0xA4 "PIO39,Digital I/O control for port 3 pins PIO3_9"
bitfld.long 0xA4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xA4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xA4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xA4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xA4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xA4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xA4 0.--3. 1. "FUNC,Selects pin function."
line.long 0xA8 "PIO310,Digital I/O control for port 3 pins PIO3_10"
bitfld.long 0xA8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xA8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xA8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xA8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xA8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xA8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xA8 0.--3. 1. "FUNC,Selects pin function."
line.long 0xAC "PIO311,Digital I/O control for port 3 pins PIO3_11"
bitfld.long 0xAC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xAC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xAC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xAC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xAC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xAC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xAC 0.--3. 1. "FUNC,Selects pin function."
line.long 0xB0 "PIO312,Digital I/O control for port 3 pins PIO3_12"
bitfld.long 0xB0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xB0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xB0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xB0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xB0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xB0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xB0 0.--3. 1. "FUNC,Selects pin function."
line.long 0xB4 "PIO313,Digital I/O control for port 3 pins PIO3_13"
bitfld.long 0xB4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xB4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xB4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xB4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xB4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xB4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xB4 0.--3. 1. "FUNC,Selects pin function."
line.long 0xB8 "PIO314,Digital I/O control for port 3 pins PIO3_14"
bitfld.long 0xB8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xB8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xB8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xB8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xB8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xB8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xB8 0.--3. 1. "FUNC,Selects pin function."
line.long 0xBC "PIO315,Digital I/O control for port 3 pins PIO3_15"
bitfld.long 0xBC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xBC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xBC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xBC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xBC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xBC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xBC 0.--3. 1. "FUNC,Selects pin function."
line.long 0xC0 "PIO316,Digital I/O control for port 3 pins PIO3_16"
bitfld.long 0xC0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xC0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xC0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xC0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xC0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xC0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xC0 0.--3. 1. "FUNC,Selects pin function."
line.long 0xC4 "PIO317,Digital I/O control for port 3 pins PIO3_17"
bitfld.long 0xC4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xC4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xC4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xC4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xC4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xC4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xC4 0.--3. 1. "FUNC,Selects pin function."
line.long 0xC8 "PIO318,Digital I/O control for port 3 pins PIO3_18"
bitfld.long 0xC8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xC8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xC8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xC8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xC8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xC8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xC8 0.--3. 1. "FUNC,Selects pin function."
line.long 0xCC "PIO319,Digital I/O control for port 3 pins PIO3_19"
bitfld.long 0xCC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xCC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xCC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xCC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xCC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xCC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xCC 0.--3. 1. "FUNC,Selects pin function."
line.long 0xD0 "PIO320,Digital I/O control for port 3 pins PIO3_20"
bitfld.long 0xD0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xD0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xD0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xD0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xD0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xD0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xD0 0.--3. 1. "FUNC,Selects pin function."
line.long 0xD4 "PIO321,Digital I/O control for port 3 pins PIO3_21"
bitfld.long 0xD4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xD4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xD4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xD4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xD4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xD4 0.--3. 1. "FUNC,Selects pin function."
line.long 0xD8 "PIO322,Digital I/O control for port 3 pins PIO3_22"
bitfld.long 0xD8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xD8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xD8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xD8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xD8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xD8 0.--3. 1. "FUNC,Selects pin function."
line.long 0xDC "PIO323,Digital I/O control for port 3 pins PIO3_23"
bitfld.long 0xDC 11. "I2CFILTER,Configures I2C features for standard mode  fast mode  and Fast Mode Plus operation." "0: Enabled. I2C 50 ns glitch filter enabled.,1: Disabled. I2C 50 ns glitch filter disabled."
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bitfld.long 0xDC 10. "I2CDRIVE,Controls the current sink capability of the pin." "0: Low drive. Output drive sink is 4 mA. This is..,1: High drive. Output drive sink is 20 mA. This is.."
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bitfld.long 0xDC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xDC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xDC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xDC 6. "I2CSLEW,Controls slew rate of I2C pad." "0: I2C mode.,1: GPIO mode."
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hexmask.long.byte 0xDC 0.--3. 1. "FUNC,Selects pin function."
line.long 0xE0 "PIO324,Digital I/O control for port 3 pins PIO3_24"
bitfld.long 0xE0 11. "I2CFILTER,Configures I2C features for standard mode  fast mode  and Fast Mode Plus operation." "0: Enabled. I2C 50 ns glitch filter enabled.,1: Disabled. I2C 50 ns glitch filter disabled."
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bitfld.long 0xE0 10. "I2CDRIVE,Controls the current sink capability of the pin." "0: Low drive. Output drive sink is 4 mA. This is..,1: High drive. Output drive sink is 20 mA. This is.."
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bitfld.long 0xE0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xE0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xE0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xE0 6. "I2CSLEW,Controls slew rate of I2C pad." "0: I2C mode.,1: GPIO mode."
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hexmask.long.byte 0xE0 0.--3. 1. "FUNC,Selects pin function."
line.long 0xE4 "PIO325,Digital I/O control for port 3 pins PIO3_25"
bitfld.long 0xE4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xE4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xE4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xE4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xE4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xE4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xE4 0.--3. 1. "FUNC,Selects pin function."
line.long 0xE8 "PIO326,Digital I/O control for port 3 pins PIO3_26"
bitfld.long 0xE8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xE8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xE8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xE8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xE8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xE8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xE8 0.--3. 1. "FUNC,Selects pin function."
line.long 0xEC "PIO327,Digital I/O control for port 3 pins PIO3_27"
bitfld.long 0xEC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xEC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xEC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xEC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xEC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xEC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xEC 0.--3. 1. "FUNC,Selects pin function."
line.long 0xF0 "PIO328,Digital I/O control for port 3 pins PIO3_28"
bitfld.long 0xF0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xF0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xF0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xF0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xF0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xF0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xF0 0.--3. 1. "FUNC,Selects pin function."
line.long 0xF4 "PIO329,Digital I/O control for port 3 pins PIO3_29"
bitfld.long 0xF4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xF4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xF4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xF4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xF4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xF4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xF4 0.--3. 1. "FUNC,Selects pin function."
line.long 0xF8 "PIO330,Digital I/O control for port 3 pins PIO3_30"
bitfld.long 0xF8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xF8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xF8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xF8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xF8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xF8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xF8 0.--3. 1. "FUNC,Selects pin function."
line.long 0xFC "PIO331,Digital I/O control for port 3 pins PIO3_31"
bitfld.long 0xFC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xFC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xFC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xFC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xFC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xFC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xFC 0.--3. 1. "FUNC,Selects pin function."
line.long 0x100 "PIO40,Digital I/O control for port 4 pins PIO4_0"
bitfld.long 0x100 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x100 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x100 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x100 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x100 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x100 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x100 0.--3. 1. "FUNC,Selects pin function."
line.long 0x104 "PIO41,Digital I/O control for port 4 pins PIO4_1"
bitfld.long 0x104 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x104 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x104 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x104 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x104 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x104 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x104 0.--3. 1. "FUNC,Selects pin function."
line.long 0x108 "PIO42,Digital I/O control for port 4 pins PIO4_2"
bitfld.long 0x108 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x108 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x108 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x108 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x108 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x108 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x108 0.--3. 1. "FUNC,Selects pin function."
line.long 0x10C "PIO43,Digital I/O control for port 4 pins PIO4_3"
bitfld.long 0x10C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x10C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x10C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x10C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x10C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x10C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x10C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x110 "PIO44,Digital I/O control for port 4 pins PIO4_4"
bitfld.long 0x110 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x110 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x110 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x110 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x110 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x110 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x110 0.--3. 1. "FUNC,Selects pin function."
line.long 0x114 "PIO45,Digital I/O control for port 4 pins PIO4_5"
bitfld.long 0x114 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x114 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x114 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x114 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x114 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x114 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x114 0.--3. 1. "FUNC,Selects pin function."
line.long 0x118 "PIO46,Digital I/O control for port 4 pins PIO4_6"
bitfld.long 0x118 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x118 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x118 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x118 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x118 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x118 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x118 0.--3. 1. "FUNC,Selects pin function."
line.long 0x11C "PIO47,Digital I/O control for port 4 pins PIO4_7"
bitfld.long 0x11C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x11C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x11C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x11C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x11C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x11C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x11C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x120 "PIO48,Digital I/O control for port 4 pins PIO4_8"
bitfld.long 0x120 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x120 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x120 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x120 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x120 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x120 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x120 0.--3. 1. "FUNC,Selects pin function."
line.long 0x124 "PIO49,Digital I/O control for port 4 pins PIO4_9"
bitfld.long 0x124 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x124 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x124 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x124 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x124 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x124 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x124 0.--3. 1. "FUNC,Selects pin function."
line.long 0x128 "PIO410,Digital I/O control for port 4 pins PIO4_10"
bitfld.long 0x128 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x128 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x128 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x128 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x128 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x128 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x128 0.--3. 1. "FUNC,Selects pin function."
line.long 0x12C "PIO411,Digital I/O control for port 4 pins PIO4_11"
bitfld.long 0x12C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x12C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x12C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x12C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x12C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x12C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x12C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x130 "PIO412,Digital I/O control for port 4 pins PIO4_12"
bitfld.long 0x130 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x130 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x130 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x130 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x130 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x130 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x130 0.--3. 1. "FUNC,Selects pin function."
line.long 0x134 "PIO413,Digital I/O control for port 4 pins PIO4_13"
bitfld.long 0x134 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x134 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x134 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x134 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x134 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x134 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x134 0.--3. 1. "FUNC,Selects pin function."
line.long 0x138 "PIO414,Digital I/O control for port 4 pins PIO4_14"
bitfld.long 0x138 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x138 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x138 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x138 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x138 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x138 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x138 0.--3. 1. "FUNC,Selects pin function."
line.long 0x13C "PIO415,Digital I/O control for port 4 pins PIO4_15"
bitfld.long 0x13C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x13C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x13C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x13C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x13C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x13C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x13C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x140 "PIO416,Digital I/O control for port 4 pins PIO4_16"
bitfld.long 0x140 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x140 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x140 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x140 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x140 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x140 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x140 0.--3. 1. "FUNC,Selects pin function."
line.long 0x144 "PIO417,Digital I/O control for port 4 pins PIO4_17"
bitfld.long 0x144 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x144 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x144 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x144 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x144 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x144 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x144 0.--3. 1. "FUNC,Selects pin function."
line.long 0x148 "PIO418,Digital I/O control for port 4 pins PIO4_18"
bitfld.long 0x148 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x148 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x148 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x148 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x148 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x148 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x148 0.--3. 1. "FUNC,Selects pin function."
line.long 0x14C "PIO419,Digital I/O control for port 4 pins PIO4_19"
bitfld.long 0x14C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x14C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x14C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x14C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x14C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x14C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x14C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x150 "PIO420,Digital I/O control for port 4 pins PIO4_20"
bitfld.long 0x150 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x150 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x150 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x150 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x150 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x150 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x150 0.--3. 1. "FUNC,Selects pin function."
line.long 0x154 "PIO421,Digital I/O control for port 4 pins PIO4_21"
bitfld.long 0x154 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x154 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x154 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x154 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x154 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x154 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x154 0.--3. 1. "FUNC,Selects pin function."
line.long 0x158 "PIO422,Digital I/O control for port 4 pins PIO4_22"
bitfld.long 0x158 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x158 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x158 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x158 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x158 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x158 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x158 0.--3. 1. "FUNC,Selects pin function."
line.long 0x15C "PIO423,Digital I/O control for port 4 pins PIO4_23"
bitfld.long 0x15C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x15C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x15C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x15C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x15C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x15C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x15C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x160 "PIO424,Digital I/O control for port 4 pins PIO4_24"
bitfld.long 0x160 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x160 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x160 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x160 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x160 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x160 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x160 0.--3. 1. "FUNC,Selects pin function."
line.long 0x164 "PIO425,Digital I/O control for port 4 pins PIO4_25"
bitfld.long 0x164 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x164 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x164 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x164 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x164 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x164 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x164 0.--3. 1. "FUNC,Selects pin function."
line.long 0x168 "PIO426,Digital I/O control for port 4 pins PIO4_26"
bitfld.long 0x168 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x168 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x168 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x168 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x168 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x168 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x168 0.--3. 1. "FUNC,Selects pin function."
line.long 0x16C "PIO427,Digital I/O control for port 4 pins PIO4_27"
bitfld.long 0x16C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x16C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x16C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x16C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x16C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x16C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x16C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x170 "PIO428,Digital I/O control for port 4 pins PIO4_28"
bitfld.long 0x170 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x170 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x170 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x170 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x170 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x170 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x170 0.--3. 1. "FUNC,Selects pin function."
line.long 0x174 "PIO429,Digital I/O control for port 4 pins PIO4_29"
bitfld.long 0x174 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x174 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x174 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x174 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x174 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x174 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x174 0.--3. 1. "FUNC,Selects pin function."
line.long 0x178 "PIO430,Digital I/O control for port 4 pins PIO4_30"
bitfld.long 0x178 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x178 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x178 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x178 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x178 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x178 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x178 0.--3. 1. "FUNC,Selects pin function."
line.long 0x17C "PIO431,Digital I/O control for port 4 pins PIO4_31"
bitfld.long 0x17C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x17C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x17C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x17C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x17C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x17C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x17C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x180 "PIO50,Digital I/O control for port 5 pins PIO5_0"
bitfld.long 0x180 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x180 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x180 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x180 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x180 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x180 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x180 0.--3. 1. "FUNC,Selects pin function."
line.long 0x184 "PIO51,Digital I/O control for port 5 pins PIO5_1"
bitfld.long 0x184 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x184 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x184 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x184 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x184 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x184 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x184 0.--3. 1. "FUNC,Selects pin function."
line.long 0x188 "PIO52,Digital I/O control for port 5 pins PIO5_2"
bitfld.long 0x188 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x188 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x188 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x188 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x188 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x188 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x188 0.--3. 1. "FUNC,Selects pin function."
line.long 0x18C "PIO53,Digital I/O control for port 5 pins PIO5_3"
bitfld.long 0x18C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x18C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x18C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x18C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x18C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x18C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x18C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x190 "PIO54,Digital I/O control for port 5 pins PIO5_4"
bitfld.long 0x190 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x190 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x190 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x190 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x190 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x190 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x190 0.--3. 1. "FUNC,Selects pin function."
line.long 0x194 "PIO55,Digital I/O control for port 5 pins PIO5_5"
bitfld.long 0x194 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x194 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x194 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x194 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x194 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x194 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x194 0.--3. 1. "FUNC,Selects pin function."
line.long 0x198 "PIO56,Digital I/O control for port 5 pins PIO5_6"
bitfld.long 0x198 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x198 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x198 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x198 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x198 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x198 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x198 0.--3. 1. "FUNC,Selects pin function."
line.long 0x19C "PIO57,Digital I/O control for port 5 pins PIO5_7"
bitfld.long 0x19C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x19C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x19C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x19C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x19C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x19C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x19C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1A0 "PIO58,Digital I/O control for port 5 pins PIO5_8"
bitfld.long 0x1A0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1A0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1A0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1A0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1A0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1A0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1A0 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1A4 "PIO59,Digital I/O control for port 5 pins PIO5_9"
bitfld.long 0x1A4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1A4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1A4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1A4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1A4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1A4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1A4 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1A8 "PIO510,Digital I/O control for port 5 pins PIO5_10"
bitfld.long 0x1A8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1A8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1A8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1A8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1A8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1A8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1A8 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1AC "PIO511,Digital I/O control for port 5 pins PIO5_11"
bitfld.long 0x1AC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1AC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1AC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1AC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1AC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1AC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1AC 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1B0 "PIO512,Digital I/O control for port 5 pins PIO5_12"
bitfld.long 0x1B0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1B0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1B0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1B0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1B0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1B0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1B0 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1B4 "PIO513,Digital I/O control for port 5 pins PIO5_13"
bitfld.long 0x1B4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1B4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1B4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1B4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1B4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1B4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1B4 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1B8 "PIO514,Digital I/O control for port 5 pins PIO5_14"
bitfld.long 0x1B8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1B8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1B8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1B8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1B8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1B8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1B8 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1BC "PIO515,Digital I/O control for port 5 pins PIO5_15"
bitfld.long 0x1BC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1BC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1BC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1BC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1BC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1BC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1BC 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1C0 "PIO516,Digital I/O control for port 5 pins PIO5_16"
bitfld.long 0x1C0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1C0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1C0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1C0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1C0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1C0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1C0 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1C4 "PIO517,Digital I/O control for port 5 pins PIO5_17"
bitfld.long 0x1C4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1C4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1C4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1C4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1C4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1C4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1C4 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1C8 "PIO518,Digital I/O control for port 5 pins PIO5_18"
bitfld.long 0x1C8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1C8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1C8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1C8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1C8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1C8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1C8 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1CC "PIO519,Digital I/O control for port 5 pins PIO5_19"
bitfld.long 0x1CC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1CC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1CC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1CC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1CC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1CC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1CC 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1D0 "PIO520,Digital I/O control for port 5 pins PIO5_20"
bitfld.long 0x1D0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1D0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1D0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1D0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1D0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1D0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1D0 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1D4 "PIO521,Digital I/O control for port 5 pins PIO5_21"
bitfld.long 0x1D4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1D4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1D4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1D4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1D4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1D4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1D4 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1D8 "PIO522,Digital I/O control for port 5 pins PIO5_22"
bitfld.long 0x1D8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1D8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1D8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1D8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1D8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1D8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1D8 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1DC "PIO523,Digital I/O control for port 5 pins PIO5_23"
bitfld.long 0x1DC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1DC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1DC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1DC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1DC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1DC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1DC 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1E0 "PIO524,Digital I/O control for port 5 pins PIO5_24"
bitfld.long 0x1E0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1E0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1E0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1E0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1E0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1E0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1E0 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1E4 "PIO525,Digital I/O control for port 5 pins PIO5_25"
bitfld.long 0x1E4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1E4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1E4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1E4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1E4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1E4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1E4 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1E8 "PIO526,Digital I/O control for port 5 pins PIO5_26"
bitfld.long 0x1E8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1E8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1E8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1E8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1E8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1E8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1E8 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1EC "PIO527,Digital I/O control for port 5 pins PIO5_27"
bitfld.long 0x1EC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1EC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1EC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1EC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1EC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1EC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1EC 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1F0 "PIO528,Digital I/O control for port 5 pins PIO5_28"
bitfld.long 0x1F0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1F0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1F0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1F0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1F0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1F0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1F0 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1F4 "PIO529,Digital I/O control for port 5 pins PIO5_29"
bitfld.long 0x1F4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1F4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1F4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1F4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1F4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1F4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1F4 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1F8 "PIO530,Digital I/O control for port 5 pins PIO5_30"
bitfld.long 0x1F8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1F8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1F8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1F8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1F8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1F8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1F8 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1FC "PIO531,Digital I/O control for port 5 pins PIO5_31"
bitfld.long 0x1FC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1FC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1FC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1FC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1FC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1FC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1FC 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54607*"))
group.long 0x100++0x1FF
line.long 0x0 "PIO20,Digital I/O control for port 2 pins PIO2_0"
bitfld.long 0x0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x0 0.--3. 1. "FUNC,Selects pin function."
line.long 0x4 "PIO21,Digital I/O control for port 2 pins PIO2_1"
bitfld.long 0x4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x4 0.--3. 1. "FUNC,Selects pin function."
line.long 0x8 "PIO22,Digital I/O control for port 2 pins PIO2_2"
bitfld.long 0x8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x8 0.--3. 1. "FUNC,Selects pin function."
line.long 0xC "PIO23,Digital I/O control for port 2 pins PIO2_3"
bitfld.long 0xC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xC 0.--3. 1. "FUNC,Selects pin function."
line.long 0x10 "PIO24,Digital I/O control for port 2 pins PIO2_4"
bitfld.long 0x10 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x10 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x10 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x10 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x10 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x10 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x10 0.--3. 1. "FUNC,Selects pin function."
line.long 0x14 "PIO25,Digital I/O control for port 2 pins PIO2_5"
bitfld.long 0x14 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x14 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x14 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x14 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x14 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x14 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x14 0.--3. 1. "FUNC,Selects pin function."
line.long 0x18 "PIO26,Digital I/O control for port 2 pins PIO2_6"
bitfld.long 0x18 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x18 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x18 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x18 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x18 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x18 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x18 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1C "PIO27,Digital I/O control for port 2 pins PIO2_7"
bitfld.long 0x1C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x1C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x1C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x1C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x1C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x1C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x1C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x20 "PIO28,Digital I/O control for port 2 pins PIO2_8"
bitfld.long 0x20 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x20 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x20 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x20 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x20 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x20 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x20 0.--3. 1. "FUNC,Selects pin function."
line.long 0x24 "PIO29,Digital I/O control for port 2 pins PIO2_9"
bitfld.long 0x24 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x24 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x24 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x24 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x24 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x24 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x24 0.--3. 1. "FUNC,Selects pin function."
line.long 0x28 "PIO210,Digital I/O control for port 2 pins PIO2_10"
bitfld.long 0x28 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x28 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x28 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x28 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x28 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x28 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x28 0.--3. 1. "FUNC,Selects pin function."
line.long 0x2C "PIO211,Digital I/O control for port 2 pins PIO2_11"
bitfld.long 0x2C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x2C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x2C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x2C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x2C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x2C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x2C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x30 "PIO212,Digital I/O control for port 2 pins PIO2_12"
bitfld.long 0x30 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x30 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x30 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x30 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x30 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x30 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x30 0.--3. 1. "FUNC,Selects pin function."
line.long 0x34 "PIO213,Digital I/O control for port 2 pins PIO2_13"
bitfld.long 0x34 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x34 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x34 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x34 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x34 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x34 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x34 0.--3. 1. "FUNC,Selects pin function."
line.long 0x38 "PIO214,Digital I/O control for port 2 pins PIO2_14"
bitfld.long 0x38 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x38 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x38 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x38 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x38 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x38 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x38 0.--3. 1. "FUNC,Selects pin function."
line.long 0x3C "PIO215,Digital I/O control for port 2 pins PIO2_15"
bitfld.long 0x3C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x3C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x3C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x3C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x3C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x3C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x3C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x40 "PIO216,Digital I/O control for port 2 pins PIO2_16"
bitfld.long 0x40 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x40 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x40 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x40 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x40 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x40 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x40 0.--3. 1. "FUNC,Selects pin function."
line.long 0x44 "PIO217,Digital I/O control for port 2 pins PIO2_17"
bitfld.long 0x44 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x44 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x44 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x44 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x44 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x44 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x44 0.--3. 1. "FUNC,Selects pin function."
line.long 0x48 "PIO218,Digital I/O control for port 2 pins PIO2_18"
bitfld.long 0x48 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x48 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x48 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x48 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x48 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x48 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x48 0.--3. 1. "FUNC,Selects pin function."
line.long 0x4C "PIO219,Digital I/O control for port 2 pins PIO2_19"
bitfld.long 0x4C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x4C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x4C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x4C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x4C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x4C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x4C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x50 "PIO220,Digital I/O control for port 2 pins PIO2_20"
bitfld.long 0x50 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x50 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x50 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x50 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x50 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x50 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x50 0.--3. 1. "FUNC,Selects pin function."
line.long 0x54 "PIO221,Digital I/O control for port 2 pins PIO2_21"
bitfld.long 0x54 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x54 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x54 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x54 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x54 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x54 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x54 0.--3. 1. "FUNC,Selects pin function."
line.long 0x58 "PIO222,Digital I/O control for port 2 pins PIO2_22"
bitfld.long 0x58 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x58 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x58 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x58 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x58 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x58 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x58 0.--3. 1. "FUNC,Selects pin function."
line.long 0x5C "PIO223,Digital I/O control for port 2 pins PIO2_23"
bitfld.long 0x5C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x5C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x5C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x5C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x5C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x5C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x5C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x60 "PIO224,Digital I/O control for port 2 pins PIO2_24"
bitfld.long 0x60 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x60 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x60 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x60 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x60 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x60 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x60 0.--3. 1. "FUNC,Selects pin function."
line.long 0x64 "PIO225,Digital I/O control for port 2 pins PIO2_25"
bitfld.long 0x64 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x64 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x64 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x64 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x64 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x64 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x64 0.--3. 1. "FUNC,Selects pin function."
line.long 0x68 "PIO226,Digital I/O control for port 2 pins PIO2_26"
bitfld.long 0x68 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x68 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x68 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x68 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x68 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x68 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x68 0.--3. 1. "FUNC,Selects pin function."
line.long 0x6C "PIO227,Digital I/O control for port 2 pins PIO2_27"
bitfld.long 0x6C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x6C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x6C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x6C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x6C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x6C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x6C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x70 "PIO228,Digital I/O control for port 2 pins PIO2_28"
bitfld.long 0x70 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x70 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x70 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x70 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x70 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x70 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x70 0.--3. 1. "FUNC,Selects pin function."
line.long 0x74 "PIO229,Digital I/O control for port 2 pins PIO2_29"
bitfld.long 0x74 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x74 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x74 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x74 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x74 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x74 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x74 0.--3. 1. "FUNC,Selects pin function."
line.long 0x78 "PIO230,Digital I/O control for port 2 pins PIO2_30"
bitfld.long 0x78 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x78 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x78 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x78 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x78 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x78 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x78 0.--3. 1. "FUNC,Selects pin function."
line.long 0x7C "PIO231,Digital I/O control for port 2 pins PIO2_31"
bitfld.long 0x7C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x7C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x7C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x7C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x7C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x7C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x7C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x80 "PIO30,Digital I/O control for port 3 pins PIO3_0"
bitfld.long 0x80 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x80 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x80 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x80 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x80 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x80 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x80 0.--3. 1. "FUNC,Selects pin function."
line.long 0x84 "PIO31,Digital I/O control for port 3 pins PIO3_1"
bitfld.long 0x84 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x84 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x84 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x84 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x84 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x84 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x84 0.--3. 1. "FUNC,Selects pin function."
line.long 0x88 "PIO32,Digital I/O control for port 3 pins PIO3_2"
bitfld.long 0x88 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x88 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x88 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x88 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x88 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x88 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x88 0.--3. 1. "FUNC,Selects pin function."
line.long 0x8C "PIO33,Digital I/O control for port 3 pins PIO3_3"
bitfld.long 0x8C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x8C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x8C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x8C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x8C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x8C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x8C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x90 "PIO34,Digital I/O control for port 3 pins PIO3_4"
bitfld.long 0x90 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x90 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x90 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x90 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x90 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x90 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x90 0.--3. 1. "FUNC,Selects pin function."
line.long 0x94 "PIO35,Digital I/O control for port 3 pins PIO3_5"
bitfld.long 0x94 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x94 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x94 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x94 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x94 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x94 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x94 0.--3. 1. "FUNC,Selects pin function."
line.long 0x98 "PIO36,Digital I/O control for port 3 pins PIO3_6"
bitfld.long 0x98 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x98 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x98 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x98 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x98 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x98 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x98 0.--3. 1. "FUNC,Selects pin function."
line.long 0x9C "PIO37,Digital I/O control for port 3 pins PIO3_7"
bitfld.long 0x9C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x9C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x9C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x9C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x9C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x9C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x9C 0.--3. 1. "FUNC,Selects pin function."
line.long 0xA0 "PIO38,Digital I/O control for port 3 pins PIO3_8"
bitfld.long 0xA0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xA0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xA0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xA0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xA0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xA0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xA0 0.--3. 1. "FUNC,Selects pin function."
line.long 0xA4 "PIO39,Digital I/O control for port 3 pins PIO3_9"
bitfld.long 0xA4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xA4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xA4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xA4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xA4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xA4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xA4 0.--3. 1. "FUNC,Selects pin function."
line.long 0xA8 "PIO310,Digital I/O control for port 3 pins PIO3_10"
bitfld.long 0xA8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xA8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xA8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xA8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xA8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xA8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xA8 0.--3. 1. "FUNC,Selects pin function."
line.long 0xAC "PIO311,Digital I/O control for port 3 pins PIO3_11"
bitfld.long 0xAC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xAC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xAC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xAC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xAC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xAC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xAC 0.--3. 1. "FUNC,Selects pin function."
line.long 0xB0 "PIO312,Digital I/O control for port 3 pins PIO3_12"
bitfld.long 0xB0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xB0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xB0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xB0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xB0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xB0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xB0 0.--3. 1. "FUNC,Selects pin function."
line.long 0xB4 "PIO313,Digital I/O control for port 3 pins PIO3_13"
bitfld.long 0xB4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xB4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xB4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xB4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xB4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xB4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xB4 0.--3. 1. "FUNC,Selects pin function."
line.long 0xB8 "PIO314,Digital I/O control for port 3 pins PIO3_14"
bitfld.long 0xB8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xB8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xB8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xB8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xB8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xB8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xB8 0.--3. 1. "FUNC,Selects pin function."
line.long 0xBC "PIO315,Digital I/O control for port 3 pins PIO3_15"
bitfld.long 0xBC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xBC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xBC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xBC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xBC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xBC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xBC 0.--3. 1. "FUNC,Selects pin function."
line.long 0xC0 "PIO316,Digital I/O control for port 3 pins PIO3_16"
bitfld.long 0xC0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xC0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xC0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xC0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xC0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xC0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xC0 0.--3. 1. "FUNC,Selects pin function."
line.long 0xC4 "PIO317,Digital I/O control for port 3 pins PIO3_17"
bitfld.long 0xC4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xC4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xC4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xC4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xC4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xC4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xC4 0.--3. 1. "FUNC,Selects pin function."
line.long 0xC8 "PIO318,Digital I/O control for port 3 pins PIO3_18"
bitfld.long 0xC8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xC8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xC8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xC8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xC8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xC8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xC8 0.--3. 1. "FUNC,Selects pin function."
line.long 0xCC "PIO319,Digital I/O control for port 3 pins PIO3_19"
bitfld.long 0xCC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xCC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xCC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xCC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xCC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xCC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xCC 0.--3. 1. "FUNC,Selects pin function."
line.long 0xD0 "PIO320,Digital I/O control for port 3 pins PIO3_20"
bitfld.long 0xD0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xD0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xD0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xD0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xD0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xD0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xD0 0.--3. 1. "FUNC,Selects pin function."
line.long 0xD4 "PIO321,Digital I/O control for port 3 pins PIO3_21"
bitfld.long 0xD4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xD4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xD4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xD4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xD4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xD4 0.--3. 1. "FUNC,Selects pin function."
line.long 0xD8 "PIO322,Digital I/O control for port 3 pins PIO3_22"
bitfld.long 0xD8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xD8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xD8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xD8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xD8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xD8 0.--3. 1. "FUNC,Selects pin function."
line.long 0xDC "PIO323,Digital I/O control for port 3 pins PIO3_23"
bitfld.long 0xDC 11. "I2CFILTER,Configures I2C features for standard mode  fast mode  and Fast Mode Plus operation." "0: Enabled. I2C 50 ns glitch filter enabled.,1: Disabled. I2C 50 ns glitch filter disabled."
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bitfld.long 0xDC 10. "I2CDRIVE,Controls the current sink capability of the pin." "0: Low drive. Output drive sink is 4 mA. This is..,1: High drive. Output drive sink is 20 mA. This is.."
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bitfld.long 0xDC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xDC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xDC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xDC 6. "I2CSLEW,Controls slew rate of I2C pad." "0: I2C mode.,1: GPIO mode."
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hexmask.long.byte 0xDC 0.--3. 1. "FUNC,Selects pin function."
line.long 0xE0 "PIO324,Digital I/O control for port 3 pins PIO3_24"
bitfld.long 0xE0 11. "I2CFILTER,Configures I2C features for standard mode  fast mode  and Fast Mode Plus operation." "0: Enabled. I2C 50 ns glitch filter enabled.,1: Disabled. I2C 50 ns glitch filter disabled."
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bitfld.long 0xE0 10. "I2CDRIVE,Controls the current sink capability of the pin." "0: Low drive. Output drive sink is 4 mA. This is..,1: High drive. Output drive sink is 20 mA. This is.."
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bitfld.long 0xE0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xE0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xE0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xE0 6. "I2CSLEW,Controls slew rate of I2C pad." "0: I2C mode.,1: GPIO mode."
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hexmask.long.byte 0xE0 0.--3. 1. "FUNC,Selects pin function."
line.long 0xE4 "PIO325,Digital I/O control for port 3 pins PIO3_25"
bitfld.long 0xE4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xE4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xE4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xE4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xE4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xE4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xE4 0.--3. 1. "FUNC,Selects pin function."
line.long 0xE8 "PIO326,Digital I/O control for port 3 pins PIO3_26"
bitfld.long 0xE8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xE8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xE8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xE8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xE8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xE8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xE8 0.--3. 1. "FUNC,Selects pin function."
line.long 0xEC "PIO327,Digital I/O control for port 3 pins PIO3_27"
bitfld.long 0xEC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xEC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xEC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xEC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xEC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xEC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xEC 0.--3. 1. "FUNC,Selects pin function."
line.long 0xF0 "PIO328,Digital I/O control for port 3 pins PIO3_28"
bitfld.long 0xF0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xF0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xF0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xF0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xF0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xF0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xF0 0.--3. 1. "FUNC,Selects pin function."
line.long 0xF4 "PIO329,Digital I/O control for port 3 pins PIO3_29"
bitfld.long 0xF4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xF4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xF4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xF4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xF4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xF4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xF4 0.--3. 1. "FUNC,Selects pin function."
line.long 0xF8 "PIO330,Digital I/O control for port 3 pins PIO3_30"
bitfld.long 0xF8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xF8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xF8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xF8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xF8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xF8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xF8 0.--3. 1. "FUNC,Selects pin function."
line.long 0xFC "PIO331,Digital I/O control for port 3 pins PIO3_31"
bitfld.long 0xFC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xFC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xFC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xFC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xFC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xFC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xFC 0.--3. 1. "FUNC,Selects pin function."
line.long 0x100 "PIO40,Digital I/O control for port 4 pins PIO4_0"
bitfld.long 0x100 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x100 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x100 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x100 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x100 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x100 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x100 0.--3. 1. "FUNC,Selects pin function."
line.long 0x104 "PIO41,Digital I/O control for port 4 pins PIO4_1"
bitfld.long 0x104 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x104 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x104 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x104 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x104 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x104 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x104 0.--3. 1. "FUNC,Selects pin function."
line.long 0x108 "PIO42,Digital I/O control for port 4 pins PIO4_2"
bitfld.long 0x108 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x108 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x108 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x108 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x108 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x108 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x108 0.--3. 1. "FUNC,Selects pin function."
line.long 0x10C "PIO43,Digital I/O control for port 4 pins PIO4_3"
bitfld.long 0x10C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x10C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x10C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x10C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x10C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x10C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x10C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x110 "PIO44,Digital I/O control for port 4 pins PIO4_4"
bitfld.long 0x110 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x110 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x110 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x110 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x110 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x110 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x110 0.--3. 1. "FUNC,Selects pin function."
line.long 0x114 "PIO45,Digital I/O control for port 4 pins PIO4_5"
bitfld.long 0x114 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x114 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x114 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x114 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x114 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x114 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x114 0.--3. 1. "FUNC,Selects pin function."
line.long 0x118 "PIO46,Digital I/O control for port 4 pins PIO4_6"
bitfld.long 0x118 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x118 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x118 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x118 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x118 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x118 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x118 0.--3. 1. "FUNC,Selects pin function."
line.long 0x11C "PIO47,Digital I/O control for port 4 pins PIO4_7"
bitfld.long 0x11C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x11C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x11C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x11C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x11C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x11C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x11C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x120 "PIO48,Digital I/O control for port 4 pins PIO4_8"
bitfld.long 0x120 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x120 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x120 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x120 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x120 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x120 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x120 0.--3. 1. "FUNC,Selects pin function."
line.long 0x124 "PIO49,Digital I/O control for port 4 pins PIO4_9"
bitfld.long 0x124 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x124 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x124 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x124 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x124 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x124 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x124 0.--3. 1. "FUNC,Selects pin function."
line.long 0x128 "PIO410,Digital I/O control for port 4 pins PIO4_10"
bitfld.long 0x128 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x128 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x128 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x128 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x128 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x128 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x128 0.--3. 1. "FUNC,Selects pin function."
line.long 0x12C "PIO411,Digital I/O control for port 4 pins PIO4_11"
bitfld.long 0x12C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x12C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x12C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x12C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x12C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x12C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x12C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x130 "PIO412,Digital I/O control for port 4 pins PIO4_12"
bitfld.long 0x130 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x130 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x130 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x130 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x130 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x130 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x130 0.--3. 1. "FUNC,Selects pin function."
line.long 0x134 "PIO413,Digital I/O control for port 4 pins PIO4_13"
bitfld.long 0x134 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x134 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x134 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x134 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x134 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x134 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x134 0.--3. 1. "FUNC,Selects pin function."
line.long 0x138 "PIO414,Digital I/O control for port 4 pins PIO4_14"
bitfld.long 0x138 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x138 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x138 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x138 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x138 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x138 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x138 0.--3. 1. "FUNC,Selects pin function."
line.long 0x13C "PIO415,Digital I/O control for port 4 pins PIO4_15"
bitfld.long 0x13C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x13C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x13C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x13C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x13C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x13C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x13C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x140 "PIO416,Digital I/O control for port 4 pins PIO4_16"
bitfld.long 0x140 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x140 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x140 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x140 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x140 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x140 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x140 0.--3. 1. "FUNC,Selects pin function."
line.long 0x144 "PIO417,Digital I/O control for port 4 pins PIO4_17"
bitfld.long 0x144 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x144 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x144 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x144 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x144 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x144 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x144 0.--3. 1. "FUNC,Selects pin function."
line.long 0x148 "PIO418,Digital I/O control for port 4 pins PIO4_18"
bitfld.long 0x148 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x148 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x148 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x148 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x148 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x148 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x148 0.--3. 1. "FUNC,Selects pin function."
line.long 0x14C "PIO419,Digital I/O control for port 4 pins PIO4_19"
bitfld.long 0x14C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x14C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x14C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x14C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x14C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x14C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x14C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x150 "PIO420,Digital I/O control for port 4 pins PIO4_20"
bitfld.long 0x150 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x150 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x150 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x150 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x150 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x150 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x150 0.--3. 1. "FUNC,Selects pin function."
line.long 0x154 "PIO421,Digital I/O control for port 4 pins PIO4_21"
bitfld.long 0x154 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x154 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x154 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x154 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x154 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x154 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x154 0.--3. 1. "FUNC,Selects pin function."
line.long 0x158 "PIO422,Digital I/O control for port 4 pins PIO4_22"
bitfld.long 0x158 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x158 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x158 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x158 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x158 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x158 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x158 0.--3. 1. "FUNC,Selects pin function."
line.long 0x15C "PIO423,Digital I/O control for port 4 pins PIO4_23"
bitfld.long 0x15C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x15C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x15C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x15C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x15C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x15C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x15C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x160 "PIO424,Digital I/O control for port 4 pins PIO4_24"
bitfld.long 0x160 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x160 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x160 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x160 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x160 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x160 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x160 0.--3. 1. "FUNC,Selects pin function."
line.long 0x164 "PIO425,Digital I/O control for port 4 pins PIO4_25"
bitfld.long 0x164 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x164 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x164 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x164 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x164 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x164 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x164 0.--3. 1. "FUNC,Selects pin function."
line.long 0x168 "PIO426,Digital I/O control for port 4 pins PIO4_26"
bitfld.long 0x168 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x168 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x168 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x168 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x168 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x168 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x168 0.--3. 1. "FUNC,Selects pin function."
line.long 0x16C "PIO427,Digital I/O control for port 4 pins PIO4_27"
bitfld.long 0x16C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x16C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x16C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x16C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x16C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x16C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x16C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x170 "PIO428,Digital I/O control for port 4 pins PIO4_28"
bitfld.long 0x170 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x170 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x170 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x170 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x170 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x170 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x170 0.--3. 1. "FUNC,Selects pin function."
line.long 0x174 "PIO429,Digital I/O control for port 4 pins PIO4_29"
bitfld.long 0x174 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x174 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x174 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x174 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x174 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x174 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x174 0.--3. 1. "FUNC,Selects pin function."
line.long 0x178 "PIO430,Digital I/O control for port 4 pins PIO4_30"
bitfld.long 0x178 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x178 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x178 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x178 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x178 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x178 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x178 0.--3. 1. "FUNC,Selects pin function."
line.long 0x17C "PIO431,Digital I/O control for port 4 pins PIO4_31"
bitfld.long 0x17C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x17C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x17C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x17C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x17C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x17C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x17C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x180 "PIO50,Digital I/O control for port 5 pins PIO5_0"
bitfld.long 0x180 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x180 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x180 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x180 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x180 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x180 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x180 0.--3. 1. "FUNC,Selects pin function."
line.long 0x184 "PIO51,Digital I/O control for port 5 pins PIO5_1"
bitfld.long 0x184 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x184 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x184 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x184 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x184 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x184 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x184 0.--3. 1. "FUNC,Selects pin function."
line.long 0x188 "PIO52,Digital I/O control for port 5 pins PIO5_2"
bitfld.long 0x188 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x188 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x188 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x188 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x188 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x188 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x188 0.--3. 1. "FUNC,Selects pin function."
line.long 0x18C "PIO53,Digital I/O control for port 5 pins PIO5_3"
bitfld.long 0x18C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x18C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x18C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x18C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x18C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x18C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x18C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x190 "PIO54,Digital I/O control for port 5 pins PIO5_4"
bitfld.long 0x190 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x190 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x190 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x190 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x190 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x190 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x190 0.--3. 1. "FUNC,Selects pin function."
line.long 0x194 "PIO55,Digital I/O control for port 5 pins PIO5_5"
bitfld.long 0x194 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x194 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x194 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x194 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x194 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x194 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x194 0.--3. 1. "FUNC,Selects pin function."
line.long 0x198 "PIO56,Digital I/O control for port 5 pins PIO5_6"
bitfld.long 0x198 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x198 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x198 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x198 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x198 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x198 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x198 0.--3. 1. "FUNC,Selects pin function."
line.long 0x19C "PIO57,Digital I/O control for port 5 pins PIO5_7"
bitfld.long 0x19C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x19C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x19C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x19C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x19C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x19C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x19C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1A0 "PIO58,Digital I/O control for port 5 pins PIO5_8"
bitfld.long 0x1A0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1A0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1A0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1A0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1A0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1A0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1A0 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1A4 "PIO59,Digital I/O control for port 5 pins PIO5_9"
bitfld.long 0x1A4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1A4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1A4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1A4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1A4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1A4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1A4 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1A8 "PIO510,Digital I/O control for port 5 pins PIO5_10"
bitfld.long 0x1A8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1A8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1A8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1A8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1A8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1A8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1A8 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1AC "PIO511,Digital I/O control for port 5 pins PIO5_11"
bitfld.long 0x1AC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1AC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1AC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1AC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1AC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1AC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1AC 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1B0 "PIO512,Digital I/O control for port 5 pins PIO5_12"
bitfld.long 0x1B0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1B0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1B0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1B0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1B0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1B0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1B0 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1B4 "PIO513,Digital I/O control for port 5 pins PIO5_13"
bitfld.long 0x1B4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1B4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1B4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1B4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1B4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1B4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1B4 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1B8 "PIO514,Digital I/O control for port 5 pins PIO5_14"
bitfld.long 0x1B8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1B8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1B8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1B8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1B8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1B8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1B8 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1BC "PIO515,Digital I/O control for port 5 pins PIO5_15"
bitfld.long 0x1BC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1BC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1BC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1BC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1BC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1BC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1BC 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1C0 "PIO516,Digital I/O control for port 5 pins PIO5_16"
bitfld.long 0x1C0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1C0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1C0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1C0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1C0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1C0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1C0 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1C4 "PIO517,Digital I/O control for port 5 pins PIO5_17"
bitfld.long 0x1C4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1C4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1C4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1C4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1C4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1C4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1C4 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1C8 "PIO518,Digital I/O control for port 5 pins PIO5_18"
bitfld.long 0x1C8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1C8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1C8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1C8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1C8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1C8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1C8 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1CC "PIO519,Digital I/O control for port 5 pins PIO5_19"
bitfld.long 0x1CC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1CC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1CC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1CC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1CC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1CC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1CC 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1D0 "PIO520,Digital I/O control for port 5 pins PIO5_20"
bitfld.long 0x1D0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1D0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1D0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1D0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1D0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1D0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1D0 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1D4 "PIO521,Digital I/O control for port 5 pins PIO5_21"
bitfld.long 0x1D4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1D4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1D4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1D4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1D4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1D4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1D4 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1D8 "PIO522,Digital I/O control for port 5 pins PIO5_22"
bitfld.long 0x1D8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1D8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1D8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1D8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1D8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1D8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1D8 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1DC "PIO523,Digital I/O control for port 5 pins PIO5_23"
bitfld.long 0x1DC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1DC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1DC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1DC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1DC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1DC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1DC 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1E0 "PIO524,Digital I/O control for port 5 pins PIO5_24"
bitfld.long 0x1E0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1E0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1E0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1E0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1E0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1E0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1E0 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1E4 "PIO525,Digital I/O control for port 5 pins PIO5_25"
bitfld.long 0x1E4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1E4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1E4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1E4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1E4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1E4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1E4 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1E8 "PIO526,Digital I/O control for port 5 pins PIO5_26"
bitfld.long 0x1E8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1E8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1E8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1E8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1E8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1E8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1E8 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1EC "PIO527,Digital I/O control for port 5 pins PIO5_27"
bitfld.long 0x1EC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1EC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1EC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1EC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1EC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1EC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1EC 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1F0 "PIO528,Digital I/O control for port 5 pins PIO5_28"
bitfld.long 0x1F0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1F0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1F0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1F0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1F0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1F0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1F0 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1F4 "PIO529,Digital I/O control for port 5 pins PIO5_29"
bitfld.long 0x1F4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1F4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1F4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1F4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1F4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1F4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1F4 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1F8 "PIO530,Digital I/O control for port 5 pins PIO5_30"
bitfld.long 0x1F8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1F8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1F8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1F8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1F8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1F8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1F8 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1FC "PIO531,Digital I/O control for port 5 pins PIO5_31"
bitfld.long 0x1FC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1FC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1FC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1FC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1FC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1FC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1FC 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54608*"))
group.long 0x100++0x1FF
line.long 0x0 "PIO20,Digital I/O control for port 2 pins PIO2_0"
bitfld.long 0x0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x0 0.--3. 1. "FUNC,Selects pin function."
line.long 0x4 "PIO21,Digital I/O control for port 2 pins PIO2_1"
bitfld.long 0x4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x4 0.--3. 1. "FUNC,Selects pin function."
line.long 0x8 "PIO22,Digital I/O control for port 2 pins PIO2_2"
bitfld.long 0x8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x8 0.--3. 1. "FUNC,Selects pin function."
line.long 0xC "PIO23,Digital I/O control for port 2 pins PIO2_3"
bitfld.long 0xC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xC 0.--3. 1. "FUNC,Selects pin function."
line.long 0x10 "PIO24,Digital I/O control for port 2 pins PIO2_4"
bitfld.long 0x10 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x10 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x10 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x10 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x10 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x10 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x10 0.--3. 1. "FUNC,Selects pin function."
line.long 0x14 "PIO25,Digital I/O control for port 2 pins PIO2_5"
bitfld.long 0x14 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x14 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x14 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x14 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x14 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x14 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x14 0.--3. 1. "FUNC,Selects pin function."
line.long 0x18 "PIO26,Digital I/O control for port 2 pins PIO2_6"
bitfld.long 0x18 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x18 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x18 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x18 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x18 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x18 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x18 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1C "PIO27,Digital I/O control for port 2 pins PIO2_7"
bitfld.long 0x1C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x20 "PIO28,Digital I/O control for port 2 pins PIO2_8"
bitfld.long 0x20 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x20 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x20 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x20 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x20 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x20 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x20 0.--3. 1. "FUNC,Selects pin function."
line.long 0x24 "PIO29,Digital I/O control for port 2 pins PIO2_9"
bitfld.long 0x24 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x24 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x24 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x24 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x24 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x24 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x24 0.--3. 1. "FUNC,Selects pin function."
line.long 0x28 "PIO210,Digital I/O control for port 2 pins PIO2_10"
bitfld.long 0x28 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x28 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x28 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x28 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x28 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x28 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x28 0.--3. 1. "FUNC,Selects pin function."
line.long 0x2C "PIO211,Digital I/O control for port 2 pins PIO2_11"
bitfld.long 0x2C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x2C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x2C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x2C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x2C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x2C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x2C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x30 "PIO212,Digital I/O control for port 2 pins PIO2_12"
bitfld.long 0x30 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x30 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x30 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x30 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x30 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x30 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x30 0.--3. 1. "FUNC,Selects pin function."
line.long 0x34 "PIO213,Digital I/O control for port 2 pins PIO2_13"
bitfld.long 0x34 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x34 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x34 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x34 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x34 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x34 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x34 0.--3. 1. "FUNC,Selects pin function."
line.long 0x38 "PIO214,Digital I/O control for port 2 pins PIO2_14"
bitfld.long 0x38 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x38 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x38 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x38 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x38 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x38 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x38 0.--3. 1. "FUNC,Selects pin function."
line.long 0x3C "PIO215,Digital I/O control for port 2 pins PIO2_15"
bitfld.long 0x3C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x3C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x3C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x3C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x3C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x3C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x3C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x40 "PIO216,Digital I/O control for port 2 pins PIO2_16"
bitfld.long 0x40 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x40 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x40 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x40 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x40 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x40 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x40 0.--3. 1. "FUNC,Selects pin function."
line.long 0x44 "PIO217,Digital I/O control for port 2 pins PIO2_17"
bitfld.long 0x44 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x44 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x44 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x44 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x44 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x44 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x44 0.--3. 1. "FUNC,Selects pin function."
line.long 0x48 "PIO218,Digital I/O control for port 2 pins PIO2_18"
bitfld.long 0x48 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x48 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x48 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x48 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x48 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x48 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x48 0.--3. 1. "FUNC,Selects pin function."
line.long 0x4C "PIO219,Digital I/O control for port 2 pins PIO2_19"
bitfld.long 0x4C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x4C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x4C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x4C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x4C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x4C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x4C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x50 "PIO220,Digital I/O control for port 2 pins PIO2_20"
bitfld.long 0x50 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x50 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x50 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x50 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x50 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x50 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x50 0.--3. 1. "FUNC,Selects pin function."
line.long 0x54 "PIO221,Digital I/O control for port 2 pins PIO2_21"
bitfld.long 0x54 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x54 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x54 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x54 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x54 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x54 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x54 0.--3. 1. "FUNC,Selects pin function."
line.long 0x58 "PIO222,Digital I/O control for port 2 pins PIO2_22"
bitfld.long 0x58 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x58 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x58 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x58 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x58 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x58 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x58 0.--3. 1. "FUNC,Selects pin function."
line.long 0x5C "PIO223,Digital I/O control for port 2 pins PIO2_23"
bitfld.long 0x5C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x5C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x5C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x5C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x5C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x5C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x5C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x60 "PIO224,Digital I/O control for port 2 pins PIO2_24"
bitfld.long 0x60 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x60 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x60 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x60 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x60 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x60 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x60 0.--3. 1. "FUNC,Selects pin function."
line.long 0x64 "PIO225,Digital I/O control for port 2 pins PIO2_25"
bitfld.long 0x64 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x64 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x64 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x64 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x64 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x64 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x64 0.--3. 1. "FUNC,Selects pin function."
line.long 0x68 "PIO226,Digital I/O control for port 2 pins PIO2_26"
bitfld.long 0x68 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x68 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x68 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x68 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x68 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x68 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x68 0.--3. 1. "FUNC,Selects pin function."
line.long 0x6C "PIO227,Digital I/O control for port 2 pins PIO2_27"
bitfld.long 0x6C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x6C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x6C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x6C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x6C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x6C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x6C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x70 "PIO228,Digital I/O control for port 2 pins PIO2_28"
bitfld.long 0x70 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x70 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x70 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x70 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x70 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x70 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x70 0.--3. 1. "FUNC,Selects pin function."
line.long 0x74 "PIO229,Digital I/O control for port 2 pins PIO2_29"
bitfld.long 0x74 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x74 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x74 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x74 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x74 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x74 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x74 0.--3. 1. "FUNC,Selects pin function."
line.long 0x78 "PIO230,Digital I/O control for port 2 pins PIO2_30"
bitfld.long 0x78 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x78 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x78 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x78 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x78 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x78 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x78 0.--3. 1. "FUNC,Selects pin function."
line.long 0x7C "PIO231,Digital I/O control for port 2 pins PIO2_31"
bitfld.long 0x7C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x7C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x7C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x7C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x7C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x7C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x7C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x80 "PIO30,Digital I/O control for port 3 pins PIO3_0"
bitfld.long 0x80 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x80 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x80 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x80 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x80 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x80 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x80 0.--3. 1. "FUNC,Selects pin function."
line.long 0x84 "PIO31,Digital I/O control for port 3 pins PIO3_1"
bitfld.long 0x84 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x84 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x84 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x84 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x84 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x84 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x84 0.--3. 1. "FUNC,Selects pin function."
line.long 0x88 "PIO32,Digital I/O control for port 3 pins PIO3_2"
bitfld.long 0x88 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x88 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x88 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x88 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x88 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x88 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x88 0.--3. 1. "FUNC,Selects pin function."
line.long 0x8C "PIO33,Digital I/O control for port 3 pins PIO3_3"
bitfld.long 0x8C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x8C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x8C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x8C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x8C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x8C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x8C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x90 "PIO34,Digital I/O control for port 3 pins PIO3_4"
bitfld.long 0x90 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x90 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x90 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x90 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x90 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x90 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x90 0.--3. 1. "FUNC,Selects pin function."
line.long 0x94 "PIO35,Digital I/O control for port 3 pins PIO3_5"
bitfld.long 0x94 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x94 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x94 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x94 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x94 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x94 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x94 0.--3. 1. "FUNC,Selects pin function."
line.long 0x98 "PIO36,Digital I/O control for port 3 pins PIO3_6"
bitfld.long 0x98 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x98 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x98 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x98 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x98 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x98 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x98 0.--3. 1. "FUNC,Selects pin function."
line.long 0x9C "PIO37,Digital I/O control for port 3 pins PIO3_7"
bitfld.long 0x9C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x9C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x9C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x9C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x9C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x9C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x9C 0.--3. 1. "FUNC,Selects pin function."
line.long 0xA0 "PIO38,Digital I/O control for port 3 pins PIO3_8"
bitfld.long 0xA0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xA0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xA0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xA0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xA0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xA0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xA0 0.--3. 1. "FUNC,Selects pin function."
line.long 0xA4 "PIO39,Digital I/O control for port 3 pins PIO3_9"
bitfld.long 0xA4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xA4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xA4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xA4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xA4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xA4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xA4 0.--3. 1. "FUNC,Selects pin function."
line.long 0xA8 "PIO310,Digital I/O control for port 3 pins PIO3_10"
bitfld.long 0xA8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xA8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xA8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xA8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xA8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xA8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xA8 0.--3. 1. "FUNC,Selects pin function."
line.long 0xAC "PIO311,Digital I/O control for port 3 pins PIO3_11"
bitfld.long 0xAC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xAC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xAC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xAC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xAC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xAC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xAC 0.--3. 1. "FUNC,Selects pin function."
line.long 0xB0 "PIO312,Digital I/O control for port 3 pins PIO3_12"
bitfld.long 0xB0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xB0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xB0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xB0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xB0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xB0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xB0 0.--3. 1. "FUNC,Selects pin function."
line.long 0xB4 "PIO313,Digital I/O control for port 3 pins PIO3_13"
bitfld.long 0xB4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xB4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xB4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xB4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xB4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xB4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xB4 0.--3. 1. "FUNC,Selects pin function."
line.long 0xB8 "PIO314,Digital I/O control for port 3 pins PIO3_14"
bitfld.long 0xB8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xB8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xB8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xB8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xB8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xB8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xB8 0.--3. 1. "FUNC,Selects pin function."
line.long 0xBC "PIO315,Digital I/O control for port 3 pins PIO3_15"
bitfld.long 0xBC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xBC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xBC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xBC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xBC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xBC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xBC 0.--3. 1. "FUNC,Selects pin function."
line.long 0xC0 "PIO316,Digital I/O control for port 3 pins PIO3_16"
bitfld.long 0xC0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xC0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xC0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xC0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xC0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xC0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xC0 0.--3. 1. "FUNC,Selects pin function."
line.long 0xC4 "PIO317,Digital I/O control for port 3 pins PIO3_17"
bitfld.long 0xC4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xC4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xC4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xC4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xC4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xC4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xC4 0.--3. 1. "FUNC,Selects pin function."
line.long 0xC8 "PIO318,Digital I/O control for port 3 pins PIO3_18"
bitfld.long 0xC8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xC8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xC8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xC8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xC8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xC8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xC8 0.--3. 1. "FUNC,Selects pin function."
line.long 0xCC "PIO319,Digital I/O control for port 3 pins PIO3_19"
bitfld.long 0xCC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xCC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xCC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xCC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xCC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xCC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xCC 0.--3. 1. "FUNC,Selects pin function."
line.long 0xD0 "PIO320,Digital I/O control for port 3 pins PIO3_20"
bitfld.long 0xD0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xD0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xD0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xD0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xD0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xD0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xD0 0.--3. 1. "FUNC,Selects pin function."
line.long 0xD4 "PIO321,Digital I/O control for port 3 pins PIO3_21"
bitfld.long 0xD4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xD4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xD4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xD4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xD4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xD4 0.--3. 1. "FUNC,Selects pin function."
line.long 0xD8 "PIO322,Digital I/O control for port 3 pins PIO3_22"
bitfld.long 0xD8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xD8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xD8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xD8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xD8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xD8 0.--3. 1. "FUNC,Selects pin function."
line.long 0xDC "PIO323,Digital I/O control for port 3 pins PIO3_23"
bitfld.long 0xDC 11. "I2CFILTER,Configures I2C features for standard mode  fast mode  and Fast Mode Plus operation." "0: Enabled. I2C 50 ns glitch filter enabled.,1: Disabled. I2C 50 ns glitch filter disabled."
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bitfld.long 0xDC 10. "I2CDRIVE,Controls the current sink capability of the pin." "0: Low drive. Output drive sink is 4 mA. This is..,1: High drive. Output drive sink is 20 mA. This is.."
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bitfld.long 0xDC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xDC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xDC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xDC 6. "I2CSLEW,Controls slew rate of I2C pad." "0: I2C mode.,1: GPIO mode."
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hexmask.long.byte 0xDC 0.--3. 1. "FUNC,Selects pin function."
line.long 0xE0 "PIO324,Digital I/O control for port 3 pins PIO3_24"
bitfld.long 0xE0 11. "I2CFILTER,Configures I2C features for standard mode  fast mode  and Fast Mode Plus operation." "0: Enabled. I2C 50 ns glitch filter enabled.,1: Disabled. I2C 50 ns glitch filter disabled."
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bitfld.long 0xE0 10. "I2CDRIVE,Controls the current sink capability of the pin." "0: Low drive. Output drive sink is 4 mA. This is..,1: High drive. Output drive sink is 20 mA. This is.."
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bitfld.long 0xE0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xE0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xE0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xE0 6. "I2CSLEW,Controls slew rate of I2C pad." "0: I2C mode.,1: GPIO mode."
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hexmask.long.byte 0xE0 0.--3. 1. "FUNC,Selects pin function."
line.long 0xE4 "PIO325,Digital I/O control for port 3 pins PIO3_25"
bitfld.long 0xE4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xE4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xE4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xE4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xE4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xE4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xE4 0.--3. 1. "FUNC,Selects pin function."
line.long 0xE8 "PIO326,Digital I/O control for port 3 pins PIO3_26"
bitfld.long 0xE8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xE8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xE8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xE8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xE8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xE8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xE8 0.--3. 1. "FUNC,Selects pin function."
line.long 0xEC "PIO327,Digital I/O control for port 3 pins PIO3_27"
bitfld.long 0xEC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xEC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xEC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xEC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xEC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xEC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xEC 0.--3. 1. "FUNC,Selects pin function."
line.long 0xF0 "PIO328,Digital I/O control for port 3 pins PIO3_28"
bitfld.long 0xF0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xF0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xF0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xF0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xF0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xF0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xF0 0.--3. 1. "FUNC,Selects pin function."
line.long 0xF4 "PIO329,Digital I/O control for port 3 pins PIO3_29"
bitfld.long 0xF4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xF4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xF4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xF4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xF4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xF4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xF4 0.--3. 1. "FUNC,Selects pin function."
line.long 0xF8 "PIO330,Digital I/O control for port 3 pins PIO3_30"
bitfld.long 0xF8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xF8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xF8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xF8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xF8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xF8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xF8 0.--3. 1. "FUNC,Selects pin function."
line.long 0xFC "PIO331,Digital I/O control for port 3 pins PIO3_31"
bitfld.long 0xFC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xFC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xFC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xFC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xFC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xFC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xFC 0.--3. 1. "FUNC,Selects pin function."
line.long 0x100 "PIO40,Digital I/O control for port 4 pins PIO4_0"
bitfld.long 0x100 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x100 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x100 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x100 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x100 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x100 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x100 0.--3. 1. "FUNC,Selects pin function."
line.long 0x104 "PIO41,Digital I/O control for port 4 pins PIO4_1"
bitfld.long 0x104 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x104 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x104 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x104 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x104 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x104 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x104 0.--3. 1. "FUNC,Selects pin function."
line.long 0x108 "PIO42,Digital I/O control for port 4 pins PIO4_2"
bitfld.long 0x108 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x108 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x108 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x108 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x108 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x108 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x108 0.--3. 1. "FUNC,Selects pin function."
line.long 0x10C "PIO43,Digital I/O control for port 4 pins PIO4_3"
bitfld.long 0x10C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x10C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x10C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x10C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x10C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x10C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x10C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x110 "PIO44,Digital I/O control for port 4 pins PIO4_4"
bitfld.long 0x110 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x110 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x110 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x110 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x110 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x110 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x110 0.--3. 1. "FUNC,Selects pin function."
line.long 0x114 "PIO45,Digital I/O control for port 4 pins PIO4_5"
bitfld.long 0x114 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x114 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x114 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x114 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x114 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x114 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x114 0.--3. 1. "FUNC,Selects pin function."
line.long 0x118 "PIO46,Digital I/O control for port 4 pins PIO4_6"
bitfld.long 0x118 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x118 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x118 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x118 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x118 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x118 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x118 0.--3. 1. "FUNC,Selects pin function."
line.long 0x11C "PIO47,Digital I/O control for port 4 pins PIO4_7"
bitfld.long 0x11C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x11C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x11C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x11C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x11C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x11C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x11C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x120 "PIO48,Digital I/O control for port 4 pins PIO4_8"
bitfld.long 0x120 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x120 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x120 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x120 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x120 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x120 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x120 0.--3. 1. "FUNC,Selects pin function."
line.long 0x124 "PIO49,Digital I/O control for port 4 pins PIO4_9"
bitfld.long 0x124 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x124 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x124 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x124 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x124 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x124 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x124 0.--3. 1. "FUNC,Selects pin function."
line.long 0x128 "PIO410,Digital I/O control for port 4 pins PIO4_10"
bitfld.long 0x128 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x128 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x128 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x128 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x128 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x128 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x128 0.--3. 1. "FUNC,Selects pin function."
line.long 0x12C "PIO411,Digital I/O control for port 4 pins PIO4_11"
bitfld.long 0x12C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x12C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x12C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x12C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x12C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x12C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x12C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x130 "PIO412,Digital I/O control for port 4 pins PIO4_12"
bitfld.long 0x130 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x130 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x130 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x130 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x130 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x130 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x130 0.--3. 1. "FUNC,Selects pin function."
line.long 0x134 "PIO413,Digital I/O control for port 4 pins PIO4_13"
bitfld.long 0x134 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x134 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x134 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x134 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x134 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x134 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x134 0.--3. 1. "FUNC,Selects pin function."
line.long 0x138 "PIO414,Digital I/O control for port 4 pins PIO4_14"
bitfld.long 0x138 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x138 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x138 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x138 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x138 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x138 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x138 0.--3. 1. "FUNC,Selects pin function."
line.long 0x13C "PIO415,Digital I/O control for port 4 pins PIO4_15"
bitfld.long 0x13C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x13C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x13C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x13C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x13C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x13C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x13C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x140 "PIO416,Digital I/O control for port 4 pins PIO4_16"
bitfld.long 0x140 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x140 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x140 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x140 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x140 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x140 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x140 0.--3. 1. "FUNC,Selects pin function."
line.long 0x144 "PIO417,Digital I/O control for port 4 pins PIO4_17"
bitfld.long 0x144 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x144 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x144 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x144 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x144 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x144 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x144 0.--3. 1. "FUNC,Selects pin function."
line.long 0x148 "PIO418,Digital I/O control for port 4 pins PIO4_18"
bitfld.long 0x148 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x148 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x148 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x148 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x148 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x148 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x148 0.--3. 1. "FUNC,Selects pin function."
line.long 0x14C "PIO419,Digital I/O control for port 4 pins PIO4_19"
bitfld.long 0x14C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x14C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x14C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x14C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x14C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x14C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x14C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x150 "PIO420,Digital I/O control for port 4 pins PIO4_20"
bitfld.long 0x150 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x150 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x150 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x150 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x150 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x150 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x150 0.--3. 1. "FUNC,Selects pin function."
line.long 0x154 "PIO421,Digital I/O control for port 4 pins PIO4_21"
bitfld.long 0x154 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x154 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x154 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x154 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x154 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x154 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x154 0.--3. 1. "FUNC,Selects pin function."
line.long 0x158 "PIO422,Digital I/O control for port 4 pins PIO4_22"
bitfld.long 0x158 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x158 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x158 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x158 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x158 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x158 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x158 0.--3. 1. "FUNC,Selects pin function."
line.long 0x15C "PIO423,Digital I/O control for port 4 pins PIO4_23"
bitfld.long 0x15C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x15C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x15C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x15C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x15C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x15C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x15C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x160 "PIO424,Digital I/O control for port 4 pins PIO4_24"
bitfld.long 0x160 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x160 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x160 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x160 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x160 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x160 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x160 0.--3. 1. "FUNC,Selects pin function."
line.long 0x164 "PIO425,Digital I/O control for port 4 pins PIO4_25"
bitfld.long 0x164 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x164 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x164 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x164 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x164 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x164 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x164 0.--3. 1. "FUNC,Selects pin function."
line.long 0x168 "PIO426,Digital I/O control for port 4 pins PIO4_26"
bitfld.long 0x168 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x168 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x168 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x168 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x168 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x168 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x168 0.--3. 1. "FUNC,Selects pin function."
line.long 0x16C "PIO427,Digital I/O control for port 4 pins PIO4_27"
bitfld.long 0x16C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x16C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x16C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x16C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x16C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x16C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x16C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x170 "PIO428,Digital I/O control for port 4 pins PIO4_28"
bitfld.long 0x170 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x170 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x170 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x170 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x170 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x170 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x170 0.--3. 1. "FUNC,Selects pin function."
line.long 0x174 "PIO429,Digital I/O control for port 4 pins PIO4_29"
bitfld.long 0x174 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x174 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x174 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x174 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x174 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x174 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x174 0.--3. 1. "FUNC,Selects pin function."
line.long 0x178 "PIO430,Digital I/O control for port 4 pins PIO4_30"
bitfld.long 0x178 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x178 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x178 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x178 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x178 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x178 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x178 0.--3. 1. "FUNC,Selects pin function."
line.long 0x17C "PIO431,Digital I/O control for port 4 pins PIO4_31"
bitfld.long 0x17C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x17C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x17C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x17C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x17C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x17C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x17C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x180 "PIO50,Digital I/O control for port 5 pins PIO5_0"
bitfld.long 0x180 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x180 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x180 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x180 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x180 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x180 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x180 0.--3. 1. "FUNC,Selects pin function."
line.long 0x184 "PIO51,Digital I/O control for port 5 pins PIO5_1"
bitfld.long 0x184 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x184 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x184 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x184 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x184 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x184 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x184 0.--3. 1. "FUNC,Selects pin function."
line.long 0x188 "PIO52,Digital I/O control for port 5 pins PIO5_2"
bitfld.long 0x188 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x188 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x188 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x188 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x188 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x188 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x188 0.--3. 1. "FUNC,Selects pin function."
line.long 0x18C "PIO53,Digital I/O control for port 5 pins PIO5_3"
bitfld.long 0x18C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x18C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x18C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x18C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x18C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x18C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x18C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x190 "PIO54,Digital I/O control for port 5 pins PIO5_4"
bitfld.long 0x190 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x190 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x190 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x190 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x190 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x190 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x190 0.--3. 1. "FUNC,Selects pin function."
line.long 0x194 "PIO55,Digital I/O control for port 5 pins PIO5_5"
bitfld.long 0x194 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x194 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x194 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x194 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x194 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x194 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x194 0.--3. 1. "FUNC,Selects pin function."
line.long 0x198 "PIO56,Digital I/O control for port 5 pins PIO5_6"
bitfld.long 0x198 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x198 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x198 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x198 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x198 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x198 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x198 0.--3. 1. "FUNC,Selects pin function."
line.long 0x19C "PIO57,Digital I/O control for port 5 pins PIO5_7"
bitfld.long 0x19C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x19C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x19C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x19C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x19C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x19C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x19C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1A0 "PIO58,Digital I/O control for port 5 pins PIO5_8"
bitfld.long 0x1A0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1A0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1A0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1A0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1A0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1A0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1A0 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1A4 "PIO59,Digital I/O control for port 5 pins PIO5_9"
bitfld.long 0x1A4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1A4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1A4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1A4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1A4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1A4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1A4 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1A8 "PIO510,Digital I/O control for port 5 pins PIO5_10"
bitfld.long 0x1A8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1A8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1A8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1A8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1A8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1A8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1A8 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1AC "PIO511,Digital I/O control for port 5 pins PIO5_11"
bitfld.long 0x1AC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1AC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1AC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1AC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1AC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1AC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1AC 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1B0 "PIO512,Digital I/O control for port 5 pins PIO5_12"
bitfld.long 0x1B0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1B0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1B0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1B0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1B0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1B0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1B0 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1B4 "PIO513,Digital I/O control for port 5 pins PIO5_13"
bitfld.long 0x1B4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1B4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1B4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1B4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1B4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1B4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1B4 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1B8 "PIO514,Digital I/O control for port 5 pins PIO5_14"
bitfld.long 0x1B8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1B8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1B8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1B8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1B8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1B8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1B8 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1BC "PIO515,Digital I/O control for port 5 pins PIO5_15"
bitfld.long 0x1BC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1BC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1BC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1BC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1BC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1BC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1BC 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1C0 "PIO516,Digital I/O control for port 5 pins PIO5_16"
bitfld.long 0x1C0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1C0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1C0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1C0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1C0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1C0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1C0 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1C4 "PIO517,Digital I/O control for port 5 pins PIO5_17"
bitfld.long 0x1C4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1C4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1C4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1C4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1C4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1C4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1C4 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1C8 "PIO518,Digital I/O control for port 5 pins PIO5_18"
bitfld.long 0x1C8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1C8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1C8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1C8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1C8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1C8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1C8 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1CC "PIO519,Digital I/O control for port 5 pins PIO5_19"
bitfld.long 0x1CC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1CC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1CC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1CC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1CC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1CC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1CC 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1D0 "PIO520,Digital I/O control for port 5 pins PIO5_20"
bitfld.long 0x1D0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1D0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1D0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1D0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1D0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1D0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1D0 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1D4 "PIO521,Digital I/O control for port 5 pins PIO5_21"
bitfld.long 0x1D4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1D4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1D4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1D4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1D4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1D4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1D4 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1D8 "PIO522,Digital I/O control for port 5 pins PIO5_22"
bitfld.long 0x1D8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1D8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1D8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1D8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1D8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1D8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1D8 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1DC "PIO523,Digital I/O control for port 5 pins PIO5_23"
bitfld.long 0x1DC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1DC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1DC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1DC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1DC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1DC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1DC 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1E0 "PIO524,Digital I/O control for port 5 pins PIO5_24"
bitfld.long 0x1E0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1E0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1E0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1E0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1E0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1E0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1E0 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1E4 "PIO525,Digital I/O control for port 5 pins PIO5_25"
bitfld.long 0x1E4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1E4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1E4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1E4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1E4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1E4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1E4 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1E8 "PIO526,Digital I/O control for port 5 pins PIO5_26"
bitfld.long 0x1E8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1E8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1E8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1E8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1E8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1E8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1E8 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1EC "PIO527,Digital I/O control for port 5 pins PIO5_27"
bitfld.long 0x1EC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1EC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1EC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1EC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1EC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1EC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1EC 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1F0 "PIO528,Digital I/O control for port 5 pins PIO5_28"
bitfld.long 0x1F0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1F0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1F0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1F0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1F0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1F0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1F0 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1F4 "PIO529,Digital I/O control for port 5 pins PIO5_29"
bitfld.long 0x1F4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1F4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1F4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1F4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1F4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1F4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1F4 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1F8 "PIO530,Digital I/O control for port 5 pins PIO5_30"
bitfld.long 0x1F8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1F8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1F8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1F8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1F8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1F8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1F8 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1FC "PIO531,Digital I/O control for port 5 pins PIO5_31"
bitfld.long 0x1FC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1FC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1FC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1FC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1FC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1FC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1FC 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54616*"))
group.long 0x100++0x1FF
line.long 0x0 "PIO20,Digital I/O control for port 2 pins PIO2_0"
bitfld.long 0x0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x0 0.--3. 1. "FUNC,Selects pin function."
line.long 0x4 "PIO21,Digital I/O control for port 2 pins PIO2_1"
bitfld.long 0x4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x4 0.--3. 1. "FUNC,Selects pin function."
line.long 0x8 "PIO22,Digital I/O control for port 2 pins PIO2_2"
bitfld.long 0x8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x8 0.--3. 1. "FUNC,Selects pin function."
line.long 0xC "PIO23,Digital I/O control for port 2 pins PIO2_3"
bitfld.long 0xC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xC 0.--3. 1. "FUNC,Selects pin function."
line.long 0x10 "PIO24,Digital I/O control for port 2 pins PIO2_4"
bitfld.long 0x10 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x10 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x10 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x10 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x10 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x10 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x10 0.--3. 1. "FUNC,Selects pin function."
line.long 0x14 "PIO25,Digital I/O control for port 2 pins PIO2_5"
bitfld.long 0x14 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x14 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x14 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x14 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x14 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x14 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x14 0.--3. 1. "FUNC,Selects pin function."
line.long 0x18 "PIO26,Digital I/O control for port 2 pins PIO2_6"
bitfld.long 0x18 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x18 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x18 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x18 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x18 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x18 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x18 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1C "PIO27,Digital I/O control for port 2 pins PIO2_7"
bitfld.long 0x1C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x1C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x1C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x1C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x1C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x1C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x1C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x20 "PIO28,Digital I/O control for port 2 pins PIO2_8"
bitfld.long 0x20 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x20 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x20 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x20 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x20 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x20 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x20 0.--3. 1. "FUNC,Selects pin function."
line.long 0x24 "PIO29,Digital I/O control for port 2 pins PIO2_9"
bitfld.long 0x24 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x24 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x24 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x24 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x24 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x24 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x24 0.--3. 1. "FUNC,Selects pin function."
line.long 0x28 "PIO210,Digital I/O control for port 2 pins PIO2_10"
bitfld.long 0x28 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x28 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x28 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x28 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x28 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x28 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x28 0.--3. 1. "FUNC,Selects pin function."
line.long 0x2C "PIO211,Digital I/O control for port 2 pins PIO2_11"
bitfld.long 0x2C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x2C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x2C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x2C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x2C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x2C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x2C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x30 "PIO212,Digital I/O control for port 2 pins PIO2_12"
bitfld.long 0x30 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x30 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x30 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x30 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x30 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x30 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x30 0.--3. 1. "FUNC,Selects pin function."
line.long 0x34 "PIO213,Digital I/O control for port 2 pins PIO2_13"
bitfld.long 0x34 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x34 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x34 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x34 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x34 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x34 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x34 0.--3. 1. "FUNC,Selects pin function."
line.long 0x38 "PIO214,Digital I/O control for port 2 pins PIO2_14"
bitfld.long 0x38 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x38 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x38 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x38 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x38 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x38 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x38 0.--3. 1. "FUNC,Selects pin function."
line.long 0x3C "PIO215,Digital I/O control for port 2 pins PIO2_15"
bitfld.long 0x3C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x3C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x3C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x3C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x3C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x3C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x3C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x40 "PIO216,Digital I/O control for port 2 pins PIO2_16"
bitfld.long 0x40 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x40 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x40 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x40 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x40 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x40 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x40 0.--3. 1. "FUNC,Selects pin function."
line.long 0x44 "PIO217,Digital I/O control for port 2 pins PIO2_17"
bitfld.long 0x44 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x44 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x44 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x44 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x44 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x44 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x44 0.--3. 1. "FUNC,Selects pin function."
line.long 0x48 "PIO218,Digital I/O control for port 2 pins PIO2_18"
bitfld.long 0x48 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x48 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x48 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x48 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x48 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x48 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x48 0.--3. 1. "FUNC,Selects pin function."
line.long 0x4C "PIO219,Digital I/O control for port 2 pins PIO2_19"
bitfld.long 0x4C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x4C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x4C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x4C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x4C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x4C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x4C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x50 "PIO220,Digital I/O control for port 2 pins PIO2_20"
bitfld.long 0x50 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x50 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x50 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x50 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x50 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x50 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x50 0.--3. 1. "FUNC,Selects pin function."
line.long 0x54 "PIO221,Digital I/O control for port 2 pins PIO2_21"
bitfld.long 0x54 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x54 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x54 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x54 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x54 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x54 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x54 0.--3. 1. "FUNC,Selects pin function."
line.long 0x58 "PIO222,Digital I/O control for port 2 pins PIO2_22"
bitfld.long 0x58 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x58 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x58 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x58 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x58 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x58 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x58 0.--3. 1. "FUNC,Selects pin function."
line.long 0x5C "PIO223,Digital I/O control for port 2 pins PIO2_23"
bitfld.long 0x5C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x5C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x5C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x5C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x5C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x5C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x5C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x60 "PIO224,Digital I/O control for port 2 pins PIO2_24"
bitfld.long 0x60 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x60 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x60 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x60 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x60 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x60 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x60 0.--3. 1. "FUNC,Selects pin function."
line.long 0x64 "PIO225,Digital I/O control for port 2 pins PIO2_25"
bitfld.long 0x64 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x64 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x64 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x64 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x64 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x64 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x64 0.--3. 1. "FUNC,Selects pin function."
line.long 0x68 "PIO226,Digital I/O control for port 2 pins PIO2_26"
bitfld.long 0x68 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x68 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x68 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x68 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x68 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x68 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x68 0.--3. 1. "FUNC,Selects pin function."
line.long 0x6C "PIO227,Digital I/O control for port 2 pins PIO2_27"
bitfld.long 0x6C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x6C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x6C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x6C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x6C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x6C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x6C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x70 "PIO228,Digital I/O control for port 2 pins PIO2_28"
bitfld.long 0x70 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x70 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x70 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x70 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x70 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x70 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x70 0.--3. 1. "FUNC,Selects pin function."
line.long 0x74 "PIO229,Digital I/O control for port 2 pins PIO2_29"
bitfld.long 0x74 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x74 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x74 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x74 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x74 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x74 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x74 0.--3. 1. "FUNC,Selects pin function."
line.long 0x78 "PIO230,Digital I/O control for port 2 pins PIO2_30"
bitfld.long 0x78 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x78 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x78 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x78 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x78 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x78 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x78 0.--3. 1. "FUNC,Selects pin function."
line.long 0x7C "PIO231,Digital I/O control for port 2 pins PIO2_31"
bitfld.long 0x7C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x7C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x7C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x7C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x7C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x7C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x7C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x80 "PIO30,Digital I/O control for port 3 pins PIO3_0"
bitfld.long 0x80 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x80 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x80 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x80 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x80 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x80 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x80 0.--3. 1. "FUNC,Selects pin function."
line.long 0x84 "PIO31,Digital I/O control for port 3 pins PIO3_1"
bitfld.long 0x84 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x84 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x84 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x84 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x84 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x84 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x84 0.--3. 1. "FUNC,Selects pin function."
line.long 0x88 "PIO32,Digital I/O control for port 3 pins PIO3_2"
bitfld.long 0x88 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x88 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x88 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x88 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x88 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x88 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x88 0.--3. 1. "FUNC,Selects pin function."
line.long 0x8C "PIO33,Digital I/O control for port 3 pins PIO3_3"
bitfld.long 0x8C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x8C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x8C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x8C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x8C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x8C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x8C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x90 "PIO34,Digital I/O control for port 3 pins PIO3_4"
bitfld.long 0x90 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x90 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x90 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x90 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x90 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x90 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x90 0.--3. 1. "FUNC,Selects pin function."
line.long 0x94 "PIO35,Digital I/O control for port 3 pins PIO3_5"
bitfld.long 0x94 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x94 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x94 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x94 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x94 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x94 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x94 0.--3. 1. "FUNC,Selects pin function."
line.long 0x98 "PIO36,Digital I/O control for port 3 pins PIO3_6"
bitfld.long 0x98 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x98 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x98 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x98 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x98 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x98 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x98 0.--3. 1. "FUNC,Selects pin function."
line.long 0x9C "PIO37,Digital I/O control for port 3 pins PIO3_7"
bitfld.long 0x9C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x9C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x9C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x9C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x9C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x9C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x9C 0.--3. 1. "FUNC,Selects pin function."
line.long 0xA0 "PIO38,Digital I/O control for port 3 pins PIO3_8"
bitfld.long 0xA0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xA0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xA0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xA0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xA0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xA0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xA0 0.--3. 1. "FUNC,Selects pin function."
line.long 0xA4 "PIO39,Digital I/O control for port 3 pins PIO3_9"
bitfld.long 0xA4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xA4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xA4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xA4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xA4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xA4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xA4 0.--3. 1. "FUNC,Selects pin function."
line.long 0xA8 "PIO310,Digital I/O control for port 3 pins PIO3_10"
bitfld.long 0xA8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xA8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xA8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xA8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xA8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xA8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xA8 0.--3. 1. "FUNC,Selects pin function."
line.long 0xAC "PIO311,Digital I/O control for port 3 pins PIO3_11"
bitfld.long 0xAC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xAC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xAC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xAC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xAC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xAC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xAC 0.--3. 1. "FUNC,Selects pin function."
line.long 0xB0 "PIO312,Digital I/O control for port 3 pins PIO3_12"
bitfld.long 0xB0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xB0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xB0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xB0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xB0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xB0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xB0 0.--3. 1. "FUNC,Selects pin function."
line.long 0xB4 "PIO313,Digital I/O control for port 3 pins PIO3_13"
bitfld.long 0xB4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xB4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xB4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xB4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xB4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xB4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xB4 0.--3. 1. "FUNC,Selects pin function."
line.long 0xB8 "PIO314,Digital I/O control for port 3 pins PIO3_14"
bitfld.long 0xB8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xB8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xB8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xB8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xB8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xB8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xB8 0.--3. 1. "FUNC,Selects pin function."
line.long 0xBC "PIO315,Digital I/O control for port 3 pins PIO3_15"
bitfld.long 0xBC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xBC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xBC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xBC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xBC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xBC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xBC 0.--3. 1. "FUNC,Selects pin function."
line.long 0xC0 "PIO316,Digital I/O control for port 3 pins PIO3_16"
bitfld.long 0xC0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xC0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xC0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xC0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xC0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xC0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xC0 0.--3. 1. "FUNC,Selects pin function."
line.long 0xC4 "PIO317,Digital I/O control for port 3 pins PIO3_17"
bitfld.long 0xC4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xC4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xC4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xC4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xC4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xC4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xC4 0.--3. 1. "FUNC,Selects pin function."
line.long 0xC8 "PIO318,Digital I/O control for port 3 pins PIO3_18"
bitfld.long 0xC8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xC8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xC8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xC8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xC8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xC8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xC8 0.--3. 1. "FUNC,Selects pin function."
line.long 0xCC "PIO319,Digital I/O control for port 3 pins PIO3_19"
bitfld.long 0xCC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xCC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xCC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xCC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xCC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xCC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xCC 0.--3. 1. "FUNC,Selects pin function."
line.long 0xD0 "PIO320,Digital I/O control for port 3 pins PIO3_20"
bitfld.long 0xD0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xD0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xD0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xD0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xD0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xD0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xD0 0.--3. 1. "FUNC,Selects pin function."
line.long 0xD4 "PIO321,Digital I/O control for port 3 pins PIO3_21"
bitfld.long 0xD4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xD4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xD4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xD4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xD4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xD4 0.--3. 1. "FUNC,Selects pin function."
line.long 0xD8 "PIO322,Digital I/O control for port 3 pins PIO3_22"
bitfld.long 0xD8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xD8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xD8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xD8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xD8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xD8 0.--3. 1. "FUNC,Selects pin function."
line.long 0xDC "PIO323,Digital I/O control for port 3 pins PIO3_23"
bitfld.long 0xDC 11. "I2CFILTER,Configures I2C features for standard mode  fast mode  and Fast Mode Plus operation." "0: Enabled. I2C 50 ns glitch filter enabled.,1: Disabled. I2C 50 ns glitch filter disabled."
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bitfld.long 0xDC 10. "I2CDRIVE,Controls the current sink capability of the pin." "0: Low drive. Output drive sink is 4 mA. This is..,1: High drive. Output drive sink is 20 mA. This is.."
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bitfld.long 0xDC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xDC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xDC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xDC 6. "I2CSLEW,Controls slew rate of I2C pad." "0: I2C mode.,1: GPIO mode."
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hexmask.long.byte 0xDC 0.--3. 1. "FUNC,Selects pin function."
line.long 0xE0 "PIO324,Digital I/O control for port 3 pins PIO3_24"
bitfld.long 0xE0 11. "I2CFILTER,Configures I2C features for standard mode  fast mode  and Fast Mode Plus operation." "0: Enabled. I2C 50 ns glitch filter enabled.,1: Disabled. I2C 50 ns glitch filter disabled."
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bitfld.long 0xE0 10. "I2CDRIVE,Controls the current sink capability of the pin." "0: Low drive. Output drive sink is 4 mA. This is..,1: High drive. Output drive sink is 20 mA. This is.."
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bitfld.long 0xE0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xE0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xE0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xE0 6. "I2CSLEW,Controls slew rate of I2C pad." "0: I2C mode.,1: GPIO mode."
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hexmask.long.byte 0xE0 0.--3. 1. "FUNC,Selects pin function."
line.long 0xE4 "PIO325,Digital I/O control for port 3 pins PIO3_25"
bitfld.long 0xE4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xE4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xE4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xE4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xE4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xE4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xE4 0.--3. 1. "FUNC,Selects pin function."
line.long 0xE8 "PIO326,Digital I/O control for port 3 pins PIO3_26"
bitfld.long 0xE8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xE8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xE8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xE8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xE8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xE8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xE8 0.--3. 1. "FUNC,Selects pin function."
line.long 0xEC "PIO327,Digital I/O control for port 3 pins PIO3_27"
bitfld.long 0xEC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xEC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xEC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xEC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xEC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xEC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xEC 0.--3. 1. "FUNC,Selects pin function."
line.long 0xF0 "PIO328,Digital I/O control for port 3 pins PIO3_28"
bitfld.long 0xF0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xF0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xF0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xF0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xF0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xF0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xF0 0.--3. 1. "FUNC,Selects pin function."
line.long 0xF4 "PIO329,Digital I/O control for port 3 pins PIO3_29"
bitfld.long 0xF4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xF4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xF4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xF4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xF4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xF4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xF4 0.--3. 1. "FUNC,Selects pin function."
line.long 0xF8 "PIO330,Digital I/O control for port 3 pins PIO3_30"
bitfld.long 0xF8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xF8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xF8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xF8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xF8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xF8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xF8 0.--3. 1. "FUNC,Selects pin function."
line.long 0xFC "PIO331,Digital I/O control for port 3 pins PIO3_31"
bitfld.long 0xFC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xFC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xFC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xFC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xFC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xFC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xFC 0.--3. 1. "FUNC,Selects pin function."
line.long 0x100 "PIO40,Digital I/O control for port 4 pins PIO4_0"
bitfld.long 0x100 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x100 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x100 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x100 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x100 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x100 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x100 0.--3. 1. "FUNC,Selects pin function."
line.long 0x104 "PIO41,Digital I/O control for port 4 pins PIO4_1"
bitfld.long 0x104 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x104 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x104 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x104 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x104 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x104 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x104 0.--3. 1. "FUNC,Selects pin function."
line.long 0x108 "PIO42,Digital I/O control for port 4 pins PIO4_2"
bitfld.long 0x108 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x108 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x108 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x108 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x108 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x108 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x108 0.--3. 1. "FUNC,Selects pin function."
line.long 0x10C "PIO43,Digital I/O control for port 4 pins PIO4_3"
bitfld.long 0x10C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x10C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x10C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x10C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x10C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x10C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x10C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x110 "PIO44,Digital I/O control for port 4 pins PIO4_4"
bitfld.long 0x110 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x110 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x110 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x110 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x110 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x110 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x110 0.--3. 1. "FUNC,Selects pin function."
line.long 0x114 "PIO45,Digital I/O control for port 4 pins PIO4_5"
bitfld.long 0x114 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x114 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x114 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x114 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x114 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x114 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x114 0.--3. 1. "FUNC,Selects pin function."
line.long 0x118 "PIO46,Digital I/O control for port 4 pins PIO4_6"
bitfld.long 0x118 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x118 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x118 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x118 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x118 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x118 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x118 0.--3. 1. "FUNC,Selects pin function."
line.long 0x11C "PIO47,Digital I/O control for port 4 pins PIO4_7"
bitfld.long 0x11C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x11C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x11C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x11C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x11C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x11C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x11C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x120 "PIO48,Digital I/O control for port 4 pins PIO4_8"
bitfld.long 0x120 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x120 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x120 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x120 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x120 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x120 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x120 0.--3. 1. "FUNC,Selects pin function."
line.long 0x124 "PIO49,Digital I/O control for port 4 pins PIO4_9"
bitfld.long 0x124 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x124 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x124 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x124 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x124 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x124 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x124 0.--3. 1. "FUNC,Selects pin function."
line.long 0x128 "PIO410,Digital I/O control for port 4 pins PIO4_10"
bitfld.long 0x128 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x128 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x128 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x128 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x128 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x128 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x128 0.--3. 1. "FUNC,Selects pin function."
line.long 0x12C "PIO411,Digital I/O control for port 4 pins PIO4_11"
bitfld.long 0x12C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x12C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x12C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x12C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x12C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x12C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x12C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x130 "PIO412,Digital I/O control for port 4 pins PIO4_12"
bitfld.long 0x130 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x130 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x130 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x130 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x130 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x130 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x130 0.--3. 1. "FUNC,Selects pin function."
line.long 0x134 "PIO413,Digital I/O control for port 4 pins PIO4_13"
bitfld.long 0x134 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x134 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x134 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x134 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x134 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x134 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x134 0.--3. 1. "FUNC,Selects pin function."
line.long 0x138 "PIO414,Digital I/O control for port 4 pins PIO4_14"
bitfld.long 0x138 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x138 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x138 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x138 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x138 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x138 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x138 0.--3. 1. "FUNC,Selects pin function."
line.long 0x13C "PIO415,Digital I/O control for port 4 pins PIO4_15"
bitfld.long 0x13C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x13C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x13C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x13C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x13C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x13C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x13C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x140 "PIO416,Digital I/O control for port 4 pins PIO4_16"
bitfld.long 0x140 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x140 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x140 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x140 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x140 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x140 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x140 0.--3. 1. "FUNC,Selects pin function."
line.long 0x144 "PIO417,Digital I/O control for port 4 pins PIO4_17"
bitfld.long 0x144 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x144 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x144 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x144 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x144 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x144 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x144 0.--3. 1. "FUNC,Selects pin function."
line.long 0x148 "PIO418,Digital I/O control for port 4 pins PIO4_18"
bitfld.long 0x148 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x148 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x148 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x148 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x148 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x148 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x148 0.--3. 1. "FUNC,Selects pin function."
line.long 0x14C "PIO419,Digital I/O control for port 4 pins PIO4_19"
bitfld.long 0x14C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x14C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x14C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x14C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x14C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x14C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x14C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x150 "PIO420,Digital I/O control for port 4 pins PIO4_20"
bitfld.long 0x150 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x150 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x150 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x150 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x150 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x150 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x150 0.--3. 1. "FUNC,Selects pin function."
line.long 0x154 "PIO421,Digital I/O control for port 4 pins PIO4_21"
bitfld.long 0x154 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x154 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x154 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x154 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x154 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x154 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x154 0.--3. 1. "FUNC,Selects pin function."
line.long 0x158 "PIO422,Digital I/O control for port 4 pins PIO4_22"
bitfld.long 0x158 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x158 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x158 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x158 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x158 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x158 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x158 0.--3. 1. "FUNC,Selects pin function."
line.long 0x15C "PIO423,Digital I/O control for port 4 pins PIO4_23"
bitfld.long 0x15C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x15C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x15C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x15C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x15C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x15C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x15C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x160 "PIO424,Digital I/O control for port 4 pins PIO4_24"
bitfld.long 0x160 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x160 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x160 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x160 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x160 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x160 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x160 0.--3. 1. "FUNC,Selects pin function."
line.long 0x164 "PIO425,Digital I/O control for port 4 pins PIO4_25"
bitfld.long 0x164 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x164 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x164 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x164 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x164 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x164 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x164 0.--3. 1. "FUNC,Selects pin function."
line.long 0x168 "PIO426,Digital I/O control for port 4 pins PIO4_26"
bitfld.long 0x168 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x168 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x168 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x168 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x168 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x168 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x168 0.--3. 1. "FUNC,Selects pin function."
line.long 0x16C "PIO427,Digital I/O control for port 4 pins PIO4_27"
bitfld.long 0x16C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x16C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x16C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x16C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x16C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x16C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x16C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x170 "PIO428,Digital I/O control for port 4 pins PIO4_28"
bitfld.long 0x170 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x170 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x170 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x170 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x170 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x170 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x170 0.--3. 1. "FUNC,Selects pin function."
line.long 0x174 "PIO429,Digital I/O control for port 4 pins PIO4_29"
bitfld.long 0x174 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x174 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x174 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x174 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x174 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x174 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x174 0.--3. 1. "FUNC,Selects pin function."
line.long 0x178 "PIO430,Digital I/O control for port 4 pins PIO4_30"
bitfld.long 0x178 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x178 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x178 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x178 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x178 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x178 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x178 0.--3. 1. "FUNC,Selects pin function."
line.long 0x17C "PIO431,Digital I/O control for port 4 pins PIO4_31"
bitfld.long 0x17C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x17C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x17C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x17C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x17C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x17C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x17C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x180 "PIO50,Digital I/O control for port 5 pins PIO5_0"
bitfld.long 0x180 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x180 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x180 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x180 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x180 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x180 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x180 0.--3. 1. "FUNC,Selects pin function."
line.long 0x184 "PIO51,Digital I/O control for port 5 pins PIO5_1"
bitfld.long 0x184 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x184 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x184 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x184 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x184 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x184 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x184 0.--3. 1. "FUNC,Selects pin function."
line.long 0x188 "PIO52,Digital I/O control for port 5 pins PIO5_2"
bitfld.long 0x188 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x188 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x188 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x188 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x188 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x188 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x188 0.--3. 1. "FUNC,Selects pin function."
line.long 0x18C "PIO53,Digital I/O control for port 5 pins PIO5_3"
bitfld.long 0x18C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x18C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x18C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x18C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x18C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x18C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x18C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x190 "PIO54,Digital I/O control for port 5 pins PIO5_4"
bitfld.long 0x190 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x190 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x190 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x190 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x190 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x190 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x190 0.--3. 1. "FUNC,Selects pin function."
line.long 0x194 "PIO55,Digital I/O control for port 5 pins PIO5_5"
bitfld.long 0x194 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x194 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x194 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x194 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x194 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x194 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x194 0.--3. 1. "FUNC,Selects pin function."
line.long 0x198 "PIO56,Digital I/O control for port 5 pins PIO5_6"
bitfld.long 0x198 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x198 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x198 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x198 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x198 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x198 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x198 0.--3. 1. "FUNC,Selects pin function."
line.long 0x19C "PIO57,Digital I/O control for port 5 pins PIO5_7"
bitfld.long 0x19C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x19C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x19C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x19C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x19C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x19C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x19C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1A0 "PIO58,Digital I/O control for port 5 pins PIO5_8"
bitfld.long 0x1A0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1A0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1A0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1A0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1A0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1A0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1A0 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1A4 "PIO59,Digital I/O control for port 5 pins PIO5_9"
bitfld.long 0x1A4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1A4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1A4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1A4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1A4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1A4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1A4 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1A8 "PIO510,Digital I/O control for port 5 pins PIO5_10"
bitfld.long 0x1A8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1A8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1A8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1A8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1A8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1A8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1A8 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1AC "PIO511,Digital I/O control for port 5 pins PIO5_11"
bitfld.long 0x1AC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1AC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1AC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1AC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1AC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1AC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1AC 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1B0 "PIO512,Digital I/O control for port 5 pins PIO5_12"
bitfld.long 0x1B0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1B0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1B0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1B0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1B0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1B0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1B0 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1B4 "PIO513,Digital I/O control for port 5 pins PIO5_13"
bitfld.long 0x1B4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1B4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1B4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1B4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1B4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1B4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1B4 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1B8 "PIO514,Digital I/O control for port 5 pins PIO5_14"
bitfld.long 0x1B8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1B8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1B8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1B8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1B8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1B8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1B8 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1BC "PIO515,Digital I/O control for port 5 pins PIO5_15"
bitfld.long 0x1BC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1BC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1BC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1BC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1BC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1BC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1BC 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1C0 "PIO516,Digital I/O control for port 5 pins PIO5_16"
bitfld.long 0x1C0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1C0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1C0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1C0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1C0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1C0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1C0 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1C4 "PIO517,Digital I/O control for port 5 pins PIO5_17"
bitfld.long 0x1C4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1C4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1C4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1C4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1C4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1C4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1C4 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1C8 "PIO518,Digital I/O control for port 5 pins PIO5_18"
bitfld.long 0x1C8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1C8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1C8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1C8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1C8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1C8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1C8 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1CC "PIO519,Digital I/O control for port 5 pins PIO5_19"
bitfld.long 0x1CC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1CC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1CC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1CC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1CC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1CC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1CC 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1D0 "PIO520,Digital I/O control for port 5 pins PIO5_20"
bitfld.long 0x1D0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1D0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1D0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1D0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1D0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1D0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1D0 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1D4 "PIO521,Digital I/O control for port 5 pins PIO5_21"
bitfld.long 0x1D4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1D4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1D4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1D4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1D4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1D4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1D4 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1D8 "PIO522,Digital I/O control for port 5 pins PIO5_22"
bitfld.long 0x1D8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1D8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1D8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1D8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1D8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1D8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1D8 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1DC "PIO523,Digital I/O control for port 5 pins PIO5_23"
bitfld.long 0x1DC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1DC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1DC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1DC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1DC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1DC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1DC 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1E0 "PIO524,Digital I/O control for port 5 pins PIO5_24"
bitfld.long 0x1E0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1E0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1E0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1E0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1E0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1E0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1E0 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1E4 "PIO525,Digital I/O control for port 5 pins PIO5_25"
bitfld.long 0x1E4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1E4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1E4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1E4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1E4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1E4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1E4 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1E8 "PIO526,Digital I/O control for port 5 pins PIO5_26"
bitfld.long 0x1E8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1E8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1E8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1E8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1E8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1E8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1E8 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1EC "PIO527,Digital I/O control for port 5 pins PIO5_27"
bitfld.long 0x1EC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1EC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1EC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1EC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1EC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1EC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1EC 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1F0 "PIO528,Digital I/O control for port 5 pins PIO5_28"
bitfld.long 0x1F0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1F0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1F0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1F0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1F0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1F0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1F0 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1F4 "PIO529,Digital I/O control for port 5 pins PIO5_29"
bitfld.long 0x1F4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1F4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1F4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1F4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1F4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1F4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1F4 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1F8 "PIO530,Digital I/O control for port 5 pins PIO5_30"
bitfld.long 0x1F8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1F8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1F8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1F8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1F8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1F8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1F8 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1FC "PIO531,Digital I/O control for port 5 pins PIO5_31"
bitfld.long 0x1FC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1FC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1FC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1FC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1FC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1FC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1FC 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54618*"))
group.long 0x100++0x1FF
line.long 0x0 "PIO20,Digital I/O control for port 2 pins PIO2_0"
bitfld.long 0x0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x0 0.--3. 1. "FUNC,Selects pin function."
line.long 0x4 "PIO21,Digital I/O control for port 2 pins PIO2_1"
bitfld.long 0x4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x4 0.--3. 1. "FUNC,Selects pin function."
line.long 0x8 "PIO22,Digital I/O control for port 2 pins PIO2_2"
bitfld.long 0x8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x8 0.--3. 1. "FUNC,Selects pin function."
line.long 0xC "PIO23,Digital I/O control for port 2 pins PIO2_3"
bitfld.long 0xC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xC 0.--3. 1. "FUNC,Selects pin function."
line.long 0x10 "PIO24,Digital I/O control for port 2 pins PIO2_4"
bitfld.long 0x10 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x10 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x10 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x10 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x10 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x10 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x10 0.--3. 1. "FUNC,Selects pin function."
line.long 0x14 "PIO25,Digital I/O control for port 2 pins PIO2_5"
bitfld.long 0x14 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x14 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x14 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x14 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x14 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x14 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x14 0.--3. 1. "FUNC,Selects pin function."
line.long 0x18 "PIO26,Digital I/O control for port 2 pins PIO2_6"
bitfld.long 0x18 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x18 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x18 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x18 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x18 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x18 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x18 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1C "PIO27,Digital I/O control for port 2 pins PIO2_7"
bitfld.long 0x1C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x20 "PIO28,Digital I/O control for port 2 pins PIO2_8"
bitfld.long 0x20 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x20 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x20 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x20 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x20 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x20 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x20 0.--3. 1. "FUNC,Selects pin function."
line.long 0x24 "PIO29,Digital I/O control for port 2 pins PIO2_9"
bitfld.long 0x24 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x24 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x24 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x24 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x24 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x24 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x24 0.--3. 1. "FUNC,Selects pin function."
line.long 0x28 "PIO210,Digital I/O control for port 2 pins PIO2_10"
bitfld.long 0x28 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x28 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x28 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x28 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x28 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x28 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x28 0.--3. 1. "FUNC,Selects pin function."
line.long 0x2C "PIO211,Digital I/O control for port 2 pins PIO2_11"
bitfld.long 0x2C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x2C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x2C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x2C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x2C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x2C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x2C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x30 "PIO212,Digital I/O control for port 2 pins PIO2_12"
bitfld.long 0x30 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x30 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x30 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x30 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x30 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x30 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x30 0.--3. 1. "FUNC,Selects pin function."
line.long 0x34 "PIO213,Digital I/O control for port 2 pins PIO2_13"
bitfld.long 0x34 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x34 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x34 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x34 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x34 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x34 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x34 0.--3. 1. "FUNC,Selects pin function."
line.long 0x38 "PIO214,Digital I/O control for port 2 pins PIO2_14"
bitfld.long 0x38 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x38 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x38 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x38 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x38 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x38 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x38 0.--3. 1. "FUNC,Selects pin function."
line.long 0x3C "PIO215,Digital I/O control for port 2 pins PIO2_15"
bitfld.long 0x3C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x3C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x3C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x3C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x3C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x3C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x3C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x40 "PIO216,Digital I/O control for port 2 pins PIO2_16"
bitfld.long 0x40 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x40 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x40 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x40 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x40 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x40 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x40 0.--3. 1. "FUNC,Selects pin function."
line.long 0x44 "PIO217,Digital I/O control for port 2 pins PIO2_17"
bitfld.long 0x44 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x44 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x44 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x44 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x44 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x44 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x44 0.--3. 1. "FUNC,Selects pin function."
line.long 0x48 "PIO218,Digital I/O control for port 2 pins PIO2_18"
bitfld.long 0x48 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x48 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x48 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x48 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x48 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x48 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x48 0.--3. 1. "FUNC,Selects pin function."
line.long 0x4C "PIO219,Digital I/O control for port 2 pins PIO2_19"
bitfld.long 0x4C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x4C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x4C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x4C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x4C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x4C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x4C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x50 "PIO220,Digital I/O control for port 2 pins PIO2_20"
bitfld.long 0x50 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x50 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x50 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x50 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x50 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x50 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x50 0.--3. 1. "FUNC,Selects pin function."
line.long 0x54 "PIO221,Digital I/O control for port 2 pins PIO2_21"
bitfld.long 0x54 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x54 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x54 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x54 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x54 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x54 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x54 0.--3. 1. "FUNC,Selects pin function."
line.long 0x58 "PIO222,Digital I/O control for port 2 pins PIO2_22"
bitfld.long 0x58 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x58 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x58 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x58 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x58 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x58 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x58 0.--3. 1. "FUNC,Selects pin function."
line.long 0x5C "PIO223,Digital I/O control for port 2 pins PIO2_23"
bitfld.long 0x5C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x5C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x5C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x5C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x5C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x5C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x5C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x60 "PIO224,Digital I/O control for port 2 pins PIO2_24"
bitfld.long 0x60 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x60 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x60 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x60 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x60 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x60 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x60 0.--3. 1. "FUNC,Selects pin function."
line.long 0x64 "PIO225,Digital I/O control for port 2 pins PIO2_25"
bitfld.long 0x64 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x64 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x64 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x64 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x64 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x64 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x64 0.--3. 1. "FUNC,Selects pin function."
line.long 0x68 "PIO226,Digital I/O control for port 2 pins PIO2_26"
bitfld.long 0x68 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x68 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x68 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x68 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x68 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x68 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x68 0.--3. 1. "FUNC,Selects pin function."
line.long 0x6C "PIO227,Digital I/O control for port 2 pins PIO2_27"
bitfld.long 0x6C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x6C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x6C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x6C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x6C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x6C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x6C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x70 "PIO228,Digital I/O control for port 2 pins PIO2_28"
bitfld.long 0x70 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x70 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x70 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x70 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x70 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x70 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x70 0.--3. 1. "FUNC,Selects pin function."
line.long 0x74 "PIO229,Digital I/O control for port 2 pins PIO2_29"
bitfld.long 0x74 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x74 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x74 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x74 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x74 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x74 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x74 0.--3. 1. "FUNC,Selects pin function."
line.long 0x78 "PIO230,Digital I/O control for port 2 pins PIO2_30"
bitfld.long 0x78 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x78 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x78 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x78 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x78 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x78 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x78 0.--3. 1. "FUNC,Selects pin function."
line.long 0x7C "PIO231,Digital I/O control for port 2 pins PIO2_31"
bitfld.long 0x7C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x7C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x7C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x7C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x7C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x7C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x7C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x80 "PIO30,Digital I/O control for port 3 pins PIO3_0"
bitfld.long 0x80 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x80 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x80 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x80 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x80 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x80 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x80 0.--3. 1. "FUNC,Selects pin function."
line.long 0x84 "PIO31,Digital I/O control for port 3 pins PIO3_1"
bitfld.long 0x84 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x84 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x84 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x84 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x84 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x84 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x84 0.--3. 1. "FUNC,Selects pin function."
line.long 0x88 "PIO32,Digital I/O control for port 3 pins PIO3_2"
bitfld.long 0x88 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x88 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x88 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x88 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x88 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x88 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x88 0.--3. 1. "FUNC,Selects pin function."
line.long 0x8C "PIO33,Digital I/O control for port 3 pins PIO3_3"
bitfld.long 0x8C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x8C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x8C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x8C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x8C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x8C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x8C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x90 "PIO34,Digital I/O control for port 3 pins PIO3_4"
bitfld.long 0x90 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x90 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x90 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x90 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x90 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x90 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x90 0.--3. 1. "FUNC,Selects pin function."
line.long 0x94 "PIO35,Digital I/O control for port 3 pins PIO3_5"
bitfld.long 0x94 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x94 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x94 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x94 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x94 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x94 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x94 0.--3. 1. "FUNC,Selects pin function."
line.long 0x98 "PIO36,Digital I/O control for port 3 pins PIO3_6"
bitfld.long 0x98 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x98 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x98 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x98 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x98 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x98 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x98 0.--3. 1. "FUNC,Selects pin function."
line.long 0x9C "PIO37,Digital I/O control for port 3 pins PIO3_7"
bitfld.long 0x9C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x9C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x9C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x9C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x9C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x9C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x9C 0.--3. 1. "FUNC,Selects pin function."
line.long 0xA0 "PIO38,Digital I/O control for port 3 pins PIO3_8"
bitfld.long 0xA0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xA0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xA0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xA0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xA0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xA0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xA0 0.--3. 1. "FUNC,Selects pin function."
line.long 0xA4 "PIO39,Digital I/O control for port 3 pins PIO3_9"
bitfld.long 0xA4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xA4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xA4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xA4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xA4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xA4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xA4 0.--3. 1. "FUNC,Selects pin function."
line.long 0xA8 "PIO310,Digital I/O control for port 3 pins PIO3_10"
bitfld.long 0xA8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xA8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xA8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xA8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xA8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xA8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xA8 0.--3. 1. "FUNC,Selects pin function."
line.long 0xAC "PIO311,Digital I/O control for port 3 pins PIO3_11"
bitfld.long 0xAC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xAC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xAC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xAC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xAC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xAC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xAC 0.--3. 1. "FUNC,Selects pin function."
line.long 0xB0 "PIO312,Digital I/O control for port 3 pins PIO3_12"
bitfld.long 0xB0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xB0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xB0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xB0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xB0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xB0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xB0 0.--3. 1. "FUNC,Selects pin function."
line.long 0xB4 "PIO313,Digital I/O control for port 3 pins PIO3_13"
bitfld.long 0xB4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xB4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xB4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xB4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xB4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xB4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xB4 0.--3. 1. "FUNC,Selects pin function."
line.long 0xB8 "PIO314,Digital I/O control for port 3 pins PIO3_14"
bitfld.long 0xB8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xB8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xB8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xB8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xB8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xB8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xB8 0.--3. 1. "FUNC,Selects pin function."
line.long 0xBC "PIO315,Digital I/O control for port 3 pins PIO3_15"
bitfld.long 0xBC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xBC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xBC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xBC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xBC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xBC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xBC 0.--3. 1. "FUNC,Selects pin function."
line.long 0xC0 "PIO316,Digital I/O control for port 3 pins PIO3_16"
bitfld.long 0xC0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xC0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xC0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xC0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xC0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xC0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xC0 0.--3. 1. "FUNC,Selects pin function."
line.long 0xC4 "PIO317,Digital I/O control for port 3 pins PIO3_17"
bitfld.long 0xC4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xC4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xC4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xC4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xC4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xC4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xC4 0.--3. 1. "FUNC,Selects pin function."
line.long 0xC8 "PIO318,Digital I/O control for port 3 pins PIO3_18"
bitfld.long 0xC8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xC8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xC8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xC8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xC8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xC8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xC8 0.--3. 1. "FUNC,Selects pin function."
line.long 0xCC "PIO319,Digital I/O control for port 3 pins PIO3_19"
bitfld.long 0xCC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xCC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xCC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xCC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xCC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xCC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xCC 0.--3. 1. "FUNC,Selects pin function."
line.long 0xD0 "PIO320,Digital I/O control for port 3 pins PIO3_20"
bitfld.long 0xD0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xD0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xD0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xD0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xD0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xD0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xD0 0.--3. 1. "FUNC,Selects pin function."
line.long 0xD4 "PIO321,Digital I/O control for port 3 pins PIO3_21"
bitfld.long 0xD4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xD4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xD4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xD4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xD4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xD4 0.--3. 1. "FUNC,Selects pin function."
line.long 0xD8 "PIO322,Digital I/O control for port 3 pins PIO3_22"
bitfld.long 0xD8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xD8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xD8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xD8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xD8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xD8 0.--3. 1. "FUNC,Selects pin function."
line.long 0xDC "PIO323,Digital I/O control for port 3 pins PIO3_23"
bitfld.long 0xDC 11. "I2CFILTER,Configures I2C features for standard mode  fast mode  and Fast Mode Plus operation." "0: Enabled. I2C 50 ns glitch filter enabled.,1: Disabled. I2C 50 ns glitch filter disabled."
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bitfld.long 0xDC 10. "I2CDRIVE,Controls the current sink capability of the pin." "0: Low drive. Output drive sink is 4 mA. This is..,1: High drive. Output drive sink is 20 mA. This is.."
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bitfld.long 0xDC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xDC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xDC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xDC 6. "I2CSLEW,Controls slew rate of I2C pad." "0: I2C mode.,1: GPIO mode."
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hexmask.long.byte 0xDC 0.--3. 1. "FUNC,Selects pin function."
line.long 0xE0 "PIO324,Digital I/O control for port 3 pins PIO3_24"
bitfld.long 0xE0 11. "I2CFILTER,Configures I2C features for standard mode  fast mode  and Fast Mode Plus operation." "0: Enabled. I2C 50 ns glitch filter enabled.,1: Disabled. I2C 50 ns glitch filter disabled."
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bitfld.long 0xE0 10. "I2CDRIVE,Controls the current sink capability of the pin." "0: Low drive. Output drive sink is 4 mA. This is..,1: High drive. Output drive sink is 20 mA. This is.."
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bitfld.long 0xE0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xE0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xE0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xE0 6. "I2CSLEW,Controls slew rate of I2C pad." "0: I2C mode.,1: GPIO mode."
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hexmask.long.byte 0xE0 0.--3. 1. "FUNC,Selects pin function."
line.long 0xE4 "PIO325,Digital I/O control for port 3 pins PIO3_25"
bitfld.long 0xE4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xE4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xE4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xE4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xE4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xE4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xE4 0.--3. 1. "FUNC,Selects pin function."
line.long 0xE8 "PIO326,Digital I/O control for port 3 pins PIO3_26"
bitfld.long 0xE8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xE8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xE8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xE8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xE8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xE8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xE8 0.--3. 1. "FUNC,Selects pin function."
line.long 0xEC "PIO327,Digital I/O control for port 3 pins PIO3_27"
bitfld.long 0xEC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xEC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xEC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xEC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xEC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xEC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xEC 0.--3. 1. "FUNC,Selects pin function."
line.long 0xF0 "PIO328,Digital I/O control for port 3 pins PIO3_28"
bitfld.long 0xF0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xF0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xF0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xF0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xF0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xF0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xF0 0.--3. 1. "FUNC,Selects pin function."
line.long 0xF4 "PIO329,Digital I/O control for port 3 pins PIO3_29"
bitfld.long 0xF4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xF4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xF4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xF4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xF4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xF4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xF4 0.--3. 1. "FUNC,Selects pin function."
line.long 0xF8 "PIO330,Digital I/O control for port 3 pins PIO3_30"
bitfld.long 0xF8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xF8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xF8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xF8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xF8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xF8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xF8 0.--3. 1. "FUNC,Selects pin function."
line.long 0xFC "PIO331,Digital I/O control for port 3 pins PIO3_31"
bitfld.long 0xFC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xFC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xFC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xFC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xFC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xFC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xFC 0.--3. 1. "FUNC,Selects pin function."
line.long 0x100 "PIO40,Digital I/O control for port 4 pins PIO4_0"
bitfld.long 0x100 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x100 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x100 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x100 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x100 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x100 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x100 0.--3. 1. "FUNC,Selects pin function."
line.long 0x104 "PIO41,Digital I/O control for port 4 pins PIO4_1"
bitfld.long 0x104 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x104 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x104 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x104 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x104 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x104 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x104 0.--3. 1. "FUNC,Selects pin function."
line.long 0x108 "PIO42,Digital I/O control for port 4 pins PIO4_2"
bitfld.long 0x108 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x108 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x108 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x108 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x108 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x108 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x108 0.--3. 1. "FUNC,Selects pin function."
line.long 0x10C "PIO43,Digital I/O control for port 4 pins PIO4_3"
bitfld.long 0x10C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x10C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x10C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x10C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x10C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x10C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x10C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x110 "PIO44,Digital I/O control for port 4 pins PIO4_4"
bitfld.long 0x110 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x110 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x110 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x110 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x110 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x110 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x110 0.--3. 1. "FUNC,Selects pin function."
line.long 0x114 "PIO45,Digital I/O control for port 4 pins PIO4_5"
bitfld.long 0x114 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x114 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x114 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x114 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x114 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x114 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x114 0.--3. 1. "FUNC,Selects pin function."
line.long 0x118 "PIO46,Digital I/O control for port 4 pins PIO4_6"
bitfld.long 0x118 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x118 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x118 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x118 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x118 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x118 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x118 0.--3. 1. "FUNC,Selects pin function."
line.long 0x11C "PIO47,Digital I/O control for port 4 pins PIO4_7"
bitfld.long 0x11C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x11C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x11C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x11C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x11C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x11C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x11C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x120 "PIO48,Digital I/O control for port 4 pins PIO4_8"
bitfld.long 0x120 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x120 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x120 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x120 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x120 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x120 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x120 0.--3. 1. "FUNC,Selects pin function."
line.long 0x124 "PIO49,Digital I/O control for port 4 pins PIO4_9"
bitfld.long 0x124 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x124 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x124 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x124 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x124 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x124 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x124 0.--3. 1. "FUNC,Selects pin function."
line.long 0x128 "PIO410,Digital I/O control for port 4 pins PIO4_10"
bitfld.long 0x128 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x128 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x128 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x128 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x128 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x128 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x128 0.--3. 1. "FUNC,Selects pin function."
line.long 0x12C "PIO411,Digital I/O control for port 4 pins PIO4_11"
bitfld.long 0x12C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x12C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x12C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x12C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x12C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x12C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x12C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x130 "PIO412,Digital I/O control for port 4 pins PIO4_12"
bitfld.long 0x130 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x130 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x130 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x130 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x130 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x130 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x130 0.--3. 1. "FUNC,Selects pin function."
line.long 0x134 "PIO413,Digital I/O control for port 4 pins PIO4_13"
bitfld.long 0x134 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x134 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x134 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x134 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x134 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x134 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x134 0.--3. 1. "FUNC,Selects pin function."
line.long 0x138 "PIO414,Digital I/O control for port 4 pins PIO4_14"
bitfld.long 0x138 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x138 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x138 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x138 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x138 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x138 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x138 0.--3. 1. "FUNC,Selects pin function."
line.long 0x13C "PIO415,Digital I/O control for port 4 pins PIO4_15"
bitfld.long 0x13C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x13C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x13C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x13C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x13C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x13C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x13C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x140 "PIO416,Digital I/O control for port 4 pins PIO4_16"
bitfld.long 0x140 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x140 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x140 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x140 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x140 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x140 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x140 0.--3. 1. "FUNC,Selects pin function."
line.long 0x144 "PIO417,Digital I/O control for port 4 pins PIO4_17"
bitfld.long 0x144 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x144 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x144 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x144 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x144 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x144 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x144 0.--3. 1. "FUNC,Selects pin function."
line.long 0x148 "PIO418,Digital I/O control for port 4 pins PIO4_18"
bitfld.long 0x148 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x148 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x148 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x148 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x148 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x148 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x148 0.--3. 1. "FUNC,Selects pin function."
line.long 0x14C "PIO419,Digital I/O control for port 4 pins PIO4_19"
bitfld.long 0x14C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x14C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x14C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x14C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x14C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x14C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x14C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x150 "PIO420,Digital I/O control for port 4 pins PIO4_20"
bitfld.long 0x150 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x150 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x150 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x150 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x150 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x150 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x150 0.--3. 1. "FUNC,Selects pin function."
line.long 0x154 "PIO421,Digital I/O control for port 4 pins PIO4_21"
bitfld.long 0x154 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x154 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x154 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x154 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x154 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x154 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x154 0.--3. 1. "FUNC,Selects pin function."
line.long 0x158 "PIO422,Digital I/O control for port 4 pins PIO4_22"
bitfld.long 0x158 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x158 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x158 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x158 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x158 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x158 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x158 0.--3. 1. "FUNC,Selects pin function."
line.long 0x15C "PIO423,Digital I/O control for port 4 pins PIO4_23"
bitfld.long 0x15C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x15C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x15C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x15C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x15C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x15C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x15C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x160 "PIO424,Digital I/O control for port 4 pins PIO4_24"
bitfld.long 0x160 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x160 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x160 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x160 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x160 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x160 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x160 0.--3. 1. "FUNC,Selects pin function."
line.long 0x164 "PIO425,Digital I/O control for port 4 pins PIO4_25"
bitfld.long 0x164 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x164 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x164 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x164 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x164 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x164 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x164 0.--3. 1. "FUNC,Selects pin function."
line.long 0x168 "PIO426,Digital I/O control for port 4 pins PIO4_26"
bitfld.long 0x168 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x168 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x168 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x168 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x168 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x168 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x168 0.--3. 1. "FUNC,Selects pin function."
line.long 0x16C "PIO427,Digital I/O control for port 4 pins PIO4_27"
bitfld.long 0x16C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x16C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x16C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x16C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x16C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x16C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x16C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x170 "PIO428,Digital I/O control for port 4 pins PIO4_28"
bitfld.long 0x170 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x170 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x170 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x170 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x170 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x170 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x170 0.--3. 1. "FUNC,Selects pin function."
line.long 0x174 "PIO429,Digital I/O control for port 4 pins PIO4_29"
bitfld.long 0x174 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x174 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x174 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x174 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x174 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x174 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x174 0.--3. 1. "FUNC,Selects pin function."
line.long 0x178 "PIO430,Digital I/O control for port 4 pins PIO4_30"
bitfld.long 0x178 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x178 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x178 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x178 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x178 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x178 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x178 0.--3. 1. "FUNC,Selects pin function."
line.long 0x17C "PIO431,Digital I/O control for port 4 pins PIO4_31"
bitfld.long 0x17C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x17C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x17C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x17C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x17C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x17C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x17C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x180 "PIO50,Digital I/O control for port 5 pins PIO5_0"
bitfld.long 0x180 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x180 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x180 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x180 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x180 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x180 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x180 0.--3. 1. "FUNC,Selects pin function."
line.long 0x184 "PIO51,Digital I/O control for port 5 pins PIO5_1"
bitfld.long 0x184 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x184 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x184 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x184 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x184 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x184 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x184 0.--3. 1. "FUNC,Selects pin function."
line.long 0x188 "PIO52,Digital I/O control for port 5 pins PIO5_2"
bitfld.long 0x188 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x188 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x188 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x188 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x188 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x188 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x188 0.--3. 1. "FUNC,Selects pin function."
line.long 0x18C "PIO53,Digital I/O control for port 5 pins PIO5_3"
bitfld.long 0x18C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x18C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x18C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x18C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x18C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x18C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x18C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x190 "PIO54,Digital I/O control for port 5 pins PIO5_4"
bitfld.long 0x190 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x190 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x190 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x190 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x190 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x190 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x190 0.--3. 1. "FUNC,Selects pin function."
line.long 0x194 "PIO55,Digital I/O control for port 5 pins PIO5_5"
bitfld.long 0x194 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x194 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x194 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x194 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x194 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x194 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x194 0.--3. 1. "FUNC,Selects pin function."
line.long 0x198 "PIO56,Digital I/O control for port 5 pins PIO5_6"
bitfld.long 0x198 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x198 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x198 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x198 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x198 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x198 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x198 0.--3. 1. "FUNC,Selects pin function."
line.long 0x19C "PIO57,Digital I/O control for port 5 pins PIO5_7"
bitfld.long 0x19C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x19C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x19C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x19C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x19C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x19C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x19C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1A0 "PIO58,Digital I/O control for port 5 pins PIO5_8"
bitfld.long 0x1A0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1A0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1A0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1A0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1A0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1A0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x1A0 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1A4 "PIO59,Digital I/O control for port 5 pins PIO5_9"
bitfld.long 0x1A4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1A4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1A4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1A4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1A4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1A4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x1A4 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1A8 "PIO510,Digital I/O control for port 5 pins PIO5_10"
bitfld.long 0x1A8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1A8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1A8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1A8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1A8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1A8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1A8 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1AC "PIO511,Digital I/O control for port 5 pins PIO5_11"
bitfld.long 0x1AC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1AC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1AC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1AC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1AC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1AC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1AC 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1B0 "PIO512,Digital I/O control for port 5 pins PIO5_12"
bitfld.long 0x1B0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1B0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1B0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1B0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1B0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1B0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1B0 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1B4 "PIO513,Digital I/O control for port 5 pins PIO5_13"
bitfld.long 0x1B4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1B4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1B4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1B4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1B4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1B4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1B4 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1B8 "PIO514,Digital I/O control for port 5 pins PIO5_14"
bitfld.long 0x1B8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1B8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1B8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1B8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1B8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1B8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1B8 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1BC "PIO515,Digital I/O control for port 5 pins PIO5_15"
bitfld.long 0x1BC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1BC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1BC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1BC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1BC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1BC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1BC 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1C0 "PIO516,Digital I/O control for port 5 pins PIO5_16"
bitfld.long 0x1C0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1C0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1C0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1C0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1C0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1C0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1C0 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1C4 "PIO517,Digital I/O control for port 5 pins PIO5_17"
bitfld.long 0x1C4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1C4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1C4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1C4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1C4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1C4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1C4 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1C8 "PIO518,Digital I/O control for port 5 pins PIO5_18"
bitfld.long 0x1C8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1C8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1C8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1C8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1C8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1C8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1C8 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1CC "PIO519,Digital I/O control for port 5 pins PIO5_19"
bitfld.long 0x1CC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1CC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1CC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1CC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1CC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1CC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1CC 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1D0 "PIO520,Digital I/O control for port 5 pins PIO5_20"
bitfld.long 0x1D0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1D0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1D0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1D0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1D0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1D0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1D0 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1D4 "PIO521,Digital I/O control for port 5 pins PIO5_21"
bitfld.long 0x1D4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1D4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1D4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1D4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1D4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1D4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1D4 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1D8 "PIO522,Digital I/O control for port 5 pins PIO5_22"
bitfld.long 0x1D8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1D8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1D8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1D8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1D8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1D8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1D8 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1DC "PIO523,Digital I/O control for port 5 pins PIO5_23"
bitfld.long 0x1DC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1DC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1DC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1DC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1DC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1DC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1DC 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1E0 "PIO524,Digital I/O control for port 5 pins PIO5_24"
bitfld.long 0x1E0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1E0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1E0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1E0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1E0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1E0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1E0 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1E4 "PIO525,Digital I/O control for port 5 pins PIO5_25"
bitfld.long 0x1E4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1E4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1E4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1E4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1E4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1E4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1E4 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1E8 "PIO526,Digital I/O control for port 5 pins PIO5_26"
bitfld.long 0x1E8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1E8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1E8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1E8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1E8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1E8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1E8 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1EC "PIO527,Digital I/O control for port 5 pins PIO5_27"
bitfld.long 0x1EC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1EC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1EC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1EC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1EC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1EC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1EC 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1F0 "PIO528,Digital I/O control for port 5 pins PIO5_28"
bitfld.long 0x1F0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1F0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1F0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1F0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1F0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1F0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1F0 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1F4 "PIO529,Digital I/O control for port 5 pins PIO5_29"
bitfld.long 0x1F4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1F4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1F4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1F4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1F4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1F4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1F4 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1F8 "PIO530,Digital I/O control for port 5 pins PIO5_30"
bitfld.long 0x1F8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1F8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1F8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1F8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1F8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1F8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1F8 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1FC "PIO531,Digital I/O control for port 5 pins PIO5_31"
bitfld.long 0x1FC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1FC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1FC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1FC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1FC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1FC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1FC 0.--3. 1. "FUNC,Selects pin function."
endif
sif (cpuis("LPC54628*"))
group.long 0x100++0x1FF
line.long 0x0 "PIO20,Digital I/O control for port 2 pins PIO2_0"
bitfld.long 0x0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x0 0.--3. 1. "FUNC,Selects pin function."
line.long 0x4 "PIO21,Digital I/O control for port 2 pins PIO2_1"
bitfld.long 0x4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x4 0.--3. 1. "FUNC,Selects pin function."
line.long 0x8 "PIO22,Digital I/O control for port 2 pins PIO2_2"
bitfld.long 0x8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x8 0.--3. 1. "FUNC,Selects pin function."
line.long 0xC "PIO23,Digital I/O control for port 2 pins PIO2_3"
bitfld.long 0xC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0xC 0.--3. 1. "FUNC,Selects pin function."
line.long 0x10 "PIO24,Digital I/O control for port 2 pins PIO2_4"
bitfld.long 0x10 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x10 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x10 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x10 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x10 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x10 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x10 0.--3. 1. "FUNC,Selects pin function."
line.long 0x14 "PIO25,Digital I/O control for port 2 pins PIO2_5"
bitfld.long 0x14 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x14 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x14 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x14 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x14 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x14 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x14 0.--3. 1. "FUNC,Selects pin function."
line.long 0x18 "PIO26,Digital I/O control for port 2 pins PIO2_6"
bitfld.long 0x18 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x18 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x18 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x18 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x18 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x18 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x18 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1C "PIO27,Digital I/O control for port 2 pins PIO2_7"
bitfld.long 0x1C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x20 "PIO28,Digital I/O control for port 2 pins PIO2_8"
bitfld.long 0x20 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x20 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x20 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x20 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x20 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x20 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x20 0.--3. 1. "FUNC,Selects pin function."
line.long 0x24 "PIO29,Digital I/O control for port 2 pins PIO2_9"
bitfld.long 0x24 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x24 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x24 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x24 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x24 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x24 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x24 0.--3. 1. "FUNC,Selects pin function."
line.long 0x28 "PIO210,Digital I/O control for port 2 pins PIO2_10"
bitfld.long 0x28 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x28 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x28 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x28 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x28 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x28 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x28 0.--3. 1. "FUNC,Selects pin function."
line.long 0x2C "PIO211,Digital I/O control for port 2 pins PIO2_11"
bitfld.long 0x2C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x2C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x2C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x2C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x2C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x2C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x2C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x30 "PIO212,Digital I/O control for port 2 pins PIO2_12"
bitfld.long 0x30 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x30 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x30 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x30 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x30 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x30 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x30 0.--3. 1. "FUNC,Selects pin function."
line.long 0x34 "PIO213,Digital I/O control for port 2 pins PIO2_13"
bitfld.long 0x34 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x34 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x34 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x34 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x34 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x34 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x34 0.--3. 1. "FUNC,Selects pin function."
line.long 0x38 "PIO214,Digital I/O control for port 2 pins PIO2_14"
bitfld.long 0x38 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x38 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x38 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x38 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x38 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x38 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x38 0.--3. 1. "FUNC,Selects pin function."
line.long 0x3C "PIO215,Digital I/O control for port 2 pins PIO2_15"
bitfld.long 0x3C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x3C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x3C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x3C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x3C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x3C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x3C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x40 "PIO216,Digital I/O control for port 2 pins PIO2_16"
bitfld.long 0x40 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x40 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x40 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x40 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x40 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x40 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x40 0.--3. 1. "FUNC,Selects pin function."
line.long 0x44 "PIO217,Digital I/O control for port 2 pins PIO2_17"
bitfld.long 0x44 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x44 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x44 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x44 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x44 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x44 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x44 0.--3. 1. "FUNC,Selects pin function."
line.long 0x48 "PIO218,Digital I/O control for port 2 pins PIO2_18"
bitfld.long 0x48 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x48 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x48 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x48 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x48 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x48 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x48 0.--3. 1. "FUNC,Selects pin function."
line.long 0x4C "PIO219,Digital I/O control for port 2 pins PIO2_19"
bitfld.long 0x4C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x4C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x4C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x4C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x4C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x4C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x4C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x50 "PIO220,Digital I/O control for port 2 pins PIO2_20"
bitfld.long 0x50 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x50 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x50 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x50 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x50 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x50 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x50 0.--3. 1. "FUNC,Selects pin function."
line.long 0x54 "PIO221,Digital I/O control for port 2 pins PIO2_21"
bitfld.long 0x54 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x54 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x54 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x54 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x54 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x54 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x54 0.--3. 1. "FUNC,Selects pin function."
line.long 0x58 "PIO222,Digital I/O control for port 2 pins PIO2_22"
bitfld.long 0x58 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x58 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x58 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x58 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x58 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x58 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x58 0.--3. 1. "FUNC,Selects pin function."
line.long 0x5C "PIO223,Digital I/O control for port 2 pins PIO2_23"
bitfld.long 0x5C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x5C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x5C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x5C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x5C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x5C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x5C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x60 "PIO224,Digital I/O control for port 2 pins PIO2_24"
bitfld.long 0x60 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x60 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x60 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x60 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x60 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x60 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x60 0.--3. 1. "FUNC,Selects pin function."
line.long 0x64 "PIO225,Digital I/O control for port 2 pins PIO2_25"
bitfld.long 0x64 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x64 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x64 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x64 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x64 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x64 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x64 0.--3. 1. "FUNC,Selects pin function."
line.long 0x68 "PIO226,Digital I/O control for port 2 pins PIO2_26"
bitfld.long 0x68 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x68 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x68 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x68 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x68 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x68 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x68 0.--3. 1. "FUNC,Selects pin function."
line.long 0x6C "PIO227,Digital I/O control for port 2 pins PIO2_27"
bitfld.long 0x6C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x6C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x6C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x6C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x6C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x6C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x6C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x70 "PIO228,Digital I/O control for port 2 pins PIO2_28"
bitfld.long 0x70 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x70 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x70 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x70 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x70 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x70 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x70 0.--3. 1. "FUNC,Selects pin function."
line.long 0x74 "PIO229,Digital I/O control for port 2 pins PIO2_29"
bitfld.long 0x74 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x74 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x74 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x74 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x74 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x74 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x74 0.--3. 1. "FUNC,Selects pin function."
line.long 0x78 "PIO230,Digital I/O control for port 2 pins PIO2_30"
bitfld.long 0x78 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x78 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x78 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x78 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x78 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x78 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x78 0.--3. 1. "FUNC,Selects pin function."
line.long 0x7C "PIO231,Digital I/O control for port 2 pins PIO2_31"
bitfld.long 0x7C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x7C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x7C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x7C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x7C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x7C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x7C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x80 "PIO30,Digital I/O control for port 3 pins PIO3_0"
bitfld.long 0x80 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x80 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x80 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x80 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x80 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x80 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x80 0.--3. 1. "FUNC,Selects pin function."
line.long 0x84 "PIO31,Digital I/O control for port 3 pins PIO3_1"
bitfld.long 0x84 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x84 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x84 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x84 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x84 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x84 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x84 0.--3. 1. "FUNC,Selects pin function."
line.long 0x88 "PIO32,Digital I/O control for port 3 pins PIO3_2"
bitfld.long 0x88 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x88 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x88 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x88 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x88 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x88 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x88 0.--3. 1. "FUNC,Selects pin function."
line.long 0x8C "PIO33,Digital I/O control for port 3 pins PIO3_3"
bitfld.long 0x8C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x8C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x8C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x8C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x8C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x8C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x8C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x90 "PIO34,Digital I/O control for port 3 pins PIO3_4"
bitfld.long 0x90 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x90 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x90 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x90 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x90 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x90 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x90 0.--3. 1. "FUNC,Selects pin function."
line.long 0x94 "PIO35,Digital I/O control for port 3 pins PIO3_5"
bitfld.long 0x94 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x94 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x94 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x94 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x94 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x94 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x94 0.--3. 1. "FUNC,Selects pin function."
line.long 0x98 "PIO36,Digital I/O control for port 3 pins PIO3_6"
bitfld.long 0x98 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x98 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x98 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x98 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x98 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x98 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x98 0.--3. 1. "FUNC,Selects pin function."
line.long 0x9C "PIO37,Digital I/O control for port 3 pins PIO3_7"
bitfld.long 0x9C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x9C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x9C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x9C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x9C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x9C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x9C 0.--3. 1. "FUNC,Selects pin function."
line.long 0xA0 "PIO38,Digital I/O control for port 3 pins PIO3_8"
bitfld.long 0xA0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xA0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xA0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xA0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xA0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xA0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xA0 0.--3. 1. "FUNC,Selects pin function."
line.long 0xA4 "PIO39,Digital I/O control for port 3 pins PIO3_9"
bitfld.long 0xA4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xA4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xA4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xA4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xA4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xA4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xA4 0.--3. 1. "FUNC,Selects pin function."
line.long 0xA8 "PIO310,Digital I/O control for port 3 pins PIO3_10"
bitfld.long 0xA8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0xA8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0xA8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0xA8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0xA8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0xA8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xA8 0.--3. 1. "FUNC,Selects pin function."
line.long 0xAC "PIO311,Digital I/O control for port 3 pins PIO3_11"
bitfld.long 0xAC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xAC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xAC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xAC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xAC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xAC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xAC 0.--3. 1. "FUNC,Selects pin function."
line.long 0xB0 "PIO312,Digital I/O control for port 3 pins PIO3_12"
bitfld.long 0xB0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xB0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xB0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xB0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xB0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xB0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xB0 0.--3. 1. "FUNC,Selects pin function."
line.long 0xB4 "PIO313,Digital I/O control for port 3 pins PIO3_13"
bitfld.long 0xB4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xB4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xB4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xB4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xB4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xB4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xB4 0.--3. 1. "FUNC,Selects pin function."
line.long 0xB8 "PIO314,Digital I/O control for port 3 pins PIO3_14"
bitfld.long 0xB8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xB8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xB8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xB8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xB8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xB8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xB8 0.--3. 1. "FUNC,Selects pin function."
line.long 0xBC "PIO315,Digital I/O control for port 3 pins PIO3_15"
bitfld.long 0xBC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xBC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xBC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xBC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xBC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xBC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xBC 0.--3. 1. "FUNC,Selects pin function."
line.long 0xC0 "PIO316,Digital I/O control for port 3 pins PIO3_16"
bitfld.long 0xC0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xC0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xC0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xC0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xC0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xC0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xC0 0.--3. 1. "FUNC,Selects pin function."
line.long 0xC4 "PIO317,Digital I/O control for port 3 pins PIO3_17"
bitfld.long 0xC4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xC4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xC4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xC4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xC4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xC4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xC4 0.--3. 1. "FUNC,Selects pin function."
line.long 0xC8 "PIO318,Digital I/O control for port 3 pins PIO3_18"
bitfld.long 0xC8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xC8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xC8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xC8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xC8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xC8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xC8 0.--3. 1. "FUNC,Selects pin function."
line.long 0xCC "PIO319,Digital I/O control for port 3 pins PIO3_19"
bitfld.long 0xCC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xCC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xCC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xCC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xCC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xCC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xCC 0.--3. 1. "FUNC,Selects pin function."
line.long 0xD0 "PIO320,Digital I/O control for port 3 pins PIO3_20"
bitfld.long 0xD0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xD0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xD0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xD0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xD0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xD0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xD0 0.--3. 1. "FUNC,Selects pin function."
line.long 0xD4 "PIO321,Digital I/O control for port 3 pins PIO3_21"
bitfld.long 0xD4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xD4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xD4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xD4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xD4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xD4 0.--3. 1. "FUNC,Selects pin function."
line.long 0xD8 "PIO322,Digital I/O control for port 3 pins PIO3_22"
bitfld.long 0xD8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xD8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xD8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xD8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xD8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xD8 0.--3. 1. "FUNC,Selects pin function."
line.long 0xDC "PIO323,Digital I/O control for port 3 pins PIO3_23"
bitfld.long 0xDC 11. "I2CFILTER,Configures I2C features for standard mode  fast mode  and Fast Mode Plus operation." "0: Enabled. I2C 50 ns glitch filter enabled.,1: Disabled. I2C 50 ns glitch filter disabled."
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bitfld.long 0xDC 10. "I2CDRIVE,Controls the current sink capability of the pin." "0: Low drive. Output drive sink is 4 mA. This is..,1: High drive. Output drive sink is 20 mA. This is.."
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bitfld.long 0xDC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xDC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xDC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xDC 6. "I2CSLEW,Controls slew rate of I2C pad." "0: I2C mode.,1: GPIO mode."
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hexmask.long.byte 0xDC 0.--3. 1. "FUNC,Selects pin function."
line.long 0xE0 "PIO324,Digital I/O control for port 3 pins PIO3_24"
bitfld.long 0xE0 11. "I2CFILTER,Configures I2C features for standard mode  fast mode  and Fast Mode Plus operation." "0: Enabled. I2C 50 ns glitch filter enabled.,1: Disabled. I2C 50 ns glitch filter disabled."
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bitfld.long 0xE0 10. "I2CDRIVE,Controls the current sink capability of the pin." "0: Low drive. Output drive sink is 4 mA. This is..,1: High drive. Output drive sink is 20 mA. This is.."
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bitfld.long 0xE0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xE0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xE0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xE0 6. "I2CSLEW,Controls slew rate of I2C pad." "0: I2C mode.,1: GPIO mode."
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hexmask.long.byte 0xE0 0.--3. 1. "FUNC,Selects pin function."
line.long 0xE4 "PIO325,Digital I/O control for port 3 pins PIO3_25"
bitfld.long 0xE4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xE4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xE4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xE4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xE4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xE4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xE4 0.--3. 1. "FUNC,Selects pin function."
line.long 0xE8 "PIO326,Digital I/O control for port 3 pins PIO3_26"
bitfld.long 0xE8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xE8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xE8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xE8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xE8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xE8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xE8 0.--3. 1. "FUNC,Selects pin function."
line.long 0xEC "PIO327,Digital I/O control for port 3 pins PIO3_27"
bitfld.long 0xEC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xEC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xEC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xEC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xEC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xEC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xEC 0.--3. 1. "FUNC,Selects pin function."
line.long 0xF0 "PIO328,Digital I/O control for port 3 pins PIO3_28"
bitfld.long 0xF0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xF0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xF0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xF0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xF0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xF0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xF0 0.--3. 1. "FUNC,Selects pin function."
line.long 0xF4 "PIO329,Digital I/O control for port 3 pins PIO3_29"
bitfld.long 0xF4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xF4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xF4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xF4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xF4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xF4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xF4 0.--3. 1. "FUNC,Selects pin function."
line.long 0xF8 "PIO330,Digital I/O control for port 3 pins PIO3_30"
bitfld.long 0xF8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xF8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xF8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xF8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xF8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xF8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xF8 0.--3. 1. "FUNC,Selects pin function."
line.long 0xFC "PIO331,Digital I/O control for port 3 pins PIO3_31"
bitfld.long 0xFC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0xFC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0xFC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0xFC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0xFC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0xFC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0xFC 0.--3. 1. "FUNC,Selects pin function."
line.long 0x100 "PIO40,Digital I/O control for port 4 pins PIO4_0"
bitfld.long 0x100 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x100 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x100 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x100 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x100 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x100 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x100 0.--3. 1. "FUNC,Selects pin function."
line.long 0x104 "PIO41,Digital I/O control for port 4 pins PIO4_1"
bitfld.long 0x104 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x104 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x104 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x104 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x104 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x104 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x104 0.--3. 1. "FUNC,Selects pin function."
line.long 0x108 "PIO42,Digital I/O control for port 4 pins PIO4_2"
bitfld.long 0x108 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x108 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x108 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x108 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x108 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x108 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x108 0.--3. 1. "FUNC,Selects pin function."
line.long 0x10C "PIO43,Digital I/O control for port 4 pins PIO4_3"
bitfld.long 0x10C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x10C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x10C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x10C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x10C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x10C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x10C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x110 "PIO44,Digital I/O control for port 4 pins PIO4_4"
bitfld.long 0x110 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x110 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x110 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x110 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x110 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x110 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x110 0.--3. 1. "FUNC,Selects pin function."
line.long 0x114 "PIO45,Digital I/O control for port 4 pins PIO4_5"
bitfld.long 0x114 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x114 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x114 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x114 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x114 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x114 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x114 0.--3. 1. "FUNC,Selects pin function."
line.long 0x118 "PIO46,Digital I/O control for port 4 pins PIO4_6"
bitfld.long 0x118 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x118 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x118 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x118 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x118 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x118 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x118 0.--3. 1. "FUNC,Selects pin function."
line.long 0x11C "PIO47,Digital I/O control for port 4 pins PIO4_7"
bitfld.long 0x11C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x11C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x11C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x11C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x11C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x11C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x11C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x120 "PIO48,Digital I/O control for port 4 pins PIO4_8"
bitfld.long 0x120 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x120 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x120 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x120 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x120 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x120 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x120 0.--3. 1. "FUNC,Selects pin function."
line.long 0x124 "PIO49,Digital I/O control for port 4 pins PIO4_9"
bitfld.long 0x124 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x124 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x124 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x124 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x124 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x124 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x124 0.--3. 1. "FUNC,Selects pin function."
line.long 0x128 "PIO410,Digital I/O control for port 4 pins PIO4_10"
bitfld.long 0x128 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x128 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x128 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x128 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x128 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x128 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x128 0.--3. 1. "FUNC,Selects pin function."
line.long 0x12C "PIO411,Digital I/O control for port 4 pins PIO4_11"
bitfld.long 0x12C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x12C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x12C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x12C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x12C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x12C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x12C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x130 "PIO412,Digital I/O control for port 4 pins PIO4_12"
bitfld.long 0x130 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x130 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x130 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x130 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x130 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x130 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x130 0.--3. 1. "FUNC,Selects pin function."
line.long 0x134 "PIO413,Digital I/O control for port 4 pins PIO4_13"
bitfld.long 0x134 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x134 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x134 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x134 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x134 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x134 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x134 0.--3. 1. "FUNC,Selects pin function."
line.long 0x138 "PIO414,Digital I/O control for port 4 pins PIO4_14"
bitfld.long 0x138 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x138 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x138 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x138 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x138 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x138 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x138 0.--3. 1. "FUNC,Selects pin function."
line.long 0x13C "PIO415,Digital I/O control for port 4 pins PIO4_15"
bitfld.long 0x13C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x13C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x13C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x13C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x13C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x13C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x13C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x140 "PIO416,Digital I/O control for port 4 pins PIO4_16"
bitfld.long 0x140 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x140 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x140 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x140 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x140 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x140 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x140 0.--3. 1. "FUNC,Selects pin function."
line.long 0x144 "PIO417,Digital I/O control for port 4 pins PIO4_17"
bitfld.long 0x144 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x144 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x144 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x144 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x144 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x144 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x144 0.--3. 1. "FUNC,Selects pin function."
line.long 0x148 "PIO418,Digital I/O control for port 4 pins PIO4_18"
bitfld.long 0x148 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x148 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x148 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x148 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x148 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x148 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x148 0.--3. 1. "FUNC,Selects pin function."
line.long 0x14C "PIO419,Digital I/O control for port 4 pins PIO4_19"
bitfld.long 0x14C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x14C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x14C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x14C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x14C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x14C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x14C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x150 "PIO420,Digital I/O control for port 4 pins PIO4_20"
bitfld.long 0x150 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x150 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x150 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x150 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x150 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x150 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x150 0.--3. 1. "FUNC,Selects pin function."
line.long 0x154 "PIO421,Digital I/O control for port 4 pins PIO4_21"
bitfld.long 0x154 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x154 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x154 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x154 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x154 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x154 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x154 0.--3. 1. "FUNC,Selects pin function."
line.long 0x158 "PIO422,Digital I/O control for port 4 pins PIO4_22"
bitfld.long 0x158 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x158 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x158 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x158 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x158 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x158 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x158 0.--3. 1. "FUNC,Selects pin function."
line.long 0x15C "PIO423,Digital I/O control for port 4 pins PIO4_23"
bitfld.long 0x15C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x15C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x15C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x15C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x15C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x15C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x15C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x160 "PIO424,Digital I/O control for port 4 pins PIO4_24"
bitfld.long 0x160 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x160 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x160 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x160 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x160 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x160 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x160 0.--3. 1. "FUNC,Selects pin function."
line.long 0x164 "PIO425,Digital I/O control for port 4 pins PIO4_25"
bitfld.long 0x164 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x164 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x164 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x164 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x164 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x164 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x164 0.--3. 1. "FUNC,Selects pin function."
line.long 0x168 "PIO426,Digital I/O control for port 4 pins PIO4_26"
bitfld.long 0x168 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x168 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x168 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x168 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x168 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x168 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x168 0.--3. 1. "FUNC,Selects pin function."
line.long 0x16C "PIO427,Digital I/O control for port 4 pins PIO4_27"
bitfld.long 0x16C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x16C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x16C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x16C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x16C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x16C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x16C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x170 "PIO428,Digital I/O control for port 4 pins PIO4_28"
bitfld.long 0x170 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x170 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x170 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x170 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x170 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x170 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x170 0.--3. 1. "FUNC,Selects pin function."
line.long 0x174 "PIO429,Digital I/O control for port 4 pins PIO4_29"
bitfld.long 0x174 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x174 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x174 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x174 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x174 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x174 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x174 0.--3. 1. "FUNC,Selects pin function."
line.long 0x178 "PIO430,Digital I/O control for port 4 pins PIO4_30"
bitfld.long 0x178 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x178 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x178 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x178 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x178 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x178 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x178 0.--3. 1. "FUNC,Selects pin function."
line.long 0x17C "PIO431,Digital I/O control for port 4 pins PIO4_31"
bitfld.long 0x17C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x17C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x17C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x17C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x17C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x17C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x17C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x180 "PIO50,Digital I/O control for port 5 pins PIO5_0"
bitfld.long 0x180 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x180 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x180 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x180 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x180 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x180 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x180 0.--3. 1. "FUNC,Selects pin function."
line.long 0x184 "PIO51,Digital I/O control for port 5 pins PIO5_1"
bitfld.long 0x184 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x184 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x184 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x184 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x184 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x184 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x184 0.--3. 1. "FUNC,Selects pin function."
line.long 0x188 "PIO52,Digital I/O control for port 5 pins PIO5_2"
bitfld.long 0x188 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x188 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x188 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x188 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x188 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x188 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x188 0.--3. 1. "FUNC,Selects pin function."
line.long 0x18C "PIO53,Digital I/O control for port 5 pins PIO5_3"
bitfld.long 0x18C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x18C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x18C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x18C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x18C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x18C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x18C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x190 "PIO54,Digital I/O control for port 5 pins PIO5_4"
bitfld.long 0x190 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x190 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x190 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x190 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x190 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x190 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x190 0.--3. 1. "FUNC,Selects pin function."
line.long 0x194 "PIO55,Digital I/O control for port 5 pins PIO5_5"
bitfld.long 0x194 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x194 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x194 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x194 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x194 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x194 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x194 0.--3. 1. "FUNC,Selects pin function."
line.long 0x198 "PIO56,Digital I/O control for port 5 pins PIO5_6"
bitfld.long 0x198 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x198 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x198 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x198 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x198 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x198 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x198 0.--3. 1. "FUNC,Selects pin function."
line.long 0x19C "PIO57,Digital I/O control for port 5 pins PIO5_7"
bitfld.long 0x19C 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x19C 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x19C 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x19C 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x19C 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x19C 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x19C 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1A0 "PIO58,Digital I/O control for port 5 pins PIO5_8"
bitfld.long 0x1A0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1A0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1A0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1A0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1A0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1A0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1A0 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1A4 "PIO59,Digital I/O control for port 5 pins PIO5_9"
bitfld.long 0x1A4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1A4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1A4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1A4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1A4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1A4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1A4 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1A8 "PIO510,Digital I/O control for port 5 pins PIO5_10"
bitfld.long 0x1A8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1A8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1A8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1A8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x1A8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x1A8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x1A8 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1AC "PIO511,Digital I/O control for port 5 pins PIO5_11"
bitfld.long 0x1AC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x1AC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x1AC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1AC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1AC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x1AC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x1AC 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1B0 "PIO512,Digital I/O control for port 5 pins PIO5_12"
bitfld.long 0x1B0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x1B0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x1B0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x1B0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1B0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x1B0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x1B0 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1B4 "PIO513,Digital I/O control for port 5 pins PIO5_13"
bitfld.long 0x1B4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x1B4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x1B4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x1B4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1B4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x1B4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x1B4 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1B8 "PIO514,Digital I/O control for port 5 pins PIO5_14"
bitfld.long 0x1B8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x1B8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x1B8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x1B8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x1B8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x1B8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x1B8 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1BC "PIO515,Digital I/O control for port 5 pins PIO5_15"
bitfld.long 0x1BC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x1BC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x1BC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x1BC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x1BC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x1BC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x1BC 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1C0 "PIO516,Digital I/O control for port 5 pins PIO5_16"
bitfld.long 0x1C0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x1C0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x1C0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x1C0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x1C0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x1C0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x1C0 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1C4 "PIO517,Digital I/O control for port 5 pins PIO5_17"
bitfld.long 0x1C4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x1C4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x1C4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
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bitfld.long 0x1C4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x1C4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x1C4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x1C4 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1C8 "PIO518,Digital I/O control for port 5 pins PIO5_18"
bitfld.long 0x1C8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x1C8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x1C8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1C8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1C8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x1C8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x1C8 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1CC "PIO519,Digital I/O control for port 5 pins PIO5_19"
bitfld.long 0x1CC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
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bitfld.long 0x1CC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x1CC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1CC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1CC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x1CC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x1CC 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1D0 "PIO520,Digital I/O control for port 5 pins PIO5_20"
bitfld.long 0x1D0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1D0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1D0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1D0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1D0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x1D0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x1D0 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1D4 "PIO521,Digital I/O control for port 5 pins PIO5_21"
bitfld.long 0x1D4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1D4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1D4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1D4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x1D4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x1D4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x1D4 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1D8 "PIO522,Digital I/O control for port 5 pins PIO5_22"
bitfld.long 0x1D8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1D8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1D8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1D8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x1D8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x1D8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x1D8 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1DC "PIO523,Digital I/O control for port 5 pins PIO5_23"
bitfld.long 0x1DC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1DC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
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bitfld.long 0x1DC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1DC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
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bitfld.long 0x1DC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x1DC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x1DC 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1E0 "PIO524,Digital I/O control for port 5 pins PIO5_24"
bitfld.long 0x1E0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1E0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1E0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1E0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1E0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x1E0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x1E0 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1E4 "PIO525,Digital I/O control for port 5 pins PIO5_25"
bitfld.long 0x1E4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1E4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1E4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1E4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1E4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x1E4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x1E4 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1E8 "PIO526,Digital I/O control for port 5 pins PIO5_26"
bitfld.long 0x1E8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1E8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1E8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1E8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1E8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
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bitfld.long 0x1E8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
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hexmask.long.byte 0x1E8 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1EC "PIO527,Digital I/O control for port 5 pins PIO5_27"
bitfld.long 0x1EC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1EC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1EC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1EC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1EC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1EC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1EC 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1F0 "PIO528,Digital I/O control for port 5 pins PIO5_28"
bitfld.long 0x1F0 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1F0 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1F0 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1F0 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1F0 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1F0 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1F0 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1F4 "PIO529,Digital I/O control for port 5 pins PIO5_29"
bitfld.long 0x1F4 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1F4 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1F4 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1F4 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1F4 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1F4 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1F4 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1F8 "PIO530,Digital I/O control for port 5 pins PIO5_30"
bitfld.long 0x1F8 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1F8 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1F8 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1F8 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1F8 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1F8 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1F8 0.--3. 1. "FUNC,Selects pin function."
line.long 0x1FC "PIO531,Digital I/O control for port 5 pins PIO5_31"
bitfld.long 0x1FC 11. "OD,Controls open-drain mode." "0: Normal. Normal push-pull output,1: Open-drain. Simulated open-drain output (high.."
newline
bitfld.long 0x1FC 10. "SLEW,Driver slew rate." "0: Standard mode output slew rate control is..,1: Fast mode slew rate control is disabled. Refer.."
newline
bitfld.long 0x1FC 9. "FILTEROFF,Controls input glitch filter." "0: Filter enabled. Noise pulses below approximately..,1: Filter disabled. No input filtering is done."
newline
bitfld.long 0x1FC 8. "DIGIMODE,Select Analog/Digital mode." "0: Analog mode.,1: Digital mode."
newline
bitfld.long 0x1FC 7. "INVERT,Input polarity." "0: Disabled. Input function is not inverted.,1: Enabled. Input is function inverted."
newline
bitfld.long 0x1FC 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)." "0: Inactive. Inactive (no pull-down/pull-up..,1: Pull-down. Pull-down resistor enabled.,2: Pull-up. Pull-up resistor enabled.,3: Repeater. Repeater mode."
newline
hexmask.long.byte 0x1FC 0.--3. 1. "FUNC,Selects pin function."
endif
tree.end
tree "ITM (Instrumentation Trace Macrocell)"
base ad:0xE0000000
group.long 0x0++0x3
line.long 0x0 "STIM0_READ,Stimulus Port Register 0 (for reading)"
bitfld.long 0x0 0. "FIFOREADY,no description available" "0,1"
group.long 0x0++0x7
line.long 0x0 "STIM0_WRITE,Stimulus Port Register 0 (for writing)"
hexmask.long 0x0 0.--31. 1. "STIMULUS,Data write to the stimulus port FIFO  for forwarding as a software event packet."
line.long 0x4 "STIM1_READ,Stimulus Port Register 1 (for reading)"
bitfld.long 0x4 0. "FIFOREADY,no description available" "0,1"
group.long 0x4++0x7
line.long 0x0 "STIM1_WRITE,Stimulus Port Register 1 (for writing)"
hexmask.long 0x0 0.--31. 1. "STIMULUS,Data write to the stimulus port FIFO  for forwarding as a software event packet."
line.long 0x4 "STIM2_READ,Stimulus Port Register 2 (for reading)"
bitfld.long 0x4 0. "FIFOREADY,no description available" "0,1"
group.long 0x8++0x7
line.long 0x0 "STIM2_WRITE,Stimulus Port Register 2 (for writing)"
hexmask.long 0x0 0.--31. 1. "STIMULUS,Data write to the stimulus port FIFO  for forwarding as a software event packet."
line.long 0x4 "STIM3_READ,Stimulus Port Register 3 (for reading)"
bitfld.long 0x4 0. "FIFOREADY,no description available" "0,1"
group.long 0xC++0x7
line.long 0x0 "STIM3_WRITE,Stimulus Port Register 3 (for writing)"
hexmask.long 0x0 0.--31. 1. "STIMULUS,Data write to the stimulus port FIFO  for forwarding as a software event packet."
line.long 0x4 "STIM4_READ,Stimulus Port Register 4 (for reading)"
bitfld.long 0x4 0. "FIFOREADY,no description available" "0,1"
group.long 0x10++0x7
line.long 0x0 "STIM4_WRITE,Stimulus Port Register 4 (for writing)"
hexmask.long 0x0 0.--31. 1. "STIMULUS,Data write to the stimulus port FIFO  for forwarding as a software event packet."
line.long 0x4 "STIM5_READ,Stimulus Port Register 5 (for reading)"
bitfld.long 0x4 0. "FIFOREADY,no description available" "0,1"
group.long 0x14++0x7
line.long 0x0 "STIM5_WRITE,Stimulus Port Register 5 (for writing)"
hexmask.long 0x0 0.--31. 1. "STIMULUS,Data write to the stimulus port FIFO  for forwarding as a software event packet."
line.long 0x4 "STIM6_READ,Stimulus Port Register 6 (for reading)"
bitfld.long 0x4 0. "FIFOREADY,no description available" "0,1"
group.long 0x18++0x7
line.long 0x0 "STIM6_WRITE,Stimulus Port Register 6 (for writing)"
hexmask.long 0x0 0.--31. 1. "STIMULUS,Data write to the stimulus port FIFO  for forwarding as a software event packet."
line.long 0x4 "STIM7_READ,Stimulus Port Register 7 (for reading)"
bitfld.long 0x4 0. "FIFOREADY,no description available" "0,1"
group.long 0x1C++0x7
line.long 0x0 "STIM7_WRITE,Stimulus Port Register 7 (for writing)"
hexmask.long 0x0 0.--31. 1. "STIMULUS,Data write to the stimulus port FIFO  for forwarding as a software event packet."
line.long 0x4 "STIM8_READ,Stimulus Port Register 8 (for reading)"
bitfld.long 0x4 0. "FIFOREADY,no description available" "0,1"
group.long 0x20++0x7
line.long 0x0 "STIM8_WRITE,Stimulus Port Register 8 (for writing)"
hexmask.long 0x0 0.--31. 1. "STIMULUS,Data write to the stimulus port FIFO  for forwarding as a software event packet."
line.long 0x4 "STIM9_READ,Stimulus Port Register 9 (for reading)"
bitfld.long 0x4 0. "FIFOREADY,no description available" "0,1"
group.long 0x24++0x7
line.long 0x0 "STIM9_WRITE,Stimulus Port Register 9 (for writing)"
hexmask.long 0x0 0.--31. 1. "STIMULUS,Data write to the stimulus port FIFO  for forwarding as a software event packet."
line.long 0x4 "STIM10_READ,Stimulus Port Register 10 (for reading)"
bitfld.long 0x4 0. "FIFOREADY,no description available" "0,1"
group.long 0x28++0x7
line.long 0x0 "STIM10_WRITE,Stimulus Port Register 10 (for writing)"
hexmask.long 0x0 0.--31. 1. "STIMULUS,Data write to the stimulus port FIFO  for forwarding as a software event packet."
line.long 0x4 "STIM11_READ,Stimulus Port Register 11 (for reading)"
bitfld.long 0x4 0. "FIFOREADY,no description available" "0,1"
group.long 0x2C++0x7
line.long 0x0 "STIM11_WRITE,Stimulus Port Register 11 (for writing)"
hexmask.long 0x0 0.--31. 1. "STIMULUS,Data write to the stimulus port FIFO  for forwarding as a software event packet."
line.long 0x4 "STIM12_READ,Stimulus Port Register 12 (for reading)"
bitfld.long 0x4 0. "FIFOREADY,no description available" "0,1"
group.long 0x30++0x7
line.long 0x0 "STIM12_WRITE,Stimulus Port Register 12 (for writing)"
hexmask.long 0x0 0.--31. 1. "STIMULUS,Data write to the stimulus port FIFO  for forwarding as a software event packet."
line.long 0x4 "STIM13_READ,Stimulus Port Register 13 (for reading)"
bitfld.long 0x4 0. "FIFOREADY,no description available" "0,1"
group.long 0x34++0x7
line.long 0x0 "STIM13_WRITE,Stimulus Port Register 13 (for writing)"
hexmask.long 0x0 0.--31. 1. "STIMULUS,Data write to the stimulus port FIFO  for forwarding as a software event packet."
line.long 0x4 "STIM14_READ,Stimulus Port Register 14 (for reading)"
bitfld.long 0x4 0. "FIFOREADY,no description available" "0,1"
group.long 0x38++0x7
line.long 0x0 "STIM14_WRITE,Stimulus Port Register 14 (for writing)"
hexmask.long 0x0 0.--31. 1. "STIMULUS,Data write to the stimulus port FIFO  for forwarding as a software event packet."
line.long 0x4 "STIM15_READ,Stimulus Port Register 15 (for reading)"
bitfld.long 0x4 0. "FIFOREADY,no description available" "0,1"
group.long 0x3C++0x7
line.long 0x0 "STIM15_WRITE,Stimulus Port Register 15 (for writing)"
hexmask.long 0x0 0.--31. 1. "STIMULUS,Data write to the stimulus port FIFO  for forwarding as a software event packet."
line.long 0x4 "STIM16_READ,Stimulus Port Register 16 (for reading)"
bitfld.long 0x4 0. "FIFOREADY,no description available" "0,1"
group.long 0x40++0x7
line.long 0x0 "STIM16_WRITE,Stimulus Port Register 16 (for writing)"
hexmask.long 0x0 0.--31. 1. "STIMULUS,Data write to the stimulus port FIFO  for forwarding as a software event packet."
line.long 0x4 "STIM17_READ,Stimulus Port Register 17 (for reading)"
bitfld.long 0x4 0. "FIFOREADY,no description available" "0,1"
group.long 0x44++0x7
line.long 0x0 "STIM17_WRITE,Stimulus Port Register 17 (for writing)"
hexmask.long 0x0 0.--31. 1. "STIMULUS,Data write to the stimulus port FIFO  for forwarding as a software event packet."
line.long 0x4 "STIM18_READ,Stimulus Port Register 18 (for reading)"
bitfld.long 0x4 0. "FIFOREADY,no description available" "0,1"
group.long 0x48++0x7
line.long 0x0 "STIM18_WRITE,Stimulus Port Register 18 (for writing)"
hexmask.long 0x0 0.--31. 1. "STIMULUS,Data write to the stimulus port FIFO  for forwarding as a software event packet."
line.long 0x4 "STIM19_READ,Stimulus Port Register 19 (for reading)"
bitfld.long 0x4 0. "FIFOREADY,no description available" "0,1"
group.long 0x4C++0x7
line.long 0x0 "STIM19_WRITE,Stimulus Port Register 19 (for writing)"
hexmask.long 0x0 0.--31. 1. "STIMULUS,Data write to the stimulus port FIFO  for forwarding as a software event packet."
line.long 0x4 "STIM20_READ,Stimulus Port Register 20 (for reading)"
bitfld.long 0x4 0. "FIFOREADY,no description available" "0,1"
group.long 0x50++0x7
line.long 0x0 "STIM20_WRITE,Stimulus Port Register 20 (for writing)"
hexmask.long 0x0 0.--31. 1. "STIMULUS,Data write to the stimulus port FIFO  for forwarding as a software event packet."
line.long 0x4 "STIM21_READ,Stimulus Port Register 21 (for reading)"
bitfld.long 0x4 0. "FIFOREADY,no description available" "0,1"
group.long 0x54++0x7
line.long 0x0 "STIM21_WRITE,Stimulus Port Register 21 (for writing)"
hexmask.long 0x0 0.--31. 1. "STIMULUS,Data write to the stimulus port FIFO  for forwarding as a software event packet."
line.long 0x4 "STIM22_READ,Stimulus Port Register 22 (for reading)"
bitfld.long 0x4 0. "FIFOREADY,no description available" "0,1"
group.long 0x58++0x7
line.long 0x0 "STIM22_WRITE,Stimulus Port Register 22 (for writing)"
hexmask.long 0x0 0.--31. 1. "STIMULUS,Data write to the stimulus port FIFO  for forwarding as a software event packet."
line.long 0x4 "STIM23_READ,Stimulus Port Register 23 (for reading)"
bitfld.long 0x4 0. "FIFOREADY,no description available" "0,1"
group.long 0x5C++0x7
line.long 0x0 "STIM23_WRITE,Stimulus Port Register 23 (for writing)"
hexmask.long 0x0 0.--31. 1. "STIMULUS,Data write to the stimulus port FIFO  for forwarding as a software event packet."
line.long 0x4 "STIM24_READ,Stimulus Port Register 24 (for reading)"
bitfld.long 0x4 0. "FIFOREADY,no description available" "0,1"
group.long 0x60++0x7
line.long 0x0 "STIM24_WRITE,Stimulus Port Register 24 (for writing)"
hexmask.long 0x0 0.--31. 1. "STIMULUS,Data write to the stimulus port FIFO  for forwarding as a software event packet."
line.long 0x4 "STIM25_READ,Stimulus Port Register 25 (for reading)"
bitfld.long 0x4 0. "FIFOREADY,no description available" "0,1"
group.long 0x64++0x7
line.long 0x0 "STIM25_WRITE,Stimulus Port Register 25 (for writing)"
hexmask.long 0x0 0.--31. 1. "STIMULUS,Data write to the stimulus port FIFO  for forwarding as a software event packet."
line.long 0x4 "STIM26_READ,Stimulus Port Register 26 (for reading)"
bitfld.long 0x4 0. "FIFOREADY,no description available" "0,1"
group.long 0x68++0x7
line.long 0x0 "STIM26_WRITE,Stimulus Port Register 26 (for writing)"
hexmask.long 0x0 0.--31. 1. "STIMULUS,Data write to the stimulus port FIFO  for forwarding as a software event packet."
line.long 0x4 "STIM27_READ,Stimulus Port Register 27 (for reading)"
bitfld.long 0x4 0. "FIFOREADY,no description available" "0,1"
group.long 0x6C++0x7
line.long 0x0 "STIM27_WRITE,Stimulus Port Register 27 (for writing)"
hexmask.long 0x0 0.--31. 1. "STIMULUS,Data write to the stimulus port FIFO  for forwarding as a software event packet."
line.long 0x4 "STIM28_READ,Stimulus Port Register 28 (for reading)"
bitfld.long 0x4 0. "FIFOREADY,no description available" "0,1"
group.long 0x70++0x7
line.long 0x0 "STIM28_WRITE,Stimulus Port Register 28 (for writing)"
hexmask.long 0x0 0.--31. 1. "STIMULUS,Data write to the stimulus port FIFO  for forwarding as a software event packet."
line.long 0x4 "STIM29_READ,Stimulus Port Register 29 (for reading)"
bitfld.long 0x4 0. "FIFOREADY,no description available" "0,1"
group.long 0x74++0x7
line.long 0x0 "STIM29_WRITE,Stimulus Port Register 29 (for writing)"
hexmask.long 0x0 0.--31. 1. "STIMULUS,Data write to the stimulus port FIFO  for forwarding as a software event packet."
line.long 0x4 "STIM30_READ,Stimulus Port Register 30 (for reading)"
bitfld.long 0x4 0. "FIFOREADY,no description available" "0,1"
group.long 0x78++0x7
line.long 0x0 "STIM30_WRITE,Stimulus Port Register 30 (for writing)"
hexmask.long 0x0 0.--31. 1. "STIMULUS,Data write to the stimulus port FIFO  for forwarding as a software event packet."
line.long 0x4 "STIM31_READ,Stimulus Port Register 31 (for reading)"
bitfld.long 0x4 0. "FIFOREADY,no description available" "0,1"
group.long 0x7C++0x3
line.long 0x0 "STIM31_WRITE,Stimulus Port Register 31 (for writing)"
hexmask.long 0x0 0.--31. 1. "STIMULUS,Data write to the stimulus port FIFO  for forwarding as a software event packet."
group.long 0xE00++0x3
line.long 0x0 "TER,Trace Enable Register"
hexmask.long 0x0 0.--31. 1. "STIMENA,For bit STIMENA[n]  in register ITM_TERx: 0 = Stimulus port (32x + n) disabled 1 = Stimulus port (32x + n) enabled"
group.long 0xE40++0x3
line.long 0x0 "TPR,Trace Privilege Register"
hexmask.long.byte 0x0 0.--3. 1. "PRIVMASK,Bit mask to enable tracing on ITM stimulus ports: Bit [0] = stimulus port [7:0] Bit [1] = stimulus port [15:8] Bit [2] = stimulus port [23:16] Bit [3] = stimulus port [31:24]"
group.long 0xE80++0x3
line.long 0x0 "TCR,Trace Control Register"
rbitfld.long 0x0 23. "BUSY,Indicates whether the ITM is currently processing events: 0: ITM is not processing any events. 1: ITM events present and being drained." "0: ITM is not processing any events,1: ITM events present and being drained"
newline
hexmask.long.byte 0x0 16.--22. 1. "TraceBusID,Identifier for multi-source trace stream formatting. If multi-source trace is in use  the debugger must write a non-zero value to this field."
newline
bitfld.long 0x0 10.--11. "GTSFREQ,Global timestamp frequency. Defines how often the ITM generates a global timestamp  based on the global timestamp clock frequency  or disables generation of global timestamps." "0: Disable generation of global timestamps.,1: Generate timestamp request whenever the ITM..,2: Generate timestamp request whenever the ITM..,3: Generate a timestamp after every packet if the.."
newline
bitfld.long 0x0 8.--9. "TSPrescale,Local timestamp prescaler  used with the trace packet reference clock." "0: No prescaling.,1: Divide by 4.,2: Divide by 16.,3: Divide by 64."
newline
bitfld.long 0x0 4. "SWOENA,no description available" "0: Timestamp counter uses the processor system clock.,1: Timestamp counter uses asynchronous clock from.."
newline
bitfld.long 0x0 3. "TXENA,no description available" "0: Disabled.,1: Enabled."
newline
bitfld.long 0x0 2. "SYNCENA,no description available" "0: Disabled.,1: Enabled."
newline
bitfld.long 0x0 1. "TSENA,no description available" "0: Disabled.,1: Enabled."
newline
bitfld.long 0x0 0. "ITMENA,no description available" "0: Disabled.,1: Enabled."
group.long 0xFB0++0x3
line.long 0x0 "LAR,Lock Access Register"
hexmask.long 0x0 0.--31. 1. "WriteAccessCode,Write Access Code. A write of 0xC5ACCE55 enables further write access to this device. An invalid write will have the affect of removing write access."
rgroup.long 0xFB4++0x3
line.long 0x0 "LSR,Lock Status Register"
bitfld.long 0x0 2. "s8BIT,Access Lock Register size. This bit reads 0 to indicate a 32-bit register is present." "0,1"
newline
bitfld.long 0x0 1. "STATUS,Lock Status. This bit is HIGH when the device is locked  and LOW when unlocked." "0,1"
newline
bitfld.long 0x0 0. "IMP,Lock mechanism is implemented. This bit always reads 1." "0,1"
rgroup.long 0xFD0++0x2F
line.long 0x0 "PID4,Peripheral Identification Register 4."
hexmask.long.byte 0x0 4.--7. 1. "c4KB,4KB Count"
newline
hexmask.long.byte 0x0 0.--3. 1. "JEP106,JEP106 continuation code."
line.long 0x4 "PID5,Peripheral Identification Register 5."
line.long 0x8 "PID6,Peripheral Identification Register 6."
line.long 0xC "PID7,Peripheral Identification Register 7."
line.long 0x10 "PID0,Peripheral Identification Register 0."
hexmask.long.byte 0x10 0.--7. 1. "PartNumber,Part Number [7:0]"
line.long 0x14 "PID1,Peripheral Identification Register 1."
hexmask.long.byte 0x14 4.--7. 1. "JEP106_identity_code,JEP106 identity code [3:0]"
newline
hexmask.long.byte 0x14 0.--3. 1. "PartNumber,Part Number [11:8]"
line.long 0x18 "PID2,Peripheral Identification Register 2."
hexmask.long.byte 0x18 4.--7. 1. "Revision,Revision"
newline
bitfld.long 0x18 0.--2. "JEP106_identity_code,JEP106 identity code [6:4]" "0,1,2,3,4,5,6,7"
line.long 0x1C "PID3,Peripheral Identification Register 3."
hexmask.long.byte 0x1C 4.--7. 1. "RevAnd,RevAnd"
newline
hexmask.long.byte 0x1C 0.--3. 1. "CustomerModified,Customer Modified."
line.long 0x20 "CID0,Component Identification Register 0."
hexmask.long.byte 0x20 0.--7. 1. "Preamble,Preamble"
line.long 0x24 "CID1,Component Identification Register 1."
hexmask.long.byte 0x24 4.--7. 1. "ComponentClass,Component class"
newline
hexmask.long.byte 0x24 0.--3. 1. "Preamble,Preamble"
line.long 0x28 "CID2,Component Identification Register 2."
hexmask.long.byte 0x28 0.--7. 1. "Preamble,Preamble"
line.long 0x2C "CID3,Component Identification Register 3."
hexmask.long.byte 0x2C 0.--7. 1. "Preamble,Preamble"
tree.end
sif (cpuis("LPC54018*")||cpuis("LPC54607*")||cpuis("LPC54608*")||cpuis("LPC54618*")||cpuis("LPC54628*")||cpuis("LPC54S018*"))
tree "LCD (LCD Controller)"
base ad:0x40083000
group.long 0x0++0x1F
line.long 0x0 "TIMH,Horizontal Timing Control register"
hexmask.long.byte 0x0 24.--31. 1. "HBP,Horizontal back porch."
hexmask.long.byte 0x0 16.--23. 1. "HFP,Horizontal front porch."
hexmask.long.byte 0x0 8.--15. 1. "HSW,Horizontal synchronization pulse width."
hexmask.long.byte 0x0 2.--7. 1. "PPL,Pixels-per-line."
line.long 0x4 "TIMV,Vertical Timing Control register"
hexmask.long.byte 0x4 24.--31. 1. "VBP,Vertical back porch."
hexmask.long.byte 0x4 16.--23. 1. "VFP,Vertical front porch."
hexmask.long.byte 0x4 10.--15. 1. "VSW,Vertical synchronization pulse width."
hexmask.long.word 0x4 0.--9. 1. "LPP,Lines per panel."
line.long 0x8 "POL,Clock and Signal Polarity Control register"
hexmask.long.byte 0x8 27.--31. 1. "PCD_HI,Upper five bits of panel clock divisor."
bitfld.long 0x8 26. "BCD,Bypass panel clock divider." "0,1"
hexmask.long.word 0x8 16.--25. 1. "CPL,Clocks per line."
bitfld.long 0x8 14. "IOE,Invert output enable." "0,1"
bitfld.long 0x8 13. "IPC,Invert panel clock." "0,1"
bitfld.long 0x8 12. "IHS,Invert horizontal synchronization." "0,1"
bitfld.long 0x8 11. "IVS,Invert vertical synchronization." "0,1"
newline
hexmask.long.byte 0x8 6.--10. 1. "ACB,AC bias pin frequency."
hexmask.long.byte 0x8 0.--4. 1. "PCD_LO,Lower five bits of panel clock divisor."
line.long 0xC "LE,Line End Control register"
bitfld.long 0xC 16. "LEE,LCD Line end enable." "0,1"
hexmask.long.byte 0xC 0.--6. 1. "LED,Line-end delay."
line.long 0x10 "UPBASE,Upper Panel Frame Base Address register"
hexmask.long 0x10 3.--31. 1. "LCDUPBASE,LCD upper panel base address."
line.long 0x14 "LPBASE,Lower Panel Frame Base Address register"
hexmask.long 0x14 3.--31. 1. "LCDLPBASE,LCD lower panel base address."
line.long 0x18 "CTRL,LCD Control register"
bitfld.long 0x18 16. "WATERMARK,LCD DMA FIFO watermark level." "0,1"
bitfld.long 0x18 12.--13. "LCDVCOMP,LCD Vertical Compare Interrupt." "0,1,2,3"
bitfld.long 0x18 11. "LCDPWR,LCD power enable." "0,1"
bitfld.long 0x18 10. "BEPO,Big-Endian Pixel Ordering." "0,1"
bitfld.long 0x18 9. "BEBO,Big-endian Byte Order." "0,1"
bitfld.long 0x18 8. "BGR,Color format selection." "0,1"
bitfld.long 0x18 7. "LCDDUAL,Single or Dual LCD panel selection." "0,1"
newline
bitfld.long 0x18 6. "LCDMONO8,Monochrome LCD interface width." "0,1"
bitfld.long 0x18 5. "LCDTFT,LCD panel TFT type selection." "0,1"
bitfld.long 0x18 4. "LCDBW,STN LCD monochrome/color selection." "0,1"
bitfld.long 0x18 1.--3. "LCDBPP,LCD bits per pixel." "0,1,2,3,4,5,6,7"
bitfld.long 0x18 0. "LCDEN,LCD enable control bit." "0,1"
line.long 0x1C "INTMSK,Interrupt Mask register"
bitfld.long 0x1C 4. "BERIM,AHB master error interrupt enable." "0,1"
bitfld.long 0x1C 3. "VCOMPIM,Vertical compare interrupt enable." "0,1"
bitfld.long 0x1C 2. "LNBUIM,LCD next base address update interrupt enable." "0,1"
bitfld.long 0x1C 1. "FUFIM,FIFO underflow interrupt enable." "0,1"
rgroup.long 0x20++0x7
line.long 0x0 "INTRAW,Raw Interrupt Status register"
bitfld.long 0x0 4. "BERRAW,AHB master bus error raw interrupt status." "0,1"
bitfld.long 0x0 3. "VCOMPRIS,Vertical compare raw interrupt status." "0,1"
bitfld.long 0x0 2. "LNBURIS,LCD next address base update raw interrupt status." "0,1"
bitfld.long 0x0 1. "FUFRIS,FIFO underflow raw interrupt status." "0,1"
line.long 0x4 "INTSTAT,Masked Interrupt Status register"
bitfld.long 0x4 4. "BERMIS,AHB master bus error masked interrupt status." "0,1"
bitfld.long 0x4 3. "VCOMPMIS,Vertical compare masked interrupt status." "0,1"
bitfld.long 0x4 2. "LNBUMIS,LCD next address base update masked interrupt status." "0,1"
bitfld.long 0x4 1. "FUFMIS,FIFO underflow masked interrupt status." "0,1"
group.long 0x28++0x3
line.long 0x0 "INTCLR,Interrupt Clear register"
sif (cpuis("LPC54018*")||cpuis("LPC54S018*"))
bitfld.long 0x0 4. "BERIC,AHB master error interrupt clear." "0,1"
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x0 4. "BERIC,AHB master error interrupt clear." "0,1"
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x0 4. "BERIC,AHB master error interrupt clear." "0,1"
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x0 4. "BERIC,AHB master error interrupt clear." "0,1"
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x0 4. "BERIC,AHB master error interrupt clear." "0,1"
endif
bitfld.long 0x0 3. "VCOMPIC,Vertical compare interrupt clear." "0,1"
bitfld.long 0x0 2. "LNBUIC,LCD next address base update interrupt clear." "0,1"
newline
bitfld.long 0x0 1. "FUFIC,FIFO underflow interrupt clear." "0,1"
rgroup.long 0x2C++0x7
line.long 0x0 "UPCURR,Upper Panel Current Address Value register"
hexmask.long 0x0 0.--31. 1. "LCDUPCURR,LCD Upper Panel Current Address."
line.long 0x4 "LPCURR,Lower Panel Current Address Value register"
hexmask.long 0x4 0.--31. 1. "LCDLPCURR,LCD Lower Panel Current Address."
repeat 128. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x200)++0x3
line.long 0x0 "PAL[$1],256x16-bit Color Palette registers"
bitfld.long 0x0 31. "I1,Intensity / unused bit." "0,1"
hexmask.long.byte 0x0 26.--30. 1. "B14_0,Blue palette data."
hexmask.long.byte 0x0 21.--25. 1. "G14_0,Green palette data."
hexmask.long.byte 0x0 16.--20. 1. "R14_0,Red palette data."
bitfld.long 0x0 15. "I0,Intensity / unused bit." "0,1"
hexmask.long.byte 0x0 10.--14. 1. "B04_0,Blue palette data."
hexmask.long.byte 0x0 5.--9. 1. "G04_0,Green palette data."
newline
hexmask.long.byte 0x0 0.--4. 1. "R04_0,Red palette data."
repeat.end
repeat 256. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x800)++0x3
line.long 0x0 "CRSR_IMG[$1],Cursor Image registers"
hexmask.long 0x0 0.--31. 1. "CRSR_IMG,Cursor Image data."
repeat.end
group.long 0xC00++0x17
line.long 0x0 "CRSR_CTRL,Cursor Control register"
bitfld.long 0x0 4.--5. "CRSRNUM1_0,Cursor image number." "0,1,2,3"
bitfld.long 0x0 0. "CRSRON,Cursor enable." "0,1"
line.long 0x4 "CRSR_CFG,Cursor Configuration register"
bitfld.long 0x4 1. "FRAMESYNC,Cursor frame synchronization type." "0,1"
bitfld.long 0x4 0. "CRSRSIZE,Cursor size selection." "0,1"
line.long 0x8 "CRSR_PAL0,Cursor Palette register 0"
hexmask.long.byte 0x8 16.--23. 1. "BLUE,Blue color component."
hexmask.long.byte 0x8 8.--15. 1. "GREEN,Green color component."
hexmask.long.byte 0x8 0.--7. 1. "RED,Red color component."
line.long 0xC "CRSR_PAL1,Cursor Palette register 1"
hexmask.long.byte 0xC 16.--23. 1. "BLUE,Blue color component."
hexmask.long.byte 0xC 8.--15. 1. "GREEN,Green color component."
hexmask.long.byte 0xC 0.--7. 1. "RED,Red color component."
line.long 0x10 "CRSR_XY,Cursor XY Position register"
hexmask.long.word 0x10 16.--25. 1. "CRSRY,Y ordinate of the cursor origin measured in pixels."
hexmask.long.word 0x10 0.--9. 1. "CRSRX,X ordinate of the cursor origin measured in pixels."
line.long 0x14 "CRSR_CLIP,Cursor Clip Position register"
hexmask.long.byte 0x14 8.--13. 1. "CRSRCLIPY,Cursor clip position for Y direction."
hexmask.long.byte 0x14 0.--5. 1. "CRSRCLIPX,Cursor clip position for X direction."
group.long 0xC20++0x3
line.long 0x0 "CRSR_INTMSK,Cursor Interrupt Mask register"
bitfld.long 0x0 0. "CRSRIM,Cursor interrupt mask." "0,1"
wgroup.long 0xC24++0x3
line.long 0x0 "CRSR_INTCLR,Cursor Interrupt Clear register"
bitfld.long 0x0 0. "CRSRIC,Cursor interrupt clear." "0,1"
rgroup.long 0xC28++0x7
line.long 0x0 "CRSR_INTRAW,Cursor Raw Interrupt Status register"
bitfld.long 0x0 0. "CRSRRIS,Cursor raw interrupt status." "0,1"
line.long 0x4 "CRSR_INTSTAT,Cursor Masked Interrupt Status register"
bitfld.long 0x4 0. "CRSRMIS,Cursor masked interrupt status." "0,1"
tree.end
endif
sif (cpuis("LPC54101*")||cpuis("LPC54102*"))
base ad:0x1C02C000
elif (cpuis("LPC54113*")||cpuis("LPC54114*"))
base ad:0x4008B000
endif
sif (cpuis("LPC54101*")||cpuis("LPC54102*")||cpuis("LPC54113*")||cpuis("LPC54114*"))
tree "MAILBOX (Mailbox)"
repeat 2. (list 0x0 0x1)(list ad:0x1C02C000 ad:0x1C02C010)
tree "MBOXIRQ[$1]"
base $2
group.long ($2)++0x3
line.long 0x0 "IRQ,Interrupt request register for the Cortex-M0+ CPU."
hexmask.long 0x0 0.--31. 1. "INTREQ,If any bit is set  an interrupt request is sent to the Cortex-M0+ interrupt controller."
wgroup.long ($2+0x4)++0x7
line.long 0x0 "IRQSET,Set bits in IRQ0"
hexmask.long 0x0 0.--31. 1. "INTREQSET,Writing 1 sets the corresponding bit in the IRQ0 register."
line.long 0x4 "IRQCLR,Clear bits in IRQ0"
hexmask.long 0x4 0.--31. 1. "INTREQCLR,Writing 1 clears the corresponding bit in the IRQ0 register."
tree.end
repeat.end
base ad:0x1C02C000
group.long 0xF8++0x3
line.long 0x0 "MUTEX,Mutual exclusion register[1]"
bitfld.long 0x0 0. "EX,Cleared when read  set when written. See usage description above." "0,1"
sif (cpuis("LPC54113*"))
repeat 2. (list 0x0 0x1)(list ad:0x4008B000 ad:0x4008B010)
tree "MBOXIRQ[$1]"
base $2
group.long ($2)++0x3
line.long 0x0 "IRQ,Interrupt request register for the Cortex-M0+ CPU."
hexmask.long 0x0 0.--31. 1. "INTREQ,If any bit is set  an interrupt request is sent to the Cortex-M0+ interrupt controller."
wgroup.long ($2+0x4)++0x7
line.long 0x0 "IRQSET,Set bits in IRQ0"
hexmask.long 0x0 0.--31. 1. "INTREQSET,Writing 1 sets the corresponding bit in the IRQ0 register."
line.long 0x4 "IRQCLR,Clear bits in IRQ0"
hexmask.long 0x4 0.--31. 1. "INTREQCLR,Writing 1 clears the corresponding bit in the IRQ0 register."
tree.end
repeat.end
endif
sif (cpuis("LPC54114*"))
repeat 2. (list 0x0 0x1)(list ad:0x4008B000 ad:0x4008B010)
tree "MBOXIRQ[$1]"
base $2
group.long ($2)++0x3
line.long 0x0 "IRQ,Interrupt request register for the Cortex-M0+ CPU."
hexmask.long 0x0 0.--31. 1. "INTREQ,If any bit is set  an interrupt request is sent to the Cortex-M0+ interrupt controller."
wgroup.long ($2+0x4)++0x7
line.long 0x0 "IRQSET,Set bits in IRQ0"
hexmask.long 0x0 0.--31. 1. "INTREQSET,Writing 1 sets the corresponding bit in the IRQ0 register."
line.long 0x4 "IRQCLR,Clear bits in IRQ0"
hexmask.long 0x4 0.--31. 1. "INTREQCLR,Writing 1 clears the corresponding bit in the IRQ0 register."
tree.end
repeat.end
endif
tree.end
endif
tree "MRT (Multi-Rate Timers)"
base ad:0x0
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
base ad:0x4000D000
elif (cpuis("LPC54101*"))
base ad:0x40074000
endif
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54101*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
tree "MRT0"
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x4000D000 ad:0x4000D010 ad:0x4000D020 ad:0x4000D030)
tree "CHANNEL[$1]"
base $2
group.long ($2)++0x3
line.long 0x0 "INTVAL,MRT Time interval value register. This value is loaded into the TIMER register."
bitfld.long 0x0 31. "LOAD,Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0." "0: No force load. The load from the INTVALn..,1: Force load. The INTVALn interval value IVALUE -1.."
hexmask.long.tbyte 0x0 0.--23. 1. "IVALUE,Time interval load value. This value is loaded into the TIMERn register and the MRT channel n starts counting down from IVALUE -1. If the timer is idle  writing a non-zero value to this bit field starts the timer immediately. If the timer is.."
rgroup.long ($2+0x4)++0x3
line.long 0x0 "TIMER,MRT Timer register. This register reads the value of the down-counter."
hexmask.long.tbyte 0x0 0.--23. 1. "VALUE,Holds the current timer value of the down-counter. The initial value of the TIMERn register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval or immediately in the following cases: INTVALn register is updated.."
group.long ($2+0x8)++0x7
line.long 0x0 "CTRL,MRT Control register. This register controls the MRT modes."
bitfld.long 0x0 1.--2. "MODE,Selects timer mode." "0: Repeat interrupt mode.,1: One-shot interrupt mode.,2: One-shot stall mode.,?"
bitfld.long 0x0 0. "INTEN,Enable the TIMERn interrupt." "0: Disabled. TIMERn interrupt is disabled.,1: Enabled. TIMERn interrupt is enabled."
line.long 0x4 "STAT,MRT Status register."
bitfld.long 0x4 2. "INUSE,Channel In Use flag. Operating details depend on the MULTITASK bit in the MODCFG register  and affects the use of IDLE_CH. See Idle channel register for details of the two operating modes." "0: This channel is not in use.,1: This channel is in use."
bitfld.long 0x4 1. "RUN,Indicates the state of TIMERn. This bit is read-only." "0: Idle state. TIMERn is stopped.,1: Running. TIMERn is running."
newline
bitfld.long 0x4 0. "INTFLAG,Monitors the interrupt flag." "0: No pending interrupt. Writing a zero is..,1: Pending interrupt. The interrupt is pending.."
tree.end
repeat.end
base ad:0x4000D000
group.long 0xF0++0x3
line.long 0x0 "MODCFG,Module Configuration register. This register provides information about this particular MRT instance. and allows choosing an overall mode for the idle channel feature."
bitfld.long 0x0 31. "MULTITASK,Selects the operating mode for the INUSE flags and the IDLE_CH register." "0: Hardware status mode. In this mode the INUSE(n)..,1: Multi-task mode."
hexmask.long.byte 0x0 4.--8. 1. "NOB,Identifies the number of timer bits in this MRT. (24 bits wide on this device.)"
hexmask.long.byte 0x0 0.--3. 1. "NOC,Identifies the number of channels in this MRT.(4 channels on this device.)"
rgroup.long 0xF4++0x3
line.long 0x0 "IDLE_CH,Idle channel register. This register returns the number of the first idle channel."
hexmask.long.byte 0x0 4.--7. 1. "CHAN,Idle channel. Reading the CHAN bits  returns the lowest idle timer channel. The number is positioned such that it can be used as an offset from the MRT base address in order to access the registers for the allocated channel. If all timer channels.."
group.long 0xF8++0x3
line.long 0x0 "IRQ_FLAG,Global interrupt flag register"
bitfld.long 0x0 3. "GFLAG3,Monitors the interrupt flag of TIMER3. See description of channel 0." "0,1"
bitfld.long 0x0 2. "GFLAG2,Monitors the interrupt flag of TIMER2. See description of channel 0." "0,1"
bitfld.long 0x0 1. "GFLAG1,Monitors the interrupt flag of TIMER1. See description of channel 0." "0,1"
newline
bitfld.long 0x0 0. "GFLAG0,Monitors the interrupt flag of TIMER0." "0: No pending interrupt. Writing a zero is..,1: Pending interrupt. The interrupt is pending.."
sif (cpuis("LPC54101*"))
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x40074000 ad:0x40074010 ad:0x40074020 ad:0x40074030)
tree "CHANNEL[$1]"
base $2
group.long ($2)++0x3
line.long 0x0 "INTVAL,MRT Time interval value register. This value is loaded into the TIMER register."
bitfld.long 0x0 31. "LOAD,Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0." "0: No force load. The load from the INTVALn..,1: Force load. The INTVALn interval value IVALUE -1.."
hexmask.long.tbyte 0x0 0.--23. 1. "IVALUE,Time interval load value. This value is loaded into the TIMERn register and the MRT channel n starts counting down from IVALUE -1. If the timer is idle  writing a non-zero value to this bit field starts the timer immediately. If the timer is.."
rgroup.long ($2+0x4)++0x3
line.long 0x0 "TIMER,MRT Timer register. This register reads the value of the down-counter."
hexmask.long.tbyte 0x0 0.--23. 1. "VALUE,Holds the current timer value of the down-counter. The initial value of the TIMERn register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval or immediately in the following cases: INTVALn register is updated.."
group.long ($2+0x8)++0x7
line.long 0x0 "CTRL,MRT Control register. This register controls the MRT modes."
bitfld.long 0x0 1.--2. "MODE,Selects timer mode." "0: Repeat interrupt mode.,1: One-shot interrupt mode.,2: One-shot stall mode.,?"
bitfld.long 0x0 0. "INTEN,Enable the TIMERn interrupt." "0: Disabled. TIMERn interrupt is disabled.,1: Enabled. TIMERn interrupt is enabled."
line.long 0x4 "STAT,MRT Status register."
bitfld.long 0x4 2. "INUSE,Channel In Use flag. Operating details depend on the MULTITASK bit in the MODCFG register  and affects the use of IDLE_CH. See Idle channel register for details of the two operating modes." "0: This channel is not in use.,1: This channel is in use."
bitfld.long 0x4 1. "RUN,Indicates the state of TIMERn. This bit is read-only." "0: Idle state. TIMERn is stopped.,1: Running. TIMERn is running."
newline
bitfld.long 0x4 0. "INTFLAG,Monitors the interrupt flag." "0: No pending interrupt. Writing a zero is..,1: Pending interrupt. The interrupt is pending.."
tree.end
repeat.end
endif
tree.end
endif
sif (cpuis("LPC54102*"))
tree "MRT0"
base ad:0x40074000
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x40074000 ad:0x40074010 ad:0x40074020 ad:0x40074030)
tree "CHANNEL[$1]"
base $2
group.long ($2)++0x3
line.long 0x0 "INTVAL,MRT Time interval value register. This value is loaded into the TIMER register."
bitfld.long 0x0 31. "LOAD,Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0." "0: No force load. The load from the INTVALn..,1: Force load. The INTVALn interval value IVALUE -1.."
hexmask.long.tbyte 0x0 0.--23. 1. "IVALUE,Time interval load value. This value is loaded into the TIMERn register and the MRT channel n starts counting down from IVALUE -1. If the timer is idle  writing a non-zero value to this bit field starts the timer immediately. If the timer is.."
rgroup.long ($2+0x4)++0x3
line.long 0x0 "TIMER,MRT Timer register. This register reads the value of the down-counter."
hexmask.long.tbyte 0x0 0.--23. 1. "VALUE,Holds the current timer value of the down-counter. The initial value of the TIMERn register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval or immediately in the following cases: INTVALn register is updated.."
group.long ($2+0x8)++0x7
line.long 0x0 "CTRL,MRT Control register. This register controls the MRT modes."
bitfld.long 0x0 1.--2. "MODE,Selects timer mode." "0: Repeat interrupt mode.,1: One-shot interrupt mode.,2: One-shot stall mode.,?"
bitfld.long 0x0 0. "INTEN,Enable the TIMERn interrupt." "0: Disabled. TIMERn interrupt is disabled.,1: Enabled. TIMERn interrupt is enabled."
line.long 0x4 "STAT,MRT Status register."
bitfld.long 0x4 2. "INUSE,Channel In Use flag. Operating details depend on the MULTITASK bit in the MODCFG register  and affects the use of IDLE_CH. See Idle channel register for details of the two operating modes." "0: This channel is not in use.,1: This channel is in use."
bitfld.long 0x4 1. "RUN,Indicates the state of TIMERn. This bit is read-only." "0: Idle state. TIMERn is stopped.,1: Running. TIMERn is running."
newline
bitfld.long 0x4 0. "INTFLAG,Monitors the interrupt flag." "0: No pending interrupt. Writing a zero is..,1: Pending interrupt. The interrupt is pending.."
tree.end
repeat.end
base ad:0x40074000
group.long 0xF0++0x3
line.long 0x0 "MODCFG,Module Configuration register. This register provides information about this particular MRT instance. and allows choosing an overall mode for the idle channel feature."
bitfld.long 0x0 31. "MULTITASK,Selects the operating mode for the INUSE flags and the IDLE_CH register." "0: Hardware status mode. In this mode the INUSE(n)..,1: Multi-task mode."
hexmask.long.byte 0x0 4.--8. 1. "NOB,Identifies the number of timer bits in this MRT. (24 bits wide on this device.)"
hexmask.long.byte 0x0 0.--3. 1. "NOC,Identifies the number of channels in this MRT.(4 channels on this device.)"
rgroup.long 0xF4++0x3
line.long 0x0 "IDLE_CH,Idle channel register. This register returns the number of the first idle channel."
hexmask.long.byte 0x0 4.--7. 1. "CHAN,Idle channel. Reading the CHAN bits  returns the lowest idle timer channel. The number is positioned such that it can be used as an offset from the MRT base address in order to access the registers for the allocated channel. If all timer channels.."
group.long 0xF8++0x3
line.long 0x0 "IRQ_FLAG,Global interrupt flag register"
bitfld.long 0x0 3. "GFLAG3,Monitors the interrupt flag of TIMER3. See description of channel 0." "0,1"
bitfld.long 0x0 2. "GFLAG2,Monitors the interrupt flag of TIMER2. See description of channel 0." "0,1"
bitfld.long 0x0 1. "GFLAG1,Monitors the interrupt flag of TIMER1. See description of channel 0." "0,1"
newline
bitfld.long 0x0 0. "GFLAG0,Monitors the interrupt flag of TIMER0." "0: No pending interrupt. Writing a zero is..,1: Pending interrupt. The interrupt is pending.."
tree.end
endif
sif (cpuis("LPC54113*"))
tree "MRT0"
base ad:0x4000D000
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x4000D000 ad:0x4000D010 ad:0x4000D020 ad:0x4000D030)
tree "CHANNEL[$1]"
base $2
group.long ($2)++0x3
line.long 0x0 "INTVAL,MRT Time interval value register. This value is loaded into the TIMER register."
bitfld.long 0x0 31. "LOAD,Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0." "0: No force load. The load from the INTVALn..,1: Force load. The INTVALn interval value IVALUE -1.."
hexmask.long.tbyte 0x0 0.--23. 1. "IVALUE,Time interval load value. This value is loaded into the TIMERn register and the MRT channel n starts counting down from IVALUE -1. If the timer is idle  writing a non-zero value to this bit field starts the timer immediately. If the timer is.."
rgroup.long ($2+0x4)++0x3
line.long 0x0 "TIMER,MRT Timer register. This register reads the value of the down-counter."
hexmask.long.tbyte 0x0 0.--23. 1. "VALUE,Holds the current timer value of the down-counter. The initial value of the TIMERn register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval or immediately in the following cases: INTVALn register is updated.."
group.long ($2+0x8)++0x7
line.long 0x0 "CTRL,MRT Control register. This register controls the MRT modes."
bitfld.long 0x0 1.--2. "MODE,Selects timer mode." "0: Repeat interrupt mode.,1: One-shot interrupt mode.,2: One-shot stall mode.,?"
bitfld.long 0x0 0. "INTEN,Enable the TIMERn interrupt." "0: Disabled. TIMERn interrupt is disabled.,1: Enabled. TIMERn interrupt is enabled."
line.long 0x4 "STAT,MRT Status register."
bitfld.long 0x4 2. "INUSE,Channel In Use flag. Operating details depend on the MULTITASK bit in the MODCFG register  and affects the use of IDLE_CH. See Idle channel register for details of the two operating modes." "0: This channel is not in use.,1: This channel is in use."
bitfld.long 0x4 1. "RUN,Indicates the state of TIMERn. This bit is read-only." "0: Idle state. TIMERn is stopped.,1: Running. TIMERn is running."
newline
bitfld.long 0x4 0. "INTFLAG,Monitors the interrupt flag." "0: No pending interrupt. Writing a zero is..,1: Pending interrupt. The interrupt is pending.."
tree.end
repeat.end
base ad:0x4000D000
group.long 0xF0++0x3
line.long 0x0 "MODCFG,Module Configuration register. This register provides information about this particular MRT instance. and allows choosing an overall mode for the idle channel feature."
bitfld.long 0x0 31. "MULTITASK,Selects the operating mode for the INUSE flags and the IDLE_CH register." "0: Hardware status mode. In this mode the INUSE(n)..,1: Multi-task mode."
hexmask.long.byte 0x0 4.--8. 1. "NOB,Identifies the number of timer bits in this MRT. (24 bits wide on this device.)"
hexmask.long.byte 0x0 0.--3. 1. "NOC,Identifies the number of channels in this MRT.(4 channels on this device.)"
rgroup.long 0xF4++0x3
line.long 0x0 "IDLE_CH,Idle channel register. This register returns the number of the first idle channel."
hexmask.long.byte 0x0 4.--7. 1. "CHAN,Idle channel. Reading the CHAN bits  returns the lowest idle timer channel. The number is positioned such that it can be used as an offset from the MRT base address in order to access the registers for the allocated channel. If all timer channels.."
group.long 0xF8++0x3
line.long 0x0 "IRQ_FLAG,Global interrupt flag register"
bitfld.long 0x0 3. "GFLAG3,Monitors the interrupt flag of TIMER3. See description of channel 0." "0,1"
bitfld.long 0x0 2. "GFLAG2,Monitors the interrupt flag of TIMER2. See description of channel 0." "0,1"
bitfld.long 0x0 1. "GFLAG1,Monitors the interrupt flag of TIMER1. See description of channel 0." "0,1"
newline
bitfld.long 0x0 0. "GFLAG0,Monitors the interrupt flag of TIMER0." "0: No pending interrupt. Writing a zero is..,1: Pending interrupt. The interrupt is pending.."
tree.end
endif
sif (cpuis("LPC54114*"))
tree "MRT0"
base ad:0x4000D000
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x4000D000 ad:0x4000D010 ad:0x4000D020 ad:0x4000D030)
tree "CHANNEL[$1]"
base $2
group.long ($2)++0x3
line.long 0x0 "INTVAL,MRT Time interval value register. This value is loaded into the TIMER register."
bitfld.long 0x0 31. "LOAD,Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0." "0: No force load. The load from the INTVALn..,1: Force load. The INTVALn interval value IVALUE -1.."
hexmask.long.tbyte 0x0 0.--23. 1. "IVALUE,Time interval load value. This value is loaded into the TIMERn register and the MRT channel n starts counting down from IVALUE -1. If the timer is idle  writing a non-zero value to this bit field starts the timer immediately. If the timer is.."
rgroup.long ($2+0x4)++0x3
line.long 0x0 "TIMER,MRT Timer register. This register reads the value of the down-counter."
hexmask.long.tbyte 0x0 0.--23. 1. "VALUE,Holds the current timer value of the down-counter. The initial value of the TIMERn register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval or immediately in the following cases: INTVALn register is updated.."
group.long ($2+0x8)++0x7
line.long 0x0 "CTRL,MRT Control register. This register controls the MRT modes."
bitfld.long 0x0 1.--2. "MODE,Selects timer mode." "0: Repeat interrupt mode.,1: One-shot interrupt mode.,2: One-shot stall mode.,?"
bitfld.long 0x0 0. "INTEN,Enable the TIMERn interrupt." "0: Disabled. TIMERn interrupt is disabled.,1: Enabled. TIMERn interrupt is enabled."
line.long 0x4 "STAT,MRT Status register."
bitfld.long 0x4 2. "INUSE,Channel In Use flag. Operating details depend on the MULTITASK bit in the MODCFG register  and affects the use of IDLE_CH. See Idle channel register for details of the two operating modes." "0: This channel is not in use.,1: This channel is in use."
bitfld.long 0x4 1. "RUN,Indicates the state of TIMERn. This bit is read-only." "0: Idle state. TIMERn is stopped.,1: Running. TIMERn is running."
newline
bitfld.long 0x4 0. "INTFLAG,Monitors the interrupt flag." "0: No pending interrupt. Writing a zero is..,1: Pending interrupt. The interrupt is pending.."
tree.end
repeat.end
base ad:0x4000D000
group.long 0xF0++0x3
line.long 0x0 "MODCFG,Module Configuration register. This register provides information about this particular MRT instance. and allows choosing an overall mode for the idle channel feature."
bitfld.long 0x0 31. "MULTITASK,Selects the operating mode for the INUSE flags and the IDLE_CH register." "0: Hardware status mode. In this mode the INUSE(n)..,1: Multi-task mode."
hexmask.long.byte 0x0 4.--8. 1. "NOB,Identifies the number of timer bits in this MRT. (24 bits wide on this device.)"
hexmask.long.byte 0x0 0.--3. 1. "NOC,Identifies the number of channels in this MRT.(4 channels on this device.)"
rgroup.long 0xF4++0x3
line.long 0x0 "IDLE_CH,Idle channel register. This register returns the number of the first idle channel."
hexmask.long.byte 0x0 4.--7. 1. "CHAN,Idle channel. Reading the CHAN bits  returns the lowest idle timer channel. The number is positioned such that it can be used as an offset from the MRT base address in order to access the registers for the allocated channel. If all timer channels.."
group.long 0xF8++0x3
line.long 0x0 "IRQ_FLAG,Global interrupt flag register"
bitfld.long 0x0 3. "GFLAG3,Monitors the interrupt flag of TIMER3. See description of channel 0." "0,1"
bitfld.long 0x0 2. "GFLAG2,Monitors the interrupt flag of TIMER2. See description of channel 0." "0,1"
bitfld.long 0x0 1. "GFLAG1,Monitors the interrupt flag of TIMER1. See description of channel 0." "0,1"
newline
bitfld.long 0x0 0. "GFLAG0,Monitors the interrupt flag of TIMER0." "0: No pending interrupt. Writing a zero is..,1: Pending interrupt. The interrupt is pending.."
tree.end
endif
sif (cpuis("LPC54605*"))
tree "MRT0"
base ad:0x4000D000
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x4000D000 ad:0x4000D010 ad:0x4000D020 ad:0x4000D030)
tree "CHANNEL[$1]"
base $2
group.long ($2)++0x3
line.long 0x0 "INTVAL,MRT Time interval value register. This value is loaded into the TIMER register."
bitfld.long 0x0 31. "LOAD,Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0." "0: No force load. The load from the INTVALn..,1: Force load. The INTVALn interval value IVALUE -1.."
hexmask.long.tbyte 0x0 0.--23. 1. "IVALUE,Time interval load value. This value is loaded into the TIMERn register and the MRT channel n starts counting down from IVALUE -1. If the timer is idle  writing a non-zero value to this bit field starts the timer immediately. If the timer is.."
rgroup.long ($2+0x4)++0x3
line.long 0x0 "TIMER,MRT Timer register. This register reads the value of the down-counter."
hexmask.long.tbyte 0x0 0.--23. 1. "VALUE,Holds the current timer value of the down-counter. The initial value of the TIMERn register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval or immediately in the following cases: INTVALn register is updated.."
group.long ($2+0x8)++0x7
line.long 0x0 "CTRL,MRT Control register. This register controls the MRT modes."
bitfld.long 0x0 1.--2. "MODE,Selects timer mode." "0: Repeat interrupt mode.,1: One-shot interrupt mode.,2: One-shot stall mode.,?"
bitfld.long 0x0 0. "INTEN,Enable the TIMERn interrupt." "0: Disabled. TIMERn interrupt is disabled.,1: Enabled. TIMERn interrupt is enabled."
line.long 0x4 "STAT,MRT Status register."
bitfld.long 0x4 2. "INUSE,Channel In Use flag. Operating details depend on the MULTITASK bit in the MODCFG register  and affects the use of IDLE_CH. See Idle channel register for details of the two operating modes." "0: This channel is not in use.,1: This channel is in use."
bitfld.long 0x4 1. "RUN,Indicates the state of TIMERn. This bit is read-only." "0: Idle state. TIMERn is stopped.,1: Running. TIMERn is running."
newline
bitfld.long 0x4 0. "INTFLAG,Monitors the interrupt flag." "0: No pending interrupt. Writing a zero is..,1: Pending interrupt. The interrupt is pending.."
tree.end
repeat.end
base ad:0x4000D000
group.long 0xF0++0x3
line.long 0x0 "MODCFG,Module Configuration register. This register provides information about this particular MRT instance. and allows choosing an overall mode for the idle channel feature."
bitfld.long 0x0 31. "MULTITASK,Selects the operating mode for the INUSE flags and the IDLE_CH register." "0: Hardware status mode. In this mode the INUSE(n)..,1: Multi-task mode."
hexmask.long.byte 0x0 4.--8. 1. "NOB,Identifies the number of timer bits in this MRT. (24 bits wide on this device.)"
hexmask.long.byte 0x0 0.--3. 1. "NOC,Identifies the number of channels in this MRT.(4 channels on this device.)"
rgroup.long 0xF4++0x3
line.long 0x0 "IDLE_CH,Idle channel register. This register returns the number of the first idle channel."
hexmask.long.byte 0x0 4.--7. 1. "CHAN,Idle channel. Reading the CHAN bits  returns the lowest idle timer channel. The number is positioned such that it can be used as an offset from the MRT base address in order to access the registers for the allocated channel. If all timer channels.."
group.long 0xF8++0x3
line.long 0x0 "IRQ_FLAG,Global interrupt flag register"
bitfld.long 0x0 3. "GFLAG3,Monitors the interrupt flag of TIMER3. See description of channel 0." "0,1"
bitfld.long 0x0 2. "GFLAG2,Monitors the interrupt flag of TIMER2. See description of channel 0." "0,1"
bitfld.long 0x0 1. "GFLAG1,Monitors the interrupt flag of TIMER1. See description of channel 0." "0,1"
newline
bitfld.long 0x0 0. "GFLAG0,Monitors the interrupt flag of TIMER0." "0: No pending interrupt. Writing a zero is..,1: Pending interrupt. The interrupt is pending.."
tree.end
endif
sif (cpuis("LPC54606*"))
tree "MRT0"
base ad:0x4000D000
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x4000D000 ad:0x4000D010 ad:0x4000D020 ad:0x4000D030)
tree "CHANNEL[$1]"
base $2
group.long ($2)++0x3
line.long 0x0 "INTVAL,MRT Time interval value register. This value is loaded into the TIMER register."
bitfld.long 0x0 31. "LOAD,Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0." "0: No force load. The load from the INTVALn..,1: Force load. The INTVALn interval value IVALUE -1.."
hexmask.long.tbyte 0x0 0.--23. 1. "IVALUE,Time interval load value. This value is loaded into the TIMERn register and the MRT channel n starts counting down from IVALUE -1. If the timer is idle  writing a non-zero value to this bit field starts the timer immediately. If the timer is.."
rgroup.long ($2+0x4)++0x3
line.long 0x0 "TIMER,MRT Timer register. This register reads the value of the down-counter."
hexmask.long.tbyte 0x0 0.--23. 1. "VALUE,Holds the current timer value of the down-counter. The initial value of the TIMERn register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval or immediately in the following cases: INTVALn register is updated.."
group.long ($2+0x8)++0x7
line.long 0x0 "CTRL,MRT Control register. This register controls the MRT modes."
bitfld.long 0x0 1.--2. "MODE,Selects timer mode." "0: Repeat interrupt mode.,1: One-shot interrupt mode.,2: One-shot stall mode.,?"
bitfld.long 0x0 0. "INTEN,Enable the TIMERn interrupt." "0: Disabled. TIMERn interrupt is disabled.,1: Enabled. TIMERn interrupt is enabled."
line.long 0x4 "STAT,MRT Status register."
bitfld.long 0x4 2. "INUSE,Channel In Use flag. Operating details depend on the MULTITASK bit in the MODCFG register  and affects the use of IDLE_CH. See Idle channel register for details of the two operating modes." "0: This channel is not in use.,1: This channel is in use."
bitfld.long 0x4 1. "RUN,Indicates the state of TIMERn. This bit is read-only." "0: Idle state. TIMERn is stopped.,1: Running. TIMERn is running."
newline
bitfld.long 0x4 0. "INTFLAG,Monitors the interrupt flag." "0: No pending interrupt. Writing a zero is..,1: Pending interrupt. The interrupt is pending.."
tree.end
repeat.end
base ad:0x4000D000
group.long 0xF0++0x3
line.long 0x0 "MODCFG,Module Configuration register. This register provides information about this particular MRT instance. and allows choosing an overall mode for the idle channel feature."
bitfld.long 0x0 31. "MULTITASK,Selects the operating mode for the INUSE flags and the IDLE_CH register." "0: Hardware status mode. In this mode the INUSE(n)..,1: Multi-task mode."
hexmask.long.byte 0x0 4.--8. 1. "NOB,Identifies the number of timer bits in this MRT. (24 bits wide on this device.)"
hexmask.long.byte 0x0 0.--3. 1. "NOC,Identifies the number of channels in this MRT.(4 channels on this device.)"
rgroup.long 0xF4++0x3
line.long 0x0 "IDLE_CH,Idle channel register. This register returns the number of the first idle channel."
hexmask.long.byte 0x0 4.--7. 1. "CHAN,Idle channel. Reading the CHAN bits  returns the lowest idle timer channel. The number is positioned such that it can be used as an offset from the MRT base address in order to access the registers for the allocated channel. If all timer channels.."
group.long 0xF8++0x3
line.long 0x0 "IRQ_FLAG,Global interrupt flag register"
bitfld.long 0x0 3. "GFLAG3,Monitors the interrupt flag of TIMER3. See description of channel 0." "0,1"
bitfld.long 0x0 2. "GFLAG2,Monitors the interrupt flag of TIMER2. See description of channel 0." "0,1"
bitfld.long 0x0 1. "GFLAG1,Monitors the interrupt flag of TIMER1. See description of channel 0." "0,1"
newline
bitfld.long 0x0 0. "GFLAG0,Monitors the interrupt flag of TIMER0." "0: No pending interrupt. Writing a zero is..,1: Pending interrupt. The interrupt is pending.."
tree.end
endif
sif (cpuis("LPC54607*"))
tree "MRT0"
base ad:0x4000D000
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x4000D000 ad:0x4000D010 ad:0x4000D020 ad:0x4000D030)
tree "CHANNEL[$1]"
base $2
group.long ($2)++0x3
line.long 0x0 "INTVAL,MRT Time interval value register. This value is loaded into the TIMER register."
bitfld.long 0x0 31. "LOAD,Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0." "0: No force load. The load from the INTVALn..,1: Force load. The INTVALn interval value IVALUE -1.."
hexmask.long.tbyte 0x0 0.--23. 1. "IVALUE,Time interval load value. This value is loaded into the TIMERn register and the MRT channel n starts counting down from IVALUE -1. If the timer is idle  writing a non-zero value to this bit field starts the timer immediately. If the timer is.."
rgroup.long ($2+0x4)++0x3
line.long 0x0 "TIMER,MRT Timer register. This register reads the value of the down-counter."
hexmask.long.tbyte 0x0 0.--23. 1. "VALUE,Holds the current timer value of the down-counter. The initial value of the TIMERn register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval or immediately in the following cases: INTVALn register is updated.."
group.long ($2+0x8)++0x7
line.long 0x0 "CTRL,MRT Control register. This register controls the MRT modes."
bitfld.long 0x0 1.--2. "MODE,Selects timer mode." "0: Repeat interrupt mode.,1: One-shot interrupt mode.,2: One-shot stall mode.,?"
bitfld.long 0x0 0. "INTEN,Enable the TIMERn interrupt." "0: Disabled. TIMERn interrupt is disabled.,1: Enabled. TIMERn interrupt is enabled."
line.long 0x4 "STAT,MRT Status register."
bitfld.long 0x4 2. "INUSE,Channel In Use flag. Operating details depend on the MULTITASK bit in the MODCFG register  and affects the use of IDLE_CH. See Idle channel register for details of the two operating modes." "0: This channel is not in use.,1: This channel is in use."
bitfld.long 0x4 1. "RUN,Indicates the state of TIMERn. This bit is read-only." "0: Idle state. TIMERn is stopped.,1: Running. TIMERn is running."
newline
bitfld.long 0x4 0. "INTFLAG,Monitors the interrupt flag." "0: No pending interrupt. Writing a zero is..,1: Pending interrupt. The interrupt is pending.."
tree.end
repeat.end
base ad:0x4000D000
group.long 0xF0++0x3
line.long 0x0 "MODCFG,Module Configuration register. This register provides information about this particular MRT instance. and allows choosing an overall mode for the idle channel feature."
bitfld.long 0x0 31. "MULTITASK,Selects the operating mode for the INUSE flags and the IDLE_CH register." "0: Hardware status mode. In this mode the INUSE(n)..,1: Multi-task mode."
hexmask.long.byte 0x0 4.--8. 1. "NOB,Identifies the number of timer bits in this MRT. (24 bits wide on this device.)"
hexmask.long.byte 0x0 0.--3. 1. "NOC,Identifies the number of channels in this MRT.(4 channels on this device.)"
rgroup.long 0xF4++0x3
line.long 0x0 "IDLE_CH,Idle channel register. This register returns the number of the first idle channel."
hexmask.long.byte 0x0 4.--7. 1. "CHAN,Idle channel. Reading the CHAN bits  returns the lowest idle timer channel. The number is positioned such that it can be used as an offset from the MRT base address in order to access the registers for the allocated channel. If all timer channels.."
group.long 0xF8++0x3
line.long 0x0 "IRQ_FLAG,Global interrupt flag register"
bitfld.long 0x0 3. "GFLAG3,Monitors the interrupt flag of TIMER3. See description of channel 0." "0,1"
bitfld.long 0x0 2. "GFLAG2,Monitors the interrupt flag of TIMER2. See description of channel 0." "0,1"
bitfld.long 0x0 1. "GFLAG1,Monitors the interrupt flag of TIMER1. See description of channel 0." "0,1"
newline
bitfld.long 0x0 0. "GFLAG0,Monitors the interrupt flag of TIMER0." "0: No pending interrupt. Writing a zero is..,1: Pending interrupt. The interrupt is pending.."
tree.end
endif
sif (cpuis("LPC54608*"))
tree "MRT0"
base ad:0x4000D000
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x4000D000 ad:0x4000D010 ad:0x4000D020 ad:0x4000D030)
tree "CHANNEL[$1]"
base $2
group.long ($2)++0x3
line.long 0x0 "INTVAL,MRT Time interval value register. This value is loaded into the TIMER register."
bitfld.long 0x0 31. "LOAD,Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0." "0: No force load. The load from the INTVALn..,1: Force load. The INTVALn interval value IVALUE -1.."
hexmask.long.tbyte 0x0 0.--23. 1. "IVALUE,Time interval load value. This value is loaded into the TIMERn register and the MRT channel n starts counting down from IVALUE -1. If the timer is idle  writing a non-zero value to this bit field starts the timer immediately. If the timer is.."
rgroup.long ($2+0x4)++0x3
line.long 0x0 "TIMER,MRT Timer register. This register reads the value of the down-counter."
hexmask.long.tbyte 0x0 0.--23. 1. "VALUE,Holds the current timer value of the down-counter. The initial value of the TIMERn register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval or immediately in the following cases: INTVALn register is updated.."
group.long ($2+0x8)++0x7
line.long 0x0 "CTRL,MRT Control register. This register controls the MRT modes."
bitfld.long 0x0 1.--2. "MODE,Selects timer mode." "0: Repeat interrupt mode.,1: One-shot interrupt mode.,2: One-shot stall mode.,?"
bitfld.long 0x0 0. "INTEN,Enable the TIMERn interrupt." "0: Disabled. TIMERn interrupt is disabled.,1: Enabled. TIMERn interrupt is enabled."
line.long 0x4 "STAT,MRT Status register."
bitfld.long 0x4 2. "INUSE,Channel In Use flag. Operating details depend on the MULTITASK bit in the MODCFG register  and affects the use of IDLE_CH. See Idle channel register for details of the two operating modes." "0: This channel is not in use.,1: This channel is in use."
bitfld.long 0x4 1. "RUN,Indicates the state of TIMERn. This bit is read-only." "0: Idle state. TIMERn is stopped.,1: Running. TIMERn is running."
newline
bitfld.long 0x4 0. "INTFLAG,Monitors the interrupt flag." "0: No pending interrupt. Writing a zero is..,1: Pending interrupt. The interrupt is pending.."
tree.end
repeat.end
base ad:0x4000D000
group.long 0xF0++0x3
line.long 0x0 "MODCFG,Module Configuration register. This register provides information about this particular MRT instance. and allows choosing an overall mode for the idle channel feature."
bitfld.long 0x0 31. "MULTITASK,Selects the operating mode for the INUSE flags and the IDLE_CH register." "0: Hardware status mode. In this mode the INUSE(n)..,1: Multi-task mode."
hexmask.long.byte 0x0 4.--8. 1. "NOB,Identifies the number of timer bits in this MRT. (24 bits wide on this device.)"
hexmask.long.byte 0x0 0.--3. 1. "NOC,Identifies the number of channels in this MRT.(4 channels on this device.)"
rgroup.long 0xF4++0x3
line.long 0x0 "IDLE_CH,Idle channel register. This register returns the number of the first idle channel."
hexmask.long.byte 0x0 4.--7. 1. "CHAN,Idle channel. Reading the CHAN bits  returns the lowest idle timer channel. The number is positioned such that it can be used as an offset from the MRT base address in order to access the registers for the allocated channel. If all timer channels.."
group.long 0xF8++0x3
line.long 0x0 "IRQ_FLAG,Global interrupt flag register"
bitfld.long 0x0 3. "GFLAG3,Monitors the interrupt flag of TIMER3. See description of channel 0." "0,1"
bitfld.long 0x0 2. "GFLAG2,Monitors the interrupt flag of TIMER2. See description of channel 0." "0,1"
bitfld.long 0x0 1. "GFLAG1,Monitors the interrupt flag of TIMER1. See description of channel 0." "0,1"
newline
bitfld.long 0x0 0. "GFLAG0,Monitors the interrupt flag of TIMER0." "0: No pending interrupt. Writing a zero is..,1: Pending interrupt. The interrupt is pending.."
tree.end
endif
sif (cpuis("LPC54616*"))
tree "MRT0"
base ad:0x4000D000
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x4000D000 ad:0x4000D010 ad:0x4000D020 ad:0x4000D030)
tree "CHANNEL[$1]"
base $2
group.long ($2)++0x3
line.long 0x0 "INTVAL,MRT Time interval value register. This value is loaded into the TIMER register."
bitfld.long 0x0 31. "LOAD,Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0." "0: No force load. The load from the INTVALn..,1: Force load. The INTVALn interval value IVALUE -1.."
hexmask.long.tbyte 0x0 0.--23. 1. "IVALUE,Time interval load value. This value is loaded into the TIMERn register and the MRT channel n starts counting down from IVALUE -1. If the timer is idle  writing a non-zero value to this bit field starts the timer immediately. If the timer is.."
rgroup.long ($2+0x4)++0x3
line.long 0x0 "TIMER,MRT Timer register. This register reads the value of the down-counter."
hexmask.long.tbyte 0x0 0.--23. 1. "VALUE,Holds the current timer value of the down-counter. The initial value of the TIMERn register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval or immediately in the following cases: INTVALn register is updated.."
group.long ($2+0x8)++0x7
line.long 0x0 "CTRL,MRT Control register. This register controls the MRT modes."
bitfld.long 0x0 1.--2. "MODE,Selects timer mode." "0: Repeat interrupt mode.,1: One-shot interrupt mode.,2: One-shot stall mode.,?"
bitfld.long 0x0 0. "INTEN,Enable the TIMERn interrupt." "0: Disabled. TIMERn interrupt is disabled.,1: Enabled. TIMERn interrupt is enabled."
line.long 0x4 "STAT,MRT Status register."
bitfld.long 0x4 2. "INUSE,Channel In Use flag. Operating details depend on the MULTITASK bit in the MODCFG register  and affects the use of IDLE_CH. See Idle channel register for details of the two operating modes." "0: This channel is not in use.,1: This channel is in use."
bitfld.long 0x4 1. "RUN,Indicates the state of TIMERn. This bit is read-only." "0: Idle state. TIMERn is stopped.,1: Running. TIMERn is running."
newline
bitfld.long 0x4 0. "INTFLAG,Monitors the interrupt flag." "0: No pending interrupt. Writing a zero is..,1: Pending interrupt. The interrupt is pending.."
tree.end
repeat.end
base ad:0x4000D000
group.long 0xF0++0x3
line.long 0x0 "MODCFG,Module Configuration register. This register provides information about this particular MRT instance. and allows choosing an overall mode for the idle channel feature."
bitfld.long 0x0 31. "MULTITASK,Selects the operating mode for the INUSE flags and the IDLE_CH register." "0: Hardware status mode. In this mode the INUSE(n)..,1: Multi-task mode."
hexmask.long.byte 0x0 4.--8. 1. "NOB,Identifies the number of timer bits in this MRT. (24 bits wide on this device.)"
hexmask.long.byte 0x0 0.--3. 1. "NOC,Identifies the number of channels in this MRT.(4 channels on this device.)"
rgroup.long 0xF4++0x3
line.long 0x0 "IDLE_CH,Idle channel register. This register returns the number of the first idle channel."
hexmask.long.byte 0x0 4.--7. 1. "CHAN,Idle channel. Reading the CHAN bits  returns the lowest idle timer channel. The number is positioned such that it can be used as an offset from the MRT base address in order to access the registers for the allocated channel. If all timer channels.."
group.long 0xF8++0x3
line.long 0x0 "IRQ_FLAG,Global interrupt flag register"
bitfld.long 0x0 3. "GFLAG3,Monitors the interrupt flag of TIMER3. See description of channel 0." "0,1"
bitfld.long 0x0 2. "GFLAG2,Monitors the interrupt flag of TIMER2. See description of channel 0." "0,1"
bitfld.long 0x0 1. "GFLAG1,Monitors the interrupt flag of TIMER1. See description of channel 0." "0,1"
newline
bitfld.long 0x0 0. "GFLAG0,Monitors the interrupt flag of TIMER0." "0: No pending interrupt. Writing a zero is..,1: Pending interrupt. The interrupt is pending.."
tree.end
endif
sif (cpuis("LPC54618*"))
tree "MRT0"
base ad:0x4000D000
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x4000D000 ad:0x4000D010 ad:0x4000D020 ad:0x4000D030)
tree "CHANNEL[$1]"
base $2
group.long ($2)++0x3
line.long 0x0 "INTVAL,MRT Time interval value register. This value is loaded into the TIMER register."
bitfld.long 0x0 31. "LOAD,Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0." "0: No force load. The load from the INTVALn..,1: Force load. The INTVALn interval value IVALUE -1.."
hexmask.long.tbyte 0x0 0.--23. 1. "IVALUE,Time interval load value. This value is loaded into the TIMERn register and the MRT channel n starts counting down from IVALUE -1. If the timer is idle  writing a non-zero value to this bit field starts the timer immediately. If the timer is.."
rgroup.long ($2+0x4)++0x3
line.long 0x0 "TIMER,MRT Timer register. This register reads the value of the down-counter."
hexmask.long.tbyte 0x0 0.--23. 1. "VALUE,Holds the current timer value of the down-counter. The initial value of the TIMERn register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval or immediately in the following cases: INTVALn register is updated.."
group.long ($2+0x8)++0x7
line.long 0x0 "CTRL,MRT Control register. This register controls the MRT modes."
bitfld.long 0x0 1.--2. "MODE,Selects timer mode." "0: Repeat interrupt mode.,1: One-shot interrupt mode.,2: One-shot stall mode.,?"
bitfld.long 0x0 0. "INTEN,Enable the TIMERn interrupt." "0: Disabled. TIMERn interrupt is disabled.,1: Enabled. TIMERn interrupt is enabled."
line.long 0x4 "STAT,MRT Status register."
bitfld.long 0x4 2. "INUSE,Channel In Use flag. Operating details depend on the MULTITASK bit in the MODCFG register  and affects the use of IDLE_CH. See Idle channel register for details of the two operating modes." "0: This channel is not in use.,1: This channel is in use."
bitfld.long 0x4 1. "RUN,Indicates the state of TIMERn. This bit is read-only." "0: Idle state. TIMERn is stopped.,1: Running. TIMERn is running."
newline
bitfld.long 0x4 0. "INTFLAG,Monitors the interrupt flag." "0: No pending interrupt. Writing a zero is..,1: Pending interrupt. The interrupt is pending.."
tree.end
repeat.end
base ad:0x4000D000
group.long 0xF0++0x3
line.long 0x0 "MODCFG,Module Configuration register. This register provides information about this particular MRT instance. and allows choosing an overall mode for the idle channel feature."
bitfld.long 0x0 31. "MULTITASK,Selects the operating mode for the INUSE flags and the IDLE_CH register." "0: Hardware status mode. In this mode the INUSE(n)..,1: Multi-task mode."
hexmask.long.byte 0x0 4.--8. 1. "NOB,Identifies the number of timer bits in this MRT. (24 bits wide on this device.)"
hexmask.long.byte 0x0 0.--3. 1. "NOC,Identifies the number of channels in this MRT.(4 channels on this device.)"
rgroup.long 0xF4++0x3
line.long 0x0 "IDLE_CH,Idle channel register. This register returns the number of the first idle channel."
hexmask.long.byte 0x0 4.--7. 1. "CHAN,Idle channel. Reading the CHAN bits  returns the lowest idle timer channel. The number is positioned such that it can be used as an offset from the MRT base address in order to access the registers for the allocated channel. If all timer channels.."
group.long 0xF8++0x3
line.long 0x0 "IRQ_FLAG,Global interrupt flag register"
bitfld.long 0x0 3. "GFLAG3,Monitors the interrupt flag of TIMER3. See description of channel 0." "0,1"
bitfld.long 0x0 2. "GFLAG2,Monitors the interrupt flag of TIMER2. See description of channel 0." "0,1"
bitfld.long 0x0 1. "GFLAG1,Monitors the interrupt flag of TIMER1. See description of channel 0." "0,1"
newline
bitfld.long 0x0 0. "GFLAG0,Monitors the interrupt flag of TIMER0." "0: No pending interrupt. Writing a zero is..,1: Pending interrupt. The interrupt is pending.."
tree.end
endif
sif (cpuis("LPC54628*"))
tree "MRT0"
base ad:0x4000D000
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x4000D000 ad:0x4000D010 ad:0x4000D020 ad:0x4000D030)
tree "CHANNEL[$1]"
base $2
group.long ($2)++0x3
line.long 0x0 "INTVAL,MRT Time interval value register. This value is loaded into the TIMER register."
bitfld.long 0x0 31. "LOAD,Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0." "0: No force load. The load from the INTVALn..,1: Force load. The INTVALn interval value IVALUE -1.."
hexmask.long.tbyte 0x0 0.--23. 1. "IVALUE,Time interval load value. This value is loaded into the TIMERn register and the MRT channel n starts counting down from IVALUE -1. If the timer is idle  writing a non-zero value to this bit field starts the timer immediately. If the timer is.."
rgroup.long ($2+0x4)++0x3
line.long 0x0 "TIMER,MRT Timer register. This register reads the value of the down-counter."
hexmask.long.tbyte 0x0 0.--23. 1. "VALUE,Holds the current timer value of the down-counter. The initial value of the TIMERn register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval or immediately in the following cases: INTVALn register is updated.."
group.long ($2+0x8)++0x7
line.long 0x0 "CTRL,MRT Control register. This register controls the MRT modes."
bitfld.long 0x0 1.--2. "MODE,Selects timer mode." "0: Repeat interrupt mode.,1: One-shot interrupt mode.,2: One-shot stall mode.,?"
bitfld.long 0x0 0. "INTEN,Enable the TIMERn interrupt." "0: Disabled. TIMERn interrupt is disabled.,1: Enabled. TIMERn interrupt is enabled."
line.long 0x4 "STAT,MRT Status register."
bitfld.long 0x4 2. "INUSE,Channel In Use flag. Operating details depend on the MULTITASK bit in the MODCFG register  and affects the use of IDLE_CH. See Idle channel register for details of the two operating modes." "0: This channel is not in use.,1: This channel is in use."
bitfld.long 0x4 1. "RUN,Indicates the state of TIMERn. This bit is read-only." "0: Idle state. TIMERn is stopped.,1: Running. TIMERn is running."
newline
bitfld.long 0x4 0. "INTFLAG,Monitors the interrupt flag." "0: No pending interrupt. Writing a zero is..,1: Pending interrupt. The interrupt is pending.."
tree.end
repeat.end
base ad:0x4000D000
group.long 0xF0++0x3
line.long 0x0 "MODCFG,Module Configuration register. This register provides information about this particular MRT instance. and allows choosing an overall mode for the idle channel feature."
bitfld.long 0x0 31. "MULTITASK,Selects the operating mode for the INUSE flags and the IDLE_CH register." "0: Hardware status mode. In this mode the INUSE(n)..,1: Multi-task mode."
hexmask.long.byte 0x0 4.--8. 1. "NOB,Identifies the number of timer bits in this MRT. (24 bits wide on this device.)"
hexmask.long.byte 0x0 0.--3. 1. "NOC,Identifies the number of channels in this MRT.(4 channels on this device.)"
rgroup.long 0xF4++0x3
line.long 0x0 "IDLE_CH,Idle channel register. This register returns the number of the first idle channel."
hexmask.long.byte 0x0 4.--7. 1. "CHAN,Idle channel. Reading the CHAN bits  returns the lowest idle timer channel. The number is positioned such that it can be used as an offset from the MRT base address in order to access the registers for the allocated channel. If all timer channels.."
group.long 0xF8++0x3
line.long 0x0 "IRQ_FLAG,Global interrupt flag register"
bitfld.long 0x0 3. "GFLAG3,Monitors the interrupt flag of TIMER3. See description of channel 0." "0,1"
bitfld.long 0x0 2. "GFLAG2,Monitors the interrupt flag of TIMER2. See description of channel 0." "0,1"
bitfld.long 0x0 1. "GFLAG1,Monitors the interrupt flag of TIMER1. See description of channel 0." "0,1"
newline
bitfld.long 0x0 0. "GFLAG0,Monitors the interrupt flag of TIMER0." "0: No pending interrupt. Writing a zero is..,1: Pending interrupt. The interrupt is pending.."
tree.end
endif
tree.end
tree "NVIC (Nested Vectored Interrupt Controller)"
base ad:0xE000E100
group.long 0x0++0xF
line.long 0x0 "NVICISER0,Interrupt Set Enable Register n"
hexmask.long 0x0 0.--31. 1. "SETENA,Interrupt set enable bits"
line.long 0x4 "NVICISER1,Interrupt Set Enable Register n"
hexmask.long 0x4 0.--31. 1. "SETENA,Interrupt set enable bits"
line.long 0x8 "NVICISER2,Interrupt Set Enable Register n"
hexmask.long 0x8 0.--31. 1. "SETENA,Interrupt set enable bits"
line.long 0xC "NVICISER3,Interrupt Set Enable Register n"
hexmask.long 0xC 0.--31. 1. "SETENA,Interrupt set enable bits"
group.long 0x80++0xF
line.long 0x0 "NVICICER0,Interrupt Clear Enable Register n"
hexmask.long 0x0 0.--31. 1. "CLRENA,Interrupt clear-enable bits"
line.long 0x4 "NVICICER1,Interrupt Clear Enable Register n"
hexmask.long 0x4 0.--31. 1. "CLRENA,Interrupt clear-enable bits"
line.long 0x8 "NVICICER2,Interrupt Clear Enable Register n"
hexmask.long 0x8 0.--31. 1. "CLRENA,Interrupt clear-enable bits"
line.long 0xC "NVICICER3,Interrupt Clear Enable Register n"
hexmask.long 0xC 0.--31. 1. "CLRENA,Interrupt clear-enable bits"
group.long 0x100++0xF
line.long 0x0 "NVICISPR0,Interrupt Set Pending Register n"
hexmask.long 0x0 0.--31. 1. "SETPEND,Interrupt set-pending bits"
line.long 0x4 "NVICISPR1,Interrupt Set Pending Register n"
hexmask.long 0x4 0.--31. 1. "SETPEND,Interrupt set-pending bits"
line.long 0x8 "NVICISPR2,Interrupt Set Pending Register n"
hexmask.long 0x8 0.--31. 1. "SETPEND,Interrupt set-pending bits"
line.long 0xC "NVICISPR3,Interrupt Set Pending Register n"
hexmask.long 0xC 0.--31. 1. "SETPEND,Interrupt set-pending bits"
group.long 0x180++0xF
line.long 0x0 "NVICICPR0,Interrupt Clear Pending Register n"
hexmask.long 0x0 0.--31. 1. "CLRPEND,Interrupt clear-pending bits"
line.long 0x4 "NVICICPR1,Interrupt Clear Pending Register n"
hexmask.long 0x4 0.--31. 1. "CLRPEND,Interrupt clear-pending bits"
line.long 0x8 "NVICICPR2,Interrupt Clear Pending Register n"
hexmask.long 0x8 0.--31. 1. "CLRPEND,Interrupt clear-pending bits"
line.long 0xC "NVICICPR3,Interrupt Clear Pending Register n"
hexmask.long 0xC 0.--31. 1. "CLRPEND,Interrupt clear-pending bits"
group.long 0x200++0xF
line.long 0x0 "NVICIABR0,Interrupt Active bit Register n"
hexmask.long 0x0 0.--31. 1. "ACTIVE,Interrupt active flags"
line.long 0x4 "NVICIABR1,Interrupt Active bit Register n"
hexmask.long 0x4 0.--31. 1. "ACTIVE,Interrupt active flags"
line.long 0x8 "NVICIABR2,Interrupt Active bit Register n"
hexmask.long 0x8 0.--31. 1. "ACTIVE,Interrupt active flags"
line.long 0xC "NVICIABR3,Interrupt Active bit Register n"
hexmask.long 0xC 0.--31. 1. "ACTIVE,Interrupt active flags"
group.byte 0x300++0x69
line.byte 0x0 "NVICIP0,Interrupt Priority Register n"
hexmask.byte 0x0 0.--7. 1. "PRI0,Priority of interrupt 0"
line.byte 0x1 "NVICIP1,Interrupt Priority Register n"
hexmask.byte 0x1 0.--7. 1. "PRI1,Priority of interrupt 1"
line.byte 0x2 "NVICIP2,Interrupt Priority Register n"
hexmask.byte 0x2 0.--7. 1. "PRI2,Priority of interrupt 2"
line.byte 0x3 "NVICIP3,Interrupt Priority Register n"
hexmask.byte 0x3 0.--7. 1. "PRI3,Priority of interrupt 3"
line.byte 0x4 "NVICIP4,Interrupt Priority Register n"
hexmask.byte 0x4 0.--7. 1. "PRI4,Priority of interrupt 4"
line.byte 0x5 "NVICIP5,Interrupt Priority Register n"
hexmask.byte 0x5 0.--7. 1. "PRI5,Priority of interrupt 5"
line.byte 0x6 "NVICIP6,Interrupt Priority Register n"
hexmask.byte 0x6 0.--7. 1. "PRI6,Priority of interrupt 6"
line.byte 0x7 "NVICIP7,Interrupt Priority Register n"
hexmask.byte 0x7 0.--7. 1. "PRI7,Priority of interrupt 7"
line.byte 0x8 "NVICIP8,Interrupt Priority Register n"
hexmask.byte 0x8 0.--7. 1. "PRI8,Priority of interrupt 8"
line.byte 0x9 "NVICIP9,Interrupt Priority Register n"
hexmask.byte 0x9 0.--7. 1. "PRI9,Priority of interrupt 9"
line.byte 0xA "NVICIP10,Interrupt Priority Register n"
hexmask.byte 0xA 0.--7. 1. "PRI10,Priority of interrupt 10"
line.byte 0xB "NVICIP11,Interrupt Priority Register n"
hexmask.byte 0xB 0.--7. 1. "PRI11,Priority of interrupt 11"
line.byte 0xC "NVICIP12,Interrupt Priority Register n"
hexmask.byte 0xC 0.--7. 1. "PRI12,Priority of interrupt 12"
line.byte 0xD "NVICIP13,Interrupt Priority Register n"
hexmask.byte 0xD 0.--7. 1. "PRI13,Priority of interrupt 13"
line.byte 0xE "NVICIP14,Interrupt Priority Register n"
hexmask.byte 0xE 0.--7. 1. "PRI14,Priority of interrupt 14"
line.byte 0xF "NVICIP15,Interrupt Priority Register n"
hexmask.byte 0xF 0.--7. 1. "PRI15,Priority of interrupt 15"
line.byte 0x10 "NVICIP16,Interrupt Priority Register n"
hexmask.byte 0x10 0.--7. 1. "PRI16,Priority of interrupt 16"
line.byte 0x11 "NVICIP17,Interrupt Priority Register n"
hexmask.byte 0x11 0.--7. 1. "PRI17,Priority of interrupt 17"
line.byte 0x12 "NVICIP18,Interrupt Priority Register n"
hexmask.byte 0x12 0.--7. 1. "PRI18,Priority of interrupt 18"
line.byte 0x13 "NVICIP19,Interrupt Priority Register n"
hexmask.byte 0x13 0.--7. 1. "PRI19,Priority of interrupt 19"
line.byte 0x14 "NVICIP20,Interrupt Priority Register n"
hexmask.byte 0x14 0.--7. 1. "PRI20,Priority of interrupt 20"
line.byte 0x15 "NVICIP21,Interrupt Priority Register n"
hexmask.byte 0x15 0.--7. 1. "PRI21,Priority of interrupt 21"
line.byte 0x16 "NVICIP22,Interrupt Priority Register n"
hexmask.byte 0x16 0.--7. 1. "PRI22,Priority of interrupt 22"
line.byte 0x17 "NVICIP23,Interrupt Priority Register n"
hexmask.byte 0x17 0.--7. 1. "PRI23,Priority of interrupt 23"
line.byte 0x18 "NVICIP24,Interrupt Priority Register n"
hexmask.byte 0x18 0.--7. 1. "PRI24,Priority of interrupt 24"
line.byte 0x19 "NVICIP25,Interrupt Priority Register n"
hexmask.byte 0x19 0.--7. 1. "PRI25,Priority of interrupt 25"
line.byte 0x1A "NVICIP26,Interrupt Priority Register n"
hexmask.byte 0x1A 0.--7. 1. "PRI26,Priority of interrupt 26"
line.byte 0x1B "NVICIP27,Interrupt Priority Register n"
hexmask.byte 0x1B 0.--7. 1. "PRI27,Priority of interrupt 27"
line.byte 0x1C "NVICIP28,Interrupt Priority Register n"
hexmask.byte 0x1C 0.--7. 1. "PRI28,Priority of interrupt 28"
line.byte 0x1D "NVICIP29,Interrupt Priority Register n"
hexmask.byte 0x1D 0.--7. 1. "PRI29,Priority of interrupt 29"
line.byte 0x1E "NVICIP30,Interrupt Priority Register n"
hexmask.byte 0x1E 0.--7. 1. "PRI30,Priority of interrupt 30"
line.byte 0x1F "NVICIP31,Interrupt Priority Register n"
hexmask.byte 0x1F 0.--7. 1. "PRI31,Priority of interrupt 31"
line.byte 0x20 "NVICIP32,Interrupt Priority Register n"
hexmask.byte 0x20 0.--7. 1. "PRI32,Priority of interrupt 32"
line.byte 0x21 "NVICIP33,Interrupt Priority Register n"
hexmask.byte 0x21 0.--7. 1. "PRI33,Priority of interrupt 33"
line.byte 0x22 "NVICIP34,Interrupt Priority Register n"
hexmask.byte 0x22 0.--7. 1. "PRI34,Priority of interrupt 34"
line.byte 0x23 "NVICIP35,Interrupt Priority Register n"
hexmask.byte 0x23 0.--7. 1. "PRI35,Priority of interrupt 35"
line.byte 0x24 "NVICIP36,Interrupt Priority Register n"
hexmask.byte 0x24 0.--7. 1. "PRI36,Priority of interrupt 36"
line.byte 0x25 "NVICIP37,Interrupt Priority Register n"
hexmask.byte 0x25 0.--7. 1. "PRI37,Priority of interrupt 37"
line.byte 0x26 "NVICIP38,Interrupt Priority Register n"
hexmask.byte 0x26 0.--7. 1. "PRI38,Priority of interrupt 38"
line.byte 0x27 "NVICIP39,Interrupt Priority Register n"
hexmask.byte 0x27 0.--7. 1. "PRI39,Priority of interrupt 39"
line.byte 0x28 "NVICIP40,Interrupt Priority Register n"
hexmask.byte 0x28 0.--7. 1. "PRI40,Priority of interrupt 40"
line.byte 0x29 "NVICIP41,Interrupt Priority Register n"
hexmask.byte 0x29 0.--7. 1. "PRI41,Priority of interrupt 41"
line.byte 0x2A "NVICIP42,Interrupt Priority Register n"
hexmask.byte 0x2A 0.--7. 1. "PRI42,Priority of interrupt 42"
line.byte 0x2B "NVICIP43,Interrupt Priority Register n"
hexmask.byte 0x2B 0.--7. 1. "PRI43,Priority of interrupt 43"
line.byte 0x2C "NVICIP44,Interrupt Priority Register n"
hexmask.byte 0x2C 0.--7. 1. "PRI44,Priority of interrupt 44"
line.byte 0x2D "NVICIP45,Interrupt Priority Register n"
hexmask.byte 0x2D 0.--7. 1. "PRI45,Priority of interrupt 45"
line.byte 0x2E "NVICIP46,Interrupt Priority Register n"
hexmask.byte 0x2E 0.--7. 1. "PRI46,Priority of interrupt 46"
line.byte 0x2F "NVICIP47,Interrupt Priority Register n"
hexmask.byte 0x2F 0.--7. 1. "PRI47,Priority of interrupt 47"
line.byte 0x30 "NVICIP48,Interrupt Priority Register n"
hexmask.byte 0x30 0.--7. 1. "PRI48,Priority of interrupt 48"
line.byte 0x31 "NVICIP49,Interrupt Priority Register n"
hexmask.byte 0x31 0.--7. 1. "PRI49,Priority of interrupt 49"
line.byte 0x32 "NVICIP50,Interrupt Priority Register n"
hexmask.byte 0x32 0.--7. 1. "PRI50,Priority of interrupt 50"
line.byte 0x33 "NVICIP51,Interrupt Priority Register n"
hexmask.byte 0x33 0.--7. 1. "PRI51,Priority of interrupt 51"
line.byte 0x34 "NVICIP52,Interrupt Priority Register n"
hexmask.byte 0x34 0.--7. 1. "PRI52,Priority of interrupt 52"
line.byte 0x35 "NVICIP53,Interrupt Priority Register n"
hexmask.byte 0x35 0.--7. 1. "PRI53,Priority of interrupt 53"
line.byte 0x36 "NVICIP54,Interrupt Priority Register n"
hexmask.byte 0x36 0.--7. 1. "PRI54,Priority of interrupt 54"
line.byte 0x37 "NVICIP55,Interrupt Priority Register n"
hexmask.byte 0x37 0.--7. 1. "PRI55,Priority of interrupt 55"
line.byte 0x38 "NVICIP56,Interrupt Priority Register n"
hexmask.byte 0x38 0.--7. 1. "PRI56,Priority of interrupt 56"
line.byte 0x39 "NVICIP57,Interrupt Priority Register n"
hexmask.byte 0x39 0.--7. 1. "PRI57,Priority of interrupt 57"
line.byte 0x3A "NVICIP58,Interrupt Priority Register n"
hexmask.byte 0x3A 0.--7. 1. "PRI58,Priority of interrupt 58"
line.byte 0x3B "NVICIP59,Interrupt Priority Register n"
hexmask.byte 0x3B 0.--7. 1. "PRI59,Priority of interrupt 59"
line.byte 0x3C "NVICIP60,Interrupt Priority Register n"
hexmask.byte 0x3C 0.--7. 1. "PRI60,Priority of interrupt 60"
line.byte 0x3D "NVICIP61,Interrupt Priority Register n"
hexmask.byte 0x3D 0.--7. 1. "PRI61,Priority of interrupt 61"
line.byte 0x3E "NVICIP62,Interrupt Priority Register n"
hexmask.byte 0x3E 0.--7. 1. "PRI62,Priority of interrupt 62"
line.byte 0x3F "NVICIP63,Interrupt Priority Register n"
hexmask.byte 0x3F 0.--7. 1. "PRI63,Priority of interrupt 63"
line.byte 0x40 "NVICIP64,Interrupt Priority Register n"
hexmask.byte 0x40 0.--7. 1. "PRI64,Priority of interrupt 64"
line.byte 0x41 "NVICIP65,Interrupt Priority Register n"
hexmask.byte 0x41 0.--7. 1. "PRI65,Priority of interrupt 65"
line.byte 0x42 "NVICIP66,Interrupt Priority Register n"
hexmask.byte 0x42 0.--7. 1. "PRI66,Priority of interrupt 66"
line.byte 0x43 "NVICIP67,Interrupt Priority Register n"
hexmask.byte 0x43 0.--7. 1. "PRI67,Priority of interrupt 67"
line.byte 0x44 "NVICIP68,Interrupt Priority Register n"
hexmask.byte 0x44 0.--7. 1. "PRI68,Priority of interrupt 68"
line.byte 0x45 "NVICIP69,Interrupt Priority Register n"
hexmask.byte 0x45 0.--7. 1. "PRI69,Priority of interrupt 69"
line.byte 0x46 "NVICIP70,Interrupt Priority Register n"
hexmask.byte 0x46 0.--7. 1. "PRI70,Priority of interrupt 70"
line.byte 0x47 "NVICIP71,Interrupt Priority Register n"
hexmask.byte 0x47 0.--7. 1. "PRI71,Priority of interrupt 71"
line.byte 0x48 "NVICIP72,Interrupt Priority Register n"
hexmask.byte 0x48 0.--7. 1. "PRI72,Priority of interrupt 72"
line.byte 0x49 "NVICIP73,Interrupt Priority Register n"
hexmask.byte 0x49 0.--7. 1. "PRI73,Priority of interrupt 73"
line.byte 0x4A "NVICIP74,Interrupt Priority Register n"
hexmask.byte 0x4A 0.--7. 1. "PRI74,Priority of interrupt 74"
line.byte 0x4B "NVICIP75,Interrupt Priority Register n"
hexmask.byte 0x4B 0.--7. 1. "PRI75,Priority of interrupt 75"
line.byte 0x4C "NVICIP76,Interrupt Priority Register n"
hexmask.byte 0x4C 0.--7. 1. "PRI76,Priority of interrupt 76"
line.byte 0x4D "NVICIP77,Interrupt Priority Register n"
hexmask.byte 0x4D 0.--7. 1. "PRI77,Priority of interrupt 77"
line.byte 0x4E "NVICIP78,Interrupt Priority Register n"
hexmask.byte 0x4E 0.--7. 1. "PRI78,Priority of interrupt 78"
line.byte 0x4F "NVICIP79,Interrupt Priority Register n"
hexmask.byte 0x4F 0.--7. 1. "PRI79,Priority of interrupt 79"
line.byte 0x50 "NVICIP80,Interrupt Priority Register n"
hexmask.byte 0x50 0.--7. 1. "PRI80,Priority of interrupt 80"
line.byte 0x51 "NVICIP81,Interrupt Priority Register n"
hexmask.byte 0x51 0.--7. 1. "PRI81,Priority of interrupt 81"
line.byte 0x52 "NVICIP82,Interrupt Priority Register n"
hexmask.byte 0x52 0.--7. 1. "PRI82,Priority of interrupt 82"
line.byte 0x53 "NVICIP83,Interrupt Priority Register n"
hexmask.byte 0x53 0.--7. 1. "PRI83,Priority of interrupt 83"
line.byte 0x54 "NVICIP84,Interrupt Priority Register n"
hexmask.byte 0x54 0.--7. 1. "PRI84,Priority of interrupt 84"
line.byte 0x55 "NVICIP85,Interrupt Priority Register n"
hexmask.byte 0x55 0.--7. 1. "PRI85,Priority of interrupt 85"
line.byte 0x56 "NVICIP86,Interrupt Priority Register n"
hexmask.byte 0x56 0.--7. 1. "PRI86,Priority of interrupt 86"
line.byte 0x57 "NVICIP87,Interrupt Priority Register n"
hexmask.byte 0x57 0.--7. 1. "PRI87,Priority of interrupt 87"
line.byte 0x58 "NVICIP88,Interrupt Priority Register n"
hexmask.byte 0x58 0.--7. 1. "PRI88,Priority of interrupt 88"
line.byte 0x59 "NVICIP89,Interrupt Priority Register n"
hexmask.byte 0x59 0.--7. 1. "PRI89,Priority of interrupt 89"
line.byte 0x5A "NVICIP90,Interrupt Priority Register n"
hexmask.byte 0x5A 0.--7. 1. "PRI90,Priority of interrupt 90"
line.byte 0x5B "NVICIP91,Interrupt Priority Register n"
hexmask.byte 0x5B 0.--7. 1. "PRI91,Priority of interrupt 91"
line.byte 0x5C "NVICIP92,Interrupt Priority Register n"
hexmask.byte 0x5C 0.--7. 1. "PRI92,Priority of interrupt 92"
line.byte 0x5D "NVICIP93,Interrupt Priority Register n"
hexmask.byte 0x5D 0.--7. 1. "PRI93,Priority of interrupt 93"
line.byte 0x5E "NVICIP94,Interrupt Priority Register n"
hexmask.byte 0x5E 0.--7. 1. "PRI94,Priority of interrupt 94"
line.byte 0x5F "NVICIP95,Interrupt Priority Register n"
hexmask.byte 0x5F 0.--7. 1. "PRI95,Priority of interrupt 95"
line.byte 0x60 "NVICIP96,Interrupt Priority Register n"
hexmask.byte 0x60 0.--7. 1. "PRI96,Priority of interrupt 96"
line.byte 0x61 "NVICIP97,Interrupt Priority Register n"
hexmask.byte 0x61 0.--7. 1. "PRI97,Priority of interrupt 97"
line.byte 0x62 "NVICIP98,Interrupt Priority Register n"
hexmask.byte 0x62 0.--7. 1. "PRI98,Priority of interrupt 98"
line.byte 0x63 "NVICIP99,Interrupt Priority Register n"
hexmask.byte 0x63 0.--7. 1. "PRI99,Priority of interrupt 99"
line.byte 0x64 "NVICIP100,Interrupt Priority Register n"
hexmask.byte 0x64 0.--7. 1. "PRI100,Priority of interrupt 100"
line.byte 0x65 "NVICIP101,Interrupt Priority Register n"
hexmask.byte 0x65 0.--7. 1. "PRI101,Priority of interrupt 101"
line.byte 0x66 "NVICIP102,Interrupt Priority Register n"
hexmask.byte 0x66 0.--7. 1. "PRI102,Priority of interrupt 102"
line.byte 0x67 "NVICIP103,Interrupt Priority Register n"
hexmask.byte 0x67 0.--7. 1. "PRI103,Priority of interrupt 103"
line.byte 0x68 "NVICIP104,Interrupt Priority Register n"
hexmask.byte 0x68 0.--7. 1. "PRI104,Priority of interrupt 104"
line.byte 0x69 "NVICIP105,Interrupt Priority Register n"
hexmask.byte 0x69 0.--7. 1. "PRI105,Priority of interrupt 105"
group.long 0xE00++0x3
line.long 0x0 "NVICSTIR,Software Trigger Interrupt Register"
hexmask.long.word 0x0 0.--8. 1. "INTID,Interrupt ID of the interrupt to trigger  in the range 0-239. For example  a value of 0x03 specifies interrupt IRQ3."
tree.end
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54605*")||cpuis("LPC54606*")||cpuis("LPC54607*")||cpuis("LPC54608*")||cpuis("LPC54616*")||cpuis("LPC54618*")||cpuis("LPC54628*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
tree "OTPC (One Time Programmable Memory Controller)"
base ad:0x40015000
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x10)++0x3
line.long 0x0 "AESKEY[$1],Register for reading the AES key."
hexmask.long 0x0 0.--31. 1. "KEY,AES key."
repeat.end
rgroup.long 0x30++0x3
line.long 0x0 "ECRP,ECRP options."
bitfld.long 0x0 31. "JTAG_DISABLE,0 => Enable SWD/JTAG; 1 => Disable SWD/JTAG.." "0: Enable SWD/JTAG,1: Disable SWD/JTAG"
bitfld.long 0x0 9. "CRP_ALLOW_ZERO,This bit controls how 0 is treated when read as a ECRP value.." "0,1"
bitfld.long 0x0 7. "CRP_ISP_DISABLE_IAP,This bit controls the ability to re-invoke ISP using IAP routines." "0,1"
bitfld.long 0x0 6. "CRP_ISP_DISABLE_PIN,This bit controls the ability to enter ISP mode using the ISP pin." "0,1"
bitfld.long 0x0 5. "IAP_PROTECTION_ENABLE,This bit controls the ability to enable checking for ECRP in IAP functions." "0,1"
newline
bitfld.long 0x0 4. "CRP_MASS_ERASE_DISABLE,Disable or enable CRP mass erase." "0,1"
rgroup.long 0x38++0x7
line.long 0x0 "USER0,User application specific options."
hexmask.long 0x0 0.--31. 1. "USER0,User application specific option."
line.long 0x4 "USER1,User application specific options."
hexmask.long 0x4 0.--31. 1. "USER1,User application specific option."
tree.end
endif
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54113*")||cpuis("LPC54114*")||cpuis("LPC54605*")||cpuis("LPC54606*")||cpuis("LPC54607*")||cpuis("LPC54608*")||cpuis("LPC54616*")||cpuis("LPC54618*")||cpuis("LPC54628*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
base ad:0x40004000
elif (cpuis("LPC54101*")||cpuis("LPC54102*"))
base ad:0x40018000
endif
tree "PINT (Pin Interrupt and Pattern Match)"
group.long 0x0++0x7
line.long 0x0 "ISEL,Pin Interrupt Mode register"
hexmask.long.byte 0x0 0.--7. 1. "PMODE,Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive"
line.long 0x4 "IENR,Pin interrupt level or rising edge interrupt enable register"
hexmask.long.byte 0x4 0.--7. 1. "ENRL,Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt."
wgroup.long 0x8++0x7
line.long 0x0 "SIENR,Pin interrupt level or rising edge interrupt set register"
hexmask.long.byte 0x0 0.--7. 1. "SETENRL,Ones written to this address set bits in the IENR  thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt."
line.long 0x4 "CIENR,Pin interrupt level (rising edge interrupt) clear register"
hexmask.long.byte 0x4 0.--7. 1. "CENRL,Ones written to this address clear bits in the IENR  thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt."
group.long 0x10++0x3
line.long 0x0 "IENF,Pin interrupt active level or falling edge interrupt enable register"
hexmask.long.byte 0x0 0.--7. 1. "ENAF,Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge.."
wgroup.long 0x14++0x7
line.long 0x0 "SIENF,Pin interrupt active level or falling edge interrupt set register"
hexmask.long.byte 0x0 0.--7. 1. "SETENAF,Ones written to this address set bits in the IENF  thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt."
line.long 0x4 "CIENF,Pin interrupt active level or falling edge interrupt clear register"
hexmask.long.byte 0x4 0.--7. 1. "CENAF,Ones written to this address clears bits in the IENF  thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled."
group.long 0x1C++0x17
line.long 0x0 "RISE,Pin interrupt rising edge register"
hexmask.long.byte 0x0 0.--7. 1. "RDET,Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been.."
line.long 0x4 "FALL,Pin interrupt falling edge register"
hexmask.long.byte 0x4 0.--7. 1. "FDET,Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has.."
line.long 0x8 "IST,Pin interrupt status register"
hexmask.long.byte 0x8 0.--7. 1. "PSTAT,Pin interrupt status. Bit n returns the status  clears the edge interrupt  or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is.."
line.long 0xC "PMCTRL,Pattern match interrupt control register"
hexmask.long.byte 0xC 24.--31. 1. "PMAT,This field displays the current state of pattern matches. A 1 in any bit of this field indicates that the corresponding product term is matched by the current state of the appropriate inputs."
bitfld.long 0xC 1. "ENA_RXEV,Enables the RXEV output to the CPU and/or to a GPIO output when the specified boolean expression evaluates to true." "0: Disabled. RXEV output to the CPU is disabled.,1: Enabled. RXEV output to the CPU is enabled."
newline
bitfld.long 0xC 0. "SEL_PMATCH,Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match function." "0: Pin interrupt. Interrupts are driven in response..,1: Pattern match. Interrupts are driven in response.."
line.long 0x10 "PMSRC,Pattern match interrupt bit-slice source register"
bitfld.long 0x10 29.--31. "SRC7,Selects the input source for bit slice 7" "0: Input 0. Selects the pin selected in the..,1: Input 1. Selects the pin selected in the..,2: Input 2. Selects the pin selected in the..,3: Input 3. Selects the pin selected in the..,4: Input 4. Selects the pin selected in the..,5: Input 5. Selects the pin selected in the..,6: Input 6. Selects the pin selected in the..,7: Input 7. Selects the pin selected in the.."
bitfld.long 0x10 26.--28. "SRC6,Selects the input source for bit slice 6" "0: Input 0. Selects the pin selected in the..,1: Input 1. Selects the pin selected in the..,2: Input 2. Selects the pin selected in the..,3: Input 3. Selects the pin selected in the..,4: Input 4. Selects the pin selected in the..,5: Input 5. Selects the pin selected in the..,6: Input 6. Selects the pin selected in the..,7: Input 7. Selects the pin selected in the.."
newline
bitfld.long 0x10 23.--25. "SRC5,Selects the input source for bit slice 5" "0: Input 0. Selects the pin selected in the..,1: Input 1. Selects the pin selected in the..,2: Input 2. Selects the pin selected in the..,3: Input 3. Selects the pin selected in the..,4: Input 4. Selects the pin selected in the..,5: Input 5. Selects the pin selected in the..,6: Input 6. Selects the pin selected in the..,7: Input 7. Selects the pin selected in the.."
bitfld.long 0x10 20.--22. "SRC4,Selects the input source for bit slice 4" "0: Input 0. Selects the pin selected in the..,1: Input 1. Selects the pin selected in the..,2: Input 2. Selects the pin selected in the..,3: Input 3. Selects the pin selected in the..,4: Input 4. Selects the pin selected in the..,5: Input 5. Selects the pin selected in the..,6: Input 6. Selects the pin selected in the..,7: Input 7. Selects the pin selected in the.."
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bitfld.long 0x10 17.--19. "SRC3,Selects the input source for bit slice 3" "0: Input 0. Selects the pin selected in the..,1: Input 1. Selects the pin selected in the..,2: Input 2. Selects the pin selected in the..,3: Input 3. Selects the pin selected in the..,4: Input 4. Selects the pin selected in the..,5: Input 5. Selects the pin selected in the..,6: Input 6. Selects the pin selected in the..,7: Input 7. Selects the pin selected in the.."
bitfld.long 0x10 14.--16. "SRC2,Selects the input source for bit slice 2" "0: Input 0. Selects the pin selected in the..,1: Input 1. Selects the pin selected in the..,2: Input 2. Selects the pin selected in the..,3: Input 3. Selects the pin selected in the..,4: Input 4. Selects the pin selected in the..,5: Input 5. Selects the pin selected in the..,6: Input 6. Selects the pin selected in the..,7: Input 7. Selects the pin selected in the.."
newline
bitfld.long 0x10 11.--13. "SRC1,Selects the input source for bit slice 1" "0: Input 0. Selects the pin selected in the..,1: Input 1. Selects the pin selected in the..,2: Input 2. Selects the pin selected in the..,3: Input 3. Selects the pin selected in the..,4: Input 4. Selects the pin selected in the..,5: Input 5. Selects the pin selected in the..,6: Input 6. Selects the pin selected in the..,7: Input 7. Selects the pin selected in the.."
bitfld.long 0x10 8.--10. "SRC0,Selects the input source for bit slice 0" "0: Input 0. Selects the pin selected in the..,1: Input 1. Selects the pin selected in the..,2: Input 2. Selects the pin selected in the..,3: Input 3. Selects the pin selected in the..,4: Input 4. Selects the pin selected in the..,5: Input 5. Selects the pin selected in the..,6: Input 6. Selects the pin selected in the..,7: Input 7. Selects the pin selected in the.."
line.long 0x14 "PMCFG,Pattern match interrupt bit slice configuration register"
bitfld.long 0x14 29.--31. "CFG7,Specifies the match contribution condition for bit slice 7." "0: Constant HIGH. This bit slice always contributes..,1: Sticky rising edge. Match occurs if a rising..,2: Sticky falling edge. Match occurs if a falling..,3: Sticky rising or falling edge. Match occurs if..,4: High level. Match (for this bit slice) occurs..,5: Low level. Match occurs when there is a low..,6: Constant 0. This bit slice never contributes to..,7: Event. Non-sticky rising or falling edge. Match.."
bitfld.long 0x14 26.--28. "CFG6,Specifies the match contribution condition for bit slice 6." "0: Constant HIGH. This bit slice always contributes..,1: Sticky rising edge. Match occurs if a rising..,2: Sticky falling edge. Match occurs if a falling..,3: Sticky rising or falling edge. Match occurs if..,4: High level. Match (for this bit slice) occurs..,5: Low level. Match occurs when there is a low..,6: Constant 0. This bit slice never contributes to..,7: Event. Non-sticky rising or falling edge. Match.."
newline
bitfld.long 0x14 23.--25. "CFG5,Specifies the match contribution condition for bit slice 5." "0: Constant HIGH. This bit slice always contributes..,1: Sticky rising edge. Match occurs if a rising..,2: Sticky falling edge. Match occurs if a falling..,3: Sticky rising or falling edge. Match occurs if..,4: High level. Match (for this bit slice) occurs..,5: Low level. Match occurs when there is a low..,6: Constant 0. This bit slice never contributes to..,7: Event. Non-sticky rising or falling edge. Match.."
bitfld.long 0x14 20.--22. "CFG4,Specifies the match contribution condition for bit slice 4." "0: Constant HIGH. This bit slice always contributes..,1: Sticky rising edge. Match occurs if a rising..,2: Sticky falling edge. Match occurs if a falling..,3: Sticky rising or falling edge. Match occurs if..,4: High level. Match (for this bit slice) occurs..,5: Low level. Match occurs when there is a low..,6: Constant 0. This bit slice never contributes to..,7: Event. Non-sticky rising or falling edge. Match.."
newline
bitfld.long 0x14 17.--19. "CFG3,Specifies the match contribution condition for bit slice 3." "0: Constant HIGH. This bit slice always contributes..,1: Sticky rising edge. Match occurs if a rising..,2: Sticky falling edge. Match occurs if a falling..,3: Sticky rising or falling edge. Match occurs if..,4: High level. Match (for this bit slice) occurs..,5: Low level. Match occurs when there is a low..,6: Constant 0. This bit slice never contributes to..,7: Event. Non-sticky rising or falling edge. Match.."
bitfld.long 0x14 14.--16. "CFG2,Specifies the match contribution condition for bit slice 2." "0: Constant HIGH. This bit slice always contributes..,1: Sticky rising edge. Match occurs if a rising..,2: Sticky falling edge. Match occurs if a falling..,3: Sticky rising or falling edge. Match occurs if..,4: High level. Match (for this bit slice) occurs..,5: Low level. Match occurs when there is a low..,6: Constant 0. This bit slice never contributes to..,7: Event. Non-sticky rising or falling edge. Match.."
newline
bitfld.long 0x14 11.--13. "CFG1,Specifies the match contribution condition for bit slice 1." "0: Constant HIGH. This bit slice always contributes..,1: Sticky rising edge. Match occurs if a rising..,2: Sticky falling edge. Match occurs if a falling..,3: Sticky rising or falling edge. Match occurs if..,4: High level. Match (for this bit slice) occurs..,5: Low level. Match occurs when there is a low..,6: Constant 0. This bit slice never contributes to..,7: Event. Non-sticky rising or falling edge. Match.."
bitfld.long 0x14 8.--10. "CFG0,Specifies the match contribution condition for bit slice 0." "0: Constant HIGH. This bit slice always contributes..,1: Sticky rising edge. Match occurs if a rising..,2: Sticky falling edge. Match occurs if a falling..,3: Sticky rising or falling edge. Match occurs if..,4: High level. Match (for this bit slice) occurs..,5: Low level. Match occurs when there is a low..,6: Constant 0. This bit slice never contributes to..,7: Event. Non-sticky rising or falling edge. Match.."
newline
bitfld.long 0x14 6. "PROD_ENDPTS6,Determines whether slice 6 is an endpoint." "0: No effect. Slice 6 is not an endpoint.,1: endpoint. Slice 6 is the endpoint of a product.."
bitfld.long 0x14 5. "PROD_ENDPTS5,Determines whether slice 5 is an endpoint." "0: No effect. Slice 5 is not an endpoint.,1: endpoint. Slice 5 is the endpoint of a product.."
newline
bitfld.long 0x14 4. "PROD_ENDPTS4,Determines whether slice 4 is an endpoint." "0: No effect. Slice 4 is not an endpoint.,1: endpoint. Slice 4 is the endpoint of a product.."
bitfld.long 0x14 3. "PROD_ENDPTS3,Determines whether slice 3 is an endpoint." "0: No effect. Slice 3 is not an endpoint.,1: endpoint. Slice 3 is the endpoint of a product.."
newline
bitfld.long 0x14 2. "PROD_ENDPTS2,Determines whether slice 2 is an endpoint." "0: No effect. Slice 2 is not an endpoint.,1: endpoint. Slice 2 is the endpoint of a product.."
bitfld.long 0x14 1. "PROD_ENDPTS1,Determines whether slice 1 is an endpoint." "0: No effect. Slice 1 is not an endpoint.,1: endpoint. Slice 1 is the endpoint of a product.."
newline
bitfld.long 0x14 0. "PROD_ENDPTS0,Determines whether slice 0 is an endpoint." "0: No effect. Slice 0 is not an endpoint.,1: endpoint. Slice 0 is the endpoint of a product.."
tree.end
sif (cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
tree "PUF (Physical Unclonable Function)"
base ad:0x4003B000
group.long 0x0++0xB
line.long 0x0 "CTRL,PUF Control register"
bitfld.long 0x0 6. "GETKEY,Begin Get Key operation" "0,1"
bitfld.long 0x0 4. "SETKEY,Begin Set User Key operation" "0,1"
bitfld.long 0x0 3. "GENERATEKEY,Begin Set Intrinsic Key operation" "0,1"
bitfld.long 0x0 2. "start,Begin Start operation" "0,1"
bitfld.long 0x0 1. "enroll,Begin Enroll operation" "0,1"
newline
bitfld.long 0x0 0. "zeroize,Begin Zeroize operation for Quiddikey and go to Error state" "0,1"
line.long 0x4 "KEYINDEX,PUF Key Index register"
hexmask.long.byte 0x4 0.--3. 1. "KEYIDX,Key index for Set Key operations"
line.long 0x8 "KEYSIZE,PUF Key Size register"
hexmask.long.byte 0x8 0.--5. 1. "KEYSIZE,Key size for Set Key operations"
rgroup.long 0x20++0x3
line.long 0x0 "STAT,PUF Status register"
bitfld.long 0x0 7. "CODEOUTAVAIL,Next part of AC/KC is available" "0,1"
bitfld.long 0x0 6. "CODEINREQ,Request for next part of AC/KC" "0,1"
bitfld.long 0x0 5. "KEYOUTAVAIL,Next part of key is available" "0,1"
bitfld.long 0x0 4. "KEYINREQ,Request for next part of key" "0,1"
bitfld.long 0x0 2. "error,Quiddikey is in the Error state and no operations can be performed" "0,1"
newline
bitfld.long 0x0 1. "SUCCESS,Last operation was successful" "0,1"
bitfld.long 0x0 0. "busy,Indicates that operation is in progress" "0,1"
rgroup.long 0x28++0x3
line.long 0x0 "ALLOW,PUF Allow register"
bitfld.long 0x0 3. "ALLOWGETKEY,Get Key operation is allowed" "0,1"
bitfld.long 0x0 2. "ALLOWSETKEY,Set Key operations are allowed" "0,1"
bitfld.long 0x0 1. "ALLOWSTART,Start operation is allowed" "0,1"
bitfld.long 0x0 0. "ALLOWENROLL,Enroll operation is allowed" "0,1"
wgroup.long 0x40++0x7
line.long 0x0 "KEYINPUT,PUF Key Input register"
hexmask.long 0x0 0.--31. 1. "KEYIN,Key input data"
line.long 0x4 "CODEINPUT,PUF Code Input register"
hexmask.long 0x4 0.--31. 1. "CODEIN,AC/KC input data"
rgroup.long 0x48++0x3
line.long 0x0 "CODEOUTPUT,PUF Code Output register"
hexmask.long 0x0 0.--31. 1. "CODEOUT,AC/KC output data"
rgroup.long 0x60++0x7
line.long 0x0 "KEYOUTINDEX,PUF Key Output Index register"
hexmask.long.byte 0x0 0.--3. 1. "KEYOUTIDX,Key index for the key that is currently output via the Key Output register"
line.long 0x4 "KEYOUTPUT,PUF Key Output register"
hexmask.long 0x4 0.--31. 1. "KEYOUT,Key output data"
group.long 0xDC++0x3
line.long 0x0 "IFSTAT,PUF Interface Status and clear register"
bitfld.long 0x0 0. "ERROR,Indicates that an APB error has occurred Writing logic1 clears the if_error bit" "0,1"
group.long 0x100++0xF
line.long 0x0 "INTEN,PUF Interrupt Enable"
bitfld.long 0x0 7. "CODEOUTAVAILEN,Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register)" "0,1"
bitfld.long 0x0 6. "CODEINREQEN,Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register)" "0,1"
bitfld.long 0x0 5. "KEYOUTAVAILEN,Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register)" "0,1"
bitfld.long 0x0 4. "KEYINREQEN,Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register)" "0,1"
bitfld.long 0x0 2. "ERROREN,Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register)" "0,1"
newline
bitfld.long 0x0 1. "SUCCESEN,Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register)" "0,1"
bitfld.long 0x0 0. "READYEN,Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register)" "0,1"
line.long 0x4 "INTSTAT,PUF interrupt status"
bitfld.long 0x4 7. "CODEOUTAVAIL,Level sensitive interrupt  cleared when interrupt source clears" "0,1"
bitfld.long 0x4 6. "CODEINREQ,Level sensitive interrupt  cleared when interrupt source clears" "0,1"
bitfld.long 0x4 5. "KEYOUTAVAIL,Level sensitive interrupt  cleared when interrupt source clears" "0,1"
bitfld.long 0x4 4. "KEYINREQ,Level sensitive interrupt  cleared when interrupt source clears" "0,1"
bitfld.long 0x4 2. "ERROR,Level sensitive interrupt  cleared when interrupt source clears" "0,1"
newline
bitfld.long 0x4 1. "SUCCESS,Level sensitive interrupt  cleared when interrupt source clears" "0,1"
bitfld.long 0x4 0. "READY,Triggers on falling edge of busy  write 1 to clear" "0,1"
line.long 0x8 "PWRCTRL,PUF RAM Power Control"
bitfld.long 0x8 1. "RAMSTAT,PUF RAM status." "0,1"
bitfld.long 0x8 0. "RAMON,Power on the PUF RAM." "0,1"
line.long 0xC "CFG,PUF config register for block bits"
bitfld.long 0xC 1. "BLOCKKEYOUTPUT,Block set key operation. Write 1 to set  cleared on reset." "0,1"
bitfld.long 0xC 0. "BLOCKENROLL_SETKEY,Block enroll operation. Write 1 to set  cleared on reset." "0,1"
tree.end
endif
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54605*")||cpuis("LPC54606*")||cpuis("LPC54607*")||cpuis("LPC54608*")||cpuis("LPC54616*")||cpuis("LPC54618*")||cpuis("LPC54628*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
base ad:0x4002D000
elif (cpuis("LPC54101*")||cpuis("LPC54102*"))
base ad:0x40070000
endif
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54101*")||cpuis("LPC54102*")||cpuis("LPC54605*")||cpuis("LPC54606*")||cpuis("LPC54607*")||cpuis("LPC54608*")||cpuis("LPC54616*")||cpuis("LPC54618*")||cpuis("LPC54628*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
tree "RIT (Repetitive Interrupt Timer)"
group.long 0x0++0x17
line.long 0x0 "COMPVAL,Compare value LSB register"
hexmask.long 0x0 0.--31. 1. "RICOMP,."
line.long 0x4 "MASK,Mask LSB register"
hexmask.long 0x4 0.--31. 1. "RIMASK,Mask register."
line.long 0x8 "CTRL,Control register"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x8 3. "RITEN,Timer enable." "0,1"
bitfld.long 0x8 2. "RITENBR,Timer enable for debug." "0,1"
newline
bitfld.long 0x8 1. "RITENCLR,Timer enable clear." "0,1"
bitfld.long 0x8 0. "RITINT,Interrupt flag." "0,1"
newline
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x8 3. "RITEN,Timer enable." "0: Timer disabled.,1: Timer enabled. This can be overruled by a debug.."
bitfld.long 0x8 2. "RITENBR,Timer enable for debug" "0: Debug has no effect on the timer operation.,1: The timer is halted when the processor is halted.."
newline
bitfld.long 0x8 1. "RITENCLR,Timer enable clear" "0: The timer will not be cleared to 0.,1: The timer will be cleared to 0 whenever the.."
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x8 3. "RITEN,Timer enable." "0: Timer disabled.,1: Timer enabled. This can be overruled by a debug.."
newline
bitfld.long 0x8 2. "RITENBR,Timer enable for debug" "0: Debug has no effect on the timer operation.,1: The timer is halted when the processor is halted.."
bitfld.long 0x8 1. "RITENCLR,Timer enable clear" "0: The timer will not be cleared to 0.,1: The timer will be cleared to 0 whenever the.."
newline
bitfld.long 0x8 0. "RITINT,Interrupt flag" "0: The counter value does not equal the masked..,1: This bit is set to 1 by hardware whenever the.."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x8 3. "RITEN,Timer enable." "0,1"
newline
bitfld.long 0x8 2. "RITENBR,Timer enable for debug." "0,1"
bitfld.long 0x8 1. "RITENCLR,Timer enable clear." "0,1"
newline
bitfld.long 0x8 0. "RITINT,Interrupt flag." "0,1"
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x8 3. "RITEN,Timer enable." "0,1"
newline
bitfld.long 0x8 2. "RITENBR,Timer enable for debug." "0,1"
bitfld.long 0x8 1. "RITENCLR,Timer enable clear." "0,1"
newline
bitfld.long 0x8 0. "RITINT,Interrupt flag." "0,1"
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x8 3. "RITEN,Timer enable." "0,1"
newline
bitfld.long 0x8 2. "RITENBR,Timer enable for debug." "0,1"
bitfld.long 0x8 1. "RITENCLR,Timer enable clear." "0,1"
newline
bitfld.long 0x8 0. "RITINT,Interrupt flag." "0,1"
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x8 3. "RITEN,Timer enable." "0,1"
newline
bitfld.long 0x8 2. "RITENBR,Timer enable for debug." "0,1"
bitfld.long 0x8 1. "RITENCLR,Timer enable clear." "0,1"
newline
bitfld.long 0x8 0. "RITINT,Interrupt flag." "0,1"
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x8 3. "RITEN,Timer enable." "0,1"
newline
bitfld.long 0x8 2. "RITENBR,Timer enable for debug." "0,1"
bitfld.long 0x8 1. "RITENCLR,Timer enable clear." "0,1"
newline
bitfld.long 0x8 0. "RITINT,Interrupt flag." "0,1"
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x8 3. "RITEN,Timer enable." "0,1"
newline
bitfld.long 0x8 2. "RITENBR,Timer enable for debug." "0,1"
bitfld.long 0x8 1. "RITENCLR,Timer enable clear." "0,1"
newline
bitfld.long 0x8 0. "RITINT,Interrupt flag." "0,1"
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x8 3. "RITEN,Timer enable." "0,1"
newline
bitfld.long 0x8 2. "RITENBR,Timer enable for debug." "0,1"
bitfld.long 0x8 1. "RITENCLR,Timer enable clear." "0,1"
newline
bitfld.long 0x8 0. "RITINT,Interrupt flag." "0,1"
endif
line.long 0xC "COUNTER,Counter LSB register"
hexmask.long 0xC 0.--31. 1. "RICOUNTER,32 LSBs of the up counter."
line.long 0x10 "COMPVAL_H,Compare value MSB register"
hexmask.long.word 0x10 0.--15. 1. "RICOMP,Compare value MSB register."
line.long 0x14 "MASK_H,Mask MSB register"
hexmask.long.word 0x14 0.--15. 1. "RIMASK,Mask register."
group.long 0x1C++0x3
line.long 0x0 "COUNTER_H,Counter MSB register"
hexmask.long.word 0x0 0.--15. 1. "RICOUNTER,16 LSBs of the up counter."
tree.end
endif
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54113*")||cpuis("LPC54114*")||cpuis("LPC54605*")||cpuis("LPC54606*")||cpuis("LPC54607*")||cpuis("LPC54608*")||cpuis("LPC54616*")||cpuis("LPC54618*")||cpuis("LPC54628*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
base ad:0x4002C000
elif (cpuis("LPC54101*")||cpuis("LPC54102*"))
base ad:0x4003C000
endif
tree "RTC (Real-Time Clock)"
group.long 0x0++0xF
line.long 0x0 "CTRL,RTC control register"
sif (cpuis("LPC54113*"))
bitfld.long 0x0 9. "RTC_OSC_BYPASS,RTC oscillator bypass control." "0: RTC oscillator is in normal crystal oscillation..,1: RTC oscillator is bypassed. RTCXIN may be driven.."
bitfld.long 0x0 8. "RTC_OSC_PD,RTC oscillator power-down control." "0: See RTC_OSC_BYPASS,1: RTC oscillator is powered-down."
newline
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x0 9. "RTC_OSC_BYPASS,RTC oscillator bypass control." "0: RTC oscillator is in normal crystal oscillation..,1: RTC oscillator is bypassed. RTCXIN may be driven.."
bitfld.long 0x0 8. "RTC_OSC_PD,RTC oscillator power-down control." "0: See RTC_OSC_BYPASS,1: RTC oscillator is powered-down."
newline
endif
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x0 8. "RTC_OSC_PD,RTC oscillator power-down control." "0: See RTC_OSC_BYPASS,1: RTC oscillator is powered-down."
bitfld.long 0x0 3. "WAKE1KHZ,RTC 1 kHz timer wake-up flag status." "0: Run. The RTC 1 kHz timer is running. Writing a 0..,1: Time-out. The 1 kHz high-resolution/wake-up.."
newline
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x0 8. "RTC_OSC_PD,RTC oscillator power-down control." "0: See RTC_OSC_BYPASS,1: RTC oscillator is powered-down."
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x0 8. "RTC_OSC_PD,RTC oscillator power-down control." "0: See RTC_OSC_BYPASS,1: RTC oscillator is powered-down."
newline
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x0 8. "RTC_OSC_PD,RTC oscillator power-down control." "0: See RTC_OSC_BYPASS,1: RTC oscillator is powered-down."
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x0 8. "RTC_OSC_PD,RTC oscillator power-down control." "0: See RTC_OSC_BYPASS,1: RTC oscillator is powered-down."
newline
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x0 8. "RTC_OSC_PD,RTC oscillator power-down control." "0: See RTC_OSC_BYPASS,1: RTC oscillator is powered-down."
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x0 8. "RTC_OSC_PD,RTC oscillator power-down control." "0: See RTC_OSC_BYPASS,1: RTC oscillator is powered-down."
newline
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x0 8. "RTC_OSC_PD,RTC oscillator power-down control." "0: See RTC_OSC_BYPASS,1: RTC oscillator is powered-down."
endif
bitfld.long 0x0 7. "RTC_EN,RTC enable." "0: Disable. The RTC 1 Hz and 1 kHz clocks are shut..,1: Enable. The 1 Hz RTC clock is running and RTC.."
newline
bitfld.long 0x0 6. "RTC1KHZ_EN,RTC 1 kHz clock enable. This bit can be set to 0 to conserve power if the 1 kHz timer is not used. This bit has no effect when the RTC is disabled (bit 7 of this register is 0)." "0: Disable. A match on the 1 kHz RTC timer will not..,1: Enable. The 1 kHz RTC timer is enabled."
bitfld.long 0x0 5. "WAKEDPD_EN,RTC 1 kHz timer wake-up enable for Deep power-down." "0: Disable. A match on the 1 kHz RTC timer will not..,1: Enable. A match on the 1 kHz RTC timer bring the.."
newline
bitfld.long 0x0 4. "ALARMDPD_EN,RTC 1 Hz timer alarm enable for Deep power-down." "0: Disable. A match on the 1 Hz RTC timer will not..,1: Enable. A match on the 1 Hz RTC timer bring the.."
sif (cpuis("LPC54101*"))
bitfld.long 0x0 3. "WAKE1KHZ,RTC 1 kHz timer wake-up flag status." "0: Run. The RTC 1 kHz timer is running. Writing a 0..,1: Time-out. The 1 kHz high-resolution/wake-up.."
newline
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x0 3. "WAKE1KHZ,RTC 1 kHz timer wake-up flag status." "0: Run. The RTC 1 kHz timer is running. Writing a 0..,1: Time-out. The 1 kHz high-resolution/wake-up.."
endif
sif (cpuis("LPC54113*"))
bitfld.long 0x0 3. "WAKE1KHZ,RTC 1 kHz timer wake-up flag status." "0: Run. The RTC 1 kHz timer is running. Writing a 0..,1: Time-out. The 1 kHz high-resolution/wake-up.."
newline
endif
sif (cpuis("LPC54114*"))
bitfld.long 0x0 3. "WAKE1KHZ,RTC 1 kHz timer wake-up flag status." "0: Run. The RTC 1 kHz timer is running. Writing a 0..,1: Time-out. The 1 kHz high-resolution/wake-up.."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x0 3. "WAKE1KHZ,RTC 1 kHz timer wake-up flag status." "0: Run. The RTC 1 kHz timer is running. Writing a 0..,1: Time-out. The 1 kHz high-resolution/wake-up.."
newline
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x0 3. "WAKE1KHZ,RTC 1 kHz timer wake-up flag status." "0: Run. The RTC 1 kHz timer is running. Writing a 0..,1: Time-out. The 1 kHz high-resolution/wake-up.."
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x0 3. "WAKE1KHZ,RTC 1 kHz timer wake-up flag status." "0: Run. The RTC 1 kHz timer is running. Writing a 0..,1: Time-out. The 1 kHz high-resolution/wake-up.."
newline
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x0 3. "WAKE1KHZ,RTC 1 kHz timer wake-up flag status." "0: Run. The RTC 1 kHz timer is running. Writing a 0..,1: Time-out. The 1 kHz high-resolution/wake-up.."
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x0 3. "WAKE1KHZ,RTC 1 kHz timer wake-up flag status." "0: Run. The RTC 1 kHz timer is running. Writing a 0..,1: Time-out. The 1 kHz high-resolution/wake-up.."
newline
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x0 3. "WAKE1KHZ,RTC 1 kHz timer wake-up flag status." "0: Run. The RTC 1 kHz timer is running. Writing a 0..,1: Time-out. The 1 kHz high-resolution/wake-up.."
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x0 3. "WAKE1KHZ,RTC 1 kHz timer wake-up flag status." "0: Run. The RTC 1 kHz timer is running. Writing a 0..,1: Time-out. The 1 kHz high-resolution/wake-up.."
newline
endif
newline
bitfld.long 0x0 2. "ALARM1HZ,RTC 1 Hz timer alarm flag status." "0: No match. No match has occurred on the 1 Hz RTC..,1: Match. A match condition has occurred on the 1.."
newline
sif (cpuis("LPC54101*"))
bitfld.long 0x0 1. "OFD,Oscillator fail detect status." "0: Run. The RTC oscillator is running properly.,1: Fail. RTC oscillator fail detected. Clear this.."
newline
endif
sif (cpuis("LPC54102*"))
bitfld.long 0x0 1. "OFD,Oscillator fail detect status." "0: Run. The RTC oscillator is running properly.,1: Fail. RTC oscillator fail detected. Clear this.."
newline
endif
newline
bitfld.long 0x0 0. "SWRESET,Software reset control" "0: Not in reset. The RTC is not held in reset. This..,1: In reset. The RTC is held in reset. All register.."
line.long 0x4 "MATCH,RTC match register"
hexmask.long 0x4 0.--31. 1. "MATVAL,Contains the match value against which the 1 Hz RTC timer will be compared to set the alarm flag RTC_ALARM and generate an alarm interrupt/wake-up if enabled."
line.long 0x8 "COUNT,RTC counter register"
hexmask.long 0x8 0.--31. 1. "VAL,A read reflects the current value of the main  1 Hz RTC timer. A write loads a new initial value into the timer. The RTC counter will count up continuously at a 1 Hz rate once the RTC Software Reset is removed (by clearing bit 0 of the CTRL.."
line.long 0xC "WAKE,High-resolution/wake-up timer control register"
hexmask.long.word 0xC 0.--15. 1. "VAL,A read reflects the current value of the high-resolution/wake-up timer. A write pre-loads a start count value into the wake-up timer and initializes a count-down sequence. Do not write to this register while counting is in progress."
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x40)++0x3
line.long 0x0 "GPREG[$1],General Purpose register"
hexmask.long 0x0 0.--31. 1. "GPDATA,Data retained during Deep power-down mode or loss of main power as long as VBAT is supplied."
repeat.end
endif
sif (cpuis("LPC54605*"))
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x40)++0x3
line.long 0x0 "GPREG[$1],General Purpose register"
hexmask.long 0x0 0.--31. 1. "GPDATA,Data retained during Deep power-down mode or loss of main power as long as VBAT is supplied."
repeat.end
endif
sif (cpuis("LPC54606*"))
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x40)++0x3
line.long 0x0 "GPREG[$1],General Purpose register"
hexmask.long 0x0 0.--31. 1. "GPDATA,Data retained during Deep power-down mode or loss of main power as long as VBAT is supplied."
repeat.end
endif
sif (cpuis("LPC54607*"))
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x40)++0x3
line.long 0x0 "GPREG[$1],General Purpose register"
hexmask.long 0x0 0.--31. 1. "GPDATA,Data retained during Deep power-down mode or loss of main power as long as VBAT is supplied."
repeat.end
endif
sif (cpuis("LPC54608*"))
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x40)++0x3
line.long 0x0 "GPREG[$1],General Purpose register"
hexmask.long 0x0 0.--31. 1. "GPDATA,Data retained during Deep power-down mode or loss of main power as long as VBAT is supplied."
repeat.end
endif
sif (cpuis("LPC54616*"))
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x40)++0x3
line.long 0x0 "GPREG[$1],General Purpose register"
hexmask.long 0x0 0.--31. 1. "GPDATA,Data retained during Deep power-down mode or loss of main power as long as VBAT is supplied."
repeat.end
endif
sif (cpuis("LPC54618*"))
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x40)++0x3
line.long 0x0 "GPREG[$1],General Purpose register"
hexmask.long 0x0 0.--31. 1. "GPDATA,Data retained during Deep power-down mode or loss of main power as long as VBAT is supplied."
repeat.end
endif
sif (cpuis("LPC54628*"))
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x40)++0x3
line.long 0x0 "GPREG[$1],General Purpose register"
hexmask.long 0x0 0.--31. 1. "GPDATA,Data retained during Deep power-down mode or loss of main power as long as VBAT is supplied."
repeat.end
endif
tree.end
tree "SCB (System Control Block)"
base ad:0xE000E000
group.long 0x8++0x3
line.long 0x0 "ACTLR,Auxiliary Control Register."
bitfld.long 0x0 2. "DISFOLD,Disables folding of IT instructions." "0,1"
bitfld.long 0x0 1. "DISDEFWBUF,Disables write buffer use during default memory map accesses." "0,1"
newline
bitfld.long 0x0 0. "DISMCYCINT,Disables interruption of multi-cycle instructions." "0,1"
rgroup.long 0xD00++0x3
line.long 0x0 "CPUID,CPUID Base Register"
hexmask.long.byte 0x0 24.--31. 1. "IMPLEMENTER,Implementer code"
hexmask.long.byte 0x0 20.--23. 1. "VARIANT,Indicates processor revision: 0x2 = Revision 2"
newline
hexmask.long.word 0x0 4.--15. 1. "PARTNO,Indicates part number"
hexmask.long.byte 0x0 0.--3. 1. "REVISION,Indicates patch release: 0x0 = Patch 0"
group.long 0xD04++0x3B
line.long 0x0 "ICSR,Interrupt Control and State Register"
bitfld.long 0x0 31. "NMIPENDSET,no description available" "0: write: no effect; read: NMI exception is not..,1: write: changes NMI exception state to pending;.."
bitfld.long 0x0 28. "PENDSVSET,no description available" "0: write: no effect; read: PendSV exception is not..,1: write: changes PendSV exception state to.."
newline
bitfld.long 0x0 27. "PENDSVCLR,no description available" "0: no effect,1: removes the pending state from the PendSV.."
bitfld.long 0x0 26. "PENDSTSET,no description available" "0: write: no effect; read: SysTick exception is not..,1: write: changes SysTick exception state to.."
newline
bitfld.long 0x0 25. "PENDSTCLR,no description available" "0: no effect,1: removes the pending state from the SysTick.."
rbitfld.long 0x0 23. "ISRPREEMPT,no description available" "0: Will not service,1: Will service a pending exception"
newline
rbitfld.long 0x0 22. "ISRPENDING,no description available" "0,1"
hexmask.long.byte 0x0 12.--17. 1. "VECTPENDING,Exception number of the highest priority pending enabled exception"
newline
rbitfld.long 0x0 11. "RETTOBASE,no description available" "0: there are preempted active exceptions to execute,1: there are no active exceptions or the.."
hexmask.long.word 0x0 0.--8. 1. "VECTACTIVE,Active exception number"
line.long 0x4 "VTOR,Vector Table Offset Register"
hexmask.long 0x4 7.--31. 1. "TBLOFF,Vector table base offset"
line.long 0x8 "AIRCR,Application Interrupt and Reset Control Register"
hexmask.long.word 0x8 16.--31. 1. "VECTKEY,Register key"
rbitfld.long 0x8 15. "ENDIANNESS,no description available" "0: Little-endian,1: Big-endian"
newline
bitfld.long 0x8 8.--10. "PRIGROUP,Interrupt priority grouping field. This field determines the split of group priority from subpriority." "0,1,2,3,4,5,6,7"
bitfld.long 0x8 2. "SYSRESETREQ,no description available" "0: no system reset request,1: asserts a signal to the outer system that.."
newline
bitfld.long 0x8 1. "VECTCLRACTIVE,no description available" "0,1"
bitfld.long 0x8 0. "VECTRESET,no description available" "0,1"
line.long 0xC "SCR,System Control Register"
bitfld.long 0xC 4. "SEVONPEND,no description available" "0: only enabled interrupts or events can wakeup the..,1: enabled events and all interrupts including.."
bitfld.long 0xC 2. "SLEEPDEEP,no description available" "0: sleep,1: deep sleep"
newline
bitfld.long 0xC 1. "SLEEPONEXIT,no description available" "0: o not sleep when returning to Thread mode,1: enter sleep or deep sleep on return from an ISR"
line.long 0x10 "CCR,Configuration and Control Register"
bitfld.long 0x10 9. "STKALIGN,Indicates stack alignment on exception entry" "0: 4-byte aligned,1: 8-byte aligned"
bitfld.long 0x10 8. "BFHFNMIGN,Enables handlers with priority -1 or -2 to ignore data BusFaults caused by load and store instructions." "0: data bus faults caused by load and store..,1: handlers running at priority -1 and -2 ignore.."
newline
bitfld.long 0x10 4. "DIV_0_TRP,Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0" "0: do not trap divide by 0,1: trap divide by 0"
bitfld.long 0x10 3. "UNALIGN_TRP,Enables unaligned access traps" "0: do not trap unaligned halfword and word accesses,1: trap unaligned halfword and word accesses"
newline
bitfld.long 0x10 1. "USERSETMPEND,Enables unprivileged software access to the STIR" "0: disable,1: enable"
bitfld.long 0x10 0. "NONBASETHRDENA,no description available" "0: processor can enter Thread mode only when no..,1: processor can enter Thread mode from any level.."
line.long 0x14 "SHPR1,System Handler Priority Register 1"
hexmask.long.byte 0x14 16.--23. 1. "PRI_6,Priority of system handler 6  UsageFault"
hexmask.long.byte 0x14 8.--15. 1. "PRI_5,Priority of system handler 5  BusFault"
newline
hexmask.long.byte 0x14 0.--7. 1. "PRI_4,Priority of system handler 4  MemManage"
line.long 0x18 "SHPR2,System Handler Priority Register 2"
hexmask.long.byte 0x18 24.--31. 1. "PRI_11,Priority of system handler 11  SVCall"
line.long 0x1C "SHPR3,System Handler Priority Register 3"
hexmask.long.byte 0x1C 24.--31. 1. "PRI_15,Priority of system handler 15  SysTick exception"
hexmask.long.byte 0x1C 16.--23. 1. "PRI_14,Priority of system handler 14  PendSV"
line.long 0x20 "SHCSR,System Handler Control and State Register"
bitfld.long 0x20 18. "USGFAULTENA,no description available" "0: disable the exception,1: enable the exception"
bitfld.long 0x20 17. "BUSFAULTENA,no description available" "0: disable the exception,1: enable the exception"
newline
bitfld.long 0x20 16. "MEMFAULTENA,no description available" "0: disable the exception,1: enable the exception"
bitfld.long 0x20 15. "SVCALLPENDED,no description available" "0: exception is not pending,1: exception is pending"
newline
bitfld.long 0x20 14. "BUSFAULTPENDED,no description available" "0: exception is not pending,1: exception is pending"
bitfld.long 0x20 13. "MEMFAULTPENDED,no description available" "0: exception is not pending,1: exception is pending"
newline
bitfld.long 0x20 12. "USGFAULTPENDED,no description available" "0: exception is not pending,1: exception is pending"
bitfld.long 0x20 11. "SYSTICKACT,no description available" "0: exception is not active,1: exception is active"
newline
bitfld.long 0x20 10. "PENDSVACT,no description available" "0: exception is not active,1: exception is active"
bitfld.long 0x20 8. "MONITORACT,no description available" "0: exception is not active,1: exception is active"
newline
bitfld.long 0x20 7. "SVCALLACT,no description available" "0: exception is not active,1: exception is active"
bitfld.long 0x20 3. "USGFAULTACT,no description available" "0: exception is not active,1: exception is active"
newline
bitfld.long 0x20 1. "BUSFAULTACT,no description available" "0: exception is not active,1: exception is active"
bitfld.long 0x20 0. "MEMFAULTACT,no description available" "0: exception is not active,1: exception is active"
line.long 0x24 "CFSR,Configurable Fault Status Registers"
bitfld.long 0x24 25. "DIVBYZERO,no description available" "0: no divide by zero fault or divide by zero..,1: the processor has executed an SDIV or UDIV.."
bitfld.long 0x24 24. "UNALIGNED,no description available" "0: no unaligned access fault or unaligned access..,1: the processor has made an unaligned memory access"
newline
bitfld.long 0x24 19. "NOCP,no description available" "0: no UsageFault caused by attempting to access a..,1: the processor has attempted to access a.."
bitfld.long 0x24 18. "INVPC,no description available" "0: no invalid PC load UsageFault,1: the processor has attempted an illegal load of.."
newline
bitfld.long 0x24 17. "INVSTATE,no description available" "0: no invalid state UsageFault,1: the processor has attempted to execute an.."
bitfld.long 0x24 16. "UNDEFINSTR,no description available" "0: no undefined instruction UsageFault,1: the processor has attempted to execute an.."
newline
bitfld.long 0x24 15. "BFARVALID,no description available" "0: value in BFAR is not a valid fault address,1: BFAR holds a valid fault address"
bitfld.long 0x24 13. "LSPERR,no description available" "0: No bus fault occurred during floating-point lazy..,1: A bus fault occurred during floating-point lazy.."
newline
bitfld.long 0x24 12. "STKERR,no description available" "0: no stacking fault,1: stacking for an exception entry has caused one.."
bitfld.long 0x24 11. "UNSTKERR,no description available" "0: no unstacking fault,1: unstack for an exception return has caused one.."
newline
bitfld.long 0x24 10. "IMPRECISERR,no description available" "0: no imprecise data bus error,1: a data bus error has occurred but the return.."
bitfld.long 0x24 9. "PRECISERR,no description available" "0: no precise data bus error,1: a data bus error has occurred and the PC value.."
newline
bitfld.long 0x24 8. "IBUSERR,no description available" "0: no instruction bus error,1: instruction bus error"
bitfld.long 0x24 7. "MMARVALID,no description available" "0: value in MMAR is not a valid fault address,1: MMAR holds a valid fault address"
newline
bitfld.long 0x24 5. "MLSPERR,no description available" "0: No MemManage fault occurred during..,1: A MemManage fault occurred during floating-point.."
bitfld.long 0x24 4. "MSTKERR,no description available" "0: no stacking fault,1: stacking for an exception entry has caused one.."
newline
bitfld.long 0x24 3. "MUNSTKERR,no description available" "0: no unstacking fault,1: unstack for an exception return has caused one.."
bitfld.long 0x24 1. "DACCVIOL,no description available" "0: no data access violation fault,1: the processor attempted a load or store at a.."
newline
bitfld.long 0x24 0. "IACCVIOL,no description available" "0: no instruction access violation fault,1: the processor attempted an instruction fetch.."
line.long 0x28 "HFSR,HardFault Status register"
bitfld.long 0x28 31. "DEBUGEVT,no description available" "0,1"
bitfld.long 0x28 30. "FORCED,no description available" "0: no forced HardFault,1: forced HardFault"
newline
bitfld.long 0x28 1. "VECTTBL,no description available" "0: no BusFault on vector table read,1: BusFault on vector table read"
line.long 0x2C "DFSR,Debug Fault Status Register"
bitfld.long 0x2C 4. "EXTERNAL,no description available" "0: No EDBGRQ debug event,1: EDBGRQ debug event"
bitfld.long 0x2C 3. "VCATCH,no description available" "0: No Vector catch triggered,1: Vector catch triggered"
newline
bitfld.long 0x2C 2. "DWTTRAP,no description available" "0: No current debug events generated by the DWT,1: At least one current debug event generated by.."
bitfld.long 0x2C 1. "BKPT,no description available" "0: No current breakpoint debug event,1: At least one current breakpoint debug event"
newline
bitfld.long 0x2C 0. "HALTED,no description available" "0: No active halt request debug event,1: Halt request debug event active"
line.long 0x30 "MMFAR,MemManage Address Register"
hexmask.long 0x30 0.--31. 1. "ADDRESS,Address of MemManage fault location"
line.long 0x34 "BFAR,BusFault Address Register"
hexmask.long 0x34 0.--31. 1. "ADDRESS,Address of the BusFault location"
line.long 0x38 "AFSR,Auxiliary Fault Status Register"
hexmask.long 0x38 0.--31. 1. "AUXFAULT,Latched version of the AUXFAULT inputs"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
group.long 0xD88++0x3
line.long 0x0 "CPACR,Coprocessor Access Control Register"
bitfld.long 0x0 22.--23. "CP11,Access privileges for coprocessor 11." "0: Access denied. Any attempted access generates a..,1: Privileged access only. An unprivileged access..,?,3: Full access."
bitfld.long 0x0 20.--21. "CP10,Access privileges for coprocessor 10." "0: Access denied. Any attempted access generates a..,1: Privileged access only. An unprivileged access..,?,3: Full access."
group.long 0xF34++0xB
line.long 0x0 "FPCCR,Floating-point Context Control Register"
bitfld.long 0x0 31. "ASPEN,Enables CONTROL2 setting on execution of a floating-point instruction. This results in automatic hardware state preservation and restoration  for floating-point context  on exception entry and exit." "0: Disable CONTROL2 setting on execution of a..,1: Enable CONTROL2 setting on execution of a.."
bitfld.long 0x0 30. "LSPEN,Lazy state preservation for floating-point context." "0: Disable automatic lazy state preservation for..,1: Enable automatic lazy state preservation for.."
newline
bitfld.long 0x0 8. "MONRDY,Permission to set the MON_PEND when the floating-point stack frame was allocated." "0: DebugMonitor is disabled or priority did not..,1: DebugMonitor is enabled and priority permits.."
bitfld.long 0x0 6. "BFRDY,Permission to set the BusFault handler to the pending state when the floating-point stack frame was allocated." "0: BusFault is disabled or priority did not permit..,1: BusFault is disabled or priority did not permit.."
newline
bitfld.long 0x0 5. "MMRDY,Permission to set the MemManage handler to the pending state when the floating-point stack frame was allocated." "0: MemManage is disabled or priority did not permit..,1: MemManage is enabled and priority permitted.."
bitfld.long 0x0 4. "HFRDY,Permission to set the HardFault handler to the pending state when the floating-point stack frame was allocated." "0: Priority did not permit setting the HardFault..,1: Priority permitted setting the HardFault handler.."
newline
bitfld.long 0x0 3. "THREAD,Mode when the floating-point stack frame was allocated." "0: Mode was not Thread Mode when the floating-point..,1: Mode was Thread Mode when the floating-point.."
bitfld.long 0x0 1. "USER,Privilege level when the floating-point stack frame was allocated." "0: Privilege level was not user when the..,1: Privilege level was user when the floating-point.."
newline
bitfld.long 0x0 0. "LSPACT,Lazy state preservation." "0: Lazy state preservation is not active.,1: Lazy state preservation is active."
line.long 0x4 "FPCAR,Floating-point Context Address Register"
hexmask.long 0x4 3.--31. 1. "ADDRESS,The location of the unpopulated floating-point register space allocated on an exception stack frame."
line.long 0x8 "FPDSCR,Floating-point Default Status Control Register"
bitfld.long 0x8 26. "AHP,Default value for FPSCR.AHP (Alternative half-precision control bit)." "0: IEEE half-precision format selected.,1: Alternative half-precision format selected."
bitfld.long 0x8 25. "DN,Default value for FPSCR.DN (Default NaN mode control bit)." "0: NaN operands propagate through to the output of..,1: Any operation involving one or more NaNs returns.."
newline
bitfld.long 0x8 24. "FZ,Default value for FPSCR.FZ (Flush-to-zero mode control bit)." "0: Flush-to-zero mode disabled. Behavior of the..,1: Flush-to-zero mode enabled."
bitfld.long 0x8 22.--23. "RMode,Default value for FPSCR.RMode (Rounding Mode control field)." "0: Round to Nearest (RN) mode,1: Round towards Plus Infinity (RP) mode.,2: Round towards Minus Infinity (RM) mode.,3: Round towards Zero (RZ) mode."
endif
sif (cpuis("LPC54605*"))
group.long 0xD88++0x3
line.long 0x0 "CPACR,Coprocessor Access Control Register"
bitfld.long 0x0 22.--23. "CP11,Access privileges for coprocessor 11." "0: Access denied. Any attempted access generates a..,1: Privileged access only. An unprivileged access..,?,3: Full access."
bitfld.long 0x0 20.--21. "CP10,Access privileges for coprocessor 10." "0: Access denied. Any attempted access generates a..,1: Privileged access only. An unprivileged access..,?,3: Full access."
group.long 0xF34++0xB
line.long 0x0 "FPCCR,Floating-point Context Control Register"
bitfld.long 0x0 31. "ASPEN,Enables CONTROL2 setting on execution of a floating-point instruction. This results in automatic hardware state preservation and restoration  for floating-point context  on exception entry and exit." "0: Disable CONTROL2 setting on execution of a..,1: Enable CONTROL2 setting on execution of a.."
bitfld.long 0x0 30. "LSPEN,Lazy state preservation for floating-point context." "0: Disable automatic lazy state preservation for..,1: Enable automatic lazy state preservation for.."
newline
bitfld.long 0x0 8. "MONRDY,Permission to set the MON_PEND when the floating-point stack frame was allocated." "0: DebugMonitor is disabled or priority did not..,1: DebugMonitor is enabled and priority permits.."
bitfld.long 0x0 6. "BFRDY,Permission to set the BusFault handler to the pending state when the floating-point stack frame was allocated." "0: BusFault is disabled or priority did not permit..,1: BusFault is disabled or priority did not permit.."
newline
bitfld.long 0x0 5. "MMRDY,Permission to set the MemManage handler to the pending state when the floating-point stack frame was allocated." "0: MemManage is disabled or priority did not permit..,1: MemManage is enabled and priority permitted.."
bitfld.long 0x0 4. "HFRDY,Permission to set the HardFault handler to the pending state when the floating-point stack frame was allocated." "0: Priority did not permit setting the HardFault..,1: Priority permitted setting the HardFault handler.."
newline
bitfld.long 0x0 3. "THREAD,Mode when the floating-point stack frame was allocated." "0: Mode was not Thread Mode when the floating-point..,1: Mode was Thread Mode when the floating-point.."
bitfld.long 0x0 1. "USER,Privilege level when the floating-point stack frame was allocated." "0: Privilege level was not user when the..,1: Privilege level was user when the floating-point.."
newline
bitfld.long 0x0 0. "LSPACT,Lazy state preservation." "0: Lazy state preservation is not active.,1: Lazy state preservation is active."
line.long 0x4 "FPCAR,Floating-point Context Address Register"
hexmask.long 0x4 3.--31. 1. "ADDRESS,The location of the unpopulated floating-point register space allocated on an exception stack frame."
line.long 0x8 "FPDSCR,Floating-point Default Status Control Register"
bitfld.long 0x8 26. "AHP,Default value for FPSCR.AHP (Alternative half-precision control bit)." "0: IEEE half-precision format selected.,1: Alternative half-precision format selected."
bitfld.long 0x8 25. "DN,Default value for FPSCR.DN (Default NaN mode control bit)." "0: NaN operands propagate through to the output of..,1: Any operation involving one or more NaNs returns.."
newline
bitfld.long 0x8 24. "FZ,Default value for FPSCR.FZ (Flush-to-zero mode control bit)." "0: Flush-to-zero mode disabled. Behavior of the..,1: Flush-to-zero mode enabled."
bitfld.long 0x8 22.--23. "RMode,Default value for FPSCR.RMode (Rounding Mode control field)." "0: Round to Nearest (RN) mode,1: Round towards Plus Infinity (RP) mode.,2: Round towards Minus Infinity (RM) mode.,3: Round towards Zero (RZ) mode."
endif
sif (cpuis("LPC54606*"))
group.long 0xD88++0x3
line.long 0x0 "CPACR,Coprocessor Access Control Register"
bitfld.long 0x0 22.--23. "CP11,Access privileges for coprocessor 11." "0: Access denied. Any attempted access generates a..,1: Privileged access only. An unprivileged access..,?,3: Full access."
bitfld.long 0x0 20.--21. "CP10,Access privileges for coprocessor 10." "0: Access denied. Any attempted access generates a..,1: Privileged access only. An unprivileged access..,?,3: Full access."
group.long 0xF34++0xB
line.long 0x0 "FPCCR,Floating-point Context Control Register"
bitfld.long 0x0 31. "ASPEN,Enables CONTROL2 setting on execution of a floating-point instruction. This results in automatic hardware state preservation and restoration  for floating-point context  on exception entry and exit." "0: Disable CONTROL2 setting on execution of a..,1: Enable CONTROL2 setting on execution of a.."
bitfld.long 0x0 30. "LSPEN,Lazy state preservation for floating-point context." "0: Disable automatic lazy state preservation for..,1: Enable automatic lazy state preservation for.."
newline
bitfld.long 0x0 8. "MONRDY,Permission to set the MON_PEND when the floating-point stack frame was allocated." "0: DebugMonitor is disabled or priority did not..,1: DebugMonitor is enabled and priority permits.."
bitfld.long 0x0 6. "BFRDY,Permission to set the BusFault handler to the pending state when the floating-point stack frame was allocated." "0: BusFault is disabled or priority did not permit..,1: BusFault is disabled or priority did not permit.."
newline
bitfld.long 0x0 5. "MMRDY,Permission to set the MemManage handler to the pending state when the floating-point stack frame was allocated." "0: MemManage is disabled or priority did not permit..,1: MemManage is enabled and priority permitted.."
bitfld.long 0x0 4. "HFRDY,Permission to set the HardFault handler to the pending state when the floating-point stack frame was allocated." "0: Priority did not permit setting the HardFault..,1: Priority permitted setting the HardFault handler.."
newline
bitfld.long 0x0 3. "THREAD,Mode when the floating-point stack frame was allocated." "0: Mode was not Thread Mode when the floating-point..,1: Mode was Thread Mode when the floating-point.."
bitfld.long 0x0 1. "USER,Privilege level when the floating-point stack frame was allocated." "0: Privilege level was not user when the..,1: Privilege level was user when the floating-point.."
newline
bitfld.long 0x0 0. "LSPACT,Lazy state preservation." "0: Lazy state preservation is not active.,1: Lazy state preservation is active."
line.long 0x4 "FPCAR,Floating-point Context Address Register"
hexmask.long 0x4 3.--31. 1. "ADDRESS,The location of the unpopulated floating-point register space allocated on an exception stack frame."
line.long 0x8 "FPDSCR,Floating-point Default Status Control Register"
bitfld.long 0x8 26. "AHP,Default value for FPSCR.AHP (Alternative half-precision control bit)." "0: IEEE half-precision format selected.,1: Alternative half-precision format selected."
bitfld.long 0x8 25. "DN,Default value for FPSCR.DN (Default NaN mode control bit)." "0: NaN operands propagate through to the output of..,1: Any operation involving one or more NaNs returns.."
newline
bitfld.long 0x8 24. "FZ,Default value for FPSCR.FZ (Flush-to-zero mode control bit)." "0: Flush-to-zero mode disabled. Behavior of the..,1: Flush-to-zero mode enabled."
bitfld.long 0x8 22.--23. "RMode,Default value for FPSCR.RMode (Rounding Mode control field)." "0: Round to Nearest (RN) mode,1: Round towards Plus Infinity (RP) mode.,2: Round towards Minus Infinity (RM) mode.,3: Round towards Zero (RZ) mode."
endif
sif (cpuis("LPC54607*"))
group.long 0xD88++0x3
line.long 0x0 "CPACR,Coprocessor Access Control Register"
bitfld.long 0x0 22.--23. "CP11,Access privileges for coprocessor 11." "0: Access denied. Any attempted access generates a..,1: Privileged access only. An unprivileged access..,?,3: Full access."
bitfld.long 0x0 20.--21. "CP10,Access privileges for coprocessor 10." "0: Access denied. Any attempted access generates a..,1: Privileged access only. An unprivileged access..,?,3: Full access."
group.long 0xF34++0xB
line.long 0x0 "FPCCR,Floating-point Context Control Register"
bitfld.long 0x0 31. "ASPEN,Enables CONTROL2 setting on execution of a floating-point instruction. This results in automatic hardware state preservation and restoration  for floating-point context  on exception entry and exit." "0: Disable CONTROL2 setting on execution of a..,1: Enable CONTROL2 setting on execution of a.."
bitfld.long 0x0 30. "LSPEN,Lazy state preservation for floating-point context." "0: Disable automatic lazy state preservation for..,1: Enable automatic lazy state preservation for.."
newline
bitfld.long 0x0 8. "MONRDY,Permission to set the MON_PEND when the floating-point stack frame was allocated." "0: DebugMonitor is disabled or priority did not..,1: DebugMonitor is enabled and priority permits.."
bitfld.long 0x0 6. "BFRDY,Permission to set the BusFault handler to the pending state when the floating-point stack frame was allocated." "0: BusFault is disabled or priority did not permit..,1: BusFault is disabled or priority did not permit.."
newline
bitfld.long 0x0 5. "MMRDY,Permission to set the MemManage handler to the pending state when the floating-point stack frame was allocated." "0: MemManage is disabled or priority did not permit..,1: MemManage is enabled and priority permitted.."
bitfld.long 0x0 4. "HFRDY,Permission to set the HardFault handler to the pending state when the floating-point stack frame was allocated." "0: Priority did not permit setting the HardFault..,1: Priority permitted setting the HardFault handler.."
newline
bitfld.long 0x0 3. "THREAD,Mode when the floating-point stack frame was allocated." "0: Mode was not Thread Mode when the floating-point..,1: Mode was Thread Mode when the floating-point.."
bitfld.long 0x0 1. "USER,Privilege level when the floating-point stack frame was allocated." "0: Privilege level was not user when the..,1: Privilege level was user when the floating-point.."
newline
bitfld.long 0x0 0. "LSPACT,Lazy state preservation." "0: Lazy state preservation is not active.,1: Lazy state preservation is active."
line.long 0x4 "FPCAR,Floating-point Context Address Register"
hexmask.long 0x4 3.--31. 1. "ADDRESS,The location of the unpopulated floating-point register space allocated on an exception stack frame."
line.long 0x8 "FPDSCR,Floating-point Default Status Control Register"
bitfld.long 0x8 26. "AHP,Default value for FPSCR.AHP (Alternative half-precision control bit)." "0: IEEE half-precision format selected.,1: Alternative half-precision format selected."
bitfld.long 0x8 25. "DN,Default value for FPSCR.DN (Default NaN mode control bit)." "0: NaN operands propagate through to the output of..,1: Any operation involving one or more NaNs returns.."
newline
bitfld.long 0x8 24. "FZ,Default value for FPSCR.FZ (Flush-to-zero mode control bit)." "0: Flush-to-zero mode disabled. Behavior of the..,1: Flush-to-zero mode enabled."
bitfld.long 0x8 22.--23. "RMode,Default value for FPSCR.RMode (Rounding Mode control field)." "0: Round to Nearest (RN) mode,1: Round towards Plus Infinity (RP) mode.,2: Round towards Minus Infinity (RM) mode.,3: Round towards Zero (RZ) mode."
endif
sif (cpuis("LPC54608*"))
group.long 0xD88++0x3
line.long 0x0 "CPACR,Coprocessor Access Control Register"
bitfld.long 0x0 22.--23. "CP11,Access privileges for coprocessor 11." "0: Access denied. Any attempted access generates a..,1: Privileged access only. An unprivileged access..,?,3: Full access."
bitfld.long 0x0 20.--21. "CP10,Access privileges for coprocessor 10." "0: Access denied. Any attempted access generates a..,1: Privileged access only. An unprivileged access..,?,3: Full access."
group.long 0xF34++0xB
line.long 0x0 "FPCCR,Floating-point Context Control Register"
bitfld.long 0x0 31. "ASPEN,Enables CONTROL2 setting on execution of a floating-point instruction. This results in automatic hardware state preservation and restoration  for floating-point context  on exception entry and exit." "0: Disable CONTROL2 setting on execution of a..,1: Enable CONTROL2 setting on execution of a.."
bitfld.long 0x0 30. "LSPEN,Lazy state preservation for floating-point context." "0: Disable automatic lazy state preservation for..,1: Enable automatic lazy state preservation for.."
newline
bitfld.long 0x0 8. "MONRDY,Permission to set the MON_PEND when the floating-point stack frame was allocated." "0: DebugMonitor is disabled or priority did not..,1: DebugMonitor is enabled and priority permits.."
bitfld.long 0x0 6. "BFRDY,Permission to set the BusFault handler to the pending state when the floating-point stack frame was allocated." "0: BusFault is disabled or priority did not permit..,1: BusFault is disabled or priority did not permit.."
newline
bitfld.long 0x0 5. "MMRDY,Permission to set the MemManage handler to the pending state when the floating-point stack frame was allocated." "0: MemManage is disabled or priority did not permit..,1: MemManage is enabled and priority permitted.."
bitfld.long 0x0 4. "HFRDY,Permission to set the HardFault handler to the pending state when the floating-point stack frame was allocated." "0: Priority did not permit setting the HardFault..,1: Priority permitted setting the HardFault handler.."
newline
bitfld.long 0x0 3. "THREAD,Mode when the floating-point stack frame was allocated." "0: Mode was not Thread Mode when the floating-point..,1: Mode was Thread Mode when the floating-point.."
bitfld.long 0x0 1. "USER,Privilege level when the floating-point stack frame was allocated." "0: Privilege level was not user when the..,1: Privilege level was user when the floating-point.."
newline
bitfld.long 0x0 0. "LSPACT,Lazy state preservation." "0: Lazy state preservation is not active.,1: Lazy state preservation is active."
line.long 0x4 "FPCAR,Floating-point Context Address Register"
hexmask.long 0x4 3.--31. 1. "ADDRESS,The location of the unpopulated floating-point register space allocated on an exception stack frame."
line.long 0x8 "FPDSCR,Floating-point Default Status Control Register"
bitfld.long 0x8 26. "AHP,Default value for FPSCR.AHP (Alternative half-precision control bit)." "0: IEEE half-precision format selected.,1: Alternative half-precision format selected."
bitfld.long 0x8 25. "DN,Default value for FPSCR.DN (Default NaN mode control bit)." "0: NaN operands propagate through to the output of..,1: Any operation involving one or more NaNs returns.."
newline
bitfld.long 0x8 24. "FZ,Default value for FPSCR.FZ (Flush-to-zero mode control bit)." "0: Flush-to-zero mode disabled. Behavior of the..,1: Flush-to-zero mode enabled."
bitfld.long 0x8 22.--23. "RMode,Default value for FPSCR.RMode (Rounding Mode control field)." "0: Round to Nearest (RN) mode,1: Round towards Plus Infinity (RP) mode.,2: Round towards Minus Infinity (RM) mode.,3: Round towards Zero (RZ) mode."
endif
sif (cpuis("LPC54616*"))
group.long 0xD88++0x3
line.long 0x0 "CPACR,Coprocessor Access Control Register"
bitfld.long 0x0 22.--23. "CP11,Access privileges for coprocessor 11." "0: Access denied. Any attempted access generates a..,1: Privileged access only. An unprivileged access..,?,3: Full access."
bitfld.long 0x0 20.--21. "CP10,Access privileges for coprocessor 10." "0: Access denied. Any attempted access generates a..,1: Privileged access only. An unprivileged access..,?,3: Full access."
group.long 0xF34++0xB
line.long 0x0 "FPCCR,Floating-point Context Control Register"
bitfld.long 0x0 31. "ASPEN,Enables CONTROL2 setting on execution of a floating-point instruction. This results in automatic hardware state preservation and restoration  for floating-point context  on exception entry and exit." "0: Disable CONTROL2 setting on execution of a..,1: Enable CONTROL2 setting on execution of a.."
bitfld.long 0x0 30. "LSPEN,Lazy state preservation for floating-point context." "0: Disable automatic lazy state preservation for..,1: Enable automatic lazy state preservation for.."
newline
bitfld.long 0x0 8. "MONRDY,Permission to set the MON_PEND when the floating-point stack frame was allocated." "0: DebugMonitor is disabled or priority did not..,1: DebugMonitor is enabled and priority permits.."
bitfld.long 0x0 6. "BFRDY,Permission to set the BusFault handler to the pending state when the floating-point stack frame was allocated." "0: BusFault is disabled or priority did not permit..,1: BusFault is disabled or priority did not permit.."
newline
bitfld.long 0x0 5. "MMRDY,Permission to set the MemManage handler to the pending state when the floating-point stack frame was allocated." "0: MemManage is disabled or priority did not permit..,1: MemManage is enabled and priority permitted.."
bitfld.long 0x0 4. "HFRDY,Permission to set the HardFault handler to the pending state when the floating-point stack frame was allocated." "0: Priority did not permit setting the HardFault..,1: Priority permitted setting the HardFault handler.."
newline
bitfld.long 0x0 3. "THREAD,Mode when the floating-point stack frame was allocated." "0: Mode was not Thread Mode when the floating-point..,1: Mode was Thread Mode when the floating-point.."
bitfld.long 0x0 1. "USER,Privilege level when the floating-point stack frame was allocated." "0: Privilege level was not user when the..,1: Privilege level was user when the floating-point.."
newline
bitfld.long 0x0 0. "LSPACT,Lazy state preservation." "0: Lazy state preservation is not active.,1: Lazy state preservation is active."
line.long 0x4 "FPCAR,Floating-point Context Address Register"
hexmask.long 0x4 3.--31. 1. "ADDRESS,The location of the unpopulated floating-point register space allocated on an exception stack frame."
line.long 0x8 "FPDSCR,Floating-point Default Status Control Register"
bitfld.long 0x8 26. "AHP,Default value for FPSCR.AHP (Alternative half-precision control bit)." "0: IEEE half-precision format selected.,1: Alternative half-precision format selected."
bitfld.long 0x8 25. "DN,Default value for FPSCR.DN (Default NaN mode control bit)." "0: NaN operands propagate through to the output of..,1: Any operation involving one or more NaNs returns.."
newline
bitfld.long 0x8 24. "FZ,Default value for FPSCR.FZ (Flush-to-zero mode control bit)." "0: Flush-to-zero mode disabled. Behavior of the..,1: Flush-to-zero mode enabled."
bitfld.long 0x8 22.--23. "RMode,Default value for FPSCR.RMode (Rounding Mode control field)." "0: Round to Nearest (RN) mode,1: Round towards Plus Infinity (RP) mode.,2: Round towards Minus Infinity (RM) mode.,3: Round towards Zero (RZ) mode."
endif
sif (cpuis("LPC54618*"))
group.long 0xD88++0x3
line.long 0x0 "CPACR,Coprocessor Access Control Register"
bitfld.long 0x0 22.--23. "CP11,Access privileges for coprocessor 11." "0: Access denied. Any attempted access generates a..,1: Privileged access only. An unprivileged access..,?,3: Full access."
bitfld.long 0x0 20.--21. "CP10,Access privileges for coprocessor 10." "0: Access denied. Any attempted access generates a..,1: Privileged access only. An unprivileged access..,?,3: Full access."
group.long 0xF34++0xB
line.long 0x0 "FPCCR,Floating-point Context Control Register"
bitfld.long 0x0 31. "ASPEN,Enables CONTROL2 setting on execution of a floating-point instruction. This results in automatic hardware state preservation and restoration  for floating-point context  on exception entry and exit." "0: Disable CONTROL2 setting on execution of a..,1: Enable CONTROL2 setting on execution of a.."
bitfld.long 0x0 30. "LSPEN,Lazy state preservation for floating-point context." "0: Disable automatic lazy state preservation for..,1: Enable automatic lazy state preservation for.."
newline
bitfld.long 0x0 8. "MONRDY,Permission to set the MON_PEND when the floating-point stack frame was allocated." "0: DebugMonitor is disabled or priority did not..,1: DebugMonitor is enabled and priority permits.."
bitfld.long 0x0 6. "BFRDY,Permission to set the BusFault handler to the pending state when the floating-point stack frame was allocated." "0: BusFault is disabled or priority did not permit..,1: BusFault is disabled or priority did not permit.."
newline
bitfld.long 0x0 5. "MMRDY,Permission to set the MemManage handler to the pending state when the floating-point stack frame was allocated." "0: MemManage is disabled or priority did not permit..,1: MemManage is enabled and priority permitted.."
bitfld.long 0x0 4. "HFRDY,Permission to set the HardFault handler to the pending state when the floating-point stack frame was allocated." "0: Priority did not permit setting the HardFault..,1: Priority permitted setting the HardFault handler.."
newline
bitfld.long 0x0 3. "THREAD,Mode when the floating-point stack frame was allocated." "0: Mode was not Thread Mode when the floating-point..,1: Mode was Thread Mode when the floating-point.."
bitfld.long 0x0 1. "USER,Privilege level when the floating-point stack frame was allocated." "0: Privilege level was not user when the..,1: Privilege level was user when the floating-point.."
newline
bitfld.long 0x0 0. "LSPACT,Lazy state preservation." "0: Lazy state preservation is not active.,1: Lazy state preservation is active."
line.long 0x4 "FPCAR,Floating-point Context Address Register"
hexmask.long 0x4 3.--31. 1. "ADDRESS,The location of the unpopulated floating-point register space allocated on an exception stack frame."
line.long 0x8 "FPDSCR,Floating-point Default Status Control Register"
bitfld.long 0x8 26. "AHP,Default value for FPSCR.AHP (Alternative half-precision control bit)." "0: IEEE half-precision format selected.,1: Alternative half-precision format selected."
bitfld.long 0x8 25. "DN,Default value for FPSCR.DN (Default NaN mode control bit)." "0: NaN operands propagate through to the output of..,1: Any operation involving one or more NaNs returns.."
newline
bitfld.long 0x8 24. "FZ,Default value for FPSCR.FZ (Flush-to-zero mode control bit)." "0: Flush-to-zero mode disabled. Behavior of the..,1: Flush-to-zero mode enabled."
bitfld.long 0x8 22.--23. "RMode,Default value for FPSCR.RMode (Rounding Mode control field)." "0: Round to Nearest (RN) mode,1: Round towards Plus Infinity (RP) mode.,2: Round towards Minus Infinity (RM) mode.,3: Round towards Zero (RZ) mode."
endif
sif (cpuis("LPC54628*"))
group.long 0xD88++0x3
line.long 0x0 "CPACR,Coprocessor Access Control Register"
bitfld.long 0x0 22.--23. "CP11,Access privileges for coprocessor 11." "0: Access denied. Any attempted access generates a..,1: Privileged access only. An unprivileged access..,?,3: Full access."
bitfld.long 0x0 20.--21. "CP10,Access privileges for coprocessor 10." "0: Access denied. Any attempted access generates a..,1: Privileged access only. An unprivileged access..,?,3: Full access."
group.long 0xF34++0xB
line.long 0x0 "FPCCR,Floating-point Context Control Register"
bitfld.long 0x0 31. "ASPEN,Enables CONTROL2 setting on execution of a floating-point instruction. This results in automatic hardware state preservation and restoration  for floating-point context  on exception entry and exit." "0: Disable CONTROL2 setting on execution of a..,1: Enable CONTROL2 setting on execution of a.."
bitfld.long 0x0 30. "LSPEN,Lazy state preservation for floating-point context." "0: Disable automatic lazy state preservation for..,1: Enable automatic lazy state preservation for.."
newline
bitfld.long 0x0 8. "MONRDY,Permission to set the MON_PEND when the floating-point stack frame was allocated." "0: DebugMonitor is disabled or priority did not..,1: DebugMonitor is enabled and priority permits.."
bitfld.long 0x0 6. "BFRDY,Permission to set the BusFault handler to the pending state when the floating-point stack frame was allocated." "0: BusFault is disabled or priority did not permit..,1: BusFault is disabled or priority did not permit.."
newline
bitfld.long 0x0 5. "MMRDY,Permission to set the MemManage handler to the pending state when the floating-point stack frame was allocated." "0: MemManage is disabled or priority did not permit..,1: MemManage is enabled and priority permitted.."
bitfld.long 0x0 4. "HFRDY,Permission to set the HardFault handler to the pending state when the floating-point stack frame was allocated." "0: Priority did not permit setting the HardFault..,1: Priority permitted setting the HardFault handler.."
newline
bitfld.long 0x0 3. "THREAD,Mode when the floating-point stack frame was allocated." "0: Mode was not Thread Mode when the floating-point..,1: Mode was Thread Mode when the floating-point.."
bitfld.long 0x0 1. "USER,Privilege level when the floating-point stack frame was allocated." "0: Privilege level was not user when the..,1: Privilege level was user when the floating-point.."
newline
bitfld.long 0x0 0. "LSPACT,Lazy state preservation." "0: Lazy state preservation is not active.,1: Lazy state preservation is active."
line.long 0x4 "FPCAR,Floating-point Context Address Register"
hexmask.long 0x4 3.--31. 1. "ADDRESS,The location of the unpopulated floating-point register space allocated on an exception stack frame."
line.long 0x8 "FPDSCR,Floating-point Default Status Control Register"
bitfld.long 0x8 26. "AHP,Default value for FPSCR.AHP (Alternative half-precision control bit)." "0: IEEE half-precision format selected.,1: Alternative half-precision format selected."
bitfld.long 0x8 25. "DN,Default value for FPSCR.DN (Default NaN mode control bit)." "0: NaN operands propagate through to the output of..,1: Any operation involving one or more NaNs returns.."
newline
bitfld.long 0x8 24. "FZ,Default value for FPSCR.FZ (Flush-to-zero mode control bit)." "0: Flush-to-zero mode disabled. Behavior of the..,1: Flush-to-zero mode enabled."
bitfld.long 0x8 22.--23. "RMode,Default value for FPSCR.RMode (Rounding Mode control field)." "0: Round to Nearest (RN) mode,1: Round towards Plus Infinity (RP) mode.,2: Round towards Minus Infinity (RM) mode.,3: Round towards Zero (RZ) mode."
endif
tree.end
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54113*")||cpuis("LPC54114*")||cpuis("LPC54605*")||cpuis("LPC54606*")||cpuis("LPC54607*")||cpuis("LPC54608*")||cpuis("LPC54616*")||cpuis("LPC54618*")||cpuis("LPC54628*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
base ad:0x40085000
elif (cpuis("LPC54101*")||cpuis("LPC54102*"))
base ad:0x1C018000
endif
tree "SCT (SCTimer/PWM)"
group.long 0x0++0x17
line.long 0x0 "CONFIG,SCT configuration register"
bitfld.long 0x0 18. "AUTOLIMIT_H,A one in this bit will cause a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event  this automatic limit causes the counter to be cleared to zero in.." "0,1"
bitfld.long 0x0 17. "AUTOLIMIT_L,A one in this bit causes a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event  this automatic limit causes the counter to be cleared to zero in.." "0,1"
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sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
hexmask.long.byte 0x0 9.--16. 1. "INSYNC,Synchronization for input N (bit 9 = input 0  bit 10 = input 1   bit 12 = input 3); all other bits are reserved. A 1 in one of these bits subjects the corresponding input to synchronization to the SCT clock  before it is used to create an event."
endif
sif (cpuis("LPC54101*"))
hexmask.long.byte 0x0 9.--12. 1. "INSYNC,Synchronization for input N (bit 9 = input 0  bit 10 = input 1   bit 12 = input 3); all other bits are reserved. A 1 in one of these bits subjects the corresponding input to synchronization to the SCT clock  before it is used to create an event."
newline
endif
sif (cpuis("LPC54102*"))
hexmask.long.byte 0x0 9.--12. 1. "INSYNC,Synchronization for input N (bit 9 = input 0  bit 10 = input 1   bit 12 = input 3); all other bits are reserved. A 1 in one of these bits subjects the corresponding input to synchronization to the SCT clock  before it is used to create an event."
endif
sif (cpuis("LPC54113*"))
hexmask.long.byte 0x0 9.--12. 1. "INSYNC,Synchronization for input N (bit 9 = input 0  bit 10 = input 1   bit 12 = input 3); all other bits are reserved. A 1 in one of these bits subjects the corresponding input to synchronization to the SCT clock  before it is used to create an event."
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endif
sif (cpuis("LPC54114*"))
hexmask.long.byte 0x0 9.--12. 1. "INSYNC,Synchronization for input N (bit 9 = input 0  bit 10 = input 1   bit 12 = input 3); all other bits are reserved. A 1 in one of these bits subjects the corresponding input to synchronization to the SCT clock  before it is used to create an event."
endif
sif (cpuis("LPC54605*"))
hexmask.long.byte 0x0 9.--12. 1. "INSYNC,Synchronization for input N (bit 9 = input 0  bit 10 = input 1   bit 12 = input 3); all other bits are reserved. A 1 in one of these bits subjects the corresponding input to synchronization to the SCT clock  before it is used to create an event."
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endif
sif (cpuis("LPC54606*"))
hexmask.long.byte 0x0 9.--12. 1. "INSYNC,Synchronization for input N (bit 9 = input 0  bit 10 = input 1   bit 12 = input 3); all other bits are reserved. A 1 in one of these bits subjects the corresponding input to synchronization to the SCT clock  before it is used to create an event."
endif
sif (cpuis("LPC54607*"))
hexmask.long.byte 0x0 9.--12. 1. "INSYNC,Synchronization for input N (bit 9 = input 0  bit 10 = input 1   bit 12 = input 3); all other bits are reserved. A 1 in one of these bits subjects the corresponding input to synchronization to the SCT clock  before it is used to create an event."
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endif
sif (cpuis("LPC54608*"))
hexmask.long.byte 0x0 9.--12. 1. "INSYNC,Synchronization for input N (bit 9 = input 0  bit 10 = input 1   bit 12 = input 3); all other bits are reserved. A 1 in one of these bits subjects the corresponding input to synchronization to the SCT clock  before it is used to create an event."
endif
sif (cpuis("LPC54616*"))
hexmask.long.byte 0x0 9.--12. 1. "INSYNC,Synchronization for input N (bit 9 = input 0  bit 10 = input 1   bit 12 = input 3); all other bits are reserved. A 1 in one of these bits subjects the corresponding input to synchronization to the SCT clock  before it is used to create an event."
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endif
sif (cpuis("LPC54618*"))
hexmask.long.byte 0x0 9.--12. 1. "INSYNC,Synchronization for input N (bit 9 = input 0  bit 10 = input 1   bit 12 = input 3); all other bits are reserved. A 1 in one of these bits subjects the corresponding input to synchronization to the SCT clock  before it is used to create an event."
endif
sif (cpuis("LPC54628*"))
hexmask.long.byte 0x0 9.--12. 1. "INSYNC,Synchronization for input N (bit 9 = input 0  bit 10 = input 1   bit 12 = input 3); all other bits are reserved. A 1 in one of these bits subjects the corresponding input to synchronization to the SCT clock  before it is used to create an event."
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endif
bitfld.long 0x0 8. "NORELOAD_H,A 1 in this bit prevents the higher match registers from being reloaded from their respective reload registers. Setting this bit eliminates the need to write to the reload registers MATCHREL if the match values are fixed. Software can write to.." "0,1"
bitfld.long 0x0 7. "NORELOAD_L,A 1 in this bit prevents the lower match registers from being reloaded from their respective reload registers. Setting this bit eliminates the need to write to the reload registers MATCHREL if the match values are fixed. Software can write to.." "0,1"
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hexmask.long.byte 0x0 3.--6. 1. "CKSEL,SCT clock select. The specific functionality of the designated input/edge is dependent on the CLKMODE bit selection in this register."
bitfld.long 0x0 1.--2. "CLKMODE,SCT clock mode" "0: System Clock Mode. The system clock clocks the..,1: Sampled System Clock Mode. The system clock..,2: SCT Input Clock Mode. The input/edge selected by..,3: Asynchronous Mode. The entire SCT module is.."
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bitfld.long 0x0 0. "UNIFY,SCT operation" "0: The SCT operates as two 16-bit counters named..,1: The SCT operates as a unified 32-bit counter."
line.long 0x4 "CTRL,SCT control register"
hexmask.long.byte 0x4 21.--28. 1. "PRE_H,Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE.."
bitfld.long 0x4 20. "BIDIR_H,Direction select" "0: The H counter counts up to its limit condition..,1: The H counter counts up to its limit then counts.."
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bitfld.long 0x4 19. "CLRCTR_H,Writing a 1 to this bit clears the H counter. This bit always reads as 0." "0,1"
bitfld.long 0x4 18. "HALT_H,When this bit is 1  the H counter does not run and no events can occur. A reset sets this bit. When the HALT_H bit is one  the STOP_H bit is cleared. It is possible to remove the halt condition while keeping the SCT in the stop condition (not.." "0,1"
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bitfld.long 0x4 17. "STOP_H,When this bit is 1 and HALT is 0  the H counter does not  run but I/O events related to the counter can occur. If such an event matches the mask in the Start register  this bit is cleared and counting resumes." "0,1"
bitfld.long 0x4 16. "DOWN_H,This bit is 1 when the H counter is counting down. Hardware sets this bit when the counter is counting  a counter limit condition occurs  and BIDIR is 1. Hardware clears this bit when the counter is counting down and a limit condition occurs or.." "0,1"
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hexmask.long.byte 0x4 5.--12. 1. "PRE_L,Specifies the factor by which the SCT clock is prescaled to produce the L or unified counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing.."
bitfld.long 0x4 4. "BIDIR_L,L or unified counter direction select" "0: Up. The counter counts up to a limit condition..,1: Up-down. The counter counts up to a limit then.."
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bitfld.long 0x4 3. "CLRCTR_L,Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0." "0,1"
bitfld.long 0x4 2. "HALT_L,When this bit is 1  the L or unified counter does not run and no events can occur. A reset sets this bit. When the HALT_L bit is one  the STOP_L bit is cleared. It is possible to remove the halt condition while keeping the SCT in the stop.." "0,1"
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bitfld.long 0x4 1. "STOP_L,When this bit is 1 and HALT is 0  the L or unified counter does not run  but I/O events related to the counter can occur. If a designated start event occurs  this bit is cleared and counting resumes." "0,1"
bitfld.long 0x4 0. "DOWN_L,This bit is 1 when the L or unified counter is counting down. Hardware sets this bit when the counter is counting up  counter limit occurs  and BIDIR = 1.Hardware clears this bit when the counter is counting down and a limit condition occurs or.." "0,1"
line.long 0x8 "LIMIT,SCT limit event select register"
hexmask.long.word 0x8 16.--31. 1. "LIMMSK_H,If bit n is one  event n is used as a counter limit for the H counter (event 0 = bit 16  event 1 = bit 17  etc.). The number of bits = number of events in this SCT."
hexmask.long.word 0x8 0.--15. 1. "LIMMSK_L,If bit n is one  event n is used as a counter limit for the L or unified counter (event 0 = bit 0  event 1 = bit 1  etc.). The number of bits = number of events in this SCT."
line.long 0xC "HALT,SCT halt event select register"
hexmask.long.word 0xC 16.--31. 1. "HALTMSK_H,If bit n is one  event n sets the HALT_H bit in the CTRL register (event 0 = bit 16  event 1 = bit 17  etc.). The number of bits = number of events in this SCT."
hexmask.long.word 0xC 0.--15. 1. "HALTMSK_L,If bit n is one  event n sets the HALT_L bit in the CTRL register (event 0 = bit 0  event 1 = bit 1  etc.). The number of bits = number of events in this SCT."
line.long 0x10 "STOP,SCT stop event select register"
hexmask.long.word 0x10 16.--31. 1. "STOPMSK_H,If bit n is one  event n sets the STOP_H bit in the CTRL register (event 0 = bit 16  event 1 = bit 17  etc.). The number of bits = number of events in this SCT."
hexmask.long.word 0x10 0.--15. 1. "STOPMSK_L,If bit n is one  event n sets the STOP_L bit in the CTRL register (event 0 = bit 0  event 1 = bit 1  etc.). The number of bits = number of events in this SCT."
line.long 0x14 "START,SCT start event select register"
hexmask.long.word 0x14 16.--31. 1. "STARTMSK_H,If bit n is one  event n clears the STOP_H bit in the CTRL register (event 0 = bit 16  event 1 = bit 17  etc.). The number of bits = number of events in this SCT."
hexmask.long.word 0x14 0.--15. 1. "STARTMSK_L,If bit n is one  event n clears the STOP_L bit in the CTRL register (event 0 = bit 0  event 1 = bit 1  etc.). The number of bits = number of events in this SCT."
group.long 0x40++0x7
line.long 0x0 "COUNT,SCT counter register"
hexmask.long.word 0x0 16.--31. 1. "CTR_H,When UNIFY = 0  read or write the 16-bit H counter value. When UNIFY = 1  read or write the upper 16 bits of the 32-bit unified counter."
hexmask.long.word 0x0 0.--15. 1. "CTR_L,When UNIFY = 0  read or write the 16-bit L counter value. When UNIFY = 1  read or write the lower 16 bits of the 32-bit unified counter."
line.long 0x4 "STATE,SCT state register"
hexmask.long.byte 0x4 16.--20. 1. "STATE_H,State variable."
hexmask.long.byte 0x4 0.--4. 1. "STATE_L,State variable."
rgroup.long 0x48++0x3
line.long 0x0 "INPUT,SCT input register"
bitfld.long 0x0 31. "SIN15,Input 15 state. Input 15 state following the synchronization specified by INSYNC." "0,1"
bitfld.long 0x0 30. "SIN14,Input 14 state. Input 14 state following the synchronization specified by INSYNC." "0,1"
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bitfld.long 0x0 29. "SIN13,Input 13 state. Input 13 state following the synchronization specified by INSYNC." "0,1"
bitfld.long 0x0 28. "SIN12,Input 12 state. Input 12 state following the synchronization specified by INSYNC." "0,1"
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bitfld.long 0x0 27. "SIN11,Input 11 state. Input 11 state following the synchronization specified by INSYNC." "0,1"
bitfld.long 0x0 26. "SIN10,Input 10 state. Input 10 state following the synchronization specified by INSYNC." "0,1"
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bitfld.long 0x0 25. "SIN9,Input 9 state. Input 9 state following the synchronization specified by INSYNC." "0,1"
bitfld.long 0x0 24. "SIN8,Input 8 state. Input 8 state following the synchronization specified by INSYNC." "0,1"
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bitfld.long 0x0 23. "SIN7,Input 7 state. Input 7 state following the synchronization specified by INSYNC." "0,1"
bitfld.long 0x0 22. "SIN6,Input 6 state. Input 6 state following the synchronization specified by INSYNC." "0,1"
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bitfld.long 0x0 21. "SIN5,Input 5 state. Input 5 state following the synchronization specified by INSYNC." "0,1"
bitfld.long 0x0 20. "SIN4,Input 4 state. Input 4 state following the synchronization specified by INSYNC." "0,1"
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bitfld.long 0x0 19. "SIN3,Input 3 state. Input 3 state following the synchronization specified by INSYNC." "0,1"
bitfld.long 0x0 18. "SIN2,Input 2 state. Input 2 state following the synchronization specified by INSYNC." "0,1"
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bitfld.long 0x0 17. "SIN1,Input 1 state. Input 1 state following the synchronization specified by INSYNC." "0,1"
bitfld.long 0x0 16. "SIN0,Input 0 state. Input 0 state following the synchronization specified by INSYNC." "0,1"
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bitfld.long 0x0 15. "AIN15,Input 15 state. Input 15 state on the last SCT clock edge." "0,1"
bitfld.long 0x0 14. "AIN14,Input 14 state. Input 14 state on the last SCT clock edge." "0,1"
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bitfld.long 0x0 13. "AIN13,Input 13 state. Input 13 state on the last SCT clock edge." "0,1"
bitfld.long 0x0 12. "AIN12,Input 12 state. Input 12 state on the last SCT clock edge." "0,1"
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bitfld.long 0x0 11. "AIN11,Input 11 state. Input 11 state on the last SCT clock edge." "0,1"
bitfld.long 0x0 10. "AIN10,Input 10 state. Input 10 state on the last SCT clock edge." "0,1"
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bitfld.long 0x0 9. "AIN9,Input 9 state. Input 9 state on the last SCT clock edge." "0,1"
bitfld.long 0x0 8. "AIN8,Input 8 state. Input 8 state on the last SCT clock edge." "0,1"
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bitfld.long 0x0 7. "AIN7,Input 7 state. Input 7 state on the last SCT clock edge." "0,1"
bitfld.long 0x0 6. "AIN6,Input 6 state. Input 6 state on the last SCT clock edge." "0,1"
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bitfld.long 0x0 5. "AIN5,Input 5 state. Input 5 state on the last SCT clock edge." "0,1"
bitfld.long 0x0 4. "AIN4,Input 4 state. Input 4 state on the last SCT clock edge." "0,1"
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bitfld.long 0x0 3. "AIN3,Input 3 state. Input 3 state on the last SCT clock edge." "0,1"
bitfld.long 0x0 2. "AIN2,Input 2 state. Input 2 state on the last SCT clock edge." "0,1"
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bitfld.long 0x0 1. "AIN1,Input 1 state. Input 1 state on the last SCT clock edge." "0,1"
bitfld.long 0x0 0. "AIN0,Input 0 state. Input 0 state on the last SCT clock edge." "0,1"
group.long 0x4C++0x17
line.long 0x0 "REGMODE,SCT match/capture mode register"
hexmask.long.word 0x0 16.--31. 1. "REGMOD_H,Each bit controls one match/capture register (register 0 = bit 16  register 1 = bit 17  etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as match registers. 1 = register operates as capture registers."
hexmask.long.word 0x0 0.--15. 1. "REGMOD_L,Each bit controls one match/capture register (register 0 = bit 0  register 1 = bit 1  etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as match register. 1 = register operates as capture register."
line.long 0x4 "OUTPUT,SCT output register"
hexmask.long.word 0x4 0.--15. 1. "OUT,Writing a 1 to bit n forces the corresponding output HIGH. Writing a 0 forces the corresponding output LOW (output 0 = bit 0  output 1 = bit 1  etc.). The number of bits = number of outputs in this SCT."
line.long 0x8 "OUTPUTDIRCTRL,SCT output counter direction control register"
bitfld.long 0x8 30.--31. "SETCLR15,Set/clear operation on output 15. Value 0x3 is reserved. Do not program this value." "0: Set and clear do not depend on the direction of..,1: Set and clear are reversed when counter L or the..,2: Set and clear are reversed when counter H is..,?"
bitfld.long 0x8 28.--29. "SETCLR14,Set/clear operation on output 14. Value 0x3 is reserved. Do not program this value." "0: Set and clear do not depend on the direction of..,1: Set and clear are reversed when counter L or the..,2: Set and clear are reversed when counter H is..,?"
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bitfld.long 0x8 26.--27. "SETCLR13,Set/clear operation on output 13. Value 0x3 is reserved. Do not program this value." "0: Set and clear do not depend on the direction of..,1: Set and clear are reversed when counter L or the..,2: Set and clear are reversed when counter H is..,?"
bitfld.long 0x8 24.--25. "SETCLR12,Set/clear operation on output 12. Value 0x3 is reserved. Do not program this value." "0: Set and clear do not depend on the direction of..,1: Set and clear are reversed when counter L or the..,2: Set and clear are reversed when counter H is..,?"
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bitfld.long 0x8 22.--23. "SETCLR11,Set/clear operation on output 11. Value 0x3 is reserved. Do not program this value." "0: Set and clear do not depend on the direction of..,1: Set and clear are reversed when counter L or the..,2: Set and clear are reversed when counter H is..,?"
bitfld.long 0x8 20.--21. "SETCLR10,Set/clear operation on output 10. Value 0x3 is reserved. Do not program this value." "0: Set and clear do not depend on the direction of..,1: Set and clear are reversed when counter L or the..,2: Set and clear are reversed when counter H is..,?"
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bitfld.long 0x8 18.--19. "SETCLR9,Set/clear operation on output 9. Value 0x3 is reserved. Do not program this value." "0: Set and clear do not depend on the direction of..,1: Set and clear are reversed when counter L or the..,2: Set and clear are reversed when counter H is..,?"
bitfld.long 0x8 16.--17. "SETCLR8,Set/clear operation on output 8. Value 0x3 is reserved. Do not program this value." "0: Set and clear do not depend on the direction of..,1: Set and clear are reversed when counter L or the..,2: Set and clear are reversed when counter H is..,?"
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bitfld.long 0x8 14.--15. "SETCLR7,Set/clear operation on output 7. Value 0x3 is reserved. Do not program this value." "0: Set and clear do not depend on the direction of..,1: Set and clear are reversed when counter L or the..,2: Set and clear are reversed when counter H is..,?"
bitfld.long 0x8 12.--13. "SETCLR6,Set/clear operation on output 6. Value 0x3 is reserved. Do not program this value." "0: Set and clear do not depend on the direction of..,1: Set and clear are reversed when counter L or the..,2: Set and clear are reversed when counter H is..,?"
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bitfld.long 0x8 10.--11. "SETCLR5,Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value." "0: Set and clear do not depend on the direction of..,1: Set and clear are reversed when counter L or the..,2: Set and clear are reversed when counter H is..,?"
bitfld.long 0x8 8.--9. "SETCLR4,Set/clear operation on output 4. Value 0x3 is reserved. Do not program this value." "0: Set and clear do not depend on the direction of..,1: Set and clear are reversed when counter L or the..,2: Set and clear are reversed when counter H is..,?"
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bitfld.long 0x8 6.--7. "SETCLR3,Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value." "0: Set and clear do not depend on the direction of..,1: Set and clear are reversed when counter L or the..,2: Set and clear are reversed when counter H is..,?"
bitfld.long 0x8 4.--5. "SETCLR2,Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value." "0: Set and clear do not depend on the direction of..,1: Set and clear are reversed when counter L or the..,2: Set and clear are reversed when counter H is..,?"
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bitfld.long 0x8 2.--3. "SETCLR1,Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value." "0: Set and clear do not depend on the direction of..,1: Set and clear are reversed when counter L or the..,2: Set and clear are reversed when counter H is..,?"
bitfld.long 0x8 0.--1. "SETCLR0,Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value." "0: Set and clear do not depend on the direction of..,1: Set and clear are reversed when counter L or the..,2: Set and clear are reversed when counter H is..,?"
line.long 0xC "RES,SCT conflict resolution register"
bitfld.long 0xC 30.--31. "O15RES,Effect of simultaneous set and clear on output 15." "0: No change.,1: Set output (or clear based on the SETCLR15 field..,2: Clear output (or set based on the SETCLR15 field).,3: Toggle output."
bitfld.long 0xC 28.--29. "O14RES,Effect of simultaneous set and clear on output 14." "0: No change.,1: Set output (or clear based on the SETCLR14 field..,2: Clear output (or set based on the SETCLR14 field).,3: Toggle output."
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bitfld.long 0xC 26.--27. "O13RES,Effect of simultaneous set and clear on output 13." "0: No change.,1: Set output (or clear based on the SETCLR13 field..,2: Clear output (or set based on the SETCLR13 field).,3: Toggle output."
bitfld.long 0xC 24.--25. "O12RES,Effect of simultaneous set and clear on output 12." "0: No change.,1: Set output (or clear based on the SETCLR12 field..,2: Clear output (or set based on the SETCLR12 field).,3: Toggle output."
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bitfld.long 0xC 22.--23. "O11RES,Effect of simultaneous set and clear on output 11." "0: No change.,1: Set output (or clear based on the SETCLR11 field..,2: Clear output (or set based on the SETCLR11 field).,3: Toggle output."
bitfld.long 0xC 20.--21. "O10RES,Effect of simultaneous set and clear on output 10." "0: No change.,1: Set output (or clear based on the SETCLR10 field..,2: Clear output (or set based on the SETCLR10 field).,3: Toggle output."
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bitfld.long 0xC 18.--19. "O9RES,Effect of simultaneous set and clear on output 9." "0: No change.,1: Set output (or clear based on the SETCLR9 field..,2: Clear output (or set based on the SETCLR9 field).,3: Toggle output."
bitfld.long 0xC 16.--17. "O8RES,Effect of simultaneous set and clear on output 8." "0: No change.,1: Set output (or clear based on the SETCLR8 field..,2: Clear output (or set based on the SETCLR8 field).,3: Toggle output."
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bitfld.long 0xC 14.--15. "O7RES,Effect of simultaneous set and clear on output 7." "0: No change.,1: Set output (or clear based on the SETCLR7 field..,2: Clear output n (or set based on the SETCLR7..,3: Toggle output."
bitfld.long 0xC 12.--13. "O6RES,Effect of simultaneous set and clear on output 6." "0: No change.,1: Set output (or clear based on the SETCLR6 field..,2: Clear output (or set based on the SETCLR6 field).,3: Toggle output."
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bitfld.long 0xC 10.--11. "O5RES,Effect of simultaneous set and clear on output 5." "0: No change.,1: Set output (or clear based on the SETCLR5 field..,2: Clear output (or set based on the SETCLR5 field).,3: Toggle output."
bitfld.long 0xC 8.--9. "O4RES,Effect of simultaneous set and clear on output 4." "0: No change.,1: Set output (or clear based on the SETCLR4 field..,2: Clear output (or set based on the SETCLR4 field).,3: Toggle output."
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bitfld.long 0xC 6.--7. "O3RES,Effect of simultaneous set and clear on output 3." "0: No change.,1: Set output (or clear based on the SETCLR3 field..,2: Clear output (or set based on the SETCLR3 field).,3: Toggle output."
bitfld.long 0xC 4.--5. "O2RES,Effect of simultaneous set and clear on output 2." "0: No change.,1: Set output (or clear based on the SETCLR2 field..,2: Clear output n (or set based on the SETCLR2..,3: Toggle output."
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bitfld.long 0xC 2.--3. "O1RES,Effect of simultaneous set and clear on output 1." "0: No change.,1: Set output (or clear based on the SETCLR1 field..,2: Clear output (or set based on the SETCLR1 field).,3: Toggle output."
bitfld.long 0xC 0.--1. "O0RES,Effect of simultaneous set and clear on output 0." "0: No change.,1: Set output (or clear based on the SETCLR0 field..,2: Clear output (or set based on the SETCLR0 field).,3: Toggle output."
line.long 0x10 "DMAREQ0,SCT DMA request 0 register"
bitfld.long 0x10 31. "DRQ0,This read-only bit indicates the state of DMA Request 0. Note that if the related DMA channel is enabled and properly set up  it is unlikely that software will see this flag  it will be cleared rapidly by the DMA service. The flag remaining set.." "0,1"
bitfld.long 0x10 30. "DRL0,A 1 in this bit triggers DMA request 0 when it loads the MATCH_L/Unified registers from the RELOAD_L/Unified registers." "0,1"
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hexmask.long.word 0x10 0.--15. 1. "DEV_0,If bit n is one  event n triggers DMA request 0 (event 0 = bit 0  event 1 = bit 1  etc.). The number of bits = number of events in this SCT."
line.long 0x14 "DMAREQ1,SCT DMA request 1 register"
bitfld.long 0x14 31. "DRQ1,This read-only bit indicates the state of DMA Request 1. Note that if the related DMA channel is enabled and properly set up  it is unlikely that software will see this flag  it will be cleared rapidly by the DMA service. The flag remaining set.." "0,1"
bitfld.long 0x14 30. "DRL1,A 1 in this bit triggers DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers." "0,1"
newline
hexmask.long.word 0x14 0.--15. 1. "DEV_1,If bit n is one  event n triggers DMA request 1 (event 0 = bit 0  event 1 = bit 1  etc.). The number of bits = number of events in this SCT."
group.long 0xF0++0x13
line.long 0x0 "EVEN,SCT event interrupt enable register"
hexmask.long.word 0x0 0.--15. 1. "IEN,The SCT requests an interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0  event 1 = bit 1  etc.). The number of bits = number of events in this SCT."
line.long 0x4 "EVFLAG,SCT event flag register"
hexmask.long.word 0x4 0.--15. 1. "FLAG,Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0  event 1 = bit 1  etc.). The number of bits = number of events in this SCT."
line.long 0x8 "CONEN,SCT conflict interrupt enable register"
hexmask.long.word 0x8 0.--15. 1. "NCEN,The SCT requests an interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0  output 1 = bit 1  etc.). The number of bits = number of outputs in this SCT."
line.long 0xC "CONFLAG,SCT conflict flag register"
bitfld.long 0xC 31. "BUSERRH,The most recent bus error from this SCT involved writing CTR H  STATE H  MATCH H  or the Output register when the H counter was not halted." "0,1"
bitfld.long 0xC 30. "BUSERRL,The most recent bus error from this SCT involved writing CTR L/Unified  STATE L/Unified  MATCH L/Unified  or the Output register when the L/U counter was not halted. A word write to certain L and H registers can be half successful and half.." "0,1"
newline
hexmask.long.word 0xC 0.--15. 1. "NCFLAG,Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0  output 1 = bit 1  etc.). The number of bits = number of outputs in this SCT."
line.long 0x10 "CAP0,SCT capture register of capture channel"
hexmask.long.word 0x10 16.--31. 1. "CAPn_H,When UNIFY = 0  read the 16-bit counter value at which this register was last captured. When UNIFY = 1  read the upper 16 bits of the 32-bit value at which this register was last captured."
hexmask.long.word 0x10 0.--15. 1. "CAPn_L,When UNIFY = 0  read the 16-bit counter value at which this register was last captured. When UNIFY = 1  read the lower 16 bits of the 32-bit value at which this register was last captured."
group.long 0x100++0x7
line.long 0x0 "MATCH0,SCT match value register of match channels"
hexmask.long.word 0x0 16.--31. 1. "MATCHn_H,When UNIFY = 0  read or write the 16-bit value to be compared to the H counter. When UNIFY = 1  read or write the upper 16 bits of the 32-bit value to be compared to the unified counter."
hexmask.long.word 0x0 0.--15. 1. "MATCHn_L,When UNIFY = 0  read or write the 16-bit value to be compared to the L counter. When UNIFY = 1  read or write the lower 16 bits of the 32-bit value to be compared to the unified counter."
line.long 0x4 "CAP1,SCT capture register of capture channel"
hexmask.long.word 0x4 16.--31. 1. "CAPn_H,When UNIFY = 0  read the 16-bit counter value at which this register was last captured. When UNIFY = 1  read the upper 16 bits of the 32-bit value at which this register was last captured."
hexmask.long.word 0x4 0.--15. 1. "CAPn_L,When UNIFY = 0  read the 16-bit counter value at which this register was last captured. When UNIFY = 1  read the lower 16 bits of the 32-bit value at which this register was last captured."
group.long 0x104++0x7
line.long 0x0 "MATCH1,SCT match value register of match channels"
hexmask.long.word 0x0 16.--31. 1. "MATCHn_H,When UNIFY = 0  read or write the 16-bit value to be compared to the H counter. When UNIFY = 1  read or write the upper 16 bits of the 32-bit value to be compared to the unified counter."
hexmask.long.word 0x0 0.--15. 1. "MATCHn_L,When UNIFY = 0  read or write the 16-bit value to be compared to the L counter. When UNIFY = 1  read or write the lower 16 bits of the 32-bit value to be compared to the unified counter."
line.long 0x4 "CAP2,SCT capture register of capture channel"
hexmask.long.word 0x4 16.--31. 1. "CAPn_H,When UNIFY = 0  read the 16-bit counter value at which this register was last captured. When UNIFY = 1  read the upper 16 bits of the 32-bit value at which this register was last captured."
hexmask.long.word 0x4 0.--15. 1. "CAPn_L,When UNIFY = 0  read the 16-bit counter value at which this register was last captured. When UNIFY = 1  read the lower 16 bits of the 32-bit value at which this register was last captured."
group.long 0x108++0x7
line.long 0x0 "MATCH2,SCT match value register of match channels"
hexmask.long.word 0x0 16.--31. 1. "MATCHn_H,When UNIFY = 0  read or write the 16-bit value to be compared to the H counter. When UNIFY = 1  read or write the upper 16 bits of the 32-bit value to be compared to the unified counter."
hexmask.long.word 0x0 0.--15. 1. "MATCHn_L,When UNIFY = 0  read or write the 16-bit value to be compared to the L counter. When UNIFY = 1  read or write the lower 16 bits of the 32-bit value to be compared to the unified counter."
line.long 0x4 "CAP3,SCT capture register of capture channel"
hexmask.long.word 0x4 16.--31. 1. "CAPn_H,When UNIFY = 0  read the 16-bit counter value at which this register was last captured. When UNIFY = 1  read the upper 16 bits of the 32-bit value at which this register was last captured."
hexmask.long.word 0x4 0.--15. 1. "CAPn_L,When UNIFY = 0  read the 16-bit counter value at which this register was last captured. When UNIFY = 1  read the lower 16 bits of the 32-bit value at which this register was last captured."
group.long 0x10C++0x7
line.long 0x0 "MATCH3,SCT match value register of match channels"
hexmask.long.word 0x0 16.--31. 1. "MATCHn_H,When UNIFY = 0  read or write the 16-bit value to be compared to the H counter. When UNIFY = 1  read or write the upper 16 bits of the 32-bit value to be compared to the unified counter."
hexmask.long.word 0x0 0.--15. 1. "MATCHn_L,When UNIFY = 0  read or write the 16-bit value to be compared to the L counter. When UNIFY = 1  read or write the lower 16 bits of the 32-bit value to be compared to the unified counter."
line.long 0x4 "CAP4,SCT capture register of capture channel"
hexmask.long.word 0x4 16.--31. 1. "CAPn_H,When UNIFY = 0  read the 16-bit counter value at which this register was last captured. When UNIFY = 1  read the upper 16 bits of the 32-bit value at which this register was last captured."
hexmask.long.word 0x4 0.--15. 1. "CAPn_L,When UNIFY = 0  read the 16-bit counter value at which this register was last captured. When UNIFY = 1  read the lower 16 bits of the 32-bit value at which this register was last captured."
group.long 0x110++0x7
line.long 0x0 "MATCH4,SCT match value register of match channels"
hexmask.long.word 0x0 16.--31. 1. "MATCHn_H,When UNIFY = 0  read or write the 16-bit value to be compared to the H counter. When UNIFY = 1  read or write the upper 16 bits of the 32-bit value to be compared to the unified counter."
hexmask.long.word 0x0 0.--15. 1. "MATCHn_L,When UNIFY = 0  read or write the 16-bit value to be compared to the L counter. When UNIFY = 1  read or write the lower 16 bits of the 32-bit value to be compared to the unified counter."
line.long 0x4 "CAP5,SCT capture register of capture channel"
hexmask.long.word 0x4 16.--31. 1. "CAPn_H,When UNIFY = 0  read the 16-bit counter value at which this register was last captured. When UNIFY = 1  read the upper 16 bits of the 32-bit value at which this register was last captured."
hexmask.long.word 0x4 0.--15. 1. "CAPn_L,When UNIFY = 0  read the 16-bit counter value at which this register was last captured. When UNIFY = 1  read the lower 16 bits of the 32-bit value at which this register was last captured."
group.long 0x114++0x7
line.long 0x0 "MATCH5,SCT match value register of match channels"
hexmask.long.word 0x0 16.--31. 1. "MATCHn_H,When UNIFY = 0  read or write the 16-bit value to be compared to the H counter. When UNIFY = 1  read or write the upper 16 bits of the 32-bit value to be compared to the unified counter."
hexmask.long.word 0x0 0.--15. 1. "MATCHn_L,When UNIFY = 0  read or write the 16-bit value to be compared to the L counter. When UNIFY = 1  read or write the lower 16 bits of the 32-bit value to be compared to the unified counter."
line.long 0x4 "CAP6,SCT capture register of capture channel"
hexmask.long.word 0x4 16.--31. 1. "CAPn_H,When UNIFY = 0  read the 16-bit counter value at which this register was last captured. When UNIFY = 1  read the upper 16 bits of the 32-bit value at which this register was last captured."
hexmask.long.word 0x4 0.--15. 1. "CAPn_L,When UNIFY = 0  read the 16-bit counter value at which this register was last captured. When UNIFY = 1  read the lower 16 bits of the 32-bit value at which this register was last captured."
group.long 0x118++0x7
line.long 0x0 "MATCH6,SCT match value register of match channels"
hexmask.long.word 0x0 16.--31. 1. "MATCHn_H,When UNIFY = 0  read or write the 16-bit value to be compared to the H counter. When UNIFY = 1  read or write the upper 16 bits of the 32-bit value to be compared to the unified counter."
hexmask.long.word 0x0 0.--15. 1. "MATCHn_L,When UNIFY = 0  read or write the 16-bit value to be compared to the L counter. When UNIFY = 1  read or write the lower 16 bits of the 32-bit value to be compared to the unified counter."
line.long 0x4 "CAP7,SCT capture register of capture channel"
hexmask.long.word 0x4 16.--31. 1. "CAPn_H,When UNIFY = 0  read the 16-bit counter value at which this register was last captured. When UNIFY = 1  read the upper 16 bits of the 32-bit value at which this register was last captured."
hexmask.long.word 0x4 0.--15. 1. "CAPn_L,When UNIFY = 0  read the 16-bit counter value at which this register was last captured. When UNIFY = 1  read the lower 16 bits of the 32-bit value at which this register was last captured."
group.long 0x11C++0x7
line.long 0x0 "MATCH7,SCT match value register of match channels"
hexmask.long.word 0x0 16.--31. 1. "MATCHn_H,When UNIFY = 0  read or write the 16-bit value to be compared to the H counter. When UNIFY = 1  read or write the upper 16 bits of the 32-bit value to be compared to the unified counter."
hexmask.long.word 0x0 0.--15. 1. "MATCHn_L,When UNIFY = 0  read or write the 16-bit value to be compared to the L counter. When UNIFY = 1  read or write the lower 16 bits of the 32-bit value to be compared to the unified counter."
line.long 0x4 "CAP8,SCT capture register of capture channel"
hexmask.long.word 0x4 16.--31. 1. "CAPn_H,When UNIFY = 0  read the 16-bit counter value at which this register was last captured. When UNIFY = 1  read the upper 16 bits of the 32-bit value at which this register was last captured."
hexmask.long.word 0x4 0.--15. 1. "CAPn_L,When UNIFY = 0  read the 16-bit counter value at which this register was last captured. When UNIFY = 1  read the lower 16 bits of the 32-bit value at which this register was last captured."
group.long 0x120++0x7
line.long 0x0 "MATCH8,SCT match value register of match channels"
hexmask.long.word 0x0 16.--31. 1. "MATCHn_H,When UNIFY = 0  read or write the 16-bit value to be compared to the H counter. When UNIFY = 1  read or write the upper 16 bits of the 32-bit value to be compared to the unified counter."
hexmask.long.word 0x0 0.--15. 1. "MATCHn_L,When UNIFY = 0  read or write the 16-bit value to be compared to the L counter. When UNIFY = 1  read or write the lower 16 bits of the 32-bit value to be compared to the unified counter."
line.long 0x4 "CAP9,SCT capture register of capture channel"
hexmask.long.word 0x4 16.--31. 1. "CAPn_H,When UNIFY = 0  read the 16-bit counter value at which this register was last captured. When UNIFY = 1  read the upper 16 bits of the 32-bit value at which this register was last captured."
hexmask.long.word 0x4 0.--15. 1. "CAPn_L,When UNIFY = 0  read the 16-bit counter value at which this register was last captured. When UNIFY = 1  read the lower 16 bits of the 32-bit value at which this register was last captured."
group.long 0x124++0x3
line.long 0x0 "MATCH9,SCT match value register of match channels"
hexmask.long.word 0x0 16.--31. 1. "MATCHn_H,When UNIFY = 0  read or write the 16-bit value to be compared to the H counter. When UNIFY = 1  read or write the upper 16 bits of the 32-bit value to be compared to the unified counter."
hexmask.long.word 0x0 0.--15. 1. "MATCHn_L,When UNIFY = 0  read or write the 16-bit value to be compared to the L counter. When UNIFY = 1  read or write the lower 16 bits of the 32-bit value to be compared to the unified counter."
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54101*")||cpuis("LPC54102*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
group.long 0x128++0x3
line.long 0x0 "CAP10,SCT capture register of capture channel"
hexmask.long.word 0x0 16.--31. 1. "CAPn_H,When UNIFY = 0  read the 16-bit counter value at which this register was last captured. When UNIFY = 1  read the upper 16 bits of the 32-bit value at which this register was last captured."
hexmask.long.word 0x0 0.--15. 1. "CAPn_L,When UNIFY = 0  read the 16-bit counter value at which this register was last captured. When UNIFY = 1  read the lower 16 bits of the 32-bit value at which this register was last captured."
group.long 0x128++0x7
line.long 0x0 "MATCH10,SCT match value register of match channels"
hexmask.long.word 0x0 16.--31. 1. "MATCHn_H,When UNIFY = 0  read or write the 16-bit value to be compared to the H counter. When UNIFY = 1  read or write the upper 16 bits of the 32-bit value to be compared to the unified counter."
hexmask.long.word 0x0 0.--15. 1. "MATCHn_L,When UNIFY = 0  read or write the 16-bit value to be compared to the L counter. When UNIFY = 1  read or write the lower 16 bits of the 32-bit value to be compared to the unified counter."
line.long 0x4 "CAP11,SCT capture register of capture channel"
hexmask.long.word 0x4 16.--31. 1. "CAPn_H,When UNIFY = 0  read the 16-bit counter value at which this register was last captured. When UNIFY = 1  read the upper 16 bits of the 32-bit value at which this register was last captured."
hexmask.long.word 0x4 0.--15. 1. "CAPn_L,When UNIFY = 0  read the 16-bit counter value at which this register was last captured. When UNIFY = 1  read the lower 16 bits of the 32-bit value at which this register was last captured."
group.long 0x12C++0x7
line.long 0x0 "MATCH11,SCT match value register of match channels"
hexmask.long.word 0x0 16.--31. 1. "MATCHn_H,When UNIFY = 0  read or write the 16-bit value to be compared to the H counter. When UNIFY = 1  read or write the upper 16 bits of the 32-bit value to be compared to the unified counter."
hexmask.long.word 0x0 0.--15. 1. "MATCHn_L,When UNIFY = 0  read or write the 16-bit value to be compared to the L counter. When UNIFY = 1  read or write the lower 16 bits of the 32-bit value to be compared to the unified counter."
line.long 0x4 "CAP12,SCT capture register of capture channel"
hexmask.long.word 0x4 16.--31. 1. "CAPn_H,When UNIFY = 0  read the 16-bit counter value at which this register was last captured. When UNIFY = 1  read the upper 16 bits of the 32-bit value at which this register was last captured."
hexmask.long.word 0x4 0.--15. 1. "CAPn_L,When UNIFY = 0  read the 16-bit counter value at which this register was last captured. When UNIFY = 1  read the lower 16 bits of the 32-bit value at which this register was last captured."
group.long 0x130++0x3
line.long 0x0 "MATCH12,SCT match value register of match channels"
hexmask.long.word 0x0 16.--31. 1. "MATCHn_H,When UNIFY = 0  read or write the 16-bit value to be compared to the H counter. When UNIFY = 1  read or write the upper 16 bits of the 32-bit value to be compared to the unified counter."
hexmask.long.word 0x0 0.--15. 1. "MATCHn_L,When UNIFY = 0  read or write the 16-bit value to be compared to the L counter. When UNIFY = 1  read or write the lower 16 bits of the 32-bit value to be compared to the unified counter."
group.long 0x228++0x3
line.long 0x0 "CAPCTRL10,SCT capture control register"
hexmask.long.word 0x0 16.--31. 1. "CAPCONn_H,If bit m is one  event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16  event 1 = bit 17  etc.). The number of bits = number of match/captures in this SCT."
hexmask.long.word 0x0 0.--15. 1. "CAPCONn_L,If bit m is one  event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0  event 1 = bit 1  etc.). The number of bits = number of match/captures in this SCT."
group.long 0x228++0x7
line.long 0x0 "MATCHREL10,SCT match reload value register"
hexmask.long.word 0x0 16.--31. 1. "RELOADn_H,When UNIFY = 0  specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1  specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register."
hexmask.long.word 0x0 0.--15. 1. "RELOADn_L,When UNIFY = 0  specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1  specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register."
line.long 0x4 "CAPCTRL11,SCT capture control register"
hexmask.long.word 0x4 16.--31. 1. "CAPCONn_H,If bit m is one  event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16  event 1 = bit 17  etc.). The number of bits = number of match/captures in this SCT."
hexmask.long.word 0x4 0.--15. 1. "CAPCONn_L,If bit m is one  event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0  event 1 = bit 1  etc.). The number of bits = number of match/captures in this SCT."
group.long 0x22C++0x7
line.long 0x0 "MATCHREL11,SCT match reload value register"
hexmask.long.word 0x0 16.--31. 1. "RELOADn_H,When UNIFY = 0  specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1  specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register."
hexmask.long.word 0x0 0.--15. 1. "RELOADn_L,When UNIFY = 0  specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1  specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register."
line.long 0x4 "CAPCTRL12,SCT capture control register"
hexmask.long.word 0x4 16.--31. 1. "CAPCONn_H,If bit m is one  event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16  event 1 = bit 17  etc.). The number of bits = number of match/captures in this SCT."
hexmask.long.word 0x4 0.--15. 1. "CAPCONn_L,If bit m is one  event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0  event 1 = bit 1  etc.). The number of bits = number of match/captures in this SCT."
group.long 0x230++0x3
line.long 0x0 "MATCHREL12,SCT match reload value register"
hexmask.long.word 0x0 16.--31. 1. "RELOADn_H,When UNIFY = 0  specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1  specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register."
hexmask.long.word 0x0 0.--15. 1. "RELOADn_L,When UNIFY = 0  specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1  specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register."
endif
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
group.long 0x134++0x3
line.long 0x0 "CAP13,SCT capture register of capture channel"
hexmask.long.word 0x0 16.--31. 1. "CAPn_H,When UNIFY = 0  read the 16-bit counter value at which this register was last captured. When UNIFY = 1  read the upper 16 bits of the 32-bit value at which this register was last captured."
hexmask.long.word 0x0 0.--15. 1. "CAPn_L,When UNIFY = 0  read the 16-bit counter value at which this register was last captured. When UNIFY = 1  read the lower 16 bits of the 32-bit value at which this register was last captured."
group.long 0x134++0x7
line.long 0x0 "MATCH13,SCT match value register of match channels"
hexmask.long.word 0x0 16.--31. 1. "MATCHn_H,When UNIFY = 0  read or write the 16-bit value to be compared to the H counter. When UNIFY = 1  read or write the upper 16 bits of the 32-bit value to be compared to the unified counter."
hexmask.long.word 0x0 0.--15. 1. "MATCHn_L,When UNIFY = 0  read or write the 16-bit value to be compared to the L counter. When UNIFY = 1  read or write the lower 16 bits of the 32-bit value to be compared to the unified counter."
line.long 0x4 "CAP14,SCT capture register of capture channel"
hexmask.long.word 0x4 16.--31. 1. "CAPn_H,When UNIFY = 0  read the 16-bit counter value at which this register was last captured. When UNIFY = 1  read the upper 16 bits of the 32-bit value at which this register was last captured."
hexmask.long.word 0x4 0.--15. 1. "CAPn_L,When UNIFY = 0  read the 16-bit counter value at which this register was last captured. When UNIFY = 1  read the lower 16 bits of the 32-bit value at which this register was last captured."
group.long 0x138++0x7
line.long 0x0 "MATCH14,SCT match value register of match channels"
hexmask.long.word 0x0 16.--31. 1. "MATCHn_H,When UNIFY = 0  read or write the 16-bit value to be compared to the H counter. When UNIFY = 1  read or write the upper 16 bits of the 32-bit value to be compared to the unified counter."
hexmask.long.word 0x0 0.--15. 1. "MATCHn_L,When UNIFY = 0  read or write the 16-bit value to be compared to the L counter. When UNIFY = 1  read or write the lower 16 bits of the 32-bit value to be compared to the unified counter."
line.long 0x4 "CAP15,SCT capture register of capture channel"
hexmask.long.word 0x4 16.--31. 1. "CAPn_H,When UNIFY = 0  read the 16-bit counter value at which this register was last captured. When UNIFY = 1  read the upper 16 bits of the 32-bit value at which this register was last captured."
hexmask.long.word 0x4 0.--15. 1. "CAPn_L,When UNIFY = 0  read the 16-bit counter value at which this register was last captured. When UNIFY = 1  read the lower 16 bits of the 32-bit value at which this register was last captured."
group.long 0x13C++0x3
line.long 0x0 "MATCH15,SCT match value register of match channels"
hexmask.long.word 0x0 16.--31. 1. "MATCHn_H,When UNIFY = 0  read or write the 16-bit value to be compared to the H counter. When UNIFY = 1  read or write the upper 16 bits of the 32-bit value to be compared to the unified counter."
hexmask.long.word 0x0 0.--15. 1. "MATCHn_L,When UNIFY = 0  read or write the 16-bit value to be compared to the L counter. When UNIFY = 1  read or write the lower 16 bits of the 32-bit value to be compared to the unified counter."
group.long 0x234++0x3
line.long 0x0 "CAPCTRL13,SCT capture control register"
hexmask.long.word 0x0 16.--31. 1. "CAPCONn_H,If bit m is one  event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16  event 1 = bit 17  etc.). The number of bits = number of match/captures in this SCT."
hexmask.long.word 0x0 0.--15. 1. "CAPCONn_L,If bit m is one  event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0  event 1 = bit 1  etc.). The number of bits = number of match/captures in this SCT."
group.long 0x234++0x7
line.long 0x0 "MATCHREL13,SCT match reload value register"
hexmask.long.word 0x0 16.--31. 1. "RELOADn_H,When UNIFY = 0  specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1  specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register."
hexmask.long.word 0x0 0.--15. 1. "RELOADn_L,When UNIFY = 0  specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1  specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register."
line.long 0x4 "CAPCTRL14,SCT capture control register"
hexmask.long.word 0x4 16.--31. 1. "CAPCONn_H,If bit m is one  event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16  event 1 = bit 17  etc.). The number of bits = number of match/captures in this SCT."
hexmask.long.word 0x4 0.--15. 1. "CAPCONn_L,If bit m is one  event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0  event 1 = bit 1  etc.). The number of bits = number of match/captures in this SCT."
group.long 0x238++0x7
line.long 0x0 "MATCHREL14,SCT match reload value register"
hexmask.long.word 0x0 16.--31. 1. "RELOADn_H,When UNIFY = 0  specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1  specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register."
hexmask.long.word 0x0 0.--15. 1. "RELOADn_L,When UNIFY = 0  specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1  specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register."
line.long 0x4 "CAPCTRL15,SCT capture control register"
hexmask.long.word 0x4 16.--31. 1. "CAPCONn_H,If bit m is one  event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16  event 1 = bit 17  etc.). The number of bits = number of match/captures in this SCT."
hexmask.long.word 0x4 0.--15. 1. "CAPCONn_L,If bit m is one  event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0  event 1 = bit 1  etc.). The number of bits = number of match/captures in this SCT."
group.long 0x23C++0x3
line.long 0x0 "MATCHREL15,SCT match reload value register"
hexmask.long.word 0x0 16.--31. 1. "RELOADn_H,When UNIFY = 0  specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1  specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register."
hexmask.long.word 0x0 0.--15. 1. "RELOADn_L,When UNIFY = 0  specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1  specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register."
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40085300 ad:0x40085308 ad:0x40085310 ad:0x40085318 ad:0x40085320 ad:0x40085328 ad:0x40085330 ad:0x40085338 ad:0x40085340 ad:0x40085348 ad:0x40085350 ad:0x40085358 ad:0x40085360 ad:0x40085368 ad:0x40085370 ad:0x40085378)
tree "EV[$1]"
base $2
group.long ($2)++0x7
line.long 0x0 "EV_STATE,SCT event state register 0"
hexmask.long.word 0x0 0.--15. 1. "STATEMSKn,If bit m is one  event n happens in state m of the counter selected by the HEVENT bit (n = event number  m = state number; state 0 = bit 0  state 1= bit 1  etc.). The number of bits = number of states in this SCT."
line.long 0x4 "EV_CTRL,SCT event control register 0"
bitfld.long 0x4 21.--22. "DIRECTION,Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0  the SCT ignores this field. Value 0x3 is reserved." "0: Direction independent. This event is triggered..,1: Counting up. This event is triggered only during..,2: Counting down. This event is triggered only..,?"
bitfld.long 0x4 20. "MATCHMEM,If this bit is one and the COMBMODE field specifies a match component to the triggering of this event  then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when.." "0,1"
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hexmask.long.byte 0x4 15.--19. 1. "STATEV,This value is loaded into or added to the state selected by HEVENT  depending on STATELD  when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero  there is no change to the STATE value."
bitfld.long 0x4 14. "STATELD,This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state." "0: STATEV value is added into STATE (the carry-out..,1: STATEV value is loaded into STATE."
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bitfld.long 0x4 12.--13. "COMBMODE,Selects how the specified match and I/O condition are used and combined." "0: OR. The event occurs when either the specified..,1: MATCH. Uses the specified match only.,2: IO. Uses the specified I/O condition only.,3: AND. The event occurs when the specified match.."
bitfld.long 0x4 10.--11. "IOCOND,Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection  an input must have a minimum pulse width of at least one SCT.." "0: LOW,1: Rise,2: Fall,3: HIGH"
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hexmask.long.byte 0x4 6.--9. 1. "IOSEL,Selects the input or output signal number associated with this event (if any). Do not select an input in this register if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event."
bitfld.long 0x4 5. "OUTSEL,Input/output select" "0: Selects the inputs selected by IOSEL.,1: Selects the outputs selected by IOSEL."
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bitfld.long 0x4 4. "HEVENT,Select L/H counter. Do not set this bit if UNIFY = 1." "0: Selects the L state and the L match register..,1: Selects the H state and the H match register.."
hexmask.long.byte 0x4 0.--3. 1. "MATCHSEL,Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running."
tree.end
repeat.end
repeat 10. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9)(list ad:0x40085500 ad:0x40085508 ad:0x40085510 ad:0x40085518 ad:0x40085520 ad:0x40085528 ad:0x40085530 ad:0x40085538 ad:0x40085540 ad:0x40085548)
tree "OUT[$1]"
base $2
group.long ($2)++0x7
line.long 0x0 "OUT_SET,SCT output 0 set register"
hexmask.long.word 0x0 0.--15. 1. "SET,A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0  output 1 = bit 1  etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode  it is possible to reverse.."
line.long 0x4 "OUT_CLR,SCT output 0 clear register"
hexmask.long.word 0x4 0.--15. 1. "CLR,A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0  event 1 = bit 1  etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode  it is possible to reverse.."
tree.end
repeat.end
endif
group.long 0x200++0x3
line.long 0x0 "CAPCTRL0,SCT capture control register"
hexmask.long.word 0x0 16.--31. 1. "CAPCONn_H,If bit m is one  event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16  event 1 = bit 17  etc.). The number of bits = number of match/captures in this SCT."
hexmask.long.word 0x0 0.--15. 1. "CAPCONn_L,If bit m is one  event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0  event 1 = bit 1  etc.). The number of bits = number of match/captures in this SCT."
group.long 0x200++0x7
line.long 0x0 "MATCHREL0,SCT match reload value register"
hexmask.long.word 0x0 16.--31. 1. "RELOADn_H,When UNIFY = 0  specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1  specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register."
hexmask.long.word 0x0 0.--15. 1. "RELOADn_L,When UNIFY = 0  specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1  specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register."
line.long 0x4 "CAPCTRL1,SCT capture control register"
hexmask.long.word 0x4 16.--31. 1. "CAPCONn_H,If bit m is one  event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16  event 1 = bit 17  etc.). The number of bits = number of match/captures in this SCT."
hexmask.long.word 0x4 0.--15. 1. "CAPCONn_L,If bit m is one  event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0  event 1 = bit 1  etc.). The number of bits = number of match/captures in this SCT."
group.long 0x204++0x7
line.long 0x0 "MATCHREL1,SCT match reload value register"
hexmask.long.word 0x0 16.--31. 1. "RELOADn_H,When UNIFY = 0  specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1  specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register."
hexmask.long.word 0x0 0.--15. 1. "RELOADn_L,When UNIFY = 0  specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1  specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register."
line.long 0x4 "CAPCTRL2,SCT capture control register"
hexmask.long.word 0x4 16.--31. 1. "CAPCONn_H,If bit m is one  event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16  event 1 = bit 17  etc.). The number of bits = number of match/captures in this SCT."
hexmask.long.word 0x4 0.--15. 1. "CAPCONn_L,If bit m is one  event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0  event 1 = bit 1  etc.). The number of bits = number of match/captures in this SCT."
group.long 0x208++0x7
line.long 0x0 "MATCHREL2,SCT match reload value register"
hexmask.long.word 0x0 16.--31. 1. "RELOADn_H,When UNIFY = 0  specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1  specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register."
hexmask.long.word 0x0 0.--15. 1. "RELOADn_L,When UNIFY = 0  specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1  specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register."
line.long 0x4 "CAPCTRL3,SCT capture control register"
hexmask.long.word 0x4 16.--31. 1. "CAPCONn_H,If bit m is one  event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16  event 1 = bit 17  etc.). The number of bits = number of match/captures in this SCT."
hexmask.long.word 0x4 0.--15. 1. "CAPCONn_L,If bit m is one  event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0  event 1 = bit 1  etc.). The number of bits = number of match/captures in this SCT."
group.long 0x20C++0x7
line.long 0x0 "MATCHREL3,SCT match reload value register"
hexmask.long.word 0x0 16.--31. 1. "RELOADn_H,When UNIFY = 0  specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1  specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register."
hexmask.long.word 0x0 0.--15. 1. "RELOADn_L,When UNIFY = 0  specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1  specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register."
line.long 0x4 "CAPCTRL4,SCT capture control register"
hexmask.long.word 0x4 16.--31. 1. "CAPCONn_H,If bit m is one  event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16  event 1 = bit 17  etc.). The number of bits = number of match/captures in this SCT."
hexmask.long.word 0x4 0.--15. 1. "CAPCONn_L,If bit m is one  event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0  event 1 = bit 1  etc.). The number of bits = number of match/captures in this SCT."
group.long 0x210++0x7
line.long 0x0 "MATCHREL4,SCT match reload value register"
hexmask.long.word 0x0 16.--31. 1. "RELOADn_H,When UNIFY = 0  specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1  specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register."
hexmask.long.word 0x0 0.--15. 1. "RELOADn_L,When UNIFY = 0  specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1  specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register."
line.long 0x4 "CAPCTRL5,SCT capture control register"
hexmask.long.word 0x4 16.--31. 1. "CAPCONn_H,If bit m is one  event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16  event 1 = bit 17  etc.). The number of bits = number of match/captures in this SCT."
hexmask.long.word 0x4 0.--15. 1. "CAPCONn_L,If bit m is one  event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0  event 1 = bit 1  etc.). The number of bits = number of match/captures in this SCT."
group.long 0x214++0x7
line.long 0x0 "MATCHREL5,SCT match reload value register"
hexmask.long.word 0x0 16.--31. 1. "RELOADn_H,When UNIFY = 0  specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1  specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register."
hexmask.long.word 0x0 0.--15. 1. "RELOADn_L,When UNIFY = 0  specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1  specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register."
line.long 0x4 "CAPCTRL6,SCT capture control register"
hexmask.long.word 0x4 16.--31. 1. "CAPCONn_H,If bit m is one  event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16  event 1 = bit 17  etc.). The number of bits = number of match/captures in this SCT."
hexmask.long.word 0x4 0.--15. 1. "CAPCONn_L,If bit m is one  event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0  event 1 = bit 1  etc.). The number of bits = number of match/captures in this SCT."
group.long 0x218++0x7
line.long 0x0 "MATCHREL6,SCT match reload value register"
hexmask.long.word 0x0 16.--31. 1. "RELOADn_H,When UNIFY = 0  specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1  specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register."
hexmask.long.word 0x0 0.--15. 1. "RELOADn_L,When UNIFY = 0  specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1  specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register."
line.long 0x4 "CAPCTRL7,SCT capture control register"
hexmask.long.word 0x4 16.--31. 1. "CAPCONn_H,If bit m is one  event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16  event 1 = bit 17  etc.). The number of bits = number of match/captures in this SCT."
hexmask.long.word 0x4 0.--15. 1. "CAPCONn_L,If bit m is one  event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0  event 1 = bit 1  etc.). The number of bits = number of match/captures in this SCT."
group.long 0x21C++0x7
line.long 0x0 "MATCHREL7,SCT match reload value register"
hexmask.long.word 0x0 16.--31. 1. "RELOADn_H,When UNIFY = 0  specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1  specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register."
hexmask.long.word 0x0 0.--15. 1. "RELOADn_L,When UNIFY = 0  specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1  specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register."
line.long 0x4 "CAPCTRL8,SCT capture control register"
hexmask.long.word 0x4 16.--31. 1. "CAPCONn_H,If bit m is one  event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16  event 1 = bit 17  etc.). The number of bits = number of match/captures in this SCT."
hexmask.long.word 0x4 0.--15. 1. "CAPCONn_L,If bit m is one  event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0  event 1 = bit 1  etc.). The number of bits = number of match/captures in this SCT."
group.long 0x220++0x7
line.long 0x0 "MATCHREL8,SCT match reload value register"
hexmask.long.word 0x0 16.--31. 1. "RELOADn_H,When UNIFY = 0  specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1  specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register."
hexmask.long.word 0x0 0.--15. 1. "RELOADn_L,When UNIFY = 0  specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1  specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register."
line.long 0x4 "CAPCTRL9,SCT capture control register"
hexmask.long.word 0x4 16.--31. 1. "CAPCONn_H,If bit m is one  event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16  event 1 = bit 17  etc.). The number of bits = number of match/captures in this SCT."
hexmask.long.word 0x4 0.--15. 1. "CAPCONn_L,If bit m is one  event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0  event 1 = bit 1  etc.). The number of bits = number of match/captures in this SCT."
group.long 0x224++0x3
line.long 0x0 "MATCHREL9,SCT match reload value register"
hexmask.long.word 0x0 16.--31. 1. "RELOADn_H,When UNIFY = 0  specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1  specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register."
hexmask.long.word 0x0 0.--15. 1. "RELOADn_L,When UNIFY = 0  specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1  specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register."
sif (cpuis("LPC54101*"))
repeat 13. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC)(list ad:0x1C018300 ad:0x1C018308 ad:0x1C018310 ad:0x1C018318 ad:0x1C018320 ad:0x1C018328 ad:0x1C018330 ad:0x1C018338 ad:0x1C018340 ad:0x1C018348 ad:0x1C018350 ad:0x1C018358 ad:0x1C018360)
tree "EV[$1]"
base $2
group.long ($2)++0x7
line.long 0x0 "EV_STATE,SCT event state register 0"
hexmask.long.word 0x0 0.--15. 1. "STATEMSKn,If bit m is one  event n happens in state m of the counter selected by the HEVENT bit (n = event number  m = state number; state 0 = bit 0  state 1= bit 1  etc.). The number of bits = number of states in this SCT."
line.long 0x4 "EV_CTRL,SCT event control register 0"
bitfld.long 0x4 21.--22. "DIRECTION,Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0  the SCT ignores this field. Value 0x3 is reserved." "0: Direction independent. This event is triggered..,1: Counting up. This event is triggered only during..,2: Counting down. This event is triggered only..,?"
bitfld.long 0x4 20. "MATCHMEM,If this bit is one and the COMBMODE field specifies a match component to the triggering of this event  then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when.." "0,1"
newline
hexmask.long.byte 0x4 15.--19. 1. "STATEV,This value is loaded into or added to the state selected by HEVENT  depending on STATELD  when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero  there is no change to the STATE value."
bitfld.long 0x4 14. "STATELD,This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state." "0: STATEV value is added into STATE (the carry-out..,1: STATEV value is loaded into STATE."
newline
bitfld.long 0x4 12.--13. "COMBMODE,Selects how the specified match and I/O condition are used and combined." "0: OR. The event occurs when either the specified..,1: MATCH. Uses the specified match only.,2: IO. Uses the specified I/O condition only.,3: AND. The event occurs when the specified match.."
bitfld.long 0x4 10.--11. "IOCOND,Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection  an input must have a minimum pulse width of at least one SCT.." "0: LOW,1: Rise,2: Fall,3: HIGH"
newline
hexmask.long.byte 0x4 6.--9. 1. "IOSEL,Selects the input or output signal number associated with this event (if any). Do not select an input in this register if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event."
bitfld.long 0x4 5. "OUTSEL,Input/output select" "0: Selects the inputs selected by IOSEL.,1: Selects the outputs selected by IOSEL."
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bitfld.long 0x4 4. "HEVENT,Select L/H counter. Do not set this bit if UNIFY = 1." "0: Selects the L state and the L match register..,1: Selects the H state and the H match register.."
hexmask.long.byte 0x4 0.--3. 1. "MATCHSEL,Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running."
tree.end
repeat.end
endif
sif (cpuis("LPC54101*"))
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list ad:0x1C018500 ad:0x1C018508 ad:0x1C018510 ad:0x1C018518 ad:0x1C018520 ad:0x1C018528 ad:0x1C018530 ad:0x1C018538)
tree "OUT[$1]"
base $2
group.long ($2)++0x7
line.long 0x0 "OUT_SET,SCT output 0 set register"
hexmask.long.word 0x0 0.--15. 1. "SET,A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0  output 1 = bit 1  etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode  it is possible to reverse.."
line.long 0x4 "OUT_CLR,SCT output 0 clear register"
hexmask.long.word 0x4 0.--15. 1. "CLR,A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0  event 1 = bit 1  etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode  it is possible to reverse.."
tree.end
repeat.end
endif
sif (cpuis("LPC54102*"))
repeat 13. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC)(list ad:0x1C018300 ad:0x1C018308 ad:0x1C018310 ad:0x1C018318 ad:0x1C018320 ad:0x1C018328 ad:0x1C018330 ad:0x1C018338 ad:0x1C018340 ad:0x1C018348 ad:0x1C018350 ad:0x1C018358 ad:0x1C018360)
tree "EV[$1]"
base $2
group.long ($2)++0x7
line.long 0x0 "EV_STATE,SCT event state register 0"
hexmask.long.word 0x0 0.--15. 1. "STATEMSKn,If bit m is one  event n happens in state m of the counter selected by the HEVENT bit (n = event number  m = state number; state 0 = bit 0  state 1= bit 1  etc.). The number of bits = number of states in this SCT."
line.long 0x4 "EV_CTRL,SCT event control register 0"
bitfld.long 0x4 21.--22. "DIRECTION,Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0  the SCT ignores this field. Value 0x3 is reserved." "0: Direction independent. This event is triggered..,1: Counting up. This event is triggered only during..,2: Counting down. This event is triggered only..,?"
bitfld.long 0x4 20. "MATCHMEM,If this bit is one and the COMBMODE field specifies a match component to the triggering of this event  then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when.." "0,1"
newline
hexmask.long.byte 0x4 15.--19. 1. "STATEV,This value is loaded into or added to the state selected by HEVENT  depending on STATELD  when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero  there is no change to the STATE value."
bitfld.long 0x4 14. "STATELD,This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state." "0: STATEV value is added into STATE (the carry-out..,1: STATEV value is loaded into STATE."
newline
bitfld.long 0x4 12.--13. "COMBMODE,Selects how the specified match and I/O condition are used and combined." "0: OR. The event occurs when either the specified..,1: MATCH. Uses the specified match only.,2: IO. Uses the specified I/O condition only.,3: AND. The event occurs when the specified match.."
bitfld.long 0x4 10.--11. "IOCOND,Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection  an input must have a minimum pulse width of at least one SCT.." "0: LOW,1: Rise,2: Fall,3: HIGH"
newline
hexmask.long.byte 0x4 6.--9. 1. "IOSEL,Selects the input or output signal number associated with this event (if any). Do not select an input in this register if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event."
bitfld.long 0x4 5. "OUTSEL,Input/output select" "0: Selects the inputs selected by IOSEL.,1: Selects the outputs selected by IOSEL."
newline
bitfld.long 0x4 4. "HEVENT,Select L/H counter. Do not set this bit if UNIFY = 1." "0: Selects the L state and the L match register..,1: Selects the H state and the H match register.."
hexmask.long.byte 0x4 0.--3. 1. "MATCHSEL,Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running."
tree.end
repeat.end
endif
sif (cpuis("LPC54102*"))
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list ad:0x1C018500 ad:0x1C018508 ad:0x1C018510 ad:0x1C018518 ad:0x1C018520 ad:0x1C018528 ad:0x1C018530 ad:0x1C018538)
tree "OUT[$1]"
base $2
group.long ($2)++0x7
line.long 0x0 "OUT_SET,SCT output 0 set register"
hexmask.long.word 0x0 0.--15. 1. "SET,A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0  output 1 = bit 1  etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode  it is possible to reverse.."
line.long 0x4 "OUT_CLR,SCT output 0 clear register"
hexmask.long.word 0x4 0.--15. 1. "CLR,A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0  event 1 = bit 1  etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode  it is possible to reverse.."
tree.end
repeat.end
endif
sif (cpuis("LPC54113*"))
repeat 10. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9)(list ad:0x40085300 ad:0x40085308 ad:0x40085310 ad:0x40085318 ad:0x40085320 ad:0x40085328 ad:0x40085330 ad:0x40085338 ad:0x40085340 ad:0x40085348)
tree "EV[$1]"
base $2
group.long ($2)++0x7
line.long 0x0 "EV_STATE,SCT event state register 0"
hexmask.long.word 0x0 0.--15. 1. "STATEMSKn,If bit m is one  event n happens in state m of the counter selected by the HEVENT bit (n = event number  m = state number; state 0 = bit 0  state 1= bit 1  etc.). The number of bits = number of states in this SCT."
line.long 0x4 "EV_CTRL,SCT event control register 0"
bitfld.long 0x4 21.--22. "DIRECTION,Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0  the SCT ignores this field. Value 0x3 is reserved." "0: Direction independent. This event is triggered..,1: Counting up. This event is triggered only during..,2: Counting down. This event is triggered only..,?"
bitfld.long 0x4 20. "MATCHMEM,If this bit is one and the COMBMODE field specifies a match component to the triggering of this event  then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when.." "0,1"
newline
hexmask.long.byte 0x4 15.--19. 1. "STATEV,This value is loaded into or added to the state selected by HEVENT  depending on STATELD  when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero  there is no change to the STATE value."
bitfld.long 0x4 14. "STATELD,This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state." "0: STATEV value is added into STATE (the carry-out..,1: STATEV value is loaded into STATE."
newline
bitfld.long 0x4 12.--13. "COMBMODE,Selects how the specified match and I/O condition are used and combined." "0: OR. The event occurs when either the specified..,1: MATCH. Uses the specified match only.,2: IO. Uses the specified I/O condition only.,3: AND. The event occurs when the specified match.."
bitfld.long 0x4 10.--11. "IOCOND,Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection  an input must have a minimum pulse width of at least one SCT.." "0: LOW,1: Rise,2: Fall,3: HIGH"
newline
hexmask.long.byte 0x4 6.--9. 1. "IOSEL,Selects the input or output signal number associated with this event (if any). Do not select an input in this register if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event."
bitfld.long 0x4 5. "OUTSEL,Input/output select" "0: Selects the inputs selected by IOSEL.,1: Selects the outputs selected by IOSEL."
newline
bitfld.long 0x4 4. "HEVENT,Select L/H counter. Do not set this bit if UNIFY = 1." "0: Selects the L state and the L match register..,1: Selects the H state and the H match register.."
hexmask.long.byte 0x4 0.--3. 1. "MATCHSEL,Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running."
tree.end
repeat.end
endif
sif (cpuis("LPC54113*"))
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list ad:0x40085500 ad:0x40085508 ad:0x40085510 ad:0x40085518 ad:0x40085520 ad:0x40085528 ad:0x40085530 ad:0x40085538)
tree "OUT[$1]"
base $2
group.long ($2)++0x7
line.long 0x0 "OUT_SET,SCT output 0 set register"
hexmask.long.word 0x0 0.--15. 1. "SET,A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0  output 1 = bit 1  etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode  it is possible to reverse.."
line.long 0x4 "OUT_CLR,SCT output 0 clear register"
hexmask.long.word 0x4 0.--15. 1. "CLR,A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0  event 1 = bit 1  etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode  it is possible to reverse.."
tree.end
repeat.end
endif
sif (cpuis("LPC54114*"))
repeat 10. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9)(list ad:0x40085300 ad:0x40085308 ad:0x40085310 ad:0x40085318 ad:0x40085320 ad:0x40085328 ad:0x40085330 ad:0x40085338 ad:0x40085340 ad:0x40085348)
tree "EV[$1]"
base $2
group.long ($2)++0x7
line.long 0x0 "EV_STATE,SCT event state register 0"
hexmask.long.word 0x0 0.--15. 1. "STATEMSKn,If bit m is one  event n happens in state m of the counter selected by the HEVENT bit (n = event number  m = state number; state 0 = bit 0  state 1= bit 1  etc.). The number of bits = number of states in this SCT."
line.long 0x4 "EV_CTRL,SCT event control register 0"
bitfld.long 0x4 21.--22. "DIRECTION,Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0  the SCT ignores this field. Value 0x3 is reserved." "0: Direction independent. This event is triggered..,1: Counting up. This event is triggered only during..,2: Counting down. This event is triggered only..,?"
bitfld.long 0x4 20. "MATCHMEM,If this bit is one and the COMBMODE field specifies a match component to the triggering of this event  then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when.." "0,1"
newline
hexmask.long.byte 0x4 15.--19. 1. "STATEV,This value is loaded into or added to the state selected by HEVENT  depending on STATELD  when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero  there is no change to the STATE value."
bitfld.long 0x4 14. "STATELD,This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state." "0: STATEV value is added into STATE (the carry-out..,1: STATEV value is loaded into STATE."
newline
bitfld.long 0x4 12.--13. "COMBMODE,Selects how the specified match and I/O condition are used and combined." "0: OR. The event occurs when either the specified..,1: MATCH. Uses the specified match only.,2: IO. Uses the specified I/O condition only.,3: AND. The event occurs when the specified match.."
bitfld.long 0x4 10.--11. "IOCOND,Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection  an input must have a minimum pulse width of at least one SCT.." "0: LOW,1: Rise,2: Fall,3: HIGH"
newline
hexmask.long.byte 0x4 6.--9. 1. "IOSEL,Selects the input or output signal number associated with this event (if any). Do not select an input in this register if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event."
bitfld.long 0x4 5. "OUTSEL,Input/output select" "0: Selects the inputs selected by IOSEL.,1: Selects the outputs selected by IOSEL."
newline
bitfld.long 0x4 4. "HEVENT,Select L/H counter. Do not set this bit if UNIFY = 1." "0: Selects the L state and the L match register..,1: Selects the H state and the H match register.."
hexmask.long.byte 0x4 0.--3. 1. "MATCHSEL,Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running."
tree.end
repeat.end
endif
sif (cpuis("LPC54114*"))
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list ad:0x40085500 ad:0x40085508 ad:0x40085510 ad:0x40085518 ad:0x40085520 ad:0x40085528 ad:0x40085530 ad:0x40085538)
tree "OUT[$1]"
base $2
group.long ($2)++0x7
line.long 0x0 "OUT_SET,SCT output 0 set register"
hexmask.long.word 0x0 0.--15. 1. "SET,A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0  output 1 = bit 1  etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode  it is possible to reverse.."
line.long 0x4 "OUT_CLR,SCT output 0 clear register"
hexmask.long.word 0x4 0.--15. 1. "CLR,A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0  event 1 = bit 1  etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode  it is possible to reverse.."
tree.end
repeat.end
endif
sif (cpuis("LPC54605*"))
repeat 10. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9)(list ad:0x40085300 ad:0x40085308 ad:0x40085310 ad:0x40085318 ad:0x40085320 ad:0x40085328 ad:0x40085330 ad:0x40085338 ad:0x40085340 ad:0x40085348)
tree "EV[$1]"
base $2
group.long ($2)++0x7
line.long 0x0 "EV_STATE,SCT event state register 0"
hexmask.long.word 0x0 0.--15. 1. "STATEMSKn,If bit m is one  event n happens in state m of the counter selected by the HEVENT bit (n = event number  m = state number; state 0 = bit 0  state 1= bit 1  etc.). The number of bits = number of states in this SCT."
line.long 0x4 "EV_CTRL,SCT event control register 0"
bitfld.long 0x4 21.--22. "DIRECTION,Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0  the SCT ignores this field. Value 0x3 is reserved." "0: Direction independent. This event is triggered..,1: Counting up. This event is triggered only during..,2: Counting down. This event is triggered only..,?"
bitfld.long 0x4 20. "MATCHMEM,If this bit is one and the COMBMODE field specifies a match component to the triggering of this event  then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when.." "0,1"
newline
hexmask.long.byte 0x4 15.--19. 1. "STATEV,This value is loaded into or added to the state selected by HEVENT  depending on STATELD  when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero  there is no change to the STATE value."
bitfld.long 0x4 14. "STATELD,This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state." "0: STATEV value is added into STATE (the carry-out..,1: STATEV value is loaded into STATE."
newline
bitfld.long 0x4 12.--13. "COMBMODE,Selects how the specified match and I/O condition are used and combined." "0: OR. The event occurs when either the specified..,1: MATCH. Uses the specified match only.,2: IO. Uses the specified I/O condition only.,3: AND. The event occurs when the specified match.."
bitfld.long 0x4 10.--11. "IOCOND,Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection  an input must have a minimum pulse width of at least one SCT.." "0: LOW,1: Rise,2: Fall,3: HIGH"
newline
hexmask.long.byte 0x4 6.--9. 1. "IOSEL,Selects the input or output signal number associated with this event (if any). Do not select an input in this register if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event."
bitfld.long 0x4 5. "OUTSEL,Input/output select" "0: Selects the inputs selected by IOSEL.,1: Selects the outputs selected by IOSEL."
newline
bitfld.long 0x4 4. "HEVENT,Select L/H counter. Do not set this bit if UNIFY = 1." "0: Selects the L state and the L match register..,1: Selects the H state and the H match register.."
hexmask.long.byte 0x4 0.--3. 1. "MATCHSEL,Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running."
tree.end
repeat.end
endif
sif (cpuis("LPC54605*"))
repeat 10. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9)(list ad:0x40085500 ad:0x40085508 ad:0x40085510 ad:0x40085518 ad:0x40085520 ad:0x40085528 ad:0x40085530 ad:0x40085538 ad:0x40085540 ad:0x40085548)
tree "OUT[$1]"
base $2
group.long ($2)++0x7
line.long 0x0 "OUT_SET,SCT output 0 set register"
hexmask.long.word 0x0 0.--15. 1. "SET,A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0  output 1 = bit 1  etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode  it is possible to reverse.."
line.long 0x4 "OUT_CLR,SCT output 0 clear register"
hexmask.long.word 0x4 0.--15. 1. "CLR,A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0  event 1 = bit 1  etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode  it is possible to reverse.."
tree.end
repeat.end
endif
sif (cpuis("LPC54606*"))
repeat 10. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9)(list ad:0x40085300 ad:0x40085308 ad:0x40085310 ad:0x40085318 ad:0x40085320 ad:0x40085328 ad:0x40085330 ad:0x40085338 ad:0x40085340 ad:0x40085348)
tree "EV[$1]"
base $2
group.long ($2)++0x7
line.long 0x0 "EV_STATE,SCT event state register 0"
hexmask.long.word 0x0 0.--15. 1. "STATEMSKn,If bit m is one  event n happens in state m of the counter selected by the HEVENT bit (n = event number  m = state number; state 0 = bit 0  state 1= bit 1  etc.). The number of bits = number of states in this SCT."
line.long 0x4 "EV_CTRL,SCT event control register 0"
bitfld.long 0x4 21.--22. "DIRECTION,Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0  the SCT ignores this field. Value 0x3 is reserved." "0: Direction independent. This event is triggered..,1: Counting up. This event is triggered only during..,2: Counting down. This event is triggered only..,?"
bitfld.long 0x4 20. "MATCHMEM,If this bit is one and the COMBMODE field specifies a match component to the triggering of this event  then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when.." "0,1"
newline
hexmask.long.byte 0x4 15.--19. 1. "STATEV,This value is loaded into or added to the state selected by HEVENT  depending on STATELD  when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero  there is no change to the STATE value."
bitfld.long 0x4 14. "STATELD,This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state." "0: STATEV value is added into STATE (the carry-out..,1: STATEV value is loaded into STATE."
newline
bitfld.long 0x4 12.--13. "COMBMODE,Selects how the specified match and I/O condition are used and combined." "0: OR. The event occurs when either the specified..,1: MATCH. Uses the specified match only.,2: IO. Uses the specified I/O condition only.,3: AND. The event occurs when the specified match.."
bitfld.long 0x4 10.--11. "IOCOND,Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection  an input must have a minimum pulse width of at least one SCT.." "0: LOW,1: Rise,2: Fall,3: HIGH"
newline
hexmask.long.byte 0x4 6.--9. 1. "IOSEL,Selects the input or output signal number associated with this event (if any). Do not select an input in this register if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event."
bitfld.long 0x4 5. "OUTSEL,Input/output select" "0: Selects the inputs selected by IOSEL.,1: Selects the outputs selected by IOSEL."
newline
bitfld.long 0x4 4. "HEVENT,Select L/H counter. Do not set this bit if UNIFY = 1." "0: Selects the L state and the L match register..,1: Selects the H state and the H match register.."
hexmask.long.byte 0x4 0.--3. 1. "MATCHSEL,Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running."
tree.end
repeat.end
endif
sif (cpuis("LPC54606*"))
repeat 10. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9)(list ad:0x40085500 ad:0x40085508 ad:0x40085510 ad:0x40085518 ad:0x40085520 ad:0x40085528 ad:0x40085530 ad:0x40085538 ad:0x40085540 ad:0x40085548)
tree "OUT[$1]"
base $2
group.long ($2)++0x7
line.long 0x0 "OUT_SET,SCT output 0 set register"
hexmask.long.word 0x0 0.--15. 1. "SET,A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0  output 1 = bit 1  etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode  it is possible to reverse.."
line.long 0x4 "OUT_CLR,SCT output 0 clear register"
hexmask.long.word 0x4 0.--15. 1. "CLR,A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0  event 1 = bit 1  etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode  it is possible to reverse.."
tree.end
repeat.end
endif
sif (cpuis("LPC54607*"))
repeat 10. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9)(list ad:0x40085300 ad:0x40085308 ad:0x40085310 ad:0x40085318 ad:0x40085320 ad:0x40085328 ad:0x40085330 ad:0x40085338 ad:0x40085340 ad:0x40085348)
tree "EV[$1]"
base $2
group.long ($2)++0x7
line.long 0x0 "EV_STATE,SCT event state register 0"
hexmask.long.word 0x0 0.--15. 1. "STATEMSKn,If bit m is one  event n happens in state m of the counter selected by the HEVENT bit (n = event number  m = state number; state 0 = bit 0  state 1= bit 1  etc.). The number of bits = number of states in this SCT."
line.long 0x4 "EV_CTRL,SCT event control register 0"
bitfld.long 0x4 21.--22. "DIRECTION,Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0  the SCT ignores this field. Value 0x3 is reserved." "0: Direction independent. This event is triggered..,1: Counting up. This event is triggered only during..,2: Counting down. This event is triggered only..,?"
bitfld.long 0x4 20. "MATCHMEM,If this bit is one and the COMBMODE field specifies a match component to the triggering of this event  then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when.." "0,1"
newline
hexmask.long.byte 0x4 15.--19. 1. "STATEV,This value is loaded into or added to the state selected by HEVENT  depending on STATELD  when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero  there is no change to the STATE value."
bitfld.long 0x4 14. "STATELD,This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state." "0: STATEV value is added into STATE (the carry-out..,1: STATEV value is loaded into STATE."
newline
bitfld.long 0x4 12.--13. "COMBMODE,Selects how the specified match and I/O condition are used and combined." "0: OR. The event occurs when either the specified..,1: MATCH. Uses the specified match only.,2: IO. Uses the specified I/O condition only.,3: AND. The event occurs when the specified match.."
bitfld.long 0x4 10.--11. "IOCOND,Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection  an input must have a minimum pulse width of at least one SCT.." "0: LOW,1: Rise,2: Fall,3: HIGH"
newline
hexmask.long.byte 0x4 6.--9. 1. "IOSEL,Selects the input or output signal number associated with this event (if any). Do not select an input in this register if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event."
bitfld.long 0x4 5. "OUTSEL,Input/output select" "0: Selects the inputs selected by IOSEL.,1: Selects the outputs selected by IOSEL."
newline
bitfld.long 0x4 4. "HEVENT,Select L/H counter. Do not set this bit if UNIFY = 1." "0: Selects the L state and the L match register..,1: Selects the H state and the H match register.."
hexmask.long.byte 0x4 0.--3. 1. "MATCHSEL,Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running."
tree.end
repeat.end
endif
sif (cpuis("LPC54607*"))
repeat 10. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9)(list ad:0x40085500 ad:0x40085508 ad:0x40085510 ad:0x40085518 ad:0x40085520 ad:0x40085528 ad:0x40085530 ad:0x40085538 ad:0x40085540 ad:0x40085548)
tree "OUT[$1]"
base $2
group.long ($2)++0x7
line.long 0x0 "OUT_SET,SCT output 0 set register"
hexmask.long.word 0x0 0.--15. 1. "SET,A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0  output 1 = bit 1  etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode  it is possible to reverse.."
line.long 0x4 "OUT_CLR,SCT output 0 clear register"
hexmask.long.word 0x4 0.--15. 1. "CLR,A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0  event 1 = bit 1  etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode  it is possible to reverse.."
tree.end
repeat.end
endif
sif (cpuis("LPC54608*"))
repeat 10. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9)(list ad:0x40085300 ad:0x40085308 ad:0x40085310 ad:0x40085318 ad:0x40085320 ad:0x40085328 ad:0x40085330 ad:0x40085338 ad:0x40085340 ad:0x40085348)
tree "EV[$1]"
base $2
group.long ($2)++0x7
line.long 0x0 "EV_STATE,SCT event state register 0"
hexmask.long.word 0x0 0.--15. 1. "STATEMSKn,If bit m is one  event n happens in state m of the counter selected by the HEVENT bit (n = event number  m = state number; state 0 = bit 0  state 1= bit 1  etc.). The number of bits = number of states in this SCT."
line.long 0x4 "EV_CTRL,SCT event control register 0"
bitfld.long 0x4 21.--22. "DIRECTION,Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0  the SCT ignores this field. Value 0x3 is reserved." "0: Direction independent. This event is triggered..,1: Counting up. This event is triggered only during..,2: Counting down. This event is triggered only..,?"
bitfld.long 0x4 20. "MATCHMEM,If this bit is one and the COMBMODE field specifies a match component to the triggering of this event  then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when.." "0,1"
newline
hexmask.long.byte 0x4 15.--19. 1. "STATEV,This value is loaded into or added to the state selected by HEVENT  depending on STATELD  when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero  there is no change to the STATE value."
bitfld.long 0x4 14. "STATELD,This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state." "0: STATEV value is added into STATE (the carry-out..,1: STATEV value is loaded into STATE."
newline
bitfld.long 0x4 12.--13. "COMBMODE,Selects how the specified match and I/O condition are used and combined." "0: OR. The event occurs when either the specified..,1: MATCH. Uses the specified match only.,2: IO. Uses the specified I/O condition only.,3: AND. The event occurs when the specified match.."
bitfld.long 0x4 10.--11. "IOCOND,Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection  an input must have a minimum pulse width of at least one SCT.." "0: LOW,1: Rise,2: Fall,3: HIGH"
newline
hexmask.long.byte 0x4 6.--9. 1. "IOSEL,Selects the input or output signal number associated with this event (if any). Do not select an input in this register if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event."
bitfld.long 0x4 5. "OUTSEL,Input/output select" "0: Selects the inputs selected by IOSEL.,1: Selects the outputs selected by IOSEL."
newline
bitfld.long 0x4 4. "HEVENT,Select L/H counter. Do not set this bit if UNIFY = 1." "0: Selects the L state and the L match register..,1: Selects the H state and the H match register.."
hexmask.long.byte 0x4 0.--3. 1. "MATCHSEL,Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running."
tree.end
repeat.end
endif
sif (cpuis("LPC54608*"))
repeat 10. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9)(list ad:0x40085500 ad:0x40085508 ad:0x40085510 ad:0x40085518 ad:0x40085520 ad:0x40085528 ad:0x40085530 ad:0x40085538 ad:0x40085540 ad:0x40085548)
tree "OUT[$1]"
base $2
group.long ($2)++0x7
line.long 0x0 "OUT_SET,SCT output 0 set register"
hexmask.long.word 0x0 0.--15. 1. "SET,A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0  output 1 = bit 1  etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode  it is possible to reverse.."
line.long 0x4 "OUT_CLR,SCT output 0 clear register"
hexmask.long.word 0x4 0.--15. 1. "CLR,A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0  event 1 = bit 1  etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode  it is possible to reverse.."
tree.end
repeat.end
endif
sif (cpuis("LPC54616*"))
repeat 10. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9)(list ad:0x40085300 ad:0x40085308 ad:0x40085310 ad:0x40085318 ad:0x40085320 ad:0x40085328 ad:0x40085330 ad:0x40085338 ad:0x40085340 ad:0x40085348)
tree "EV[$1]"
base $2
group.long ($2)++0x7
line.long 0x0 "EV_STATE,SCT event state register 0"
hexmask.long.word 0x0 0.--15. 1. "STATEMSKn,If bit m is one  event n happens in state m of the counter selected by the HEVENT bit (n = event number  m = state number; state 0 = bit 0  state 1= bit 1  etc.). The number of bits = number of states in this SCT."
line.long 0x4 "EV_CTRL,SCT event control register 0"
bitfld.long 0x4 21.--22. "DIRECTION,Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0  the SCT ignores this field. Value 0x3 is reserved." "0: Direction independent. This event is triggered..,1: Counting up. This event is triggered only during..,2: Counting down. This event is triggered only..,?"
bitfld.long 0x4 20. "MATCHMEM,If this bit is one and the COMBMODE field specifies a match component to the triggering of this event  then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when.." "0,1"
newline
hexmask.long.byte 0x4 15.--19. 1. "STATEV,This value is loaded into or added to the state selected by HEVENT  depending on STATELD  when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero  there is no change to the STATE value."
bitfld.long 0x4 14. "STATELD,This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state." "0: STATEV value is added into STATE (the carry-out..,1: STATEV value is loaded into STATE."
newline
bitfld.long 0x4 12.--13. "COMBMODE,Selects how the specified match and I/O condition are used and combined." "0: OR. The event occurs when either the specified..,1: MATCH. Uses the specified match only.,2: IO. Uses the specified I/O condition only.,3: AND. The event occurs when the specified match.."
bitfld.long 0x4 10.--11. "IOCOND,Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection  an input must have a minimum pulse width of at least one SCT.." "0: LOW,1: Rise,2: Fall,3: HIGH"
newline
hexmask.long.byte 0x4 6.--9. 1. "IOSEL,Selects the input or output signal number associated with this event (if any). Do not select an input in this register if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event."
bitfld.long 0x4 5. "OUTSEL,Input/output select" "0: Selects the inputs selected by IOSEL.,1: Selects the outputs selected by IOSEL."
newline
bitfld.long 0x4 4. "HEVENT,Select L/H counter. Do not set this bit if UNIFY = 1." "0: Selects the L state and the L match register..,1: Selects the H state and the H match register.."
hexmask.long.byte 0x4 0.--3. 1. "MATCHSEL,Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running."
tree.end
repeat.end
endif
sif (cpuis("LPC54616*"))
repeat 10. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9)(list ad:0x40085500 ad:0x40085508 ad:0x40085510 ad:0x40085518 ad:0x40085520 ad:0x40085528 ad:0x40085530 ad:0x40085538 ad:0x40085540 ad:0x40085548)
tree "OUT[$1]"
base $2
group.long ($2)++0x7
line.long 0x0 "OUT_SET,SCT output 0 set register"
hexmask.long.word 0x0 0.--15. 1. "SET,A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0  output 1 = bit 1  etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode  it is possible to reverse.."
line.long 0x4 "OUT_CLR,SCT output 0 clear register"
hexmask.long.word 0x4 0.--15. 1. "CLR,A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0  event 1 = bit 1  etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode  it is possible to reverse.."
tree.end
repeat.end
endif
sif (cpuis("LPC54618*"))
repeat 10. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9)(list ad:0x40085300 ad:0x40085308 ad:0x40085310 ad:0x40085318 ad:0x40085320 ad:0x40085328 ad:0x40085330 ad:0x40085338 ad:0x40085340 ad:0x40085348)
tree "EV[$1]"
base $2
group.long ($2)++0x7
line.long 0x0 "EV_STATE,SCT event state register 0"
hexmask.long.word 0x0 0.--15. 1. "STATEMSKn,If bit m is one  event n happens in state m of the counter selected by the HEVENT bit (n = event number  m = state number; state 0 = bit 0  state 1= bit 1  etc.). The number of bits = number of states in this SCT."
line.long 0x4 "EV_CTRL,SCT event control register 0"
bitfld.long 0x4 21.--22. "DIRECTION,Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0  the SCT ignores this field. Value 0x3 is reserved." "0: Direction independent. This event is triggered..,1: Counting up. This event is triggered only during..,2: Counting down. This event is triggered only..,?"
bitfld.long 0x4 20. "MATCHMEM,If this bit is one and the COMBMODE field specifies a match component to the triggering of this event  then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when.." "0,1"
newline
hexmask.long.byte 0x4 15.--19. 1. "STATEV,This value is loaded into or added to the state selected by HEVENT  depending on STATELD  when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero  there is no change to the STATE value."
bitfld.long 0x4 14. "STATELD,This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state." "0: STATEV value is added into STATE (the carry-out..,1: STATEV value is loaded into STATE."
newline
bitfld.long 0x4 12.--13. "COMBMODE,Selects how the specified match and I/O condition are used and combined." "0: OR. The event occurs when either the specified..,1: MATCH. Uses the specified match only.,2: IO. Uses the specified I/O condition only.,3: AND. The event occurs when the specified match.."
bitfld.long 0x4 10.--11. "IOCOND,Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection  an input must have a minimum pulse width of at least one SCT.." "0: LOW,1: Rise,2: Fall,3: HIGH"
newline
hexmask.long.byte 0x4 6.--9. 1. "IOSEL,Selects the input or output signal number associated with this event (if any). Do not select an input in this register if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event."
bitfld.long 0x4 5. "OUTSEL,Input/output select" "0: Selects the inputs selected by IOSEL.,1: Selects the outputs selected by IOSEL."
newline
bitfld.long 0x4 4. "HEVENT,Select L/H counter. Do not set this bit if UNIFY = 1." "0: Selects the L state and the L match register..,1: Selects the H state and the H match register.."
hexmask.long.byte 0x4 0.--3. 1. "MATCHSEL,Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running."
tree.end
repeat.end
endif
sif (cpuis("LPC54618*"))
repeat 10. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9)(list ad:0x40085500 ad:0x40085508 ad:0x40085510 ad:0x40085518 ad:0x40085520 ad:0x40085528 ad:0x40085530 ad:0x40085538 ad:0x40085540 ad:0x40085548)
tree "OUT[$1]"
base $2
group.long ($2)++0x7
line.long 0x0 "OUT_SET,SCT output 0 set register"
hexmask.long.word 0x0 0.--15. 1. "SET,A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0  output 1 = bit 1  etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode  it is possible to reverse.."
line.long 0x4 "OUT_CLR,SCT output 0 clear register"
hexmask.long.word 0x4 0.--15. 1. "CLR,A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0  event 1 = bit 1  etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode  it is possible to reverse.."
tree.end
repeat.end
endif
sif (cpuis("LPC54628*"))
repeat 10. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9)(list ad:0x40085300 ad:0x40085308 ad:0x40085310 ad:0x40085318 ad:0x40085320 ad:0x40085328 ad:0x40085330 ad:0x40085338 ad:0x40085340 ad:0x40085348)
tree "EV[$1]"
base $2
group.long ($2)++0x7
line.long 0x0 "EV_STATE,SCT event state register 0"
hexmask.long.word 0x0 0.--15. 1. "STATEMSKn,If bit m is one  event n happens in state m of the counter selected by the HEVENT bit (n = event number  m = state number; state 0 = bit 0  state 1= bit 1  etc.). The number of bits = number of states in this SCT."
line.long 0x4 "EV_CTRL,SCT event control register 0"
bitfld.long 0x4 21.--22. "DIRECTION,Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0  the SCT ignores this field. Value 0x3 is reserved." "0: Direction independent. This event is triggered..,1: Counting up. This event is triggered only during..,2: Counting down. This event is triggered only..,?"
bitfld.long 0x4 20. "MATCHMEM,If this bit is one and the COMBMODE field specifies a match component to the triggering of this event  then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when.." "0,1"
newline
hexmask.long.byte 0x4 15.--19. 1. "STATEV,This value is loaded into or added to the state selected by HEVENT  depending on STATELD  when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero  there is no change to the STATE value."
bitfld.long 0x4 14. "STATELD,This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state." "0: STATEV value is added into STATE (the carry-out..,1: STATEV value is loaded into STATE."
newline
bitfld.long 0x4 12.--13. "COMBMODE,Selects how the specified match and I/O condition are used and combined." "0: OR. The event occurs when either the specified..,1: MATCH. Uses the specified match only.,2: IO. Uses the specified I/O condition only.,3: AND. The event occurs when the specified match.."
bitfld.long 0x4 10.--11. "IOCOND,Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection  an input must have a minimum pulse width of at least one SCT.." "0: LOW,1: Rise,2: Fall,3: HIGH"
newline
hexmask.long.byte 0x4 6.--9. 1. "IOSEL,Selects the input or output signal number associated with this event (if any). Do not select an input in this register if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event."
bitfld.long 0x4 5. "OUTSEL,Input/output select" "0: Selects the inputs selected by IOSEL.,1: Selects the outputs selected by IOSEL."
newline
bitfld.long 0x4 4. "HEVENT,Select L/H counter. Do not set this bit if UNIFY = 1." "0: Selects the L state and the L match register..,1: Selects the H state and the H match register.."
hexmask.long.byte 0x4 0.--3. 1. "MATCHSEL,Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running."
tree.end
repeat.end
endif
sif (cpuis("LPC54628*"))
repeat 10. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9)(list ad:0x40085500 ad:0x40085508 ad:0x40085510 ad:0x40085518 ad:0x40085520 ad:0x40085528 ad:0x40085530 ad:0x40085538 ad:0x40085540 ad:0x40085548)
tree "OUT[$1]"
base $2
group.long ($2)++0x7
line.long 0x0 "OUT_SET,SCT output 0 set register"
hexmask.long.word 0x0 0.--15. 1. "SET,A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0  output 1 = bit 1  etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode  it is possible to reverse.."
line.long 0x4 "OUT_CLR,SCT output 0 clear register"
hexmask.long.word 0x4 0.--15. 1. "CLR,A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0  event 1 = bit 1  etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode  it is possible to reverse.."
tree.end
repeat.end
endif
tree.end
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54605*")||cpuis("LPC54606*")||cpuis("LPC54607*")||cpuis("LPC54608*")||cpuis("LPC54616*")||cpuis("LPC54618*")||cpuis("LPC54628*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
tree "SDIF (SDMMC)"
base ad:0x4009B000
group.long 0x0++0xB
line.long 0x0 "CTRL,Control register"
bitfld.long 0x0 25. "USE_INTERNAL_DMAC,SD/MMC DMA use." "0,1"
bitfld.long 0x0 18. "CARD_VOLTAGE_A2,Controls the state of the SD_VOLT2 pin." "0,1"
bitfld.long 0x0 17. "CARD_VOLTAGE_A1,Controls the state of the SD_VOLT1 pin." "0,1"
newline
bitfld.long 0x0 16. "CARD_VOLTAGE_A0,Controls the state of the SD_VOLT0 pin." "0,1"
bitfld.long 0x0 11. "CEATA_DEVICE_INTERRUPT_STATUS,CEATA device interrupt status." "0,1"
bitfld.long 0x0 10. "SEND_AUTO_STOP_CCSD,Send auto stop ccsd." "0,1"
newline
bitfld.long 0x0 9. "SEND_CCSD,Send ccsd." "0,1"
bitfld.long 0x0 8. "ABORT_READ_DATA,Abort read data." "0,1"
bitfld.long 0x0 7. "SEND_IRQ_RESPONSE,Send irq response." "0,1"
newline
bitfld.long 0x0 6. "READ_WAIT,Read/wait." "0,1"
bitfld.long 0x0 4. "INT_ENABLE,Global interrupt enable/disable bit." "0,1"
bitfld.long 0x0 2. "DMA_RESET,DMA reset." "0,1"
newline
bitfld.long 0x0 1. "FIFO_RESET,Fifo reset." "0,1"
bitfld.long 0x0 0. "CONTROLLER_RESET,Controller reset." "0,1"
line.long 0x4 "PWREN,Power Enable register"
bitfld.long 0x4 0. "POWER_ENABLE,Power on/off switch for card; once power is turned on  software should wait for regulator/switch ramp-up time before trying to initialize card." "0,1"
line.long 0x8 "CLKDIV,Clock Divider register"
hexmask.long.byte 0x8 0.--7. 1. "CLK_DIVIDER0,Clock divider-0 value."
group.long 0x10++0x1F
line.long 0x0 "CLKENA,Clock Enable register"
bitfld.long 0x0 16. "CCLK_LOW_POWER,Low-power control for SD card clock." "0,1"
bitfld.long 0x0 0. "CCLK_ENABLE,Clock-enable control for SD card clock." "0,1"
line.long 0x4 "TMOUT,Time-out register"
hexmask.long.tbyte 0x4 8.--31. 1. "DATA_TIMEOUT,Value for card Data Read time-out; same value also used for Data Starvation by Host time-out."
hexmask.long.byte 0x4 0.--7. 1. "RESPONSE_TIMEOUT,Response time-out value."
line.long 0x8 "CTYPE,Card Type register"
bitfld.long 0x8 16. "CARD_WIDTH1,Indicates if card is 8-bit: 0 - Non 8-bit mode 1 - 8-bit mode." "0,1"
bitfld.long 0x8 0. "CARD_WIDTH0,Indicates if card is 1-bit or 4-bit: 0 - 1-bit mode 1 - 4-bit mode 1 and 4-bit modes only work when 8-bit mode in CARD_WIDTH1 is not enabled (bit 16 in this register is set to 0)." "0,1"
line.long 0xC "BLKSIZ,Block Size register"
hexmask.long.word 0xC 0.--15. 1. "BLOCK_SIZE,Block size."
line.long 0x10 "BYTCNT,Byte Count register"
hexmask.long 0x10 0.--31. 1. "BYTE_COUNT,Number of bytes to be transferred; should be integer multiple of Block Size for block transfers."
line.long 0x14 "INTMASK,Interrupt Mask register"
bitfld.long 0x14 16. "SDIO_INT_MASK,Mask SDIO interrupt." "0,1"
bitfld.long 0x14 15. "EBE,End-bit error (read)/Write no CRC." "0,1"
bitfld.long 0x14 14. "ACD,Auto command done." "0,1"
newline
bitfld.long 0x14 13. "SBE,Start-bit error." "0,1"
bitfld.long 0x14 12. "HLE,Hardware locked write error." "0,1"
bitfld.long 0x14 11. "FRUN,FIFO underrun/overrun error." "0,1"
newline
bitfld.long 0x14 10. "HTO,Data starvation-by-host time-out (HTO)." "0,1"
bitfld.long 0x14 9. "DRTO,Data read time-out." "0,1"
bitfld.long 0x14 8. "RTO,Response time-out." "0,1"
newline
bitfld.long 0x14 7. "DCRC,Data CRC error." "0,1"
bitfld.long 0x14 6. "RCRC,Response CRC error." "0,1"
bitfld.long 0x14 5. "RXDR,Receive FIFO data request." "0,1"
newline
bitfld.long 0x14 4. "TXDR,Transmit FIFO data request." "0,1"
bitfld.long 0x14 3. "DTO,Data transfer over." "0,1"
bitfld.long 0x14 2. "CDONE,Command done." "0,1"
newline
bitfld.long 0x14 1. "RE,Response error." "0,1"
bitfld.long 0x14 0. "CDET,Card detect." "0,1"
line.long 0x18 "CMDARG,Command Argument register"
hexmask.long 0x18 0.--31. 1. "CMD_ARG,Value indicates command argument to be passed to card."
line.long 0x1C "CMD,Command register"
bitfld.long 0x1C 31. "START_CMD,Start command." "0,1"
bitfld.long 0x1C 29. "USE_HOLD_REG,Use Hold Register." "0,1"
bitfld.long 0x1C 28. "VOLT_SWITCH,Voltage switch bit." "0,1"
newline
bitfld.long 0x1C 27. "BOOT_MODE,Boot Mode." "0,1"
bitfld.long 0x1C 26. "DISABLE_BOOT,Disable Boot." "0,1"
bitfld.long 0x1C 25. "EXPECT_BOOT_ACK,Expect Boot Acknowledge." "0,1"
newline
bitfld.long 0x1C 24. "ENABLE_BOOT,Enable Boot - this bit should be set only for mandatory boot mode." "0,1"
bitfld.long 0x1C 23. "CCS_EXPECTED,CCS expected." "0,1"
bitfld.long 0x1C 22. "READ_CEATA_DEVICE,Read ceata device." "0,1"
newline
bitfld.long 0x1C 21. "UPDATE_CLOCK_REGISTERS_ONLY,Update clock registers only." "0,1"
bitfld.long 0x1C 15. "SEND_INITIALIZATION,Send initialization." "0,1"
bitfld.long 0x1C 14. "STOP_ABORT_CMD,Stop abort command." "0,1"
newline
bitfld.long 0x1C 13. "WAIT_PRVDATA_COMPLETE,Wait prvdata complete." "0,1"
bitfld.long 0x1C 12. "SEND_AUTO_STOP,Send auto stop." "0,1"
bitfld.long 0x1C 11. "TRANSFER_MODE,Transfer mode." "0,1"
newline
bitfld.long 0x1C 10. "READ_WRITE,read/write." "0,1"
bitfld.long 0x1C 9. "DATA_EXPECTED,Data expected." "0,1"
bitfld.long 0x1C 8. "CHECK_RESPONSE_CRC,Check response CRC." "0,1"
newline
bitfld.long 0x1C 7. "RESPONSE_LENGTH,Response length." "0,1"
bitfld.long 0x1C 6. "RESPONSE_EXPECT,Response expect." "0,1"
hexmask.long.byte 0x1C 0.--5. 1. "CMD_INDEX,Command index."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x30)++0x3
line.long 0x0 "RESP[$1],Response register"
hexmask.long 0x0 0.--31. 1. "RESPONSE,Bits of response."
repeat.end
group.long 0x40++0x7
line.long 0x0 "MINTSTS,Masked Interrupt Status register"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
rbitfld.long 0x0 16. "SDIO_INTERRUPT,Interrupt from SDIO card." "0,1"
rbitfld.long 0x0 15. "EBE,End-bit error (read)/write no CRC." "0,1"
rbitfld.long 0x0 14. "ACD,Auto command done." "0,1"
newline
rbitfld.long 0x0 13. "SBE,Start-bit error." "0,1"
rbitfld.long 0x0 12. "HLE,Hardware locked write error." "0,1"
rbitfld.long 0x0 11. "FRUN,FIFO underrun/overrun error." "0,1"
newline
rbitfld.long 0x0 10. "HTO,Data starvation-by-host time-out (HTO)." "0,1"
rbitfld.long 0x0 9. "DRTO,Data read time-out." "0,1"
rbitfld.long 0x0 8. "RTO,Response time-out." "0,1"
newline
rbitfld.long 0x0 7. "DCRC,Data CRC error." "0,1"
rbitfld.long 0x0 6. "RCRC,Response CRC error." "0,1"
rbitfld.long 0x0 5. "RXDR,Receive FIFO data request." "0,1"
newline
rbitfld.long 0x0 4. "TXDR,Transmit FIFO data request." "0,1"
rbitfld.long 0x0 3. "DTO,Data transfer over." "0,1"
rbitfld.long 0x0 2. "CDONE,Command done." "0,1"
newline
rbitfld.long 0x0 1. "RE,Response error." "0,1"
rbitfld.long 0x0 0. "CDET,Card detect." "0,1"
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x0 16. "SDIO_INTERRUPT,Interrupt from SDIO card." "0,1"
newline
bitfld.long 0x0 15. "EBE,End-bit error (read)/write no CRC." "0,1"
bitfld.long 0x0 14. "ACD,Auto command done." "0,1"
bitfld.long 0x0 13. "SBE,Start-bit error." "0,1"
newline
bitfld.long 0x0 12. "HLE,Hardware locked write error." "0,1"
bitfld.long 0x0 11. "FRUN,FIFO underrun/overrun error." "0,1"
bitfld.long 0x0 10. "HTO,Data starvation-by-host time-out (HTO)." "0,1"
newline
bitfld.long 0x0 9. "DRTO,Data read time-out." "0,1"
bitfld.long 0x0 8. "RTO,Response time-out." "0,1"
bitfld.long 0x0 7. "DCRC,Data CRC error." "0,1"
newline
bitfld.long 0x0 6. "RCRC,Response CRC error." "0,1"
bitfld.long 0x0 5. "RXDR,Receive FIFO data request." "0,1"
bitfld.long 0x0 4. "TXDR,Transmit FIFO data request." "0,1"
newline
bitfld.long 0x0 3. "DTO,Data transfer over." "0,1"
bitfld.long 0x0 2. "CDONE,Command done." "0,1"
bitfld.long 0x0 1. "RE,Response error." "0,1"
newline
bitfld.long 0x0 0. "CDET,Card detect." "0,1"
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x0 16. "SDIO_INTERRUPT,Interrupt from SDIO card." "0,1"
bitfld.long 0x0 15. "EBE,End-bit error (read)/write no CRC." "0,1"
newline
bitfld.long 0x0 14. "ACD,Auto command done." "0,1"
bitfld.long 0x0 13. "SBE,Start-bit error." "0,1"
bitfld.long 0x0 12. "HLE,Hardware locked write error." "0,1"
newline
bitfld.long 0x0 11. "FRUN,FIFO underrun/overrun error." "0,1"
bitfld.long 0x0 10. "HTO,Data starvation-by-host time-out (HTO)." "0,1"
bitfld.long 0x0 9. "DRTO,Data read time-out." "0,1"
newline
bitfld.long 0x0 8. "RTO,Response time-out." "0,1"
bitfld.long 0x0 7. "DCRC,Data CRC error." "0,1"
bitfld.long 0x0 6. "RCRC,Response CRC error." "0,1"
newline
bitfld.long 0x0 5. "RXDR,Receive FIFO data request." "0,1"
bitfld.long 0x0 4. "TXDR,Transmit FIFO data request." "0,1"
bitfld.long 0x0 3. "DTO,Data transfer over." "0,1"
newline
bitfld.long 0x0 2. "CDONE,Command done." "0,1"
bitfld.long 0x0 1. "RE,Response error." "0,1"
bitfld.long 0x0 0. "CDET,Card detect." "0,1"
newline
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x0 16. "SDIO_INTERRUPT,Interrupt from SDIO card." "0,1"
bitfld.long 0x0 15. "EBE,End-bit error (read)/write no CRC." "0,1"
bitfld.long 0x0 14. "ACD,Auto command done." "0,1"
newline
bitfld.long 0x0 13. "SBE,Start-bit error." "0,1"
bitfld.long 0x0 12. "HLE,Hardware locked write error." "0,1"
bitfld.long 0x0 11. "FRUN,FIFO underrun/overrun error." "0,1"
newline
bitfld.long 0x0 10. "HTO,Data starvation-by-host time-out (HTO)." "0,1"
bitfld.long 0x0 9. "DRTO,Data read time-out." "0,1"
bitfld.long 0x0 8. "RTO,Response time-out." "0,1"
newline
bitfld.long 0x0 7. "DCRC,Data CRC error." "0,1"
bitfld.long 0x0 6. "RCRC,Response CRC error." "0,1"
bitfld.long 0x0 5. "RXDR,Receive FIFO data request." "0,1"
newline
bitfld.long 0x0 4. "TXDR,Transmit FIFO data request." "0,1"
bitfld.long 0x0 3. "DTO,Data transfer over." "0,1"
bitfld.long 0x0 2. "CDONE,Command done." "0,1"
newline
bitfld.long 0x0 1. "RE,Response error." "0,1"
bitfld.long 0x0 0. "CDET,Card detect." "0,1"
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x0 16. "SDIO_INTERRUPT,Interrupt from SDIO card." "0,1"
newline
bitfld.long 0x0 15. "EBE,End-bit error (read)/write no CRC." "0,1"
bitfld.long 0x0 14. "ACD,Auto command done." "0,1"
bitfld.long 0x0 13. "SBE,Start-bit error." "0,1"
newline
bitfld.long 0x0 12. "HLE,Hardware locked write error." "0,1"
bitfld.long 0x0 11. "FRUN,FIFO underrun/overrun error." "0,1"
bitfld.long 0x0 10. "HTO,Data starvation-by-host time-out (HTO)." "0,1"
newline
bitfld.long 0x0 9. "DRTO,Data read time-out." "0,1"
bitfld.long 0x0 8. "RTO,Response time-out." "0,1"
bitfld.long 0x0 7. "DCRC,Data CRC error." "0,1"
newline
bitfld.long 0x0 6. "RCRC,Response CRC error." "0,1"
bitfld.long 0x0 5. "RXDR,Receive FIFO data request." "0,1"
bitfld.long 0x0 4. "TXDR,Transmit FIFO data request." "0,1"
newline
bitfld.long 0x0 3. "DTO,Data transfer over." "0,1"
bitfld.long 0x0 2. "CDONE,Command done." "0,1"
bitfld.long 0x0 1. "RE,Response error." "0,1"
newline
bitfld.long 0x0 0. "CDET,Card detect." "0,1"
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x0 16. "SDIO_INTERRUPT,Interrupt from SDIO card." "0,1"
bitfld.long 0x0 15. "EBE,End-bit error (read)/write no CRC." "0,1"
newline
bitfld.long 0x0 14. "ACD,Auto command done." "0,1"
bitfld.long 0x0 13. "SBE,Start-bit error." "0,1"
bitfld.long 0x0 12. "HLE,Hardware locked write error." "0,1"
newline
bitfld.long 0x0 11. "FRUN,FIFO underrun/overrun error." "0,1"
bitfld.long 0x0 10. "HTO,Data starvation-by-host time-out (HTO)." "0,1"
bitfld.long 0x0 9. "DRTO,Data read time-out." "0,1"
newline
bitfld.long 0x0 8. "RTO,Response time-out." "0,1"
bitfld.long 0x0 7. "DCRC,Data CRC error." "0,1"
bitfld.long 0x0 6. "RCRC,Response CRC error." "0,1"
newline
bitfld.long 0x0 5. "RXDR,Receive FIFO data request." "0,1"
bitfld.long 0x0 4. "TXDR,Transmit FIFO data request." "0,1"
bitfld.long 0x0 3. "DTO,Data transfer over." "0,1"
newline
bitfld.long 0x0 2. "CDONE,Command done." "0,1"
bitfld.long 0x0 1. "RE,Response error." "0,1"
bitfld.long 0x0 0. "CDET,Card detect." "0,1"
newline
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x0 16. "SDIO_INTERRUPT,Interrupt from SDIO card." "0,1"
bitfld.long 0x0 15. "EBE,End-bit error (read)/write no CRC." "0,1"
bitfld.long 0x0 14. "ACD,Auto command done." "0,1"
newline
bitfld.long 0x0 13. "SBE,Start-bit error." "0,1"
bitfld.long 0x0 12. "HLE,Hardware locked write error." "0,1"
bitfld.long 0x0 11. "FRUN,FIFO underrun/overrun error." "0,1"
newline
bitfld.long 0x0 10. "HTO,Data starvation-by-host time-out (HTO)." "0,1"
bitfld.long 0x0 9. "DRTO,Data read time-out." "0,1"
bitfld.long 0x0 8. "RTO,Response time-out." "0,1"
newline
bitfld.long 0x0 7. "DCRC,Data CRC error." "0,1"
bitfld.long 0x0 6. "RCRC,Response CRC error." "0,1"
bitfld.long 0x0 5. "RXDR,Receive FIFO data request." "0,1"
newline
bitfld.long 0x0 4. "TXDR,Transmit FIFO data request." "0,1"
bitfld.long 0x0 3. "DTO,Data transfer over." "0,1"
bitfld.long 0x0 2. "CDONE,Command done." "0,1"
newline
bitfld.long 0x0 1. "RE,Response error." "0,1"
bitfld.long 0x0 0. "CDET,Card detect." "0,1"
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x0 16. "SDIO_INTERRUPT,Interrupt from SDIO card." "0,1"
newline
bitfld.long 0x0 15. "EBE,End-bit error (read)/write no CRC." "0,1"
bitfld.long 0x0 14. "ACD,Auto command done." "0,1"
bitfld.long 0x0 13. "SBE,Start-bit error." "0,1"
newline
bitfld.long 0x0 12. "HLE,Hardware locked write error." "0,1"
bitfld.long 0x0 11. "FRUN,FIFO underrun/overrun error." "0,1"
bitfld.long 0x0 10. "HTO,Data starvation-by-host time-out (HTO)." "0,1"
newline
bitfld.long 0x0 9. "DRTO,Data read time-out." "0,1"
bitfld.long 0x0 8. "RTO,Response time-out." "0,1"
bitfld.long 0x0 7. "DCRC,Data CRC error." "0,1"
newline
bitfld.long 0x0 6. "RCRC,Response CRC error." "0,1"
bitfld.long 0x0 5. "RXDR,Receive FIFO data request." "0,1"
bitfld.long 0x0 4. "TXDR,Transmit FIFO data request." "0,1"
newline
bitfld.long 0x0 3. "DTO,Data transfer over." "0,1"
bitfld.long 0x0 2. "CDONE,Command done." "0,1"
bitfld.long 0x0 1. "RE,Response error." "0,1"
newline
bitfld.long 0x0 0. "CDET,Card detect." "0,1"
endif
line.long 0x4 "RINTSTS,Raw Interrupt Status register"
bitfld.long 0x4 16. "SDIO_INTERRUPT,Interrupt from SDIO card." "0,1"
bitfld.long 0x4 15. "EBE,End-bit error (read)/write no CRC." "0,1"
bitfld.long 0x4 14. "ACD,Auto command done." "0,1"
newline
bitfld.long 0x4 13. "SBE,Start-bit error." "0,1"
bitfld.long 0x4 12. "HLE,Hardware locked write error." "0,1"
bitfld.long 0x4 11. "FRUN,FIFO underrun/overrun error." "0,1"
newline
bitfld.long 0x4 10. "HTO,Data starvation-by-host time-out (HTO)." "0,1"
bitfld.long 0x4 9. "DRTO_BDS,Data read time-out (DRTO)/Boot Data Start (BDS)." "0,1"
bitfld.long 0x4 8. "RTO_BAR,Response time-out (RTO)/Boot Ack Received (BAR)." "0,1"
newline
bitfld.long 0x4 7. "DCRC,Data CRC error." "0,1"
bitfld.long 0x4 6. "RCRC,Response CRC error." "0,1"
bitfld.long 0x4 5. "RXDR,Receive FIFO data request." "0,1"
newline
bitfld.long 0x4 4. "TXDR,Transmit FIFO data request." "0,1"
bitfld.long 0x4 3. "DTO,Data transfer over." "0,1"
bitfld.long 0x4 2. "CDONE,Command done." "0,1"
newline
bitfld.long 0x4 1. "RE,Response error." "0,1"
bitfld.long 0x4 0. "CDET,Card detect." "0,1"
rgroup.long 0x48++0x3
line.long 0x0 "STATUS,Status register"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
rbitfld.long 0x0 31. "DMA_REQ,DMA request signal state." "0,1"
rbitfld.long 0x0 30. "DMA_ACK,DMA acknowledge signal state." "0,1"
hexmask.long.word 0x0 17.--29. 1. "FIFO_COUNT,FIFO count - Number of filled locations in FIFO."
newline
hexmask.long.byte 0x0 11.--16. 1. "RESPONSE_INDEX,Index of previous response  including any auto-stop sent by core."
rbitfld.long 0x0 10. "DATA_STATE_MC_BUSY,Data transmit or receive state-machine is busy." "0,1"
rbitfld.long 0x0 9. "DATA_BUSY,Inverted version of raw selected card_data[0] 0 - card data not busy 1 - card data busy." "0,1"
newline
rbitfld.long 0x0 8. "DATA_3_STATUS,Raw selected card_data[3]; checks whether card is present 0 - card not present 1 - card present." "0,1"
hexmask.long.byte 0x0 4.--7. 1. "CMDFSMSTATES,Command FSM states: 0 - Idle 1 - Send init sequence 2 - Tx cmd start bit 3 - Tx cmd tx bit 4 - Tx cmd index + arg 5 - Tx cmd crc7 6 - Tx cmd end bit 7 - Rx resp start bit 8 - Rx resp IRQ response 9 - Rx resp tx bit 10 - Rx resp cmd idx 11 -.."
rbitfld.long 0x0 3. "FIFO_FULL,FIFO is full status." "0,1"
newline
rbitfld.long 0x0 2. "FIFO_EMPTY,FIFO is empty status." "0,1"
rbitfld.long 0x0 1. "FIFO_TX_WATERMARK,FIFO reached Transmit watermark level; not qualified with data transfer." "0,1"
rbitfld.long 0x0 0. "FIFO_RX_WATERMARK,FIFO reached Receive watermark level; not qualified with data transfer." "0,1"
newline
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x0 31. "DMA_REQ,DMA request signal state." "0,1"
bitfld.long 0x0 30. "DMA_ACK,DMA acknowledge signal state." "0,1"
hexmask.long.word 0x0 17.--29. 1. "FIFO_COUNT,FIFO count - Number of filled locations in FIFO."
newline
hexmask.long.byte 0x0 11.--16. 1. "RESPONSE_INDEX,Index of previous response  including any auto-stop sent by core."
bitfld.long 0x0 10. "DATA_STATE_MC_BUSY,Data transmit or receive state-machine is busy." "0,1"
bitfld.long 0x0 9. "DATA_BUSY,Inverted version of raw selected card_data[0] 0 - card data not busy 1 - card data busy." "0,1"
newline
bitfld.long 0x0 8. "DATA_3_STATUS,Raw selected card_data[3]; checks whether card is present 0 - card not present 1 - card present." "0,1"
hexmask.long.byte 0x0 4.--7. 1. "CMDFSMSTATES,Command FSM states: 0 - Idle 1 - Send init sequence 2 - Tx cmd start bit 3 - Tx cmd tx bit 4 - Tx cmd index + arg 5 - Tx cmd crc7 6 - Tx cmd end bit 7 - Rx resp start bit 8 - Rx resp IRQ response 9 - Rx resp tx bit 10 - Rx resp cmd idx 11 -.."
bitfld.long 0x0 3. "FIFO_FULL,FIFO is full status." "0,1"
newline
bitfld.long 0x0 2. "FIFO_EMPTY,FIFO is empty status." "0,1"
bitfld.long 0x0 1. "FIFO_TX_WATERMARK,FIFO reached Transmit watermark level; not qualified with data transfer." "0,1"
bitfld.long 0x0 0. "FIFO_RX_WATERMARK,FIFO reached Receive watermark level; not qualified with data transfer." "0,1"
newline
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x0 31. "DMA_REQ,DMA request signal state." "0,1"
bitfld.long 0x0 30. "DMA_ACK,DMA acknowledge signal state." "0,1"
hexmask.long.word 0x0 17.--29. 1. "FIFO_COUNT,FIFO count - Number of filled locations in FIFO."
newline
hexmask.long.byte 0x0 11.--16. 1. "RESPONSE_INDEX,Index of previous response  including any auto-stop sent by core."
bitfld.long 0x0 10. "DATA_STATE_MC_BUSY,Data transmit or receive state-machine is busy." "0,1"
bitfld.long 0x0 9. "DATA_BUSY,Inverted version of raw selected card_data[0] 0 - card data not busy 1 - card data busy." "0,1"
newline
bitfld.long 0x0 8. "DATA_3_STATUS,Raw selected card_data[3]; checks whether card is present 0 - card not present 1 - card present." "0,1"
hexmask.long.byte 0x0 4.--7. 1. "CMDFSMSTATES,Command FSM states: 0 - Idle 1 - Send init sequence 2 - Tx cmd start bit 3 - Tx cmd tx bit 4 - Tx cmd index + arg 5 - Tx cmd crc7 6 - Tx cmd end bit 7 - Rx resp start bit 8 - Rx resp IRQ response 9 - Rx resp tx bit 10 - Rx resp cmd idx 11 -.."
bitfld.long 0x0 3. "FIFO_FULL,FIFO is full status." "0,1"
newline
bitfld.long 0x0 2. "FIFO_EMPTY,FIFO is empty status." "0,1"
bitfld.long 0x0 1. "FIFO_TX_WATERMARK,FIFO reached Transmit watermark level; not qualified with data transfer." "0,1"
bitfld.long 0x0 0. "FIFO_RX_WATERMARK,FIFO reached Receive watermark level; not qualified with data transfer." "0,1"
newline
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x0 31. "DMA_REQ,DMA request signal state." "0,1"
bitfld.long 0x0 30. "DMA_ACK,DMA acknowledge signal state." "0,1"
hexmask.long.word 0x0 17.--29. 1. "FIFO_COUNT,FIFO count - Number of filled locations in FIFO."
newline
hexmask.long.byte 0x0 11.--16. 1. "RESPONSE_INDEX,Index of previous response  including any auto-stop sent by core."
bitfld.long 0x0 10. "DATA_STATE_MC_BUSY,Data transmit or receive state-machine is busy." "0,1"
bitfld.long 0x0 9. "DATA_BUSY,Inverted version of raw selected card_data[0] 0 - card data not busy 1 - card data busy." "0,1"
newline
bitfld.long 0x0 8. "DATA_3_STATUS,Raw selected card_data[3]; checks whether card is present 0 - card not present 1 - card present." "0,1"
hexmask.long.byte 0x0 4.--7. 1. "CMDFSMSTATES,Command FSM states: 0 - Idle 1 - Send init sequence 2 - Tx cmd start bit 3 - Tx cmd tx bit 4 - Tx cmd index + arg 5 - Tx cmd crc7 6 - Tx cmd end bit 7 - Rx resp start bit 8 - Rx resp IRQ response 9 - Rx resp tx bit 10 - Rx resp cmd idx 11 -.."
bitfld.long 0x0 3. "FIFO_FULL,FIFO is full status." "0,1"
newline
bitfld.long 0x0 2. "FIFO_EMPTY,FIFO is empty status." "0,1"
bitfld.long 0x0 1. "FIFO_TX_WATERMARK,FIFO reached Transmit watermark level; not qualified with data transfer." "0,1"
bitfld.long 0x0 0. "FIFO_RX_WATERMARK,FIFO reached Receive watermark level; not qualified with data transfer." "0,1"
newline
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x0 31. "DMA_REQ,DMA request signal state." "0,1"
bitfld.long 0x0 30. "DMA_ACK,DMA acknowledge signal state." "0,1"
hexmask.long.word 0x0 17.--29. 1. "FIFO_COUNT,FIFO count - Number of filled locations in FIFO."
newline
hexmask.long.byte 0x0 11.--16. 1. "RESPONSE_INDEX,Index of previous response  including any auto-stop sent by core."
bitfld.long 0x0 10. "DATA_STATE_MC_BUSY,Data transmit or receive state-machine is busy." "0,1"
bitfld.long 0x0 9. "DATA_BUSY,Inverted version of raw selected card_data[0] 0 - card data not busy 1 - card data busy." "0,1"
newline
bitfld.long 0x0 8. "DATA_3_STATUS,Raw selected card_data[3]; checks whether card is present 0 - card not present 1 - card present." "0,1"
hexmask.long.byte 0x0 4.--7. 1. "CMDFSMSTATES,Command FSM states: 0 - Idle 1 - Send init sequence 2 - Tx cmd start bit 3 - Tx cmd tx bit 4 - Tx cmd index + arg 5 - Tx cmd crc7 6 - Tx cmd end bit 7 - Rx resp start bit 8 - Rx resp IRQ response 9 - Rx resp tx bit 10 - Rx resp cmd idx 11 -.."
bitfld.long 0x0 3. "FIFO_FULL,FIFO is full status." "0,1"
newline
bitfld.long 0x0 2. "FIFO_EMPTY,FIFO is empty status." "0,1"
bitfld.long 0x0 1. "FIFO_TX_WATERMARK,FIFO reached Transmit watermark level; not qualified with data transfer." "0,1"
bitfld.long 0x0 0. "FIFO_RX_WATERMARK,FIFO reached Receive watermark level; not qualified with data transfer." "0,1"
newline
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x0 31. "DMA_REQ,DMA request signal state." "0,1"
bitfld.long 0x0 30. "DMA_ACK,DMA acknowledge signal state." "0,1"
hexmask.long.word 0x0 17.--29. 1. "FIFO_COUNT,FIFO count - Number of filled locations in FIFO."
newline
hexmask.long.byte 0x0 11.--16. 1. "RESPONSE_INDEX,Index of previous response  including any auto-stop sent by core."
bitfld.long 0x0 10. "DATA_STATE_MC_BUSY,Data transmit or receive state-machine is busy." "0,1"
bitfld.long 0x0 9. "DATA_BUSY,Inverted version of raw selected card_data[0] 0 - card data not busy 1 - card data busy." "0,1"
newline
bitfld.long 0x0 8. "DATA_3_STATUS,Raw selected card_data[3]; checks whether card is present 0 - card not present 1 - card present." "0,1"
hexmask.long.byte 0x0 4.--7. 1. "CMDFSMSTATES,Command FSM states: 0 - Idle 1 - Send init sequence 2 - Tx cmd start bit 3 - Tx cmd tx bit 4 - Tx cmd index + arg 5 - Tx cmd crc7 6 - Tx cmd end bit 7 - Rx resp start bit 8 - Rx resp IRQ response 9 - Rx resp tx bit 10 - Rx resp cmd idx 11 -.."
bitfld.long 0x0 3. "FIFO_FULL,FIFO is full status." "0,1"
newline
bitfld.long 0x0 2. "FIFO_EMPTY,FIFO is empty status." "0,1"
bitfld.long 0x0 1. "FIFO_TX_WATERMARK,FIFO reached Transmit watermark level; not qualified with data transfer." "0,1"
bitfld.long 0x0 0. "FIFO_RX_WATERMARK,FIFO reached Receive watermark level; not qualified with data transfer." "0,1"
newline
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x0 31. "DMA_REQ,DMA request signal state." "0,1"
bitfld.long 0x0 30. "DMA_ACK,DMA acknowledge signal state." "0,1"
hexmask.long.word 0x0 17.--29. 1. "FIFO_COUNT,FIFO count - Number of filled locations in FIFO."
newline
hexmask.long.byte 0x0 11.--16. 1. "RESPONSE_INDEX,Index of previous response  including any auto-stop sent by core."
bitfld.long 0x0 10. "DATA_STATE_MC_BUSY,Data transmit or receive state-machine is busy." "0,1"
bitfld.long 0x0 9. "DATA_BUSY,Inverted version of raw selected card_data[0] 0 - card data not busy 1 - card data busy." "0,1"
newline
bitfld.long 0x0 8. "DATA_3_STATUS,Raw selected card_data[3]; checks whether card is present 0 - card not present 1 - card present." "0,1"
hexmask.long.byte 0x0 4.--7. 1. "CMDFSMSTATES,Command FSM states: 0 - Idle 1 - Send init sequence 2 - Tx cmd start bit 3 - Tx cmd tx bit 4 - Tx cmd index + arg 5 - Tx cmd crc7 6 - Tx cmd end bit 7 - Rx resp start bit 8 - Rx resp IRQ response 9 - Rx resp tx bit 10 - Rx resp cmd idx 11 -.."
bitfld.long 0x0 3. "FIFO_FULL,FIFO is full status." "0,1"
newline
bitfld.long 0x0 2. "FIFO_EMPTY,FIFO is empty status." "0,1"
bitfld.long 0x0 1. "FIFO_TX_WATERMARK,FIFO reached Transmit watermark level; not qualified with data transfer." "0,1"
bitfld.long 0x0 0. "FIFO_RX_WATERMARK,FIFO reached Receive watermark level; not qualified with data transfer." "0,1"
newline
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x0 31. "DMA_REQ,DMA request signal state." "0,1"
bitfld.long 0x0 30. "DMA_ACK,DMA acknowledge signal state." "0,1"
hexmask.long.word 0x0 17.--29. 1. "FIFO_COUNT,FIFO count - Number of filled locations in FIFO."
newline
hexmask.long.byte 0x0 11.--16. 1. "RESPONSE_INDEX,Index of previous response  including any auto-stop sent by core."
bitfld.long 0x0 10. "DATA_STATE_MC_BUSY,Data transmit or receive state-machine is busy." "0,1"
bitfld.long 0x0 9. "DATA_BUSY,Inverted version of raw selected card_data[0] 0 - card data not busy 1 - card data busy." "0,1"
newline
bitfld.long 0x0 8. "DATA_3_STATUS,Raw selected card_data[3]; checks whether card is present 0 - card not present 1 - card present." "0,1"
hexmask.long.byte 0x0 4.--7. 1. "CMDFSMSTATES,Command FSM states: 0 - Idle 1 - Send init sequence 2 - Tx cmd start bit 3 - Tx cmd tx bit 4 - Tx cmd index + arg 5 - Tx cmd crc7 6 - Tx cmd end bit 7 - Rx resp start bit 8 - Rx resp IRQ response 9 - Rx resp tx bit 10 - Rx resp cmd idx 11 -.."
bitfld.long 0x0 3. "FIFO_FULL,FIFO is full status." "0,1"
newline
bitfld.long 0x0 2. "FIFO_EMPTY,FIFO is empty status." "0,1"
bitfld.long 0x0 1. "FIFO_TX_WATERMARK,FIFO reached Transmit watermark level; not qualified with data transfer." "0,1"
bitfld.long 0x0 0. "FIFO_RX_WATERMARK,FIFO reached Receive watermark level; not qualified with data transfer." "0,1"
endif
group.long 0x4C++0xB
line.long 0x0 "FIFOTH,FIFO Threshold Watermark register"
bitfld.long 0x0 28.--30. "DMA_MTS,Burst size of multiple transaction; should be programmed same as DW-DMA controller multiple-transaction-size SRC/DEST_MSIZE." "0,1,2,3,4,5,6,7"
hexmask.long.word 0x0 16.--27. 1. "RX_WMARK,FIFO threshold watermark level when receiving data to card."
hexmask.long.word 0x0 0.--11. 1. "TX_WMARK,FIFO threshold watermark level when transmitting data to card."
line.long 0x4 "CDETECT,Card Detect register"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
rbitfld.long 0x4 0. "CARD_DETECT,Card detect." "0,1"
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x4 0. "CARD_DETECT,Card detect." "0,1"
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x4 0. "CARD_DETECT,Card detect." "0,1"
newline
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x4 0. "CARD_DETECT,Card detect." "0,1"
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x4 0. "CARD_DETECT,Card detect." "0,1"
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x4 0. "CARD_DETECT,Card detect." "0,1"
newline
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x4 0. "CARD_DETECT,Card detect." "0,1"
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x4 0. "CARD_DETECT,Card detect." "0,1"
endif
line.long 0x8 "WRTPRT,Write Protect register"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
rbitfld.long 0x8 0. "WRITE_PROTECT,Write protect." "0,1"
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x8 0. "WRITE_PROTECT,Write protect." "0,1"
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x8 0. "WRITE_PROTECT,Write protect." "0,1"
newline
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x8 0. "WRITE_PROTECT,Write protect." "0,1"
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x8 0. "WRITE_PROTECT,Write protect." "0,1"
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x8 0. "WRITE_PROTECT,Write protect." "0,1"
newline
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x8 0. "WRITE_PROTECT,Write protect." "0,1"
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x8 0. "WRITE_PROTECT,Write protect." "0,1"
endif
rgroup.long 0x5C++0x7
line.long 0x0 "TCBCNT,Transferred CIU Card Byte Count register"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
hexmask.long 0x0 0.--31. 1. "TRANS_CARD_BYTE_COUNT,Number of bytes transferred by CIU unit to card."
endif
sif (cpuis("LPC54605*"))
hexmask.long 0x0 0.--31. 1. "TRANS_CARD_BYTE_COUNT,Number of bytes transferred by CIU unit to card."
endif
sif (cpuis("LPC54606*"))
hexmask.long 0x0 0.--31. 1. "TRANS_CARD_BYTE_COUNT,Number of bytes transferred by CIU unit to card."
newline
endif
sif (cpuis("LPC54607*"))
hexmask.long 0x0 0.--31. 1. "TRANS_CARD_BYTE_COUNT,Number of bytes transferred by CIU unit to card."
endif
sif (cpuis("LPC54608*"))
hexmask.long 0x0 0.--31. 1. "TRANS_CARD_BYTE_COUNT,Number of bytes transferred by CIU unit to card."
endif
sif (cpuis("LPC54616*"))
hexmask.long 0x0 0.--31. 1. "TRANS_CARD_BYTE_COUNT,Number of bytes transferred by CIU unit to card."
newline
endif
sif (cpuis("LPC54618*"))
hexmask.long 0x0 0.--31. 1. "TRANS_CARD_BYTE_COUNT,Number of bytes transferred by CIU unit to card."
endif
sif (cpuis("LPC54628*"))
hexmask.long 0x0 0.--31. 1. "TRANS_CARD_BYTE_COUNT,Number of bytes transferred by CIU unit to card."
endif
line.long 0x4 "TBBCNT,Transferred Host to BIU-FIFO Byte Count register"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
hexmask.long 0x4 0.--31. 1. "TRANS_FIFO_BYTE_COUNT,Number of bytes transferred between Host/DMA memory and BIU FIFO."
endif
sif (cpuis("LPC54605*"))
hexmask.long 0x4 0.--31. 1. "TRANS_FIFO_BYTE_COUNT,Number of bytes transferred between Host/DMA memory and BIU FIFO."
endif
sif (cpuis("LPC54606*"))
hexmask.long 0x4 0.--31. 1. "TRANS_FIFO_BYTE_COUNT,Number of bytes transferred between Host/DMA memory and BIU FIFO."
newline
endif
sif (cpuis("LPC54607*"))
hexmask.long 0x4 0.--31. 1. "TRANS_FIFO_BYTE_COUNT,Number of bytes transferred between Host/DMA memory and BIU FIFO."
endif
sif (cpuis("LPC54608*"))
hexmask.long 0x4 0.--31. 1. "TRANS_FIFO_BYTE_COUNT,Number of bytes transferred between Host/DMA memory and BIU FIFO."
endif
sif (cpuis("LPC54616*"))
hexmask.long 0x4 0.--31. 1. "TRANS_FIFO_BYTE_COUNT,Number of bytes transferred between Host/DMA memory and BIU FIFO."
newline
endif
sif (cpuis("LPC54618*"))
hexmask.long 0x4 0.--31. 1. "TRANS_FIFO_BYTE_COUNT,Number of bytes transferred between Host/DMA memory and BIU FIFO."
endif
sif (cpuis("LPC54628*"))
hexmask.long 0x4 0.--31. 1. "TRANS_FIFO_BYTE_COUNT,Number of bytes transferred between Host/DMA memory and BIU FIFO."
endif
group.long 0x64++0x3
line.long 0x0 "DEBNCE,Debounce Count register"
hexmask.long.tbyte 0x0 0.--23. 1. "DEBOUNCE_COUNT,Number of host clocks (SD_CLK) used by debounce filter logic for card detect; typical debounce time is 5-25 ms."
group.long 0x78++0x3
line.long 0x0 "RST_N,Hardware Reset"
bitfld.long 0x0 0. "CARD_RESET,Hardware reset." "0,1"
group.long 0x80++0x3
line.long 0x0 "BMOD,Bus Mode register"
bitfld.long 0x0 8.--10. "PBL,Programmable Burst Length." "0,1,2,3,4,5,6,7"
bitfld.long 0x0 7. "DE,SD/MMC DMA Enable." "0,1"
hexmask.long.byte 0x0 2.--6. 1. "DSL,Descriptor Skip Length."
newline
bitfld.long 0x0 1. "FB,Fixed Burst." "0,1"
bitfld.long 0x0 0. "SWR,Software Reset." "0,1"
wgroup.long 0x84++0x3
line.long 0x0 "PLDMND,Poll Demand register"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
hexmask.long 0x0 0.--31. 1. "PD,Poll Demand."
endif
sif (cpuis("LPC54605*"))
hexmask.long 0x0 0.--31. 1. "PD,Poll Demand."
endif
sif (cpuis("LPC54606*"))
hexmask.long 0x0 0.--31. 1. "PD,Poll Demand."
newline
endif
sif (cpuis("LPC54607*"))
hexmask.long 0x0 0.--31. 1. "PD,Poll Demand."
endif
sif (cpuis("LPC54608*"))
hexmask.long 0x0 0.--31. 1. "PD,Poll Demand."
endif
sif (cpuis("LPC54616*"))
hexmask.long 0x0 0.--31. 1. "PD,Poll Demand."
newline
endif
sif (cpuis("LPC54618*"))
hexmask.long 0x0 0.--31. 1. "PD,Poll Demand."
endif
sif (cpuis("LPC54628*"))
hexmask.long 0x0 0.--31. 1. "PD,Poll Demand."
endif
group.long 0x88++0xB
line.long 0x0 "DBADDR,Descriptor List Base Address register"
hexmask.long 0x0 0.--31. 1. "SDL,Start of Descriptor List."
line.long 0x4 "IDSTS,Internal DMAC Status register"
hexmask.long.byte 0x4 13.--16. 1. "FSM,DMAC state machine present state."
bitfld.long 0x4 10.--12. "EB,Error Bits." "0,1,2,3,4,5,6,7"
bitfld.long 0x4 9. "AIS,Abnormal Interrupt Summary." "0,1"
newline
bitfld.long 0x4 8. "NIS,Normal Interrupt Summary." "0,1"
bitfld.long 0x4 5. "CES,Card Error Summary." "0,1"
bitfld.long 0x4 4. "DU,Descriptor Unavailable Interrupt." "0,1"
newline
bitfld.long 0x4 2. "FBE,Fatal Bus Error Interrupt." "0,1"
bitfld.long 0x4 1. "RI,Receive Interrupt." "0,1"
bitfld.long 0x4 0. "TI,Transmit Interrupt." "0,1"
line.long 0x8 "IDINTEN,Internal DMAC Interrupt Enable register"
bitfld.long 0x8 9. "AIS,Abnormal Interrupt Summary Enable." "0,1"
bitfld.long 0x8 8. "NIS,Normal Interrupt Summary Enable." "0,1"
bitfld.long 0x8 5. "CES,Card Error summary Interrupt Enable." "0,1"
newline
bitfld.long 0x8 4. "DU,Descriptor Unavailable Interrupt." "0,1"
bitfld.long 0x8 2. "FBE,Fatal Bus Error Enable." "0,1"
bitfld.long 0x8 1. "RI,Receive Interrupt Enable." "0,1"
newline
bitfld.long 0x8 0. "TI,Transmit Interrupt Enable." "0,1"
rgroup.long 0x94++0x7
line.long 0x0 "DSCADDR,Current Host Descriptor Address register"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
hexmask.long 0x0 0.--31. 1. "HDA,Host Descriptor Address Pointer."
endif
sif (cpuis("LPC54605*"))
hexmask.long 0x0 0.--31. 1. "HDA,Host Descriptor Address Pointer."
endif
sif (cpuis("LPC54606*"))
hexmask.long 0x0 0.--31. 1. "HDA,Host Descriptor Address Pointer."
newline
endif
sif (cpuis("LPC54607*"))
hexmask.long 0x0 0.--31. 1. "HDA,Host Descriptor Address Pointer."
endif
sif (cpuis("LPC54608*"))
hexmask.long 0x0 0.--31. 1. "HDA,Host Descriptor Address Pointer."
endif
sif (cpuis("LPC54616*"))
hexmask.long 0x0 0.--31. 1. "HDA,Host Descriptor Address Pointer."
newline
endif
sif (cpuis("LPC54618*"))
hexmask.long 0x0 0.--31. 1. "HDA,Host Descriptor Address Pointer."
endif
sif (cpuis("LPC54628*"))
hexmask.long 0x0 0.--31. 1. "HDA,Host Descriptor Address Pointer."
endif
line.long 0x4 "BUFADDR,Current Buffer Descriptor Address register"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
hexmask.long 0x4 0.--31. 1. "HBA,Host Buffer Address Pointer."
endif
sif (cpuis("LPC54605*"))
hexmask.long 0x4 0.--31. 1. "HBA,Host Buffer Address Pointer."
endif
sif (cpuis("LPC54606*"))
hexmask.long 0x4 0.--31. 1. "HBA,Host Buffer Address Pointer."
newline
endif
sif (cpuis("LPC54607*"))
hexmask.long 0x4 0.--31. 1. "HBA,Host Buffer Address Pointer."
endif
sif (cpuis("LPC54608*"))
hexmask.long 0x4 0.--31. 1. "HBA,Host Buffer Address Pointer."
endif
sif (cpuis("LPC54616*"))
hexmask.long 0x4 0.--31. 1. "HBA,Host Buffer Address Pointer."
newline
endif
sif (cpuis("LPC54618*"))
hexmask.long 0x4 0.--31. 1. "HBA,Host Buffer Address Pointer."
endif
sif (cpuis("LPC54628*"))
hexmask.long 0x4 0.--31. 1. "HBA,Host Buffer Address Pointer."
endif
group.long 0x100++0x7
line.long 0x0 "CARDTHRCTL,Card Threshold Control"
hexmask.long.byte 0x0 16.--23. 1. "CARDTHRESHOLD,Card Threshold size."
bitfld.long 0x0 1. "BSYCLRINTEN,Busy Clear Interrupt Enable." "0,1"
bitfld.long 0x0 0. "CARDRDTHREN,Card Read Threshold Enable." "0,1"
line.long 0x4 "BACKENDPWR,Power control"
bitfld.long 0x4 0. "BACKENDPWR,Back-end Power control for card application." "0,1"
repeat 64. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x200)++0x3
line.long 0x0 "FIFO[$1],SDIF FIFO"
hexmask.long 0x0 0.--31. 1. "DATA,SDIF FIFO."
repeat.end
sif (cpuis("LPC54605*"))
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x30)++0x3
line.long 0x0 "RESP[$1],Response register"
hexmask.long 0x0 0.--31. 1. "RESPONSE,Bits of response."
repeat.end
endif
sif (cpuis("LPC54605*"))
group.long 0x48++0x3
line.long 0x0 "STATUS,Status register"
endif
sif (cpuis("LPC54605*"))
group.long 0x5C++0x3
line.long 0x0 "TCBCNT,Transferred CIU Card Byte Count register"
endif
sif (cpuis("LPC54605*"))
group.long 0x60++0x3
line.long 0x0 "TBBCNT,Transferred Host to BIU-FIFO Byte Count register"
endif
sif (cpuis("LPC54605*"))
group.long 0x84++0x3
line.long 0x0 "PLDMND,Poll Demand register"
endif
sif (cpuis("LPC54605*"))
group.long 0x94++0x3
line.long 0x0 "DSCADDR,Current Host Descriptor Address register"
endif
sif (cpuis("LPC54605*"))
group.long 0x98++0x3
line.long 0x0 "BUFADDR,Current Buffer Descriptor Address register"
endif
sif (cpuis("LPC54606*"))
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x30)++0x3
line.long 0x0 "RESP[$1],Response register"
hexmask.long 0x0 0.--31. 1. "RESPONSE,Bits of response."
repeat.end
endif
sif (cpuis("LPC54606*"))
group.long 0x48++0x3
line.long 0x0 "STATUS,Status register"
endif
sif (cpuis("LPC54606*"))
group.long 0x5C++0x3
line.long 0x0 "TCBCNT,Transferred CIU Card Byte Count register"
endif
sif (cpuis("LPC54606*"))
group.long 0x60++0x3
line.long 0x0 "TBBCNT,Transferred Host to BIU-FIFO Byte Count register"
endif
sif (cpuis("LPC54606*"))
group.long 0x84++0x3
line.long 0x0 "PLDMND,Poll Demand register"
endif
sif (cpuis("LPC54606*"))
group.long 0x94++0x3
line.long 0x0 "DSCADDR,Current Host Descriptor Address register"
endif
sif (cpuis("LPC54606*"))
group.long 0x98++0x3
line.long 0x0 "BUFADDR,Current Buffer Descriptor Address register"
endif
sif (cpuis("LPC54607*"))
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x30)++0x3
line.long 0x0 "RESP[$1],Response register"
hexmask.long 0x0 0.--31. 1. "RESPONSE,Bits of response."
repeat.end
endif
sif (cpuis("LPC54607*"))
group.long 0x48++0x3
line.long 0x0 "STATUS,Status register"
endif
sif (cpuis("LPC54607*"))
group.long 0x5C++0x3
line.long 0x0 "TCBCNT,Transferred CIU Card Byte Count register"
endif
sif (cpuis("LPC54607*"))
group.long 0x60++0x3
line.long 0x0 "TBBCNT,Transferred Host to BIU-FIFO Byte Count register"
endif
sif (cpuis("LPC54607*"))
group.long 0x84++0x3
line.long 0x0 "PLDMND,Poll Demand register"
endif
sif (cpuis("LPC54607*"))
group.long 0x94++0x3
line.long 0x0 "DSCADDR,Current Host Descriptor Address register"
endif
sif (cpuis("LPC54607*"))
group.long 0x98++0x3
line.long 0x0 "BUFADDR,Current Buffer Descriptor Address register"
endif
sif (cpuis("LPC54608*"))
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x30)++0x3
line.long 0x0 "RESP[$1],Response register"
hexmask.long 0x0 0.--31. 1. "RESPONSE,Bits of response."
repeat.end
endif
sif (cpuis("LPC54608*"))
group.long 0x48++0x3
line.long 0x0 "STATUS,Status register"
endif
sif (cpuis("LPC54608*"))
group.long 0x5C++0x3
line.long 0x0 "TCBCNT,Transferred CIU Card Byte Count register"
endif
sif (cpuis("LPC54608*"))
group.long 0x60++0x3
line.long 0x0 "TBBCNT,Transferred Host to BIU-FIFO Byte Count register"
endif
sif (cpuis("LPC54608*"))
group.long 0x84++0x3
line.long 0x0 "PLDMND,Poll Demand register"
endif
sif (cpuis("LPC54608*"))
group.long 0x94++0x3
line.long 0x0 "DSCADDR,Current Host Descriptor Address register"
endif
sif (cpuis("LPC54608*"))
group.long 0x98++0x3
line.long 0x0 "BUFADDR,Current Buffer Descriptor Address register"
endif
sif (cpuis("LPC54616*"))
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x30)++0x3
line.long 0x0 "RESP[$1],Response register"
hexmask.long 0x0 0.--31. 1. "RESPONSE,Bits of response."
repeat.end
endif
sif (cpuis("LPC54616*"))
group.long 0x48++0x3
line.long 0x0 "STATUS,Status register"
endif
sif (cpuis("LPC54616*"))
group.long 0x5C++0x3
line.long 0x0 "TCBCNT,Transferred CIU Card Byte Count register"
endif
sif (cpuis("LPC54616*"))
group.long 0x60++0x3
line.long 0x0 "TBBCNT,Transferred Host to BIU-FIFO Byte Count register"
endif
sif (cpuis("LPC54616*"))
group.long 0x84++0x3
line.long 0x0 "PLDMND,Poll Demand register"
endif
sif (cpuis("LPC54616*"))
group.long 0x94++0x3
line.long 0x0 "DSCADDR,Current Host Descriptor Address register"
endif
sif (cpuis("LPC54616*"))
group.long 0x98++0x3
line.long 0x0 "BUFADDR,Current Buffer Descriptor Address register"
endif
sif (cpuis("LPC54618*"))
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x30)++0x3
line.long 0x0 "RESP[$1],Response register"
hexmask.long 0x0 0.--31. 1. "RESPONSE,Bits of response."
repeat.end
endif
sif (cpuis("LPC54618*"))
group.long 0x48++0x3
line.long 0x0 "STATUS,Status register"
endif
sif (cpuis("LPC54618*"))
group.long 0x5C++0x3
line.long 0x0 "TCBCNT,Transferred CIU Card Byte Count register"
endif
sif (cpuis("LPC54618*"))
group.long 0x60++0x3
line.long 0x0 "TBBCNT,Transferred Host to BIU-FIFO Byte Count register"
endif
sif (cpuis("LPC54618*"))
group.long 0x84++0x3
line.long 0x0 "PLDMND,Poll Demand register"
endif
sif (cpuis("LPC54618*"))
group.long 0x94++0x3
line.long 0x0 "DSCADDR,Current Host Descriptor Address register"
endif
sif (cpuis("LPC54618*"))
group.long 0x98++0x3
line.long 0x0 "BUFADDR,Current Buffer Descriptor Address register"
endif
sif (cpuis("LPC54628*"))
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x30)++0x3
line.long 0x0 "RESP[$1],Response register"
hexmask.long 0x0 0.--31. 1. "RESPONSE,Bits of response."
repeat.end
endif
sif (cpuis("LPC54628*"))
group.long 0x48++0x3
line.long 0x0 "STATUS,Status register"
endif
sif (cpuis("LPC54628*"))
group.long 0x5C++0x3
line.long 0x0 "TCBCNT,Transferred CIU Card Byte Count register"
endif
sif (cpuis("LPC54628*"))
group.long 0x60++0x3
line.long 0x0 "TBBCNT,Transferred Host to BIU-FIFO Byte Count register"
endif
sif (cpuis("LPC54628*"))
group.long 0x84++0x3
line.long 0x0 "PLDMND,Poll Demand register"
endif
sif (cpuis("LPC54628*"))
group.long 0x94++0x3
line.long 0x0 "DSCADDR,Current Host Descriptor Address register"
endif
sif (cpuis("LPC54628*"))
group.long 0x98++0x3
line.long 0x0 "BUFADDR,Current Buffer Descriptor Address register"
endif
tree.end
endif
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54628*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
tree "SHA (Secure Hash Algorithm)"
base ad:0x400A4000
group.long 0x0++0xB
line.long 0x0 "CTRL,Control register"
bitfld.long 0x0 8. "DMA,When this bit is set  the DMA is used to fill INDATA." "0,1"
bitfld.long 0x0 4. "NEW,When this bit is set  a new hash operation is started." "0,1"
bitfld.long 0x0 0.--1. "MODE,This field is used to select the operational mode of SHA block." "0,1,2,3"
line.long 0x4 "STATUS,Status register"
bitfld.long 0x4 2. "ERROR,This field indicates if an error has occurred." "0,1"
bitfld.long 0x4 1. "DIGEST,This field indicates if a DIGEST is ready and waiting and there is no active next block that has already started." "0,1"
bitfld.long 0x4 0. "WAITING,This field indicates if the block is waiting for more data to process." "0,1"
line.long 0x8 "INTENSET,Interrupt Enable register"
bitfld.long 0x8 2. "ERROR,This field indicates if interrupt is generated on an ERROR (as defined in STAT register)." "0,1"
bitfld.long 0x8 1. "DIGEST,This field indicates if interrupt is generated when Digest is ready (completed a Hash or completed a full sequence)." "0,1"
bitfld.long 0x8 0. "WAITING,This field indicates if interrupt should be enabled when waiting for input data." "0,1"
wgroup.long 0xC++0x3
line.long 0x0 "INTENCLR,Interrupt Clear register"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x0 2. "ERROR,Writing a 1 clears the interrupt enabled by the INTENSET register." "0,1"
bitfld.long 0x0 1. "DIGEST,Writing a 1 clears the interrupt enabled by the INTENSET register." "0,1"
bitfld.long 0x0 0. "WAITING,Writing a 1 clears the interrupt enabled by the INTENSET register." "0,1"
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x0 2. "ERROR,Writing a 1 clears the interrupt enabled by the INTENSET register." "0,1"
bitfld.long 0x0 1. "DIGEST,Writing a 1 clears the interrupt enabled by the INTENSET register." "0,1"
bitfld.long 0x0 0. "WAITING,Writing a 1 clears the interrupt enabled by the INTENSET register." "0,1"
endif
group.long 0x10++0x7
line.long 0x0 "MEMCTRL,Memory Control register"
hexmask.long.word 0x0 16.--26. 1. "COUNT,This field indicates the number of 512-bit blocks to copy starting at MEMADDR."
bitfld.long 0x0 0. "MASTER,This field is used to enable SHA block as AHB bus master." "0,1"
line.long 0x4 "MEMADDR,Memory Address register"
hexmask.long 0x4 0.--31. 1. "BASEADDR,This field indicates the base address in Internal Flash  SRAM0  SRAMX  or SPIFI to start copying from."
wgroup.long 0x20++0x3
line.long 0x0 "INDATA,Input Data register"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
hexmask.long 0x0 0.--31. 1. "DATA,In this field the next word is written in little-endian format."
endif
sif (cpuis("LPC54628*"))
hexmask.long 0x0 0.--31. 1. "DATA,In this field the next word is written in little-endian format."
endif
repeat 7. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x24)++0x3
line.long 0x0 "ALIAS[$1],Alias register"
hexmask.long 0x0 0.--31. 1. "DATA,In this field the next word is written in little-endian format."
repeat.end
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x40)++0x3
line.long 0x0 "DIGEST[$1],Digest register"
hexmask.long 0x0 0.--31. 1. "DIGEST,This field contains one word of the Digest."
repeat.end
sif (cpuis("LPC54628*"))
group.long 0xC++0x3
line.long 0x0 "INTENCLR,Interrupt Clear register"
endif
sif (cpuis("LPC54628*"))
group.long 0x20++0x3
line.long 0x0 "INDATA,Input Data register"
endif
sif (cpuis("LPC54628*"))
repeat 7. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x24)++0x3
line.long 0x0 "ALIAS[$1],Alias register"
hexmask.long 0x0 0.--31. 1. "DATA,In this field the next word is written in little-endian format."
repeat.end
endif
tree.end
endif
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54605*")||cpuis("LPC54606*")||cpuis("LPC54607*")||cpuis("LPC54608*")||cpuis("LPC54616*")||cpuis("LPC54618*")||cpuis("LPC54628*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
tree "SMARTCARD (Smart Card Interface)"
base ad:0x0
tree "SMARTCARD0"
base ad:0x40036000
group.long 0x0++0x3
line.long 0x0 "DLL,Divisor Latch LSB"
hexmask.long.byte 0x0 0.--7. 1. "DLLSB,The SCIn Divisor Latch LSB Register  along with the SCInDLM register  determines the baud rate of the SCIn."
rgroup.long 0x0++0x3
line.long 0x0 "RBR,Receiver Buffer Register"
hexmask.long.byte 0x0 0.--7. 1. "RBR,The SCIn Receiver Buffer Register contains the oldest received byte in the SCIn Rx FIFO."
wgroup.long 0x0++0x3
line.long 0x0 "THR,Transmit Holding Register"
hexmask.long.byte 0x0 0.--7. 1. "THR,Writing to the SCIn Transmit Holding Register causes the data to be stored in the SCIn transmit FIFO."
group.long 0x4++0x3
line.long 0x0 "DLM,Divisor Latch MSB"
hexmask.long.byte 0x0 0.--7. 1. "DLMSB,The SCIn Divisor Latch MSB Register  along with the DLL register  determines the baud rate of the SCIn."
group.long 0x4++0x3
line.long 0x0 "IER,Interrupt Enable Register"
bitfld.long 0x0 2. "RXIE,RX Line Status Interrupt Enable." "0,1"
bitfld.long 0x0 1. "THREIE,THRE Interrupt Enable." "0,1"
bitfld.long 0x0 0. "RBRIE,RBR Interrupt Enable." "0,1"
wgroup.long 0x8++0x3
line.long 0x0 "FCR,FIFO Control Register"
bitfld.long 0x0 6.--7. "RXTRIGLVL,RX Trigger Level." "0,1,2,3"
bitfld.long 0x0 3. "DMAMODE,DMA Mode Select." "0,1"
bitfld.long 0x0 2. "TXFIFORES,TX FIFO Reset." "0,1"
bitfld.long 0x0 1. "RXFIFORES,RX FIFO Reset." "0,1"
bitfld.long 0x0 0. "FIFOEN,FIFO Enable." "0,1"
rgroup.long 0x8++0x3
line.long 0x0 "IIR,Interrupt ID Register"
bitfld.long 0x0 6.--7. "FIFOENABLE,Copies of SCInFCR[0]." "0,1,2,3"
bitfld.long 0x0 1.--3. "INTID,Interrupt identification." "0,1,2,3,4,5,6,7"
bitfld.long 0x0 0. "INTSTATUS,Interrupt status." "0,1"
group.long 0xC++0x3
line.long 0x0 "LCR,Line Control Register"
bitfld.long 0x0 7. "DLAB,Divisor Latch Access Bit." "0,1"
bitfld.long 0x0 4.--5. "PS,Parity Select." "0,1,2,3"
bitfld.long 0x0 3. "PE,Parity Enable." "0,1"
bitfld.long 0x0 2. "SBS,Stop Bit Select." "0,1"
bitfld.long 0x0 0.--1. "WLS,Word Length Select." "0,1,2,3"
rgroup.long 0x14++0x3
line.long 0x0 "LSR,Line Status Register"
bitfld.long 0x0 7. "RXFE,Error in RX FIFO." "0,1"
bitfld.long 0x0 6. "TEMT,Transmitter Empty." "0,1"
bitfld.long 0x0 5. "THRE,Transmitter Holding Register Empty." "0,1"
bitfld.long 0x0 3. "FE,Framing Error." "0,1"
bitfld.long 0x0 2. "PE,Parity Error." "0,1"
bitfld.long 0x0 1. "OE,Overrun Error." "0,1"
bitfld.long 0x0 0. "RDR,Receiver Data Ready." "0,1"
group.long 0x1C++0x3
line.long 0x0 "SCR,Scratch Pad Register"
hexmask.long.byte 0x0 0.--7. 1. "PAD,A readable  writable byte."
group.long 0x2C++0x3
line.long 0x0 "OSR,Oversampling register"
hexmask.long.byte 0x0 8.--14. 1. "FDINT,These bits act as a more-significant extension of the OSint field  allowing an oversampling ratio up to 2048 as required by ISO7816-3."
hexmask.long.byte 0x0 4.--7. 1. "OSINT,Integer part of the oversampling ratio  minus 1."
bitfld.long 0x0 1.--3. "OSFRAC,Fractional part of the oversampling ratio  in units of 1/8th of an input clock period." "0,1,2,3,4,5,6,7"
group.long 0x48++0x3
line.long 0x0 "SCICTRL,Smart Card Interface control register"
hexmask.long.byte 0x0 8.--15. 1. "GUARDTIME,Extra guard time."
bitfld.long 0x0 5.--7. "TXRETRY,Maximum number of retransmissions in case of a negative acknowledge (protocol T=0)." "0,1,2,3,4,5,6,7"
bitfld.long 0x0 2. "PROTSEL,Protocol selection as defined in the ISO7816-3 standard." "0,1"
bitfld.long 0x0 1. "NACKDIS,NACK response disable." "0,1"
bitfld.long 0x0 0. "SCIEN,Smart Card Interface Enable." "0,1"
tree.end
tree "SMARTCARD1"
base ad:0x40037000
group.long 0x0++0x3
line.long 0x0 "DLL,Divisor Latch LSB"
hexmask.long.byte 0x0 0.--7. 1. "DLLSB,The SCIn Divisor Latch LSB Register  along with the SCInDLM register  determines the baud rate of the SCIn."
rgroup.long 0x0++0x3
line.long 0x0 "RBR,Receiver Buffer Register"
hexmask.long.byte 0x0 0.--7. 1. "RBR,The SCIn Receiver Buffer Register contains the oldest received byte in the SCIn Rx FIFO."
wgroup.long 0x0++0x3
line.long 0x0 "THR,Transmit Holding Register"
hexmask.long.byte 0x0 0.--7. 1. "THR,Writing to the SCIn Transmit Holding Register causes the data to be stored in the SCIn transmit FIFO."
group.long 0x4++0x3
line.long 0x0 "DLM,Divisor Latch MSB"
hexmask.long.byte 0x0 0.--7. 1. "DLMSB,The SCIn Divisor Latch MSB Register  along with the DLL register  determines the baud rate of the SCIn."
group.long 0x4++0x3
line.long 0x0 "IER,Interrupt Enable Register"
bitfld.long 0x0 2. "RXIE,RX Line Status Interrupt Enable." "0,1"
bitfld.long 0x0 1. "THREIE,THRE Interrupt Enable." "0,1"
bitfld.long 0x0 0. "RBRIE,RBR Interrupt Enable." "0,1"
wgroup.long 0x8++0x3
line.long 0x0 "FCR,FIFO Control Register"
bitfld.long 0x0 6.--7. "RXTRIGLVL,RX Trigger Level." "0,1,2,3"
bitfld.long 0x0 3. "DMAMODE,DMA Mode Select." "0,1"
bitfld.long 0x0 2. "TXFIFORES,TX FIFO Reset." "0,1"
bitfld.long 0x0 1. "RXFIFORES,RX FIFO Reset." "0,1"
bitfld.long 0x0 0. "FIFOEN,FIFO Enable." "0,1"
rgroup.long 0x8++0x3
line.long 0x0 "IIR,Interrupt ID Register"
bitfld.long 0x0 6.--7. "FIFOENABLE,Copies of SCInFCR[0]." "0,1,2,3"
bitfld.long 0x0 1.--3. "INTID,Interrupt identification." "0,1,2,3,4,5,6,7"
bitfld.long 0x0 0. "INTSTATUS,Interrupt status." "0,1"
group.long 0xC++0x3
line.long 0x0 "LCR,Line Control Register"
bitfld.long 0x0 7. "DLAB,Divisor Latch Access Bit." "0,1"
bitfld.long 0x0 4.--5. "PS,Parity Select." "0,1,2,3"
bitfld.long 0x0 3. "PE,Parity Enable." "0,1"
bitfld.long 0x0 2. "SBS,Stop Bit Select." "0,1"
bitfld.long 0x0 0.--1. "WLS,Word Length Select." "0,1,2,3"
rgroup.long 0x14++0x3
line.long 0x0 "LSR,Line Status Register"
bitfld.long 0x0 7. "RXFE,Error in RX FIFO." "0,1"
bitfld.long 0x0 6. "TEMT,Transmitter Empty." "0,1"
bitfld.long 0x0 5. "THRE,Transmitter Holding Register Empty." "0,1"
bitfld.long 0x0 3. "FE,Framing Error." "0,1"
bitfld.long 0x0 2. "PE,Parity Error." "0,1"
bitfld.long 0x0 1. "OE,Overrun Error." "0,1"
bitfld.long 0x0 0. "RDR,Receiver Data Ready." "0,1"
group.long 0x1C++0x3
line.long 0x0 "SCR,Scratch Pad Register"
hexmask.long.byte 0x0 0.--7. 1. "PAD,A readable  writable byte."
group.long 0x2C++0x3
line.long 0x0 "OSR,Oversampling register"
hexmask.long.byte 0x0 8.--14. 1. "FDINT,These bits act as a more-significant extension of the OSint field  allowing an oversampling ratio up to 2048 as required by ISO7816-3."
hexmask.long.byte 0x0 4.--7. 1. "OSINT,Integer part of the oversampling ratio  minus 1."
bitfld.long 0x0 1.--3. "OSFRAC,Fractional part of the oversampling ratio  in units of 1/8th of an input clock period." "0,1,2,3,4,5,6,7"
group.long 0x48++0x3
line.long 0x0 "SCICTRL,Smart Card Interface control register"
hexmask.long.byte 0x0 8.--15. 1. "GUARDTIME,Extra guard time."
bitfld.long 0x0 5.--7. "TXRETRY,Maximum number of retransmissions in case of a negative acknowledge (protocol T=0)." "0,1,2,3,4,5,6,7"
bitfld.long 0x0 2. "PROTSEL,Protocol selection as defined in the ISO7816-3 standard." "0,1"
bitfld.long 0x0 1. "NACKDIS,NACK response disable." "0,1"
bitfld.long 0x0 0. "SCIEN,Smart Card Interface Enable." "0,1"
tree.end
tree.end
endif
tree "SPI (Serial Peripheral Interface)"
base ad:0x0
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
base ad:0x40086000
elif (cpuis("LPC54101*"))
base ad:0x400A4000
endif
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54101*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
tree "SPI0"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
newline
bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
newline
bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
newline
bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
newline
bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
newline
hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
newline
rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
newline
bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
newline
bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
newline
bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
newline
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
newline
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
newline
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
newline
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
newline
rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
newline
rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
newline
rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
newline
bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
newline
bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
newline
bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
newline
bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
newline
bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
wgroup.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
newline
bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
newline
hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
newline
bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
newline
bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
newline
bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
endif
sif (cpuis("LPC54101*"))
group.long 0x0++0x2B
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low. The value in..,1: High. The SSEL3 pin is active high. The value in.."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low. The value in..,1: High. The SSEL2 pin is active high. The value in.."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low. The value in..,1: High. The SSEL1 pin is active high. The value in.."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low. The value in..,1: High. The SSEL0 pin is active high. The value in.."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
newline
bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
newline
bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
newline
hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. ... 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position"
bitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
newline
bitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
newline
bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
bitfld.long 0x8 3. "TXUR,Transmitter Underrun interrupt flag. This flag applies only to slave mode (Master = 0). In this case  the transmitter must begin sending new data on the next input clock if the transmitter is idle. If that data is not available in the transmitter.." "0,1"
newline
bitfld.long 0x8 2. "RXOV,Receiver Overrun interrupt flag. This flag applies only to slave mode (Master = 0). This flag is set when the beginning of a received character is detected while the receiver buffer is still in use. If this occurs  the receiver buffer contents are.." "0,1"
bitfld.long 0x8 1. "TXRDY,Transmitter Ready flag. When 1  this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT or TXDATCTL until the data is moved to the.." "0,1"
newline
bitfld.long 0x8 0. "RXRDY,Receiver Ready flag. When 1  indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT register." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable" "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when the.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
newline
bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
bitfld.long 0xC 3. "TXUREN,TX underrun interrupt enable. Determines whether an interrupt occurs when a transmitter underrun occurs. This happens in slave mode when there is a need to transmit data when none is available." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated if the.."
newline
bitfld.long 0xC 2. "RXOVEN,RX overrun interrupt enable. Determines whether an interrupt occurs when a receiver overrun occurs. This happens in slave mode when there is a need for the receiver to move newly received data to the RXDAT register when it is already in use. The.." "0: Disabled. No interrupt will be generated when a..,1: Enabled. An interrupt will be generated if a.."
bitfld.long 0xC 1. "TXRDYEN,TX ready interrupt enable. Determines whether an interrupt occurs when the transmitter holding register is available." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when.."
newline
bitfld.long 0xC 0. "RXRDYEN,RX ready interrupt enable. Determines whether an interrupt occurs when receiver data is available." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when.."
line.long 0x10 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x10 8. "MSTIDLE,Writing 1 clears the corresponding bits in the MSTIDLE register." "0,1"
bitfld.long 0x10 5. "SSDEN,Writing 1 clears the corresponding bits in the INTENSET register." "0,1"
newline
bitfld.long 0x10 4. "SSAEN,Writing 1 clears the corresponding bits in the INTENSET register." "0,1"
bitfld.long 0x10 3. "TXUREN,Writing 1 clears the corresponding bits in the INTENSET register." "0,1"
newline
bitfld.long 0x10 2. "RXOVEN,Writing 1 clears the corresponding bits in the INTENSET register." "0,1"
bitfld.long 0x10 1. "TXRDYEN,Writing 1 clears the corresponding bits in the INTENSET register." "0,1"
newline
bitfld.long 0x10 0. "RXRDYEN,Writing 1 clears the corresponding bits in the INTENSET register." "0,1"
line.long 0x14 "RXDAT,SPI Receive Data"
bitfld.long 0x14 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x14 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
newline
bitfld.long 0x14 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x14 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
newline
bitfld.long 0x14 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x14 0.--15. 1. "RXDAT,Receiver Data. This contains the next piece of received data. The number of bits that are used depends on the LEN setting in TXCTL / TXDATCTL."
line.long 0x18 "TXDATCTL,SPI Transmit Data with Control"
hexmask.long.byte 0x18 24.--27. 1. "LEN,Data Length. Specifies the data length from 1 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0 = Data transfer is 1 bit in length. 0x1 = Data transfer is 2 bits in length."
bitfld.long 0x18 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver.Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
newline
bitfld.long 0x18 21. "EOF,End of Frame. Between frames  a delay may be inserted  as defined by the FRAME_DELAY value in the DLY register. The end of a frame may not be particularly meaningful if the FRAME_DELAY value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x18 20. "EOT,End of Transfer. The asserted SSEL will be deasserted at the end of a transfer  and remain so for at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
newline
bitfld.long 0x18 19. "TXSSEL3_N,Transmit Slave Select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default. The active state of the SSEL3 pin is configured by bits in the CFG register." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x18 18. "TXSSEL2_N,Transmit Slave Select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default. The active state of the SSEL2 pin is configured by bits in the CFG register." "0: SSEL2 asserted.,1: SSEL2 not asserted."
newline
bitfld.long 0x18 17. "TXSSEL1_N,Transmit Slave Select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default. The active state of the SSEL1 pin is configured by bits in the CFG register." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x18 16. "TXSSEL0_N,Transmit Slave Select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default. The active state of the SSEL0 pin is configured by bits in the CFG register." "0: SSEL0 asserted.,1: SSEL0 not asserted."
newline
hexmask.long.word 0x18 0.--15. 1. "TXDAT,Transmit Data. This field provides from 1 to 16 bits of data to be transmitted."
line.long 0x1C "TXDAT,SPI Transmit Data"
hexmask.long.word 0x1C 0.--15. 1. "DATA,Transmit Data. This field provides from 4 to 16 bits of data to be transmitted."
line.long 0x20 "TXCTL,SPI Transmit Control"
hexmask.long.byte 0x20 24.--27. 1. "LEN,Data transfer Length."
bitfld.long 0x20 22. "RXIGNORE,Receive Ignore." "0,1"
newline
bitfld.long 0x20 21. "EOF,End of Frame." "0,1"
bitfld.long 0x20 20. "EOT,End of Transfer." "0,1"
newline
bitfld.long 0x20 19. "TXSSEL3_n,Transmit Slave Select 3." "0,1"
bitfld.long 0x20 18. "TXSSEL2_N,Transmit Slave Select 2." "0,1"
newline
bitfld.long 0x20 17. "TXSSEL1_N,Transmit Slave Select 1." "0,1"
bitfld.long 0x20 16. "TXSSEL0_N,Transmit Slave Select 0." "0,1"
line.long 0x24 "DIV,SPI clock Divider"
hexmask.long.word 0x24 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the PCLK for the SPI is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in PCLK/1  the value 1 results in PCLK/2  up to the maximum possible divide value of.."
line.long 0x28 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x28 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x28 5. "SSD,Slave Select Deassert." "0,1"
newline
bitfld.long 0x28 4. "SSA,Slave Select Assert." "0,1"
bitfld.long 0x28 3. "TXUR,Transmitter Underrun interrupt flag." "0,1"
newline
bitfld.long 0x28 2. "RXOV,Receiver Overrun interrupt flag." "0,1"
bitfld.long 0x28 1. "TXRDY,Transmitter Ready flag." "0,1"
newline
bitfld.long 0x28 0. "RXRDY,Receiver Ready flag." "0,1"
endif
tree.end
endif
tree "SPI2"
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
newline
bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
newline
bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
newline
bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
newline
bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
newline
hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
newline
rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
newline
bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
newline
bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
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bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
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rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
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bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
wgroup.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "SPI3"
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
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bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
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rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
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bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
wgroup.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "SPI4"
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
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bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
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rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
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bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
wgroup.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "SPI5"
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
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bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
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rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
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bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
wgroup.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "SPI6"
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
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bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
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rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
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bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
wgroup.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "SPI7"
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
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bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
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rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
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bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
wgroup.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "SPI8"
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
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bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
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rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
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bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
wgroup.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
newline
bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
newline
bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "SPI9"
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
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bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
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rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
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bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
wgroup.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "SPI10"
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
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bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
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rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
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bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
wgroup.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
newline
bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
newline
bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
newline
hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
newline
bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
newline
bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
newline
bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
newline
bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
newline
hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
base ad:0x40087000
elif (cpuis("LPC54101*"))
base ad:0x400A8000
endif
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54101*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
tree "SPI1"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
newline
bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
newline
bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
newline
bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
newline
rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
newline
bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
newline
bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
newline
bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
newline
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
newline
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
newline
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
newline
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
newline
rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
newline
rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
newline
rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
newline
bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
newline
bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
newline
bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
newline
bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
newline
bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
newline
bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
wgroup.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
newline
bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
newline
bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
newline
bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
newline
hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
newline
bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
newline
bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
newline
bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
newline
bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
newline
hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
endif
sif (cpuis("LPC54101*"))
group.long 0x0++0x2B
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low. The value in..,1: High. The SSEL3 pin is active high. The value in.."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low. The value in..,1: High. The SSEL2 pin is active high. The value in.."
newline
bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low. The value in..,1: High. The SSEL1 pin is active high. The value in.."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low. The value in..,1: High. The SSEL0 pin is active high. The value in.."
newline
bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
newline
bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
newline
bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
newline
hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. ... 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position"
bitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
newline
bitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
newline
bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
bitfld.long 0x8 3. "TXUR,Transmitter Underrun interrupt flag. This flag applies only to slave mode (Master = 0). In this case  the transmitter must begin sending new data on the next input clock if the transmitter is idle. If that data is not available in the transmitter.." "0,1"
newline
bitfld.long 0x8 2. "RXOV,Receiver Overrun interrupt flag. This flag applies only to slave mode (Master = 0). This flag is set when the beginning of a received character is detected while the receiver buffer is still in use. If this occurs  the receiver buffer contents are.." "0,1"
bitfld.long 0x8 1. "TXRDY,Transmitter Ready flag. When 1  this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT or TXDATCTL until the data is moved to the.." "0,1"
newline
bitfld.long 0x8 0. "RXRDY,Receiver Ready flag. When 1  indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT register." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable" "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when the.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
newline
bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
bitfld.long 0xC 3. "TXUREN,TX underrun interrupt enable. Determines whether an interrupt occurs when a transmitter underrun occurs. This happens in slave mode when there is a need to transmit data when none is available." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated if the.."
newline
bitfld.long 0xC 2. "RXOVEN,RX overrun interrupt enable. Determines whether an interrupt occurs when a receiver overrun occurs. This happens in slave mode when there is a need for the receiver to move newly received data to the RXDAT register when it is already in use. The.." "0: Disabled. No interrupt will be generated when a..,1: Enabled. An interrupt will be generated if a.."
bitfld.long 0xC 1. "TXRDYEN,TX ready interrupt enable. Determines whether an interrupt occurs when the transmitter holding register is available." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when.."
newline
bitfld.long 0xC 0. "RXRDYEN,RX ready interrupt enable. Determines whether an interrupt occurs when receiver data is available." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when.."
line.long 0x10 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x10 8. "MSTIDLE,Writing 1 clears the corresponding bits in the MSTIDLE register." "0,1"
bitfld.long 0x10 5. "SSDEN,Writing 1 clears the corresponding bits in the INTENSET register." "0,1"
newline
bitfld.long 0x10 4. "SSAEN,Writing 1 clears the corresponding bits in the INTENSET register." "0,1"
bitfld.long 0x10 3. "TXUREN,Writing 1 clears the corresponding bits in the INTENSET register." "0,1"
newline
bitfld.long 0x10 2. "RXOVEN,Writing 1 clears the corresponding bits in the INTENSET register." "0,1"
bitfld.long 0x10 1. "TXRDYEN,Writing 1 clears the corresponding bits in the INTENSET register." "0,1"
newline
bitfld.long 0x10 0. "RXRDYEN,Writing 1 clears the corresponding bits in the INTENSET register." "0,1"
line.long 0x14 "RXDAT,SPI Receive Data"
bitfld.long 0x14 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x14 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
newline
bitfld.long 0x14 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x14 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
newline
bitfld.long 0x14 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x14 0.--15. 1. "RXDAT,Receiver Data. This contains the next piece of received data. The number of bits that are used depends on the LEN setting in TXCTL / TXDATCTL."
line.long 0x18 "TXDATCTL,SPI Transmit Data with Control"
hexmask.long.byte 0x18 24.--27. 1. "LEN,Data Length. Specifies the data length from 1 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0 = Data transfer is 1 bit in length. 0x1 = Data transfer is 2 bits in length."
bitfld.long 0x18 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver.Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
newline
bitfld.long 0x18 21. "EOF,End of Frame. Between frames  a delay may be inserted  as defined by the FRAME_DELAY value in the DLY register. The end of a frame may not be particularly meaningful if the FRAME_DELAY value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x18 20. "EOT,End of Transfer. The asserted SSEL will be deasserted at the end of a transfer  and remain so for at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
newline
bitfld.long 0x18 19. "TXSSEL3_N,Transmit Slave Select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default. The active state of the SSEL3 pin is configured by bits in the CFG register." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x18 18. "TXSSEL2_N,Transmit Slave Select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default. The active state of the SSEL2 pin is configured by bits in the CFG register." "0: SSEL2 asserted.,1: SSEL2 not asserted."
newline
bitfld.long 0x18 17. "TXSSEL1_N,Transmit Slave Select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default. The active state of the SSEL1 pin is configured by bits in the CFG register." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x18 16. "TXSSEL0_N,Transmit Slave Select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default. The active state of the SSEL0 pin is configured by bits in the CFG register." "0: SSEL0 asserted.,1: SSEL0 not asserted."
newline
hexmask.long.word 0x18 0.--15. 1. "TXDAT,Transmit Data. This field provides from 1 to 16 bits of data to be transmitted."
line.long 0x1C "TXDAT,SPI Transmit Data"
hexmask.long.word 0x1C 0.--15. 1. "DATA,Transmit Data. This field provides from 4 to 16 bits of data to be transmitted."
line.long 0x20 "TXCTL,SPI Transmit Control"
hexmask.long.byte 0x20 24.--27. 1. "LEN,Data transfer Length."
bitfld.long 0x20 22. "RXIGNORE,Receive Ignore." "0,1"
newline
bitfld.long 0x20 21. "EOF,End of Frame." "0,1"
bitfld.long 0x20 20. "EOT,End of Transfer." "0,1"
newline
bitfld.long 0x20 19. "TXSSEL3_n,Transmit Slave Select 3." "0,1"
bitfld.long 0x20 18. "TXSSEL2_N,Transmit Slave Select 2." "0,1"
newline
bitfld.long 0x20 17. "TXSSEL1_N,Transmit Slave Select 1." "0,1"
bitfld.long 0x20 16. "TXSSEL0_N,Transmit Slave Select 0." "0,1"
line.long 0x24 "DIV,SPI clock Divider"
hexmask.long.word 0x24 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the PCLK for the SPI is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in PCLK/1  the value 1 results in PCLK/2  up to the maximum possible divide value of.."
line.long 0x28 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x28 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x28 5. "SSD,Slave Select Deassert." "0,1"
newline
bitfld.long 0x28 4. "SSA,Slave Select Assert." "0,1"
bitfld.long 0x28 3. "TXUR,Transmitter Underrun interrupt flag." "0,1"
newline
bitfld.long 0x28 2. "RXOV,Receiver Overrun interrupt flag." "0,1"
bitfld.long 0x28 1. "TXRDY,Transmitter Ready flag." "0,1"
newline
bitfld.long 0x28 0. "RXRDY,Receiver Ready flag." "0,1"
endif
tree.end
endif
sif (cpuis("LPC54102*"))
tree "SPI0"
base ad:0x400A4000
group.long 0x0++0x2B
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low. The value in..,1: High. The SSEL3 pin is active high. The value in.."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low. The value in..,1: High. The SSEL2 pin is active high. The value in.."
newline
bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low. The value in..,1: High. The SSEL1 pin is active high. The value in.."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low. The value in..,1: High. The SSEL0 pin is active high. The value in.."
newline
bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
newline
bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
newline
bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
newline
hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. ... 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position"
bitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
newline
bitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
newline
bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
bitfld.long 0x8 3. "TXUR,Transmitter Underrun interrupt flag. This flag applies only to slave mode (Master = 0). In this case  the transmitter must begin sending new data on the next input clock if the transmitter is idle. If that data is not available in the transmitter.." "0,1"
newline
bitfld.long 0x8 2. "RXOV,Receiver Overrun interrupt flag. This flag applies only to slave mode (Master = 0). This flag is set when the beginning of a received character is detected while the receiver buffer is still in use. If this occurs  the receiver buffer contents are.." "0,1"
bitfld.long 0x8 1. "TXRDY,Transmitter Ready flag. When 1  this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT or TXDATCTL until the data is moved to the.." "0,1"
newline
bitfld.long 0x8 0. "RXRDY,Receiver Ready flag. When 1  indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT register." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable" "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when the.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
newline
bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
bitfld.long 0xC 3. "TXUREN,TX underrun interrupt enable. Determines whether an interrupt occurs when a transmitter underrun occurs. This happens in slave mode when there is a need to transmit data when none is available." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated if the.."
newline
bitfld.long 0xC 2. "RXOVEN,RX overrun interrupt enable. Determines whether an interrupt occurs when a receiver overrun occurs. This happens in slave mode when there is a need for the receiver to move newly received data to the RXDAT register when it is already in use. The.." "0: Disabled. No interrupt will be generated when a..,1: Enabled. An interrupt will be generated if a.."
bitfld.long 0xC 1. "TXRDYEN,TX ready interrupt enable. Determines whether an interrupt occurs when the transmitter holding register is available." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when.."
newline
bitfld.long 0xC 0. "RXRDYEN,RX ready interrupt enable. Determines whether an interrupt occurs when receiver data is available." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when.."
line.long 0x10 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x10 8. "MSTIDLE,Writing 1 clears the corresponding bits in the MSTIDLE register." "0,1"
bitfld.long 0x10 5. "SSDEN,Writing 1 clears the corresponding bits in the INTENSET register." "0,1"
newline
bitfld.long 0x10 4. "SSAEN,Writing 1 clears the corresponding bits in the INTENSET register." "0,1"
bitfld.long 0x10 3. "TXUREN,Writing 1 clears the corresponding bits in the INTENSET register." "0,1"
newline
bitfld.long 0x10 2. "RXOVEN,Writing 1 clears the corresponding bits in the INTENSET register." "0,1"
bitfld.long 0x10 1. "TXRDYEN,Writing 1 clears the corresponding bits in the INTENSET register." "0,1"
newline
bitfld.long 0x10 0. "RXRDYEN,Writing 1 clears the corresponding bits in the INTENSET register." "0,1"
line.long 0x14 "RXDAT,SPI Receive Data"
bitfld.long 0x14 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x14 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
newline
bitfld.long 0x14 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x14 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
newline
bitfld.long 0x14 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x14 0.--15. 1. "RXDAT,Receiver Data. This contains the next piece of received data. The number of bits that are used depends on the LEN setting in TXCTL / TXDATCTL."
line.long 0x18 "TXDATCTL,SPI Transmit Data with Control"
hexmask.long.byte 0x18 24.--27. 1. "LEN,Data Length. Specifies the data length from 1 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0 = Data transfer is 1 bit in length. 0x1 = Data transfer is 2 bits in length."
bitfld.long 0x18 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver.Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
newline
bitfld.long 0x18 21. "EOF,End of Frame. Between frames  a delay may be inserted  as defined by the FRAME_DELAY value in the DLY register. The end of a frame may not be particularly meaningful if the FRAME_DELAY value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x18 20. "EOT,End of Transfer. The asserted SSEL will be deasserted at the end of a transfer  and remain so for at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
newline
bitfld.long 0x18 19. "TXSSEL3_N,Transmit Slave Select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default. The active state of the SSEL3 pin is configured by bits in the CFG register." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x18 18. "TXSSEL2_N,Transmit Slave Select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default. The active state of the SSEL2 pin is configured by bits in the CFG register." "0: SSEL2 asserted.,1: SSEL2 not asserted."
newline
bitfld.long 0x18 17. "TXSSEL1_N,Transmit Slave Select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default. The active state of the SSEL1 pin is configured by bits in the CFG register." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x18 16. "TXSSEL0_N,Transmit Slave Select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default. The active state of the SSEL0 pin is configured by bits in the CFG register." "0: SSEL0 asserted.,1: SSEL0 not asserted."
newline
hexmask.long.word 0x18 0.--15. 1. "TXDAT,Transmit Data. This field provides from 1 to 16 bits of data to be transmitted."
line.long 0x1C "TXDAT,SPI Transmit Data"
hexmask.long.word 0x1C 0.--15. 1. "DATA,Transmit Data. This field provides from 4 to 16 bits of data to be transmitted."
line.long 0x20 "TXCTL,SPI Transmit Control"
hexmask.long.byte 0x20 24.--27. 1. "LEN,Data transfer Length."
bitfld.long 0x20 22. "RXIGNORE,Receive Ignore." "0,1"
newline
bitfld.long 0x20 21. "EOF,End of Frame." "0,1"
bitfld.long 0x20 20. "EOT,End of Transfer." "0,1"
newline
bitfld.long 0x20 19. "TXSSEL3_n,Transmit Slave Select 3." "0,1"
bitfld.long 0x20 18. "TXSSEL2_N,Transmit Slave Select 2." "0,1"
newline
bitfld.long 0x20 17. "TXSSEL1_N,Transmit Slave Select 1." "0,1"
bitfld.long 0x20 16. "TXSSEL0_N,Transmit Slave Select 0." "0,1"
line.long 0x24 "DIV,SPI clock Divider"
hexmask.long.word 0x24 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the PCLK for the SPI is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in PCLK/1  the value 1 results in PCLK/2  up to the maximum possible divide value of.."
line.long 0x28 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x28 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x28 5. "SSD,Slave Select Deassert." "0,1"
newline
bitfld.long 0x28 4. "SSA,Slave Select Assert." "0,1"
bitfld.long 0x28 3. "TXUR,Transmitter Underrun interrupt flag." "0,1"
newline
bitfld.long 0x28 2. "RXOV,Receiver Overrun interrupt flag." "0,1"
bitfld.long 0x28 1. "TXRDY,Transmitter Ready flag." "0,1"
newline
bitfld.long 0x28 0. "RXRDY,Receiver Ready flag." "0,1"
tree.end
tree "SPI1"
base ad:0x400A8000
group.long 0x0++0x2B
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low. The value in..,1: High. The SSEL3 pin is active high. The value in.."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low. The value in..,1: High. The SSEL2 pin is active high. The value in.."
newline
bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low. The value in..,1: High. The SSEL1 pin is active high. The value in.."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low. The value in..,1: High. The SSEL0 pin is active high. The value in.."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
newline
bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. ... 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position"
bitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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bitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
bitfld.long 0x8 3. "TXUR,Transmitter Underrun interrupt flag. This flag applies only to slave mode (Master = 0). In this case  the transmitter must begin sending new data on the next input clock if the transmitter is idle. If that data is not available in the transmitter.." "0,1"
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bitfld.long 0x8 2. "RXOV,Receiver Overrun interrupt flag. This flag applies only to slave mode (Master = 0). This flag is set when the beginning of a received character is detected while the receiver buffer is still in use. If this occurs  the receiver buffer contents are.." "0,1"
bitfld.long 0x8 1. "TXRDY,Transmitter Ready flag. When 1  this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT or TXDATCTL until the data is moved to the.." "0,1"
newline
bitfld.long 0x8 0. "RXRDY,Receiver Ready flag. When 1  indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT register." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable" "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when the.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
bitfld.long 0xC 3. "TXUREN,TX underrun interrupt enable. Determines whether an interrupt occurs when a transmitter underrun occurs. This happens in slave mode when there is a need to transmit data when none is available." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated if the.."
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bitfld.long 0xC 2. "RXOVEN,RX overrun interrupt enable. Determines whether an interrupt occurs when a receiver overrun occurs. This happens in slave mode when there is a need for the receiver to move newly received data to the RXDAT register when it is already in use. The.." "0: Disabled. No interrupt will be generated when a..,1: Enabled. An interrupt will be generated if a.."
bitfld.long 0xC 1. "TXRDYEN,TX ready interrupt enable. Determines whether an interrupt occurs when the transmitter holding register is available." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when.."
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bitfld.long 0xC 0. "RXRDYEN,RX ready interrupt enable. Determines whether an interrupt occurs when receiver data is available." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when.."
line.long 0x10 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x10 8. "MSTIDLE,Writing 1 clears the corresponding bits in the MSTIDLE register." "0,1"
bitfld.long 0x10 5. "SSDEN,Writing 1 clears the corresponding bits in the INTENSET register." "0,1"
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bitfld.long 0x10 4. "SSAEN,Writing 1 clears the corresponding bits in the INTENSET register." "0,1"
bitfld.long 0x10 3. "TXUREN,Writing 1 clears the corresponding bits in the INTENSET register." "0,1"
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bitfld.long 0x10 2. "RXOVEN,Writing 1 clears the corresponding bits in the INTENSET register." "0,1"
bitfld.long 0x10 1. "TXRDYEN,Writing 1 clears the corresponding bits in the INTENSET register." "0,1"
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bitfld.long 0x10 0. "RXRDYEN,Writing 1 clears the corresponding bits in the INTENSET register." "0,1"
line.long 0x14 "RXDAT,SPI Receive Data"
bitfld.long 0x14 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x14 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x14 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x14 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x14 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x14 0.--15. 1. "RXDAT,Receiver Data. This contains the next piece of received data. The number of bits that are used depends on the LEN setting in TXCTL / TXDATCTL."
line.long 0x18 "TXDATCTL,SPI Transmit Data with Control"
hexmask.long.byte 0x18 24.--27. 1. "LEN,Data Length. Specifies the data length from 1 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0 = Data transfer is 1 bit in length. 0x1 = Data transfer is 2 bits in length."
bitfld.long 0x18 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver.Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x18 21. "EOF,End of Frame. Between frames  a delay may be inserted  as defined by the FRAME_DELAY value in the DLY register. The end of a frame may not be particularly meaningful if the FRAME_DELAY value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x18 20. "EOT,End of Transfer. The asserted SSEL will be deasserted at the end of a transfer  and remain so for at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x18 19. "TXSSEL3_N,Transmit Slave Select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default. The active state of the SSEL3 pin is configured by bits in the CFG register." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x18 18. "TXSSEL2_N,Transmit Slave Select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default. The active state of the SSEL2 pin is configured by bits in the CFG register." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x18 17. "TXSSEL1_N,Transmit Slave Select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default. The active state of the SSEL1 pin is configured by bits in the CFG register." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x18 16. "TXSSEL0_N,Transmit Slave Select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default. The active state of the SSEL0 pin is configured by bits in the CFG register." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x18 0.--15. 1. "TXDAT,Transmit Data. This field provides from 1 to 16 bits of data to be transmitted."
line.long 0x1C "TXDAT,SPI Transmit Data"
hexmask.long.word 0x1C 0.--15. 1. "DATA,Transmit Data. This field provides from 4 to 16 bits of data to be transmitted."
line.long 0x20 "TXCTL,SPI Transmit Control"
hexmask.long.byte 0x20 24.--27. 1. "LEN,Data transfer Length."
bitfld.long 0x20 22. "RXIGNORE,Receive Ignore." "0,1"
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bitfld.long 0x20 21. "EOF,End of Frame." "0,1"
bitfld.long 0x20 20. "EOT,End of Transfer." "0,1"
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bitfld.long 0x20 19. "TXSSEL3_n,Transmit Slave Select 3." "0,1"
bitfld.long 0x20 18. "TXSSEL2_N,Transmit Slave Select 2." "0,1"
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bitfld.long 0x20 17. "TXSSEL1_N,Transmit Slave Select 1." "0,1"
bitfld.long 0x20 16. "TXSSEL0_N,Transmit Slave Select 0." "0,1"
line.long 0x24 "DIV,SPI clock Divider"
hexmask.long.word 0x24 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the PCLK for the SPI is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in PCLK/1  the value 1 results in PCLK/2  up to the maximum possible divide value of.."
line.long 0x28 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x28 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x28 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x28 4. "SSA,Slave Select Assert." "0,1"
bitfld.long 0x28 3. "TXUR,Transmitter Underrun interrupt flag." "0,1"
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bitfld.long 0x28 2. "RXOV,Receiver Overrun interrupt flag." "0,1"
bitfld.long 0x28 1. "TXRDY,Transmitter Ready flag." "0,1"
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bitfld.long 0x28 0. "RXRDY,Receiver Ready flag." "0,1"
tree.end
endif
sif (cpuis("LPC54113*"))
tree "SPI0"
base ad:0x40086000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
newline
bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
newline
bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
newline
bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
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bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
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rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
newline
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
newline
rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
newline
rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
newline
rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
newline
bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
newline
bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
tree.end
tree "SPI1"
base ad:0x40087000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
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bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
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rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
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bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
newline
bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
tree.end
tree "SPI2"
base ad:0x40088000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
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bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
newline
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
newline
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
newline
bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
newline
bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
tree.end
tree "SPI3"
base ad:0x40089000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
newline
bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
newline
bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
newline
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
newline
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
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bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
newline
rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
tree.end
tree "SPI4"
base ad:0x4008A000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
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bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
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rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
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bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
newline
bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
newline
bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
tree.end
tree "SPI5"
base ad:0x40096000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
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bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
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rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
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bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
tree.end
tree "SPI6"
base ad:0x40097000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
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bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
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rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
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bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
newline
bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
newline
bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
newline
bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
newline
bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
newline
hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
newline
bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
newline
bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
newline
bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
tree.end
tree "SPI7"
base ad:0x40098000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
newline
bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
newline
bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
newline
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
newline
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
newline
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
newline
rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
newline
rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
newline
bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
newline
bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
newline
bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
newline
bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
newline
bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
newline
bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
newline
bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
newline
bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
newline
bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
newline
hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
newline
bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
newline
bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
newline
bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
newline
bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
tree.end
endif
sif (cpuis("LPC54114*"))
tree "SPI0"
base ad:0x40086000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
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bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
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rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
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bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
tree.end
tree "SPI1"
base ad:0x40087000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
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bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
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rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
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bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
tree.end
tree "SPI2"
base ad:0x40088000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
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bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
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rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
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bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
tree.end
tree "SPI3"
base ad:0x40089000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
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bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
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rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
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bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
newline
bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
newline
bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
tree.end
tree "SPI4"
base ad:0x4008A000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
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bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
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rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
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bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
tree.end
tree "SPI5"
base ad:0x40096000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
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bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
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rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
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bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
tree.end
tree "SPI6"
base ad:0x40097000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
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bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
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rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
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bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
newline
bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
newline
bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
tree.end
tree "SPI7"
base ad:0x40098000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
newline
bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
newline
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
newline
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
newline
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
newline
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
newline
rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
newline
rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
newline
rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
newline
bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
newline
bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
newline
bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
newline
bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
newline
bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
newline
bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
newline
bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
newline
bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
newline
bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
newline
hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
newline
bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
newline
bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
newline
bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
newline
bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
tree.end
endif
sif (cpuis("LPC54605*"))
tree "SPI0"
base ad:0x40086000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
newline
bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
newline
bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
newline
bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
newline
bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
newline
hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
newline
rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
newline
bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
newline
bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
newline
bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
newline
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
newline
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
newline
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
newline
bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
newline
rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
newline
rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
newline
rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
newline
bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
newline
bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
newline
bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
newline
bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
newline
bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
newline
bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "SPI1"
base ad:0x40087000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "SPI2"
base ad:0x40088000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "SPI3"
base ad:0x40089000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "SPI4"
base ad:0x4008A000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "SPI5"
base ad:0x40096000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "SPI6"
base ad:0x40097000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "SPI7"
base ad:0x40098000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "SPI8"
base ad:0x40099000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "SPI9"
base ad:0x4009A000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
endif
sif (cpuis("LPC54606*"))
tree "SPI0"
base ad:0x40086000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
newline
bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
newline
bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
newline
bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
newline
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
newline
rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "SPI1"
base ad:0x40087000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "SPI2"
base ad:0x40088000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
newline
bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
newline
bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
newline
bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
newline
bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "SPI3"
base ad:0x40089000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
newline
bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "SPI4"
base ad:0x4008A000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "SPI5"
base ad:0x40096000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "SPI6"
base ad:0x40097000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "SPI7"
base ad:0x40098000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "SPI8"
base ad:0x40099000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
newline
bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
newline
bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "SPI9"
base ad:0x4009A000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
newline
bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
newline
bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
newline
bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
newline
hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
newline
rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
newline
bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
newline
bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
newline
bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
newline
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
newline
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
newline
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
newline
bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
newline
rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
newline
rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
newline
rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
newline
bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
newline
bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
newline
bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
newline
bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
newline
bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
newline
bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
newline
bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
newline
bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
newline
bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
newline
hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
newline
bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
newline
bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
newline
bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
newline
bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
newline
hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
endif
sif (cpuis("LPC54607*"))
tree "SPI0"
base ad:0x40086000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
newline
bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
newline
bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
newline
bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
newline
bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
newline
hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
newline
rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
newline
bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
newline
bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
newline
bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
newline
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "SPI1"
base ad:0x40087000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "SPI2"
base ad:0x40088000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "SPI3"
base ad:0x40089000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "SPI4"
base ad:0x4008A000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "SPI5"
base ad:0x40096000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "SPI6"
base ad:0x40097000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "SPI7"
base ad:0x40098000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "SPI8"
base ad:0x40099000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
newline
bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
newline
bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
newline
bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "SPI9"
base ad:0x4009A000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
newline
rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
newline
bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
newline
bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
newline
bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
newline
hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
newline
bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
newline
bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
newline
bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
newline
bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
endif
sif (cpuis("LPC54608*"))
tree "SPI0"
base ad:0x40086000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
newline
bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
newline
bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
newline
bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
newline
bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "SPI1"
base ad:0x40087000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "SPI2"
base ad:0x40088000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "SPI3"
base ad:0x40089000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
newline
bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
newline
bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
newline
bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "SPI4"
base ad:0x4008A000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
newline
bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "SPI5"
base ad:0x40096000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "SPI6"
base ad:0x40097000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "SPI7"
base ad:0x40098000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "SPI8"
base ad:0x40099000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "SPI9"
base ad:0x4009A000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
newline
bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
newline
bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
newline
hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
endif
sif (cpuis("LPC54616*"))
tree "SPI0"
base ad:0x40086000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
newline
bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
newline
bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
newline
bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
newline
bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
newline
hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
newline
rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
newline
bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
newline
bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
newline
bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
newline
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
newline
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
newline
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
newline
bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
newline
rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
newline
rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
newline
rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
newline
bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
newline
bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
newline
bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
newline
bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
newline
bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
newline
bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
newline
bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
newline
bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
newline
bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
newline
hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
newline
bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
newline
bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
newline
bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
newline
bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
newline
hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "SPI1"
base ad:0x40087000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
newline
bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
newline
bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
newline
bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
newline
bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
newline
hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
newline
rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
newline
bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
newline
bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
newline
bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "SPI2"
base ad:0x40088000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "SPI3"
base ad:0x40089000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "SPI4"
base ad:0x4008A000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "SPI5"
base ad:0x40096000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "SPI6"
base ad:0x40097000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "SPI7"
base ad:0x40098000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
newline
bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
newline
bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
newline
bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "SPI8"
base ad:0x40099000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "SPI9"
base ad:0x4009A000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
newline
bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
newline
bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
newline
bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
newline
hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
newline
bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
newline
bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
newline
bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
newline
bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
newline
hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
endif
sif (cpuis("LPC54618*"))
tree "SPI0"
base ad:0x40086000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
newline
bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
newline
bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
newline
bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
newline
bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
newline
bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
newline
bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
newline
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
newline
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
newline
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
newline
bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
newline
rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
newline
rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
newline
rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
newline
bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
newline
bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
newline
bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
newline
bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
newline
bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
newline
bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
newline
bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
newline
bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
newline
bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
newline
hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
newline
bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
newline
bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
newline
bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
newline
bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
newline
hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "SPI1"
base ad:0x40087000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
newline
bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
newline
bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
newline
bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
newline
bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "SPI2"
base ad:0x40088000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "SPI3"
base ad:0x40089000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "SPI4"
base ad:0x4008A000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
newline
bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
newline
bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
newline
bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "SPI5"
base ad:0x40096000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "SPI6"
base ad:0x40097000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "SPI7"
base ad:0x40098000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "SPI8"
base ad:0x40099000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "SPI9"
base ad:0x4009A000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
newline
bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
newline
bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
newline
bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
newline
bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
endif
sif (cpuis("LPC54628*"))
tree "SPI0"
base ad:0x40086000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
newline
bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
newline
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
newline
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
newline
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
newline
bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
newline
rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
newline
rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
newline
rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
newline
bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
newline
bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
newline
bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
newline
bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
newline
bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
newline
bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
newline
bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
newline
bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
newline
hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
newline
bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
newline
bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "SPI1"
base ad:0x40087000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
newline
bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
newline
bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
newline
bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
newline
bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
newline
bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "SPI2"
base ad:0x40088000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "SPI3"
base ad:0x40089000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "SPI4"
base ad:0x4008A000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "SPI5"
base ad:0x40096000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "SPI6"
base ad:0x40097000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "SPI7"
base ad:0x40098000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
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bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "SPI8"
base ad:0x40099000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
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bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
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bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
newline
bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
newline
bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
newline
bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
newline
bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "SPI9"
base ad:0x4009A000
group.long 0x400++0xF
line.long 0x0 "CFG,SPI Configuration register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity select." "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity select." "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
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bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity select." "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity select." "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
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bitfld.long 0x0 7. "LOOP,Loopback mode enable. Loopback mode applies only to Master mode  and connects transmit and receive data connected together to allow simple software testing." "0: Disabled.,1: Enabled."
bitfld.long 0x0 5. "CPOL,Clock Polarity select." "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
newline
bitfld.long 0x0 4. "CPHA,Clock Phase select." "0: Change. The SPI captures serial data on the..,1: Capture. The SPI changes serial data on the.."
bitfld.long 0x0 3. "LSBF,LSB First mode enable." "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
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bitfld.long 0x0 2. "MASTER,Master mode select." "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
bitfld.long 0x0 0. "ENABLE,SPI enable." "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,SPI Delay register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times."
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,If the EOF flag is set  controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are.."
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hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time.."
line.long 0x8 "STAT,SPI Status. Some status flags can be cleared by writing a 1 to that bit position."
rbitfld.long 0x8 8. "MSTIDLE,Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data." "0,1"
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress  as if the EOT flag had been set prior to the last transmission. This capability is.." "0,1"
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rbitfld.long 0x8 6. "STALLED,Stalled status flag. This indicates whether the SPI is currently in a stall condition." "0,1"
bitfld.long 0x8 5. "SSD,Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software." "0,1"
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bitfld.long 0x8 4. "SSA,Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted  in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy  and allows waking up the device from.." "0,1"
line.long 0xC "INTENSET,SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 8. "MSTIDLEEN,Master idle interrupt enable." "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0xC 5. "SSDEN,Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
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bitfld.long 0xC 4. "SSAEN,Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted." "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."
bitfld.long 0x0 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x424++0x3
line.long 0x0 "DIV,SPI clock Divider"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1  the value 1 results in FCLK/2  up to the maximum possible divide.."
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x0 8. "MSTIDLE,Master Idle status flag." "0,1"
bitfld.long 0x0 5. "SSD,Slave Select Deassert." "0,1"
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bitfld.long 0x0 4. "SSA,Slave Select Assert." "0,1"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
newline
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
newline
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
newline
rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
newline
rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
newline
bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
newline
bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5.."
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of frame. Between frames  a delay may be inserted  as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x0 20. "EOT,End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register." "0: SSEL not deasserted. This piece of data is not..,1: SSEL deasserted. This piece of data is treated.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default." "0: SSEL3 asserted.,1: SSEL3 not asserted."
bitfld.long 0x0 18. "TXSSEL2_N,Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default." "0: SSEL2 asserted.,1: SSEL2 not asserted."
newline
bitfld.long 0x0 17. "TXSSEL1_N,Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default." "0: SSEL1 asserted.,1: SSEL1 not asserted."
bitfld.long 0x0 16. "TXSSEL0_N,Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default." "0: SSEL0 asserted.,1: SSEL0 not asserted."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
newline
bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
newline
bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 20. "SOT,Start of transfer flag." "0,1"
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select for receive." "0,1"
newline
bitfld.long 0x0 18. "RXSSEL2_N,Slave Select for receive." "0,1"
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select for receive." "0,1"
newline
bitfld.long 0x0 16. "RXSSEL0_N,Slave Select for receive." "0,1"
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received data from the FIFO."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
newline
hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
endif
tree.end
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54113*")||cpuis("LPC54114*")||cpuis("LPC54605*")||cpuis("LPC54606*")||cpuis("LPC54607*")||cpuis("LPC54608*")||cpuis("LPC54616*")||cpuis("LPC54618*")||cpuis("LPC54628*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
tree "SPIFI (SPI Flash Interface)"
base ad:0x40080000
group.long 0x0++0x1F
line.long 0x0 "CTRL,SPIFI control register"
bitfld.long 0x0 31. "DMAEN,A 1 in this bit enables the DMA Request output from the SPIFI. Set this bit only when a DMA channel is used to transfer data in peripheral mode. Do not set this bit when a DMA channel is used for memory-to-memory transfers from the SPIFI memory.." "0,1"
bitfld.long 0x0 30. "FBCLK,Feedback clock select." "0: Internal clock. The SPIFI samples read data..,1: Feedback clock. Read data is sampled using a.."
newline
bitfld.long 0x0 29. "RFCLK,Select active clock edge for input data." "0: Rising edge. Read data is sampled on rising..,1: Falling edge. Read data is sampled on falling.."
bitfld.long 0x0 28. "DUAL,Select dual protocol." "0: Quad protocol. This protocol uses IO3:0.,1: Dual protocol. This protocol uses IO1:0."
newline
bitfld.long 0x0 27. "PRFTCH_DIS,Cache prefetching enable. The SPIFI includes an internal cache. A 1 in this bit disables prefetching of cache lines." "0: Enable. Cache prefetching enabled.,1: Disable. Disables prefetching of cache lines."
bitfld.long 0x0 23. "MODE3,SPI Mode 3 select." "0: SCK LOW. The SPIFI drives SCK low after the..,1: SCK HIGH. the SPIFI keeps SCK high after the.."
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bitfld.long 0x0 22. "INTEN,If this bit is 1 when a command ends  the SPIFI will assert its interrupt request output. See INTRQ in the status register for further details." "0,1"
bitfld.long 0x0 21. "D_PRFTCH_DIS,This bit allows conditioning of memory mode prefetches based on the AHB HPROT (instruction/data) access information. A 1 in this register means that the SPIFI will not attempt a speculative prefetch when it encounters data accesses." "0,1"
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hexmask.long.byte 0x0 16.--19. 1. "CSHIGH,This field controls the minimum CS high time  expressed as a number of serial clock periods minus one."
hexmask.long.word 0x0 0.--15. 1. "TIMEOUT,This field contains the number of serial clock periods without the processor reading data in memory mode  which will cause the SPIFI hardware to terminate the command by driving the CS pin high and negating the CMD bit in the Status register."
line.long 0x4 "CMD,SPIFI command register"
hexmask.long.byte 0x4 24.--31. 1. "OPCODE,The opcode of the command (not used for some FRAMEFORM values)."
bitfld.long 0x4 21.--23. "FRAMEFORM,This field controls the opcode and address fields." "?,1: Opcode. Opcode only no address.,2: Opcode one byte. Opcode least significant byte..,3: Opcode two bytes. Opcode two least significant..,4: Opcode three bytes. Opcode three least..,5: Opcode four bytes. Opcode 4 bytes of address.,6: No opcode three bytes. No opcode 3 least..,7: No opcode four bytes. No opcode 4 bytes of.."
newline
bitfld.long 0x4 19.--20. "FIELDFORM,This field controls how the fields of the command are sent." "0: All serial. All fields of the command are serial.,1: Quad/dual data. Data field is quad/dual other..,2: Serial opcode. Opcode field is serial. Other..,3: All quad/dual. All fields of the command are in.."
bitfld.long 0x4 16.--18. "INTLEN,This field controls how many intermediate bytes precede the data. (Each such byte may require 8 or 2 SCK cycles  depending on whether the intermediate field is in serial  2-bit  or 4-bit format.) Intermediate bytes are output by the SPIFI  and.." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 15. "DOUT,If the DATALEN field is not zero  this bit controls the direction of the data:" "0: Input from serial flash.,1: Output to serial flash."
bitfld.long 0x4 14. "POLL,This bit should be written as 1 only with an opcode that a) contains an input data field  and b) causes the serial flash device to return byte status repetitively (e.g.  a Read Status command). When this bit is 1  the SPIFI hardware continues to.." "?,?"
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hexmask.long.word 0x4 0.--13. 1. "DATALEN,Except when the POLL bit in this register is 1  this field controls how many data bytes are in the command. 0 indicates that the command does not contain a data field."
line.long 0x8 "ADDR,SPIFI address register"
hexmask.long 0x8 0.--31. 1. "ADDRESS,Address."
line.long 0xC "IDATA,SPIFI intermediate data register"
hexmask.long 0xC 0.--31. 1. "IDATA,Value of intermediate bytes."
line.long 0x10 "CLIMIT,SPIFI limit register"
hexmask.long 0x10 0.--31. 1. "CLIMIT,Zero-based upper limit of cacheable memory"
line.long 0x14 "DATA,SPIFI data register"
hexmask.long 0x14 0.--31. 1. "DATA,Input or output data"
line.long 0x18 "MCMD,SPIFI memory command register"
hexmask.long.byte 0x18 24.--31. 1. "OPCODE,The opcode of the command (not used for some FRAMEFORM values)."
bitfld.long 0x18 21.--23. "FRAMEFORM,This field controls the opcode and address fields." "?,1: Opcode. Opcode only no address.,2: Opcode one byte. Opcode least-significant byte..,3: Opcode two bytes. Opcode 2 least-significant..,4: Opcode three bytes. Opcode 3 least-significant..,5: Opcode four bytes. Opcode 4 bytes of address.,6: No opcode three bytes. No opcode 3..,7: No opcode 4 bytes of address."
newline
bitfld.long 0x18 19.--20. "FIELDFORM,This field controls how the fields of the command are sent." "0: All serial. All fields of the command are serial.,1: Quad/dual data. Data field is quad/dual other..,2: Serial opcode. Opcode field is serial. Other..,3: All quad/dual. All fields of the command are in.."
bitfld.long 0x18 16.--18. "INTLEN,This field controls how many intermediate bytes precede the data. (Each such byte may require 8 or 2 SCK cycles  depending on whether the intermediate field is in serial  2-bit  or 4-bit format.) Intermediate bytes are output by the SPIFI  and.." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x18 15. "DOUT,This bit should be written as 0." "0,1"
bitfld.long 0x18 14. "POLL,This bit should be written as 0." "0,1"
line.long 0x1C "STAT,SPIFI status register"
sif (cpuis("LPC54113*"))
hexmask.long.byte 0x1C 24.--31. 1. "VERSION,-"
endif
sif (cpuis("LPC54114*"))
hexmask.long.byte 0x1C 24.--31. 1. "VERSION,-"
newline
endif
bitfld.long 0x1C 5. "INTRQ,This bit reflects the SPIFI interrupt request. Write a 1 to this bit to clear it. This bit is set when a CMD was previously 1 and has been cleared due to the deassertion of CS." "0,1"
bitfld.long 0x1C 4. "RESET,Write a 1 to this bit to abort a current command or memory mode. This bit is cleared when the hardware is ready for a new command to be written to the Command register." "0,1"
newline
bitfld.long 0x1C 1. "CMD,This bit is 1 when the Command register is written. It is cleared by a hardware reset  a write to the RESET bit in this register  or the deassertion of CS which indicates that the command has completed communication with the SPI Flash." "0,1"
bitfld.long 0x1C 0. "MCINIT,This bit is set when software successfully writes the Memory Command register  and is cleared by Reset or by writing a 1 to the RESET bit in this register." "0,1"
tree.end
endif
tree "SYSCON (System Configuration)"
base ad:0x40000000
sif (cpuis("LPC54101*"))
group.long 0x0++0x7
line.long 0x0 "SYSMEMREMAP,System memory remap"
bitfld.long 0x0 0.--1. "MAP,System memory remap. Value 0x3 is reserved." "0: Boot Loader Mode. Interrupt vectors are..,1: User RAM Mode. Interrupt vectors are re-mapped..,2: User Flash Mode. Interrupt vectors are not..,?"
line.long 0x4 "AHBMATPRIO,AHB multilayer matrix priority control"
bitfld.long 0x4 16.--17. "PRI_M0,Cortex-M0+ bus priority." "0,1,2,3"
bitfld.long 0x4 14.--15. "PRI_FIFO,System FIFO bus priority" "0,1,2,3"
newline
bitfld.long 0x4 8.--9. "PRI_DMA,DMA controller priority." "0,1,2,3"
bitfld.long 0x4 4.--5. "PRI_SYS,System bus priority." "0,1,2,3"
newline
bitfld.long 0x4 2.--3. "PRI_DCODE,D-Code bus priority." "0,1,2,3"
bitfld.long 0x4 0.--1. "PRI_ICODE,I-Code bus priority. Should be lower than PRI_DCODE for proper operation." "0,1,2,3"
group.long 0x14++0x3
line.long 0x0 "SYSTCKCAL,System tick counter calibration"
bitfld.long 0x0 25. "NOREF,Initial value for the Systick timer." "0,1"
bitfld.long 0x0 24. "SKEW,Initial value for the Systick timer." "0,1"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "CAL,System tick timer calibration value."
group.long 0x1C++0x7
line.long 0x0 "NMISRC,NMI Source Select"
bitfld.long 0x0 31. "NMIENM4,Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQM4." "0,1"
bitfld.long 0x0 30. "NMIENM0,Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQM0." "0,1"
newline
hexmask.long.byte 0x0 8.--13. 1. "IRQM0,The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the Cortex-M0+  if enabled by NMIENM0."
hexmask.long.byte 0x0 0.--5. 1. "IRQM4,The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the Cortex-M4  if enabled by NMIENM4."
line.long 0x4 "ASYNCAPBCTRL,Asynchronous APB Control"
bitfld.long 0x4 0. "ENABLE,Enables the asynchronous APB bridge and subsystem." "0: Disabled. Asynchronous APB bridge is disabled.,1: Enabled. Asynchronous APB bridge is enabled."
group.long 0x40++0xB
line.long 0x0 "SYSRSTSTAT,System reset status register"
bitfld.long 0x0 4. "SYSRST,Status of the software system reset" "0: No System reset detected,1: System reset detected. Writing a one clears this.."
bitfld.long 0x0 3. "BOD,Status of the Brown-out detect reset" "0: No BOD reset detected,1: BOD reset detected. Writing a one clears this.."
newline
bitfld.long 0x0 2. "WDT,Status of the Watchdog reset" "0: No WDT reset detected,1: WDT reset detected. Writing a one clears this.."
bitfld.long 0x0 1. "EXTRST,Status of the external RESET pin. External reset status." "0: No reset event detected.,1: Reset detected. Writing a one clears this reset."
newline
bitfld.long 0x0 0. "POR,POR reset status" "0: No POR detected,1: POR detected. Writing a one clears this reset."
line.long 0x4 "PRESETCTRL0,Peripheral reset control n"
bitfld.long 0x4 27. "ADC0_RST,ADC0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 22. "WWDT_RST,Watchdog timer reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 21. "CRC_RST,CRC generator reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 20. "DMA_RST,DMA reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 19. "GINT_RST,Grouped interrupt (GINT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 18. "PINT_RST,Pin interrupt (PINT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 15. "GPIO1_RST,GPIO1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 14. "GPIO0_RST,GPIO0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 13. "IOCON_RST,IOCON reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 11. "MUX_RST,Input mux reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 8. "FMC_RST,Flash accelerator reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 7. "FLASH_RST,Flash controller reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
line.long 0x8 "PRESETCTRL1,Peripheral reset control n"
bitfld.long 0x8 27. "CT32B4_RST,CT32B 4 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x8 26. "CT32B3_RST,CT32B 3 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x8 22. "CT32B2_RST,CT32B 2 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x8 10. "UTICK_RST,Micro-tick Timer reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x8 9. "FIFO_RST,System FIFO reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x8 2. "SCT0_RST,State configurable timer 0 (SCT0) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x8 1. "RIT_RST,Repetitive interrupt timer (RIT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x8 0. "MRT_RST,Multi-rate timer (MRT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
endif
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
group.long 0x10++0x3
line.long 0x0 "AHBMATPRIO,AHB multilayer matrix priority control"
bitfld.long 0x0 20.--21. "PRI_MCAN2,MCAN2 priority." "0,1,2,3"
bitfld.long 0x0 18.--19. "PRI_MCAN1,MCAN1 priority." "0,1,2,3"
newline
bitfld.long 0x0 16.--17. "PRI_SDIO,SDIO priority." "0,1,2,3"
bitfld.long 0x0 14.--15. "PRI_USB1,USB1 DMA priority." "0,1,2,3"
newline
bitfld.long 0x0 12.--13. "PRI_USB0,USB0 DMA priority." "0,1,2,3"
bitfld.long 0x0 10.--11. "PRI_LCD,LCD DMA priority." "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "PRI_ETH,Ethernet DMA priority." "0,1,2,3"
bitfld.long 0x0 6.--7. "PRI_DMA,DMA controller priority." "0,1,2,3"
newline
bitfld.long 0x0 4.--5. "PRI_SYS,System bus priority." "0,1,2,3"
bitfld.long 0x0 2.--3. "PRI_DCODE,D-Code bus priority." "0,1,2,3"
newline
bitfld.long 0x0 0.--1. "PRI_ICODE,I-Code bus priority." "0,1,2,3"
group.long 0x40++0x3
line.long 0x0 "SYSTCKCAL,System tick counter calibration"
bitfld.long 0x0 25. "NOREF,Initial value for the Systick timer." "0,1"
bitfld.long 0x0 24. "SKEW,Initial value for the Systick timer." "0,1"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "CAL,System tick timer calibration value."
group.long 0x48++0x7
line.long 0x0 "NMISRC,NMI Source Select"
bitfld.long 0x0 31. "NMIENM4,Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQM4." "0,1"
hexmask.long.byte 0x0 0.--5. 1. "IRQM4,The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the Cortex-M4  if enabled by NMIENM4."
line.long 0x4 "ASYNCAPBCTRL,Asynchronous APB Control"
bitfld.long 0x4 0. "ENABLE,Enables the asynchronous APB bridge and subsystem." "0: Disabled. Asynchronous APB bridge is disabled.,1: Enabled. Asynchronous APB bridge is enabled."
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0xC0)++0x3
line.long 0x0 "PIOPORCAP[$1],POR captured value of port n"
hexmask.long 0x0 0.--31. 1. "PIOPORCAP,State of PIOn_31 through PIOn_0 at power-on reset"
repeat.end
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0xD0)++0x3
line.long 0x0 "PIORESCAP[$1],Reset captured value of port n"
hexmask.long 0x0 0.--31. 1. "PIORESCAP,State of PIOn_31 through PIOn_0 for resets other than POR."
repeat.end
group.long 0x100++0xB
line.long 0x0 "PRESETCTRL0,Peripheral reset control n"
bitfld.long 0x0 27. "ADC0_RST,ADC0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 22. "WWDT_RST,Watchdog timer reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x0 21. "CRC_RST,CRC generator reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 20. "DMA_RST,DMA reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x0 19. "GINT_RST,Grouped interrupt (GINT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 18. "PINT_RST,Pin interrupt (PINT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x0 17. "GPIO3_RST,GPIO3 reset control." "0,1"
bitfld.long 0x0 16. "GPIO2_RST,GPIO2 reset control." "0,1"
newline
bitfld.long 0x0 15. "GPIO1_RST,GPIO1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 14. "GPIO0_RST,GPIO0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x0 13. "IOCON_RST,IOCON reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 11. "MUX_RST,Input mux reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x0 10. "SPIFI_RST,SPIFI reset control." "0,1"
line.long 0x4 "PRESETCTRL1,Peripheral reset control n"
bitfld.long 0x4 27. "CTIMER1_RST,CTIMER1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 26. "CTIMER0_RST,CTIMER0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 25. "USB0D_RST,USB0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 22. "CTIMER2_RST,CTIMER2 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function" "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 19. "DMIC_RST,Digital microphone interface reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 18. "FC7_RST,Flexcomm 7 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 17. "FC6_RST,Flexcomm 6 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 16. "FC5_RST,Flexcomm 5 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 15. "FC4_RST,Flexcomm 4 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 14. "FC3_RST,Flexcomm 3 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 13. "FC2_RST,Flexcomm 2 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 12. "FC1_RST,Flexcomm 1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 11. "FC0_RST,Flexcomm 0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 10. "UTICK_RST,Micro-tick Timer reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 8. "MCAN1_RST,0 = Clear reset to this function." "0: Clear reset to this function,?"
bitfld.long 0x4 7. "MCAN0_RST,0 = Clear reset to this function." "0: Clear reset to this function,?"
newline
bitfld.long 0x4 2. "SCT0_RST,State configurable timer 0 (SCT0) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 0. "MRT_RST,Multi-rate timer (MRT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
line.long 0x8 "PRESETCTRL2,Peripheral reset control n"
bitfld.long 0x8 21. "FC10_RST,Flexcomm 10 reset control." "0,1"
bitfld.long 0x8 20. "SC1_RST,Smart card 1 reset control." "0,1"
newline
bitfld.long 0x8 19. "SC0_RST,Smart card 0 reset control." "0,1"
bitfld.long 0x8 18. "SHA_RST,SHA reset control." "0,1"
newline
bitfld.long 0x8 17. "USB0HSL_RST,USB0 HOST slave reset control." "0,1"
bitfld.long 0x8 16. "USB0HMR_RST,USB0 HOST master reset control." "0,1"
newline
bitfld.long 0x8 15. "FC9_RST,Flexcomm 9 reset control." "0,1"
bitfld.long 0x8 14. "FC8_RST,Flexcomm 8 reset control." "0,1"
newline
bitfld.long 0x8 13. "RNG_RST,RNG reset control." "0,1"
bitfld.long 0x8 12. "OTP_RST,OTP reset control." "0,1"
newline
bitfld.long 0x8 10. "GPIO5_RST,GPIO5 reset control." "0,1"
bitfld.long 0x8 9. "GPIO4_RST,GPIO4 reset control." "0,1"
newline
bitfld.long 0x8 8. "ETH_RST,Ethernet reset control." "0,1"
bitfld.long 0x8 7. "EMC_RESET,EMC reset control." "0,1"
newline
bitfld.long 0x8 6. "USB1RAM_RST,USB1 RAM reset control." "0,1"
bitfld.long 0x8 5. "USB1D_RST,USB1 Device reset control." "0,1"
newline
bitfld.long 0x8 4. "USB1H_RST,USB1 Host reset control." "0,1"
bitfld.long 0x8 3. "SDIO_RST,SDIO reset control." "0,1"
newline
bitfld.long 0x8 2. "LCD_RST,LCD reset control." "0,1"
repeat 3. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x120)++0x3
line.long 0x0 "PRESETCTRLSET[$1],Set bits in PRESETCTRLn"
hexmask.long 0x0 0.--31. 1. "RST_SET,Writing ones to this register sets the corresponding bit or bits in the PRESETCTRLn register  if they are implemented. Bits that do not correspond to defined bits in PRESETCTRLn are reserved and only zeroes should be written to them."
repeat.end
repeat 3. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x140)++0x3
line.long 0x0 "PRESETCTRLCLR[$1],Clear bits in PRESETCTRLn"
hexmask.long 0x0 0.--31. 1. "RST_CLR,Writing ones to this register clears the corresponding bit or bits in the PRESETCTRLn register  if they are implemented. Bits that do not correspond to defined bits in PRESETCTRLn are reserved and only zeroes should be written to them."
repeat.end
group.long 0x1F0++0x3
line.long 0x0 "SYSRSTSTAT,System reset status register"
bitfld.long 0x0 4. "SYSRST,Status of the software system reset" "0: No System reset detected,1: System reset detected. Writing a one clears this.."
bitfld.long 0x0 3. "BOD,Status of the Brown-out detect reset" "0: No BOD reset detected,1: BOD reset detected. Writing a one clears this.."
newline
bitfld.long 0x0 2. "WDT,Status of the Watchdog reset" "0: No WDT reset detected,1: WDT reset detected. Writing a one clears this.."
bitfld.long 0x0 1. "EXTRST,Status of the external RESET pin. External reset status" "0: No reset event detected.,1: Reset detected. Writing a one clears this reset."
newline
bitfld.long 0x0 0. "POR,POR reset status" "0: No POR detected,1: POR detected. Writing a one clears this reset."
group.long 0x200++0xB
line.long 0x0 "AHBCLKCTRL0,AHB Clock control n"
bitfld.long 0x0 27. "ADC0,Enables the clock for the ADC0 register interface." "0,1"
bitfld.long 0x0 23. "RTC,Enables the bus clock for the RTC. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 22. "WWDT,Enables the clock for the Watchdog Timer. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 21. "CRC,Enables the clock for the CRC engine. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 20. "DMA,Enables the clock for the DMA controller. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 19. "GINT,Enables the clock for the grouped pin interrupt block. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 18. "PINT,Enables the clock for the pin interrupt block.0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 17. "GPIO3,Enables the clock for the GPIO3 port registers." "0,1"
newline
bitfld.long 0x0 16. "GPIO2,Enables the clock for the GPIO2 port registers." "0,1"
bitfld.long 0x0 15. "GPIO1,Enables the clock for the GPIO1 port registers. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 14. "GPIO0,Enables the clock for the GPIO0 port registers. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 13. "IOCON,Enables the clock for the IOCON block. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 11. "INPUTMUX,Enables the clock for the input muxes. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 10. "SPIFI,Enables the clock for the SPIFI. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 5. "SRAM3,Enables the clock for SRAM3." "0,1"
bitfld.long 0x0 4. "SRAM2,Enables the clock for SRAM2. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 3. "SRAM1,Enables the clock for SRAM1. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 1. "ROM,Enables the clock for the Boot ROM. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
line.long 0x4 "AHBCLKCTRL1,AHB Clock control n"
bitfld.long 0x4 27. "CTIMER1,Enables the clock for timer CTIMER1. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 26. "CTIMER0,Enables the clock for timer CTIMER0. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 25. "USB0D,Enables the clock for the USB0 device interface. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 22. "CTIMER2,Enables the clock for CTIMER 2. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 19. "DMIC,Enables the clock for the digital microphone interface. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 18. "FLEXCOMM7,Enables the clock for Flexcomm 7. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 17. "FLEXCOMM6,Enables the clock for Flexcomm 6. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 16. "FLEXCOMM5,Enables the clock for Flexcomm 5. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 15. "FLEXCOMM4,Enables the clock for Flexcomm 4. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 14. "FLEXCOMM3,Enables the clock for Flexcomm 3. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 13. "FLEXCOMM2,Enables the clock for Flexcomm 2. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 12. "FLEXCOMM1,Enables the clock for Flexcomm 1. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 11. "FLEXCOMM0,Enables the clock for Flexcomm 0. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 10. "UTICK,Enables the clock for the Micro-tick Timer. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 8. "MCAN1,Enables the clock for MCAN1." "0,1"
bitfld.long 0x4 7. "MCAN0,Enables the clock for MCAN0." "0,1"
newline
bitfld.long 0x4 2. "SCT0,Enables the clock for SCT0." "0,1"
bitfld.long 0x4 1. "RIT,Enables the clock for the Repetitive Interrupt Timer." "0,1"
newline
bitfld.long 0x4 0. "MRT,Enables the clock for the Multi-Rate Timer." "0,1"
line.long 0x8 "AHBCLKCTRL2,AHB Clock control n"
bitfld.long 0x8 21. "FLEXCOMM10,Enables the clock for the Flexcomm10 interface." "0,1"
bitfld.long 0x8 20. "SC1,Enables the clock for the Smart card1 interface." "0,1"
newline
bitfld.long 0x8 19. "SC0,Enables the clock for the Smart card0 interface." "0,1"
bitfld.long 0x8 18. "SHA,Enables the clock for the SHA interface." "0,1"
newline
bitfld.long 0x8 17. "USB0HSL,Enables the clock for the USB host slave interface." "0,1"
bitfld.long 0x8 16. "USB0HMR,Enables the clock for the USB host master interface." "0,1"
newline
bitfld.long 0x8 15. "FLEXCOMM9,Enables the clock for the Flexcomm9 interface." "0,1"
bitfld.long 0x8 14. "FLEXCOMM8,Enables the clock for the Flexcomm8 interface." "0,1"
newline
bitfld.long 0x8 13. "RNG,Enables the clock for the RNG interface." "0,1"
bitfld.long 0x8 12. "OTP,Enables the clock for the OTP interface." "0,1"
newline
bitfld.long 0x8 10. "GPIO5,Enables the clock for the GPIO5 interface." "0,1"
bitfld.long 0x8 9. "GPIO4,Enables the clock for the GPIO4 interface." "0,1"
newline
bitfld.long 0x8 8. "ETH,Enables the clock for the ethernet interface." "0,1"
bitfld.long 0x8 7. "EMC,Enables the clock for the EMC interface." "0,1"
newline
bitfld.long 0x8 6. "USB1RAM,Enables the clock for the USB1 RAM interface." "0,1"
bitfld.long 0x8 5. "USB1D,Enables the clock for the USB1 device interface." "0,1"
newline
bitfld.long 0x8 4. "USB1H,Enables the clock for the USB1 host interface." "0,1"
bitfld.long 0x8 3. "SDIO,Enables the clock for the SDIO interface." "0,1"
newline
bitfld.long 0x8 2. "LCD,Enables the clock for the LCD interface." "0,1"
repeat 3. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x220)++0x3
line.long 0x0 "AHBCLKCTRLSET[$1],Set bits in AHBCLKCTRLn"
hexmask.long 0x0 0.--31. 1. "CLK_SET,Writing ones to this register sets the corresponding bit or bits in the AHBCLKCTRLn register  if they are implemented. Bits that do not correspond to defined bits in AHBCLKCTRLn are reserved and only zeroes should be written to them."
repeat.end
repeat 3. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x240)++0x3
line.long 0x0 "AHBCLKCTRLCLR[$1],Clear bits in AHBCLKCTRLn"
hexmask.long 0x0 0.--31. 1. "CLK_CLR,Writing ones to this register clears the corresponding bit or bits in the AHBCLKCTRLn register  if they are implemented. Bits that do not correspond to defined bits in AHBCLKCTRLn are reserved and only zeroes should be written to them."
repeat.end
group.long 0x27C++0xF
line.long 0x0 "STICKCLKSEL,Systick timer clock source selection"
bitfld.long 0x0 0.--2. "SEL,Systick timer clock source selection" "0: Main clock (main_clk),1: Watchdog oscillator (wdt_clk),2: RTC oscillator 32 kHz output (32k_clk),3: FRO 12 MHz (fro_12m),?,?,?,7: None this may be selected to reduce power when.."
line.long 0x4 "MAINCLKSELA,Main clock source select A"
bitfld.long 0x4 0.--1. "SEL,Clock source for main clock source selector A" "0: FRO 12 MHz (fro_12m),1: CLKIN (clk_in),2: Watchdog oscillator (wdt_clk),3: FRO 96 or 48 MHz (fro_hf)"
line.long 0x8 "MAINCLKSELB,Main clock source select B"
bitfld.long 0x8 0.--1. "SEL,Clock source for main clock source selector B. Selects the clock source for the main clock." "0: MAINCLKSELA. Use the clock source selected in..,?,2: System PLL output (pll_clk),3: RTC oscillator 32 kHz output (32k_clk)"
line.long 0xC "CLKOUTSELA,CLKOUT clock source select A"
bitfld.long 0xC 0.--2. "SEL,CLKOUT clock source selection" "0: Main clock (main_clk),1: CLKIN (clk_in),2: Watchdog oscillator (wdt_clk),3: FRO 96 or 48 MHz (fro_hf),4: PLL output (pll_clk),5: USB PLL clock (usb_pll_clk),6: Audio PLL clock (audio_pll_clk),7: RTC oscillator 32 kHz output (32k_clk)"
group.long 0x290++0x3
line.long 0x0 "SYSPLLCLKSEL,PLL clock source select"
bitfld.long 0x0 0.--2. "SEL,System PLL clock source selection." "0: FRO 12 MHz (fro_12m),1: CLKIN (clk_in),?,3: RTC oscillator 32 kHz output (32k_clk),?,?,?,7: None this may be selected in order to reduce.."
group.long 0x298++0x3
line.long 0x0 "AUDPLLCLKSEL,Audio PLL clock source select"
bitfld.long 0x0 0.--2. "SEL,Audio PLL clock source selection." "0: FRO 12 MHz (fro_12m),1: CLKIN (clk_in),?,?,?,?,?,7: None this may be selected in order to reduce.."
group.long 0x2A0++0xF
line.long 0x0 "SPIFICLKSEL,SPIFI clock source select"
bitfld.long 0x0 0.--2. "SEL,System PLL clock source selection" "0: Main clock (main_clk),1: System PLL output (pll_clk),2: USB PLL clock (usb_pll_clk),3: FRO 96 or 48 MHz (fro_hf),4: Audio PLL clock (audio_pll_clk),?,?,7: None this may be selected in order to reduce.."
line.long 0x4 "ADCCLKSEL,ADC clock source select"
bitfld.long 0x4 0.--2. "SEL,ADC clock source selection" "0: FRO 96 or 48 MHz (fro_hf),1: System PLL output (pll_clk),2: USB PLL clock (usb_pll_clk),3: Audio PLL clock (audio_pll_clk),?,?,?,7: None this may be selected in order to reduce.."
line.long 0x8 "USB0CLKSEL,USB0 clock source select"
bitfld.long 0x8 0.--2. "SEL,USB0 device clock source selection." "0: FRO 96 or 48 MHz (fro_hf),1: System PLL output (pll_clk),2: USB PLL clock (usb_pll_clk),?,?,?,?,7: None this may be selected in order to reduce.."
line.long 0xC "USB1CLKSEL,USB1 clock source select"
bitfld.long 0xC 0.--2. "SEL,USB1 PHY clock source selection." "0: Main clock (main_clk),1: System PLL output (pll_clk),2: USB PLL clock (usb_pll_clk),?,?,?,?,7: None this may be selected in order to reduce.."
repeat 10. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2B0)++0x3
line.long 0x0 "FCLKSEL[$1],Flexcomm clock source select"
bitfld.long 0x0 0.--2. "SEL,Flexcomm clock source selection. One per Flexcomm." "0: FRO 12 MHz (fro_12m),1: FRO HF DIV (fro_hf_div),2: Audio PLL clock (audio_pll_clk),3: MCLK pin input when selected in IOCON (mclk_in),4: FRG clock the output of the fractional rate..,?,?,7: None this may be selected in order to reduce.."
repeat.end
group.long 0x2D8++0x3
line.long 0x0 "FCLKSEL10,Flexcomm 10 clock source select"
bitfld.long 0x0 0.--2. "SEL,Flexcomm clock source selection. One per Flexcomm." "0: Main clock (main_clk),1: System PLL output (pll_clk),2: USB PLL clock (usb_pll_clk),3: FRO 96 or 48 MHz (fro_hf),4: Audio PLL clock (audio_pll_clk),?,?,7: None this may be selected in order to reduce.."
group.long 0x2E0++0x3
line.long 0x0 "MCLKCLKSEL,MCLK clock source select"
bitfld.long 0x0 0.--2. "SEL,MCLK source select. This may be used by Flexcomms that support I2S  and/or by the digital microphone subsystem." "0: FRO HF DIV (fro_hf_div),1: Audio PLL clock (audio_pll_clk),?,?,?,?,?,7: None this may be selected in order to reduce.."
group.long 0x2E8++0x13
line.long 0x0 "FRGCLKSEL,Fractional Rate Generator clock source select"
bitfld.long 0x0 0.--2. "SEL,Fractional Rate Generator clock source select." "0: Main clock (main_clk),1: System PLL output (pll_clk),2: FRO 12 MHz (fro_12m),3: FRO 96 or 48 MHz (fro_hf),?,?,?,7: None this may be selected in order to reduce.."
line.long 0x4 "DMICCLKSEL,Digital microphone (DMIC) subsystem clock select"
bitfld.long 0x4 0.--2. "SEL,DMIC (audio subsystem) clock source select." "0: FRO 12 MHz (fro_12m),1: FRO HF DIV (fro_hf_div),2: Audio PLL clock (audio_pll_clk),3: MCLK pin input when selected in IOCON (mclk_in),4: Main clock (main_clk),5: Watchdog oscillator (wdt_clk),?,7: None this may be selected in order to reduce.."
line.long 0x8 "SCTCLKSEL,SCTimer/PWM clock source select"
bitfld.long 0x8 0.--2. "SEL,SCT clock source select." "0: Main clock (main_clk),1: System PLL output (pll_clk),2: FRO 96 or 48 MHz (fro_hf),3: Audio PLL clock (audio_pll_clk),?,?,?,7: None this may be selected in order to reduce.."
line.long 0xC "LCDCLKSEL,LCD clock source select"
bitfld.long 0xC 0.--1. "SEL,LCD clock source select." "0: Main clock (main_clk),1: LCDCLKIN (LCDCLK_EXT),2: FRO 96 or 48 MHz (fro_hf),3: None this may be selected in order to reduce.."
line.long 0x10 "SDIOCLKSEL,SDIO clock source select"
bitfld.long 0x10 0.--2. "SEL,SDIO clock source select." "0: Main clock (main_clk),1: System PLL output (pll_clk),2: USB PLL clock (usb_pll_clk),3: FRO 96 or 48 MHz (fro_hf),4: Audio PLL clock (audio_pll_clk),?,?,7: None this may be selected in order to reduce.."
group.long 0x300++0x17
line.long 0x0 "SYSTICKCLKDIV,SYSTICK clock divider"
bitfld.long 0x0 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x0 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x0 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count." "0,1"
hexmask.long.byte 0x0 0.--7. 1. "DIV,Clock divider value. 0: Divide by 1 up to 255: Divide by 256."
line.long 0x4 "ARMTRACECLKDIV,ARM Trace clock divider"
bitfld.long 0x4 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x4 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x4 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x4 0.--7. 1. "DIV,Clock divider value."
line.long 0x8 "CAN0CLKDIV,MCAN0 clock divider"
bitfld.long 0x8 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x8 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x8 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x8 0.--7. 1. "DIV,Clock divider value."
line.long 0xC "CAN1CLKDIV,MCAN1 clock divider"
bitfld.long 0xC 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0xC 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0xC 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count." "0,1"
hexmask.long.byte 0xC 0.--7. 1. "DIV,Clock divider value. 0: Divide by 1 up to 255: Divide by 256."
line.long 0x10 "SC0CLKDIV,Smartcard0 clock divider"
bitfld.long 0x10 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x10 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x10 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x10 0.--7. 1. "DIV,Clock divider value."
line.long 0x14 "SC1CLKDIV,Smartcard1 clock divider"
bitfld.long 0x14 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x14 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x14 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x14 0.--7. 1. "DIV,Clock divider value."
group.long 0x380++0xB
line.long 0x0 "AHBCLKDIV,AHB clock divider"
bitfld.long 0x0 31. "REQFLAG,Divider status flag." "0,1"
hexmask.long.byte 0x0 0.--7. 1. "DIV,Clock divider value. 0: Divide by 1 up to 255: Divide by 256."
line.long 0x4 "CLKOUTDIV,CLKOUT clock divider"
bitfld.long 0x4 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x4 30. "HALT,Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output." "0,1"
newline
bitfld.long 0x4 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count." "0,1"
hexmask.long.byte 0x4 0.--7. 1. "DIV,Clock divider value. 0: Divide by 1 up to 255: Divide by 256."
line.long 0x8 "FROHFDIV,FROHF clock divider"
bitfld.long 0x8 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x8 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x8 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x8 0.--7. 1. "DIV,Clock divider value."
group.long 0x390++0x13
line.long 0x0 "SPIFICLKDIV,SPIFI clock divider"
bitfld.long 0x0 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x0 30. "HALT,Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output." "0,1"
newline
bitfld.long 0x0 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count." "0,1"
hexmask.long.byte 0x0 0.--7. 1. "DIV,Clock divider value."
line.long 0x4 "ADCCLKDIV,ADC clock divider"
bitfld.long 0x4 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x4 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x4 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x4 0.--7. 1. "DIV,Clock divider value."
line.long 0x8 "USB0CLKDIV,USB0 clock divider"
bitfld.long 0x8 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x8 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x8 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x8 0.--7. 1. "DIV,Clock divider value."
line.long 0xC "USB1CLKDIV,USB1 clock divider"
bitfld.long 0xC 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0xC 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0xC 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0xC 0.--7. 1. "DIV,Clock divider value."
line.long 0x10 "FRGCTRL,Fractional rate divider"
hexmask.long.byte 0x10 8.--15. 1. "MULT,Numerator of the fractional divider. MULT is equal to the programmed value."
hexmask.long.byte 0x10 0.--7. 1. "DIV,Denominator of the fractional divider. DIV is equal to the programmed value +1. Always set to 0xFF to use with the fractional baud rate generator."
group.long 0x3A8++0x17
line.long 0x0 "DMICCLKDIV,DMIC clock divider"
bitfld.long 0x0 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x0 30. "HALT,Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output." "0,1"
newline
bitfld.long 0x0 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count." "0,1"
hexmask.long.byte 0x0 0.--7. 1. "DIV,Clock divider value. 0: Divide by 1 up to 255: Divide by 256."
line.long 0x4 "MCLKDIV,I2S MCLK clock divider"
bitfld.long 0x4 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x4 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x4 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x4 0.--7. 1. "DIV,Clock divider value. 0: Divide by 1 up to 255: Divide by 256."
line.long 0x8 "LCDCLKDIV,LCD clock divider"
bitfld.long 0x8 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x8 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x8 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x8 0.--7. 1. "DIV,Clock divider value."
line.long 0xC "SCTCLKDIV,SCT/PWM clock divider"
bitfld.long 0xC 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0xC 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0xC 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0xC 0.--7. 1. "DIV,Clock divider value."
line.long 0x10 "EMCCLKDIV,EMC clock divider"
bitfld.long 0x10 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x10 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x10 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x10 0.--7. 1. "DIV,Clock divider value."
line.long 0x14 "SDIOCLKDIV,SDIO clock divider"
bitfld.long 0x14 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x14 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x14 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x14 0.--7. 1. "DIV,Clock divider value."
group.long 0x40C++0x7
line.long 0x0 "USB0CLKCTRL,USB0 clock control"
bitfld.long 0x0 4. "PU_DISABLE,Internal pull-up disable control." "0,1"
bitfld.long 0x0 3. "POL_FS_HOST_CLK,USB0 Host USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt." "0,1"
newline
bitfld.long 0x0 2. "AP_FS_HOST_CLK,USB0 Host USB0_NEEDCLK signal control." "0,1"
bitfld.long 0x0 1. "POL_FS_DEV_CLK,USB0 Device USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt." "0,1"
newline
bitfld.long 0x0 0. "AP_FS_DEV_CLK,USB0 Device USB0_NEEDCLK signal control." "0,1"
line.long 0x4 "USB0CLKSTAT,USB0 clock status"
bitfld.long 0x4 1. "HOST_NEED_CLKST,USB0 Host USB0_NEEDCLK signal status." "0,1"
bitfld.long 0x4 0. "DEV_NEED_CLKST,USB0 Device USB0_NEEDCLK signal status." "0,1"
group.long 0x418++0x3
line.long 0x0 "FREQMECTRL,Frequency measure register"
bitfld.long 0x0 31. "PROG,Set this bit to one to initiate a frequency measurement cycle. Hardware clears this bit when the measurement cycle has completed and there is valid capture data in the CAPVAL field (bits 13:0)." "0,1"
hexmask.long.word 0x0 0.--13. 1. "CAPVAL,Stores the capture result which is used to calculate the frequency of the target clock. This field is read-only."
group.long 0x420++0xB
line.long 0x0 "MCLKIO,MCLK input/output control"
bitfld.long 0x0 0. "DIR,MCLK direction control." "0,1"
line.long 0x4 "USB1CLKCTRL,USB1 clock control"
bitfld.long 0x4 4. "HS_DEV_WAKEUP_N,External user wake-up signal for device mode; asserting this signal (active low) will result in exiting the low power mode; input to asynchronous control logic." "0,1"
bitfld.long 0x4 3. "POL_FS_HOST_CLK,USB1 Host need_clock polarity for triggering the USB1 wake-up interrupt." "0,1"
newline
bitfld.long 0x4 2. "AP_FS_HOST_CLK,USB1 Host need_clock signal control." "0,1"
bitfld.long 0x4 1. "POL_FS_DEV_CLK,USB1 Device need_clock polarity for triggering the USB1 wake-up interrupt." "0,1"
newline
bitfld.long 0x4 0. "AP_FS_DEV_CLK,USB1 Device need_clock signal control." "0,1"
line.long 0x8 "USB1CLKSTAT,USB1 clock status"
bitfld.long 0x8 1. "HOST_NEED_CLKST,USB1 Device host USB1_NEEDCLK signal status." "0,1"
bitfld.long 0x8 0. "DEV_NEED_CLKST,USB1 Device USB1_NEEDCLK signal status." "0,1"
group.long 0x444++0x13
line.long 0x0 "EMCSYSCTRL,EMC system control"
bitfld.long 0x0 3. "EMCFBCLKINSEL,External Memory Controller clock select." "0,1"
bitfld.long 0x0 2. "EMCBC,External Memory Controller burst control." "0,1"
newline
bitfld.long 0x0 1. "EMCRD,EMC Reset Disable." "0,1"
bitfld.long 0x0 0. "EMCSC,EMC Shift Control." "0,1"
line.long 0x4 "EMCDYCTRL,EMC clock delay control"
hexmask.long.byte 0x4 8.--12. 1. "FBCLK_DELAY,Programmable delay value for the feedback clock that controls input data sampling."
hexmask.long.byte 0x4 0.--4. 1. "CMD_DELAY,Programmable delay value for EMC outputs in command delayed mode."
line.long 0x8 "EMCCAL,EMC delay chain calibration control"
bitfld.long 0x8 15. "DONE,Measurement completion flag." "0,1"
bitfld.long 0x8 14. "START,Start control bit for the EMC calibration counter." "0,1"
newline
hexmask.long.byte 0x8 0.--7. 1. "CALVALUE,Returns the count of the approximately 50 MHz ring oscillator that occur during 32 clocks of the FRO 12 MHz."
line.long 0xC "ETHPHYSEL,Ethernet PHY Selection"
bitfld.long 0xC 2. "PHY_SEL,PHY interface select." "0,1"
line.long 0x10 "ETHSBDCTRL,Ethernet SBD flow control"
bitfld.long 0x10 0.--1. "SBD_CTRL,Sideband Flow Control." "0,1,2,3"
group.long 0x460++0x3
line.long 0x0 "SDIOCLKCTRL,SDIO CCLKIN phase and delay control"
bitfld.long 0x0 31. "CCLK_SAMPLE_DELAY_ACTIVE,Enables sample delay  as controlled by the CCLK_SAMPLE_DELAY field." "0,1"
hexmask.long.byte 0x0 24.--28. 1. "CCLK_SAMPLE_DELAY,Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in."
newline
bitfld.long 0x0 23. "CCLK_DRV_DELAY_ACTIVE,Enables drive delay  as controlled by the CCLK_DRV_DELAY field." "0,1"
hexmask.long.byte 0x0 16.--20. 1. "CCLK_DRV_DELAY,Programmable delay value by which cclk_in_drv is delayed with regard to cclk_in."
newline
bitfld.long 0x0 7. "PHASE_ACTIVE,sdio_clk by 2  before feeding into ccl_in  cclk_in_sample  and cclk_in_drv." "0,1"
bitfld.long 0x0 2.--3. "CCLK_SAMPLE_PHASE,Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in." "0,1,2,3"
newline
bitfld.long 0x0 0.--1. "CCLK_DRV_PHASE,Programmable delay value by which cclk_in_drv is phase-shifted with regard to cclk_in." "0,1,2,3"
group.long 0x470++0x3
line.long 0x0 "KEYMUXSEL,AES key source selection"
bitfld.long 0x0 7. "LOCK,LOCK stat." "0,1"
bitfld.long 0x0 0.--1. "SEL,PHY interface select." "0,1,2,3"
group.long 0x500++0xF
line.long 0x0 "FROCTRL,FRO oscillator control"
bitfld.long 0x0 30. "HSPDCLK,High speed clock enable." "0,1"
bitfld.long 0x0 25. "USBMODCHG,USB Mode value Change flag." "0,1"
newline
bitfld.long 0x0 24. "USBCLKADJ,USB clock adjust mode." "0,1"
hexmask.long.byte 0x0 16.--23. 1. "FREQTRIM,Frequency trim."
newline
bitfld.long 0x0 14. "SEL,Select the FRO HF output frequency." "0,1"
line.long 0x4 "SYSOSCCTRL,System oscillator control"
bitfld.long 0x4 1. "FREQRANGE,Determines frequency range for system oscillator." "0,1"
line.long 0x8 "WDTOSCCTRL,Watchdog oscillator control"
hexmask.long.byte 0x8 5.--9. 1. "FREQSEL,Frequency select."
hexmask.long.byte 0x8 0.--4. 1. "DIVSEL,Divider select."
line.long 0xC "RTCOSCCTRL,RTC oscillator 32 kHz output control"
bitfld.long 0xC 0. "EN,RTC 32 kHz clock enable." "0,1"
group.long 0x51C++0x7
line.long 0x0 "USBPLLCTRL,USB PLL control"
bitfld.long 0x0 14. "FBSEL,Feedback divider input clock control." "0,1"
bitfld.long 0x0 13. "BYPASS,Input clock bypass control." "0: CCO clock is sent to post dividers..,1: PLL input clock is sent to post dividers.."
newline
bitfld.long 0x0 12. "DIRECT,Direct CCO clock output control." "0: CCO Clock signal goes through post divider.,1: CCO Clock signal goes directly to output(s).."
bitfld.long 0x0 10.--11. "NSEL,PLL feedback Divider value." "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "PSEL,PLL Divider value." "0,1,2,3"
hexmask.long.byte 0x0 0.--7. 1. "MSEL,PLL feedback Divider value."
line.long 0x4 "USBPLLSTAT,USB PLL status"
bitfld.long 0x4 0. "LOCK,USBPLL lock indicator." "0,1"
group.long 0x580++0x13
line.long 0x0 "SYSPLLCTRL,System PLL control"
bitfld.long 0x0 20. "DIRECTO,PLL0 direct output enable." "0: Disabled. The PLL output divider (P divider) is..,1: Enabled. The PLL output divider (P divider) is.."
bitfld.long 0x0 19. "DIRECTI,PLL0 direct input enable." "0,1"
newline
bitfld.long 0x0 17. "UPLIMOFF,Disable upper frequency limiter." "0,1"
bitfld.long 0x0 15. "BYPASS,PLL bypass control." "0: Bypass disabled. PLL CCO is sent to the PLL..,1: Bypass enabled. PLL input clock is sent directly.."
newline
hexmask.long.byte 0x0 10.--14. 1. "SELP,Bandwidth select P value."
hexmask.long.byte 0x0 4.--9. 1. "SELI,Bandwidth select I value."
newline
hexmask.long.byte 0x0 0.--3. 1. "SELR,Bandwidth select R value."
line.long 0x4 "SYSPLLSTAT,PLL status"
bitfld.long 0x4 0. "LOCK,PLL lock indicator." "0,1"
line.long 0x8 "SYSPLLNDEC,PLL N divider"
bitfld.long 0x8 10. "NREQ,NDEC reload request." "0,1"
hexmask.long.word 0x8 0.--9. 1. "NDEC,Decoded N-divider coefficient value."
line.long 0xC "SYSPLLPDEC,PLL P divider"
bitfld.long 0xC 7. "PREQ,." "0,1"
hexmask.long.byte 0xC 0.--6. 1. "PDEC,Decoded P-divider coefficient value."
line.long 0x10 "SYSPLLMDEC,System PLL M divider"
bitfld.long 0x10 17. "MREQ,MDEC reload request." "0,1"
hexmask.long.tbyte 0x10 0.--16. 1. "MDEC,Decoded M-divider coefficient value."
group.long 0x5A0++0x17
line.long 0x0 "AUDPLLCTRL,Audio PLL control"
bitfld.long 0x0 20. "DIRECTO,PLL direct output enable" "0: Disabled. The PLL output divider (P divider) is..,1: Enabled. The PLL output divider (P divider) is.."
bitfld.long 0x0 19. "DIRECTI,PLL direct input enable." "0,1"
newline
bitfld.long 0x0 17. "UPLIMOFF,Disable upper frequency limiter." "0,1"
bitfld.long 0x0 15. "BYPASS,PLL bypass control." "0: Bypass disabled. PLL CCO is sent to the PLL..,1: Bypass enabled. PLL input clock is sent directly.."
newline
hexmask.long.byte 0x0 10.--14. 1. "SELP,."
hexmask.long.byte 0x0 4.--9. 1. "SELI,Bandwidth select I value."
newline
hexmask.long.byte 0x0 0.--3. 1. "SELR,Bandwidth select R value."
line.long 0x4 "AUDPLLSTAT,Audio PLL status"
bitfld.long 0x4 0. "LOCK,PLL lock indicator." "0,1"
line.long 0x8 "AUDPLLNDEC,Audio PLL N divider"
bitfld.long 0x8 10. "NREQ,NDEC reload request." "0,1"
hexmask.long.word 0x8 0.--9. 1. "NDEC,Decoded N-divider coefficient value."
line.long 0xC "AUDPLLPDEC,Audio PLL P divider"
bitfld.long 0xC 7. "PREQ,PDEC reload request." "0,1"
hexmask.long.byte 0xC 0.--6. 1. "PDEC,Decoded P-divider coefficient value."
line.long 0x10 "AUDPLLMDEC,Audio PLL M divider"
bitfld.long 0x10 17. "MREQ,MDEC reload request." "0,1"
hexmask.long.tbyte 0x10 0.--16. 1. "MDEC,Decoded M-divider coefficient value."
line.long 0x14 "AUDPLLFRAC,Audio PLL fractional divider control"
bitfld.long 0x14 23. "SEL_EXT,Select fractional divider." "0,1"
bitfld.long 0x14 22. "REQ,Writing 1 to REQ signal loads CTRL value into fractional wrapper modulator." "0,1"
newline
hexmask.long.tbyte 0x14 0.--21. 1. "CTRL,PLL fractional divider control word"
group.long 0x600++0x7
line.long 0x0 "PDSLEEPCFG0,Sleep configuration register"
bitfld.long 0x0 29. "PDEN_VD6,Power control for EEPROM." "0,1"
bitfld.long 0x0 28. "PDEN_VD5,Power control both USB0 PHY and USB1 PHY." "0,1"
newline
bitfld.long 0x0 27. "PDEN_VD4,Power control for all SRAMs and ROM." "0,1"
bitfld.long 0x0 26. "PDEN_VD3,Power control for all PLLs." "0,1"
newline
bitfld.long 0x0 23. "PDEN_VREFP,VREFP to the ADC must be enabled for the ADC to work (also enable/disable bit 9  10  and 19)." "0,1"
bitfld.long 0x0 22. "PDEN_SYS_PLL,System PLL (PLL0) power (also enable/disable bit 26)." "0,1"
newline
bitfld.long 0x0 21. "PDEN_USB0_PHY,USB0 PHY power (also enable/disable bit 28)." "0,1"
bitfld.long 0x0 20. "PDEN_WDT_OSC,Watchdog oscillator." "0,1"
newline
bitfld.long 0x0 19. "PDEN_VDDA,Vdda to the ADC  must be enabled for the ADC to work (also enable/disable bit 9  10  and 23)." "0,1"
bitfld.long 0x0 17. "PDEN_ROM,ROM (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 16. "PDEN_USB_RAM,PDEN_USB_SRAM controls USB_RAM (also enable/disable bit 27)." "0,1"
bitfld.long 0x0 15. "PDEN_SRAM1_2_3,PDEN_SRAM1_2_3 controls SRAM1  SRAM2  and SRAM3 (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 14. "PDEN_SRAM0,PDEN_SRAM0 controls SRAM0 (also enable/disable bit 27)." "0,1"
bitfld.long 0x0 13. "PDEN_SRAMX,PDEN_SRAMX controls SRAMX (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 10. "PDEN_ADC0,ADC power." "0,1"
bitfld.long 0x0 9. "PDEN_VD2_ANA,Analog supply for System Oscillator (also enable/disable bit 3 in PDRUNCFG1 register)  Temperature Sensor (also  enable/disable bit 6)  ADC (also  enable/disable bits 10  19  and 23)." "0,1"
newline
bitfld.long 0x0 8. "PDEN_BOD_INTR,Brown-out Detect interrupt." "0,1"
bitfld.long 0x0 7. "PDEN_BOD_RST,Brown-out Detect reset." "0,1"
newline
bitfld.long 0x0 6. "PDEN_TS,Temp sensor." "0,1"
bitfld.long 0x0 4. "PDEN_FRO,FRO oscillator." "0,1"
line.long 0x4 "PDSLEEPCFG1,Sleep configuration register"
bitfld.long 0x4 7. "PDEN_RNG,Random Number Generator Power." "0,1"
bitfld.long 0x4 3. "PDEN_SYSOSC,System Oscillator Power (also  enable/disable bit 9 in PDRUNCFG0 register)." "0,1"
newline
bitfld.long 0x4 2. "PDEN_AUD_PLL,Audio PLL (PLL2) power and fractional divider (also  enable/disable bit 26 in PDRUNCFG0 register)." "0,1"
bitfld.long 0x4 1. "PDEN_USB1_PLL,USB PLL (PLL1) power (also  enable/disable bit 26 in PDRUNCFG0 register)." "0,1"
newline
bitfld.long 0x4 0. "PDEN_USB1_PHY,USB1 high speed PHY (also  enable/disable bit 28 in PDRUNCFG0 register)." "0,1"
group.long 0x610++0x7
line.long 0x0 "PDRUNCFG0,Power configuration register"
bitfld.long 0x0 29. "PDEN_VD6,Power control for OTP and SRAMX from address 0x00010000 to 0x0002FFFF." "0,1"
bitfld.long 0x0 28. "PDEN_VD5,Power control both USB0 PHY and USB1 PHY." "0,1"
newline
bitfld.long 0x0 27. "PDEN_VD4,Power control for all SRAMs and ROM." "0,1"
bitfld.long 0x0 26. "PDEN_VD3,Power control for all PLLs." "0,1"
newline
bitfld.long 0x0 23. "PDEN_VREFP,VREFP to the ADC must be enabled for the ADC to work (also enable/disable bit 9  10  and 19)." "0,1"
bitfld.long 0x0 22. "PDEN_SYS_PLL,System PLL (PLL0) power (also enable/disable bit 26)." "0,1"
newline
bitfld.long 0x0 21. "PDEN_USB0_PHY,USB0 PHY power (also enable/disable bit 28)." "0,1"
bitfld.long 0x0 20. "PDEN_WDT_OSC,Watchdog oscillator." "0,1"
newline
bitfld.long 0x0 19. "PDEN_VDDA,Vdda to the ADC  must be enabled for the ADC to work (also enable/disable bit 9  10  and 23)." "0,1"
bitfld.long 0x0 17. "PDEN_ROM,ROM (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 16. "PDEN_USB_RAM,PDEN_USB_SRAM controls USB_RAM (also enable/disable bit 27)." "0,1"
bitfld.long 0x0 15. "PDEN_SRAM1_2_3,PDEN_SRAM1_2_3 controls SRAM1  SRAM2  and SRAM3 (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 14. "PDEN_SRAM0,PDEN_SRAM0 controls SRAM0 (also enable/disable bit 27)." "0,1"
bitfld.long 0x0 13. "PDEN_SRAMX,PPDEN_SRAMX controls only SRAMX address 0x0 to 0x0000FFFF.Bit 29 (PDEN_VD6) controls SRAMX address 0x00010000 to 0x0002FFFF.." "0,1"
newline
bitfld.long 0x0 10. "PDEN_ADC0,ADC power." "0,1"
bitfld.long 0x0 9. "PDEN_VD2_ANA,Analog supply for System Oscillator (also enable/disable bit 3 in PDRUNCFG1 register)  Temperature Sensor (also  enable/disable bit 6)  ADC (also  enable/disable bits 10  19  and 23)." "0,1"
newline
bitfld.long 0x0 8. "PDEN_BOD_INTR,Brown-out Detect interrupt." "0,1"
bitfld.long 0x0 7. "PDEN_BOD_RST,Brown-out Detect reset." "0,1"
newline
bitfld.long 0x0 6. "PDEN_TS,Temp sensor." "0,1"
bitfld.long 0x0 4. "PDEN_FRO,FRO oscillator." "0,1"
line.long 0x4 "PDRUNCFG1,Power configuration register"
bitfld.long 0x4 7. "PDEN_RNG,Random Number Generator Power." "0,1"
bitfld.long 0x4 3. "PDEN_SYSOSC,System Oscillator Power (also  enable/disable bit 9 in PDRUNCFG0 register)." "0,1"
newline
bitfld.long 0x4 2. "PDEN_AUD_PLL,Audio PLL (PLL2) power and fractional divider (also  enable/disable bit 26 in PDRUNCFG0 register)." "0,1"
bitfld.long 0x4 1. "PDEN_USB1_PLL,USB PLL (PLL1) power (also  enable/disable bit 26 in PDRUNCFG0 register)." "0,1"
newline
bitfld.long 0x4 0. "PDEN_USB1_PHY,USB1 high speed PHY (also  enable/disable bit 28 in PDRUNCFG0 register)." "0,1"
group.long 0x620++0x7
line.long 0x0 "PDRUNCFGSET0,Power configuration set register"
bitfld.long 0x0 29. "PDEN_VD6,Power control for EEPROM." "0,1"
bitfld.long 0x0 28. "PDEN_VD5,Power control both USB0 PHY and USB1 PHY." "0,1"
newline
bitfld.long 0x0 27. "PDEN_VD4,Power control for all SRAMs and ROM." "0,1"
bitfld.long 0x0 26. "PDEN_VD3,Power control for all PLLs." "0,1"
newline
bitfld.long 0x0 23. "PDEN_VREFP,VREFP to the ADC must be enabled for the ADC to work (also enable/disable bit 9  10  and 19)." "0,1"
bitfld.long 0x0 22. "PDEN_SYS_PLL,System PLL (PLL0) power (also enable/disable bit 26)." "0,1"
newline
bitfld.long 0x0 21. "PDEN_USB0_PHY,USB0 PHY power (also enable/disable bit 28)." "0,1"
bitfld.long 0x0 20. "PDEN_WDT_OSC,Watchdog oscillator." "0,1"
newline
bitfld.long 0x0 19. "PDEN_VDDA,Vdda to the ADC  must be enabled for the ADC to work (also enable/disable bit 9  10  and 23)." "0,1"
bitfld.long 0x0 17. "PDEN_ROM,ROM (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 16. "PDEN_USB_RAM,PDEN_USB_SRAM controls USB_RAM (also enable/disable bit 27)." "0,1"
bitfld.long 0x0 15. "PDEN_SRAM1_2_3,PDEN_SRAM1_2_3 controls SRAM1  SRAM2  and SRAM3 (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 14. "PDEN_SRAM0,PDEN_SRAM0 controls SRAM0 (also enable/disable bit 27)." "0,1"
bitfld.long 0x0 13. "PDEN_SRAMX,PDEN_SRAMX controls SRAMX (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 10. "PDEN_ADC0,ADC power." "0,1"
bitfld.long 0x0 9. "PDEN_VD2_ANA,Analog supply for System Oscillator (also enable/disable bit 3 in PDRUNCFG1 register)  Temperature Sensor (also  enable/disable bit 6)  ADC (also  enable/disable bits 10  19  and 23)." "0,1"
newline
bitfld.long 0x0 8. "PDEN_BOD_INTR,Brown-out Detect interrupt." "0,1"
bitfld.long 0x0 7. "PDEN_BOD_RST,Brown-out Detect reset." "0,1"
newline
bitfld.long 0x0 6. "PDEN_TS,Temp sensor." "0,1"
bitfld.long 0x0 4. "PDEN_FRO,FRO oscillator." "0,1"
line.long 0x4 "PDRUNCFGSET1,Power configuration set register"
bitfld.long 0x4 7. "PDEN_RNG,Random Number Generator Power." "0,1"
bitfld.long 0x4 3. "PDEN_SYSOSC,System Oscillator Power (also  enable/disable bit 9 in PDRUNCFG0 register)." "0,1"
newline
bitfld.long 0x4 2. "PDEN_AUD_PLL,Audio PLL (PLL2) power and fractional divider (also  enable/disable bit 26 in PDRUNCFG0 register)." "0,1"
bitfld.long 0x4 1. "PDEN_USB1_PLL,USB PLL (PLL1) power (also  enable/disable bit 26 in PDRUNCFG0 register)." "0,1"
newline
bitfld.long 0x4 0. "PDEN_USB1_PHY,USB1 high speed PHY (also  enable/disable bit 28 in PDRUNCFG0 register)." "0,1"
group.long 0x630++0x7
line.long 0x0 "PDRUNCFGCLR0,Power configuration clear register"
bitfld.long 0x0 29. "PDEN_VD6,Power control for EEPROM." "0,1"
bitfld.long 0x0 28. "PDEN_VD5,Power control both USB0 PHY and USB1 PHY." "0,1"
newline
bitfld.long 0x0 27. "PDEN_VD4,Power control for all SRAMs and ROM." "0,1"
bitfld.long 0x0 26. "PDEN_VD3,Power control for all PLLs." "0,1"
newline
bitfld.long 0x0 23. "PDEN_VREFP,VREFP to the ADC must be enabled for the ADC to work (also enable/disable bit 9  10  and 19)." "0,1"
bitfld.long 0x0 22. "PDEN_SYS_PLL,System PLL (PLL0) power (also enable/disable bit 26)." "0,1"
newline
bitfld.long 0x0 21. "PDEN_USB0_PHY,USB0 PHY power (also enable/disable bit 28)." "0,1"
bitfld.long 0x0 20. "PDEN_WDT_OSC,Watchdog oscillator." "0,1"
newline
bitfld.long 0x0 19. "PDEN_VDDA,Vdda to the ADC  must be enabled for the ADC to work (also enable/disable bit 9  10  and 23)." "0,1"
bitfld.long 0x0 17. "PDEN_ROM,ROM (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 16. "PDEN_USB_RAM,PDEN_USB_SRAM controls USB_RAM (also enable/disable bit 27)." "0,1"
bitfld.long 0x0 15. "PDEN_SRAM1_2_3,PDEN_SRAM1_2_3 controls SRAM1  SRAM2  and SRAM3 (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 14. "PDEN_SRAM0,PDEN_SRAM0 controls SRAM0 (also enable/disable bit 27)." "0,1"
bitfld.long 0x0 13. "PDEN_SRAMX,PDEN_SRAMX controls SRAMX (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 10. "PDEN_ADC0,ADC power." "0,1"
bitfld.long 0x0 9. "PDEN_VD2_ANA,Analog supply for System Oscillator (also enable/disable bit 3 in PDRUNCFG1 register)  Temperature Sensor (also  enable/disable bit 6)  ADC (also  enable/disable bits 10  19  and 23)." "0,1"
newline
bitfld.long 0x0 8. "PDEN_BOD_INTR,Brown-out Detect interrupt." "0,1"
bitfld.long 0x0 7. "PDEN_BOD_RST,Brown-out Detect reset." "0,1"
newline
bitfld.long 0x0 6. "PDEN_TS,Temp sensor." "0,1"
bitfld.long 0x0 4. "PDEN_FRO,FRO oscillator." "0,1"
line.long 0x4 "PDRUNCFGCLR1,Power configuration clear register"
bitfld.long 0x4 7. "PDEN_RNG,Random Number Generator Power." "0,1"
bitfld.long 0x4 3. "PDEN_SYSOSC,System Oscillator Power (also  enable/disable bit 9 in PDRUNCFG0 register)." "0,1"
newline
bitfld.long 0x4 2. "PDEN_AUD_PLL,Audio PLL (PLL2) power and fractional divider (also  enable/disable bit 26 in PDRUNCFG0 register)." "0,1"
bitfld.long 0x4 1. "PDEN_USB1_PLL,USB PLL (PLL1) power (also  enable/disable bit 26 in PDRUNCFG0 register)." "0,1"
newline
bitfld.long 0x4 0. "PDEN_USB1_PHY,USB1 high speed PHY (also  enable/disable bit 28 in PDRUNCFG0 register)." "0,1"
group.long 0x680++0x7
line.long 0x0 "STARTER0,Start logic 0 wake-up enable register"
bitfld.long 0x0 30. "FLEXCOMM10,Flexcomm10 peripheral interrupt wake-up." "0,1"
bitfld.long 0x0 29. "RTC,RTC interrupt alarm and wake-up timer." "0,1"
newline
bitfld.long 0x0 28. "USB0,USB function interrupt wake-up." "0,1"
bitfld.long 0x0 27. "USB0_NEEDCLK,USB activity interrupt wake-up." "0,1"
newline
bitfld.long 0x0 26. "HWVAD,Hardware voice activity detect interrupt wake-up." "0,1"
bitfld.long 0x0 25. "DMIC,Digital microphone interrupt wake-up." "0,1"
newline
bitfld.long 0x0 21. "FLEXCOMM7,Flexcomm7 peripheral interrupt wake-up." "0,1"
bitfld.long 0x0 20. "FLEXCOMM6,Flexcomm6 peripheral interrupt wake-up." "0,1"
newline
bitfld.long 0x0 19. "FLEXCOMM5,Flexcomm5 peripheral interrupt wake-up." "0,1"
bitfld.long 0x0 18. "FLEXCOMM4,Flexcomm4 peripheral interrupt wake-up." "0,1"
newline
bitfld.long 0x0 17. "FLEXCOMM3,Flexcomm3 peripheral interrupt wake-up." "0,1"
bitfld.long 0x0 16. "FLEXCOMM2,Flexcomm2 peripheral interrupt wake-up." "0,1"
newline
bitfld.long 0x0 15. "FLEXCOMM1,Flexcomm1 peripheral interrupt wake-up." "0,1"
bitfld.long 0x0 14. "FLEXCOMM0,Flexcomm0 peripheral interrupt wake-up." "0,1"
newline
bitfld.long 0x0 8. "UTICK,Micro-tick Timer wake-up." "0,1"
bitfld.long 0x0 7. "PIN_INT3,GPIO pin interrupt 3 wake-up." "0,1"
newline
bitfld.long 0x0 6. "PIN_INT2,GPIO pin interrupt 2 wake-up." "0,1"
bitfld.long 0x0 5. "PIN_INT1,GPIO pin interrupt 1 wake-up." "0,1"
newline
bitfld.long 0x0 4. "PIN_INT0,GPIO pin interrupt 0 wake-up." "0,1"
bitfld.long 0x0 3. "GINT1,Group interrupt 1 wake-up." "0,1"
newline
bitfld.long 0x0 2. "GINT0,Group interrupt 0 wake-up." "0,1"
bitfld.long 0x0 1. "DMA,DMA wake-up." "0,1"
newline
bitfld.long 0x0 0. "WDT_BOD,WWDT and BOD interrupt wake-up." "0,1"
line.long 0x4 "STARTER1,Start logic 0 wake-up enable register"
bitfld.long 0x4 16. "USB1_ACT,USB 1 activity wake-up." "0,1"
bitfld.long 0x4 15. "USB1,USB 1 wake-up." "0,1"
newline
bitfld.long 0x4 9. "FLEXCOMM9,Flexcomm Interface 9 wake-up." "0,1"
bitfld.long 0x4 8. "FLEXCOMM8,Flexcomm Interface 8 wake-up." "0,1"
newline
bitfld.long 0x4 3. "PINT7,GPIO pin interrupt 7 wake-up." "0,1"
bitfld.long 0x4 2. "PINT6,GPIO pin interrupt 6 wake-up." "0,1"
newline
bitfld.long 0x4 1. "PINT5,GPIO pin interrupt 5 wake-up." "0,1"
bitfld.long 0x4 0. "PINT4,GPIO pin interrupt 4 wake-up." "0,1"
group.long 0x780++0x3
line.long 0x0 "HWWAKE,Configures special cases of hardware wake-up"
bitfld.long 0x0 3. "WAKEDMA,Wake for DMA. When 1  DMA being busy will cause peripheral clocking to remain running until DMA completes. This is generally used in conjunction with bit 1 and/or 2 in order to prevent peripheral clocking from being shut down as soon as the cause.." "0,1"
bitfld.long 0x0 2. "WAKEDMIC,Wake for Digital Microphone. When 1  the digital microphone input FIFO reaching the level specified by TRIGLVL of either channel will cause peripheral clocking to wake up temporarily while the related status is asserted." "0,1"
newline
bitfld.long 0x0 1. "FCWAKE,Wake for Flexcomms. When 1  any Flexcomm FIFO reaching the level specified by its own TXLVL will cause peripheral clocking to wake up temporarily while the related status is asserted." "0,1"
bitfld.long 0x0 0. "FORCEWAKE,Force peripheral clocking to stay on during Deep Sleep and Power-down modes. When 1  clocking to peripherals is prevented from being shut down when the CPU enters Deep Sleep and Power-down modes. This is intended to allow a coprocessor to.." "0,1"
group.long 0xE04++0x3
line.long 0x0 "AUTOCGOR,Auto Clock-Gate Override Register"
bitfld.long 0x0 4. "RAM3,When 1  automatic clock gating for RAM1 are turned off." "0,1"
bitfld.long 0x0 3. "RAM2,When 1  automatic clock gating for RAM1 are turned off." "0,1"
newline
bitfld.long 0x0 2. "RAM1,When 1  automatic clock gating for RAM1 are turned off." "0,1"
bitfld.long 0x0 1. "RAM0X,When 1  automatic clock gating for RAMX and RAM0 are turned off." "0,1"
rgroup.long 0xFF4++0xB
line.long 0x0 "JTAGIDCODE,JTAG ID code register"
hexmask.long 0x0 0.--31. 1. "JTAGID,JTAG ID code."
line.long 0x4 "DEVICE_ID0,Part ID register"
hexmask.long 0x4 0.--31. 1. "PARTID,Part ID"
line.long 0x8 "DEVICE_ID1,Boot ROM and die revision register"
hexmask.long 0x8 0.--31. 1. "REVID,Revision."
group.long 0x20044++0x3
line.long 0x0 "BODCTRL,Brown-Out Detect control"
bitfld.long 0x0 7. "BODINTSTAT,BOD interrupt status. When 1  a BOD interrupt has occurred. Cleared by writing 1 to this bit." "0,1"
bitfld.long 0x0 6. "BODRSTSTAT,BOD reset status. When 1  a BOD reset has occurred. Cleared by writing 1 to this bit." "0,1"
newline
bitfld.long 0x0 5. "BODINTENA,BOD interrupt enable" "0: Disable interrupt function.,1: Enable interrupt function."
bitfld.long 0x0 3.--4. "BODINTLEV,BOD interrupt level" "0: Level 0: 2.05 V,1: Level 1: 2.45 V,2: Level 2: 2.75 V,3: Level 3: 3.05 V"
newline
bitfld.long 0x0 2. "BODRSTENA,BOD reset enable" "0: Disable reset function.,1: Enable reset function."
bitfld.long 0x0 0.--1. "BODRSTLEV,BOD reset level" "0: Level 0: 1.5 V,1: Level 1: 1.85 V,2: Level 2: 2.0 V,3: Level 3: 2.3 V"
endif
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x6A0)++0x3
line.long 0x0 "STARTERSET[$1],Set bits in STARTER"
hexmask.long 0x0 0.--31. 1. "START_SET,Writing ones to this register sets the corresponding bit or bits in the STARTER0 register  if they are implemented."
repeat.end
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x6C0)++0x3
line.long 0x0 "STARTERCLR[$1],Clear bits in STARTER0"
hexmask.long 0x0 0.--31. 1. "START_CLR,Writing ones to this register clears the corresponding bit or bits in the STARTER0 register  if they are implemented."
repeat.end
sif (cpuis("LPC54101*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x4C)++0x3
line.long 0x0 "PRESETCTRLSET[$1],Set bits in PRESETCTRL n"
hexmask.long 0x0 0.--31. 1. "RST_SET,Writing ones to this register sets the corresponding bit or bits in the PRESETCTRL n register  if they are implemented. Bits that do not correspond to defined bits in PRESETCTRL0 are reserved and only zeroes should be written to them."
repeat.end
endif
sif (cpuis("LPC54101*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x54)++0x3
line.long 0x0 "PRESETCTRLCLR[$1],Clear bits in PRESETCTRL n"
hexmask.long 0x0 0.--31. 1. "RST_CLR,Writing ones to this register clears the corresponding bit or bits in the PRESETCTRL n register  if they are implemented. Bits that do not correspond to defined bits in PRESETCTRL0 are reserved and only zeroes should be written to them."
repeat.end
group.long 0x5C++0x7
line.long 0x0 "PIOPORCAP0,POR captured PIO status 0"
hexmask.long 0x0 0.--31. 1. "PIOPORSTAT,State of PIO0_31 through PIO0_0 at power-on reset"
line.long 0x4 "PIOPORCAP1,POR captured PIO status 1"
hexmask.long 0x4 0.--31. 1. "PIOPORSTAT,State of PIO1_31 through PIO1_0 at power-on reset"
group.long 0x68++0x7
line.long 0x0 "PIORESCAP0,Reset captured PIO status 0"
hexmask.long 0x0 0.--31. 1. "PIORESSTAT,State of PIO0_31 through PIO0_0 for resets other than power-on reset."
line.long 0x4 "PIORESCAP1,Reset captured PIO status 1"
hexmask.long 0x4 0.--31. 1. "PIORESSTAT,State of PIO1_31 through PIO1_0 for resets other than power-on reset."
group.long 0x80++0x7
line.long 0x0 "MAINCLKSELA,Main clock source select A"
bitfld.long 0x0 0.--1. "SEL,Clock source for main clock source selector A" "0: IRC Oscillator,1: CLKIN,2: Watchdog oscillator,?"
line.long 0x4 "MAINCLKSELB,Main clock source select B"
bitfld.long 0x4 0.--1. "SEL,Clock source for main clock source selector B. Selects the clock source for the main clock." "0: MAINCLKSELA. Use the clock source selected in..,1: System PLL input.,2: System PLL output.,3: RTC osc output. RTC oscillator 32 kHz output."
group.long 0x8C++0x3
line.long 0x0 "ADCCLKSEL,ADC clock source select"
bitfld.long 0x0 0.--1. "SEL,ADC clock source." "0: Main clock,1: System PLL output,2: IRC Oscillator,?"
group.long 0x94++0x7
line.long 0x0 "CLKOUTSELA,CLKOUT clock source select A"
bitfld.long 0x0 0.--1. "SEL,CLKOUT clock source" "0: Main clock,1: CLKIN,2: Watchdog oscillator,3: IRC oscillator"
line.long 0x4 "CLKOUTSELB,CLKOUT clock source select B"
bitfld.long 0x4 0.--1. "SEL,CLKOUT clock source" "0: CLKOUTSELA. Clock source selected in the..,?,?,3: RTC 32 kHz clock"
group.long 0xA0++0x3
line.long 0x0 "SYSPLLCLKSEL,PLL clock source select"
bitfld.long 0x0 0.--1. "SEL,System PLL clock source" "0: IRC Oscillator,1: CLKIN,2: Watchdog oscillator,3: RTC 32 kHz clock"
group.long 0xC0++0x7
line.long 0x0 "AHBCLKCTRL0,AHB Clock control n"
bitfld.long 0x0 27. "ADC0,Enables the clock for the ADC0 register interface. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 26. "MAILBOX,Enables the clock for the Mailbox. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 23. "RTC,Enables the clock for the RTC. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 22. "WWDT,Enables the clock for the Watchdog Timer. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 21. "CRC,Enables the clock for the CRC engine. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 20. "DMA,Enables the clock for the DMA controller. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 19. "GINT,Enables the clock for the grouped pin interrupt block. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 18. "PINT,Enables the clock for the pin interrupt block.0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 15. "GPIO1,Enables the clock for the GPIO1 port registers. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 14. "GPIO0,Enables the clock for the GPIO0 port registers. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 13. "IOCON,Enables the clock for the IOCON block. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 11. "INPUTMUX,Enables the clock for the input muxes. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 8. "FMC,Enables the clock for the Flash accelerator. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 7. "FLASH,Enables the clock for the flash controller. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 4. "SRAM2,Enables the clock for SRAM2. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 3. "SRAM1,Enables the clock for SRAM1. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 1. "ROM,Enables the clock for the Boot ROM. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
line.long 0x4 "AHBCLKCTRL1,AHB Clock control n"
bitfld.long 0x4 27. "CT32B4,Enables the clock for CT32B 4. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 26. "CT32B3,Enables the clock for CT32B 3. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 22. "CT32B2,Enables the clock for CT32B 2. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 10. "UTICK,Enables the clock for the Micro-tick Timer. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 9. "FIFO,Enables the clock for system FIFOs. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 2. "SCT0,Enables the clock for SCT0. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 1. "RIT,Enables the clock for the repetitive interrupt timer. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 0. "MRT,Enables the clock for the Multi-Rate Timer. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
endif
sif (cpuis("LPC54101*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0xC8)++0x3
line.long 0x0 "AHBCLKCTRLSET[$1],Set bits in AHBCLKCTRL n"
hexmask.long 0x0 0.--31. 1. "CLK_SET,Writing ones to this register sets the corresponding bit or bits in the AHBCLKCTRL0 register  if they are implemented. Bits that do not correspond to defined bits in AHBCLKCTRL0 are reserved and only zeroes should be written to them."
repeat.end
endif
sif (cpuis("LPC54101*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0xD0)++0x3
line.long 0x0 "AHBCLKCTRLCLR[$1],Clear bits in AHBCLKCTRL n"
hexmask.long 0x0 0.--31. 1. "CLK_CLR,Writing ones to this register clears the corresponding bit or bits in the AHBCLKCTRL0 register  if they are implemented. Bits that do not correspond to defined bits in AHBCLKCTRL0 are reserved and only zeroes should be written to them."
repeat.end
group.long 0xE0++0x7
line.long 0x0 "SYSTICKCLKDIV,SYSTICK clock divider"
hexmask.long.byte 0x0 0.--7. 1. "DIV,SYSTICK clock divider value. 0: Disable SYSTICK timer clock. 1: Divide by 1. to 255: Divide by 255."
line.long 0x4 "TRACECLKDIV,TRACE clock divider"
hexmask.long.byte 0x4 0.--7. 1. "DIV,TRACE clock divider value. 0: Disable TRACE clock. 1: Divide by 1. to 255: Divide by 255."
group.long 0x100++0x3
line.long 0x0 "AHBCLKDIV,System clock divider"
hexmask.long.byte 0x0 0.--7. 1. "DIV,System AHB clock divider value. 0: System clock disabled. 1: Divide by 1. to 255: Divide by 255."
group.long 0x108++0x7
line.long 0x0 "ADCCLKDIV,ADC clock divider"
hexmask.long.byte 0x0 0.--7. 1. "DIV,ADC clock divider value. 0: Disable ADC clock. 1: Divide by 1. to 255: Divide by 255."
line.long 0x4 "CLKOUTDIV,CLKOUT clock divider"
hexmask.long.byte 0x4 0.--7. 1. "DIV,CLKOUT clock divider value. 0: Disable CLKOUT clock divider. 1: Divide by 1. to 255: Divide by 255."
group.long 0x120++0x7
line.long 0x0 "FREQMECTRL,Frequency measure register"
bitfld.long 0x0 31. "PROG,Set this bit to one to initiate a frequency measurement cycle. Hardware clears this bit when the measurement cycle has completed and there is valid capture data in the CAPVAL field (bits 13:0)." "0,1"
hexmask.long.word 0x0 0.--13. 1. "CAPVAL,Stores the capture result which is used to calculate the frequency of the target clock. This field is read-only."
line.long 0x4 "FLASHCFG,Flash wait states configuration"
hexmask.long.byte 0x4 12.--15. 1. "FLASHTIM,Flash memory access time. FLASHTIM +1 is equal to the number of system clocks used for flash access."
bitfld.long 0x4 6. "PREFOVR,Prefetch override." "0,1"
newline
bitfld.long 0x4 5. "PREFEN,Prefetch enable." "0,1"
bitfld.long 0x4 4. "ACCEL,Acceleration enable." "0,1"
newline
bitfld.long 0x4 2.--3. "DATACFG,Data read configuration. This field determines how flash accelerator buffers are used for data accesses." "0,1,2,3"
bitfld.long 0x4 0.--1. "FETCHCFG,Instruction fetch configuration. This field determines how flash accelerator buffers are used for instruction fetches." "0,1,2,3"
group.long 0x148++0x3
line.long 0x0 "FIFOCTRL,Serial interface FIFO enables"
bitfld.long 0x0 13. "SPI1RXFIFOEN,SPI1 receiver FIFO enable" "0,1"
bitfld.long 0x0 12. "SPI0RXFIFOEN,SPI0 receiver FIFO enable" "0,1"
newline
bitfld.long 0x0 11. "U3RXFIFOEN,USART3 receiver FIFO enable" "0,1"
bitfld.long 0x0 10. "U2RXFIFOEN,USART2 receiver FIFO enable" "0,1"
newline
bitfld.long 0x0 9. "U1RXFIFOEN,USART1 receiver FIFO enable" "0,1"
bitfld.long 0x0 8. "U0RXFIFOEN,USART0 receiver FIFO enable" "0,1"
newline
bitfld.long 0x0 5. "SPI1TXFIFOEN,SPI1 transmitter FIFO enable" "0,1"
bitfld.long 0x0 4. "SPI0TXFIFOEN,SPI0 transmitter FIFO enable" "0,1"
newline
bitfld.long 0x0 3. "U3TXFIFOEN,USART3 transmitter FIFO enable" "0,1"
bitfld.long 0x0 2. "U2TXFIFOEN,USART2 transmitter FIFO enable" "0,1"
newline
bitfld.long 0x0 1. "U1TXFIFOEN,USART1 transmitter FIFO enable" "0,1"
bitfld.long 0x0 0. "U0TXFIFOEN,USART0 transmitter FIFO enable" "0,1"
group.long 0x184++0x3
line.long 0x0 "IRCCTRL,IRC oscillator control"
hexmask.long.byte 0x0 0.--7. 1. "TRIM,Trim value"
group.long 0x190++0x3
line.long 0x0 "RTCOSCCTRL,RTC oscillator 32 kHz output control"
bitfld.long 0x0 0. "EN,RTC 32 kHz clock enable." "0: Disabled. RTC clock off.,1: Enabled. RTC clock on."
group.long 0x1B0++0x17
line.long 0x0 "SYSPLLCTRL,PLL control"
bitfld.long 0x0 20. "DIRECTO,PLL0 direct output enable" "0: Disabled. The PLL output divider (P divider) is..,1: Enabled. The PLL output divider (P divider) is.."
bitfld.long 0x0 19. "DIRECTI,PLL0 direct input enable" "0: Disabled. The PLL input divider (N divider)..,1: Enabled. The PLL input divider (N divider) is.."
newline
bitfld.long 0x0 18. "BANDSEL,PLL filter control. Set this bit to one when the SSGC is disabled or at low frequencies." "0: SSCG control. The PLL filter uses the parameters..,1: MDEC control. The PLL filter uses the.."
bitfld.long 0x0 17. "UPLIMOFF,Enable spread spectrum/fractional mode" "0: Normal mode.,1: SSGC mode. Spread spectrum/fractional mode."
newline
bitfld.long 0x0 16. "BYPASSCCODIV2,Bypass feedback clock divide by 2." "0: Divide by 2. The CCO feedback clock is divided..,1: Bypass. The CCO feedback clock is divided only.."
bitfld.long 0x0 15. "BYPASS,PLL bypass control" "0: Disabled. PLL CCO is used to create the PLL..,1: Enabled. PLL is bypassed the PLL input clock is.."
newline
hexmask.long.byte 0x0 10.--14. 1. "SELP,Bandwidth select P value"
hexmask.long.byte 0x0 4.--9. 1. "SELI,Bandwidth select I value"
newline
hexmask.long.byte 0x0 0.--3. 1. "SELR,Bandwidth select R value"
line.long 0x4 "SYSPLLSTAT,PLL status"
bitfld.long 0x4 0. "LOCK,PLL0 lock indicator" "0,1"
line.long 0x8 "SYSPLLNDEC,PLL N decoder"
bitfld.long 0x8 10. "NREQ,NDEC reload request. When a 1 is written to this bit  the NDEC value is loaded into the PLL. Must be cleared by software for any subsequent load  or the PLL can be powered down and back up via the PDEN_SYS_PLL bit in the PDRUNCFG register if the.." "0,1"
hexmask.long.word 0x8 0.--9. 1. "NDEC,Decoded N-divider coefficient value"
line.long 0xC "SYSPLLPDEC,PLL P decoder"
bitfld.long 0xC 7. "PREQ,PDEC reload request. When a 1 is written to this bit  the PDEC value is loaded into the PLL. Must be cleared by software for any subsequent load  or the PLL can be powered down and back up via the PDEN_SYS_PLL bit in the PDRUNCFG register if the.." "0,1"
hexmask.long.byte 0xC 0.--6. 1. "PDEC,Decoded P-divider coefficient value"
line.long 0x10 "SYSPLLSSCTRL0,PLL spread spectrum control 0"
bitfld.long 0x10 18. "SEL_EXT,Select spread spectrum mode." "0: Spread spectrum mode. Spread spectrum mode..,1: MDEC enabled. Spread spectrum clock generator.."
bitfld.long 0x10 17. "MREQ,MDEC reload request. When a 1 is written to this bit  the MDEC value is loaded into the PLL. Must be cleared by software for any subsequent load  or the PLL can be powered down and back up via the PDEN_SYS_PLL bit in the PDRUNCFG register if the.." "0,1"
newline
hexmask.long.tbyte 0x10 0.--16. 1. "MDEC,Decoded M-divider coefficient value"
line.long 0x14 "SYSPLLSSCTRL1,PLL spread spectrum control 1"
bitfld.long 0x14 29. "DITHER,Select modulation frequency." "0: Fixed. Fixed modulation frequency.,1: Dither. Randomly dither between two modulation.."
bitfld.long 0x14 28. "PD,Power down." "0: Enabled. Spread spectrum controller is enabled,1: Disabled. Spread spectrum controller is disabled"
newline
bitfld.long 0x14 26.--27. "MC,Modulation waveform control 0 = no compensation Compensation for low pass filtering of the PLL to get a triangular modulation at the output of the PLL  giving a flat frequency spectrum. 0b00 => no compensation 0b10 => recommended setting 0b11 => max." "0: no compensation,?,2: recommended setting,3: max"
bitfld.long 0x14 23.--25. "MR,Programmable frequency modulation depth deltafmodpk-pk = Fref x k/Fcco = k/MDdec 0 = no spread 0b000 => k = 0 (no spread spectrum) 0b001 => k = 1 0b010 => k = 1.5 0b011 => k = 2 0b100 => k = 3 0b101 => k = 4 0b110 => k = 6 0b111 => k = 8" "0: k = 0,1: k = 1,2: k = 1,3: k = 2,4: k = 3,5: k = 4,6: k = 6,7: k = 8"
newline
bitfld.long 0x14 20.--22. "MF,Programmable modulation frequency fm = Fref/Nss with Fref = Fin/N 0b000 => Nss = 512 (fm = 3.9 - 7.8 kHz) 0b001 => Nss = 384 (fm = 5.2 - 10.4 kHz) 0b010 => Nss = 256 (fm = 7.8 - 15.6 kHz) 0b011 => Nss = 128 (fm = 15.6 - 31.3 kHz) 0b100 => Nss = 64 (fm.." "0: Nss = 512,1: Nss = 384,2: Nss = 256,3: Nss = 128,4: Nss = 64,5: Nss = 32,6: Nss = 24,7: Nss = 16"
bitfld.long 0x14 19. "MDREQ,MD reload request. When a 1 is written to this bit  the MD value is loaded into the PLL. This bit is cleared when the load is complete." "0,1"
newline
hexmask.long.tbyte 0x14 0.--18. 1. "MD,M- divider value with fraction. MD[18:11] : integer portion of the feedback divider value. MD[10:0] : fractional portion of the feedback divider value."
group.long 0x210++0xB
line.long 0x0 "PDRUNCFG,Power configuration register"
bitfld.long 0x0 24. "PDEN_32K_OSC,32 kHz RTC oscillator. 0 = Powered; 1 = Powered down." "0: Powered,1: Powered down"
bitfld.long 0x0 23. "PDEN_VREFP,Vrefp to the ADC  must be enabled for the ADC to work. Also see bit 19. 0 = Powered; 1 = Powered down." "0: Powered,1: Powered down"
newline
bitfld.long 0x0 22. "PDEN_SYS_PLL,PLL0. 0 = Powered; 1 = Powered down." "0: Powered,1: Powered down"
bitfld.long 0x0 20. "PDEN_WDT_OSC,Watchdog oscillator. 0 = Powered; 1 = Powered down." "0: Powered,1: Powered down"
newline
bitfld.long 0x0 19. "PDEN_VDDA,Vdda to the ADC  must be enabled for the ADC to work. Also see bit 23. 0 = Powered; 1 = Powered down." "0: Powered,1: Powered down"
bitfld.long 0x0 17. "PDEN_ROM,ROM. 0 = Powered; 1 = Powered down." "0: Powered,1: Powered down"
newline
bitfld.long 0x0 16. "PDEN_SRAM2,SRAM2 (undedicated 8 kB RAM). 0 = Powered; 1 = Powered down." "0: Powered,1: Powered down"
bitfld.long 0x0 15. "PDEN_SRAM1,SRAM1. 0 = Powered; 1 = Powered down." "0: Powered,1: Powered down"
newline
bitfld.long 0x0 14. "PDEN_SRAM0B,Remaining portion of SRAM0). 0 = Powered; 1 = Powered down." "0: Powered,1: Powered down"
bitfld.long 0x0 13. "PDEN_SRAM0A,First 8 kB of SRAM0). 0 = Powered; 1 = Powered down." "0: Powered,1: Powered down"
newline
bitfld.long 0x0 10. "PDEN_ADC0,ADC0. 0 = Powered; 1 = Powered down." "0: Powered,1: Powered down"
bitfld.long 0x0 8. "PDEN_BOD_INTR,Brown-out Detect interrupt. 0 = Powered; 1 = Powered down." "0: Powered,1: Powered down"
newline
bitfld.long 0x0 7. "PDEN_BOD_RST,Brown-out Detect reset. 0 = Powered; 1 = Powered down." "0: Powered,1: Powered down"
bitfld.long 0x0 5. "PDEN_FLASH,Flash memory. 0 = Powered; 1 = Powered down." "0: Powered,1: Powered down"
newline
bitfld.long 0x0 4. "PDEN_IRC,IRC oscillator. 0 = Powered; 1 = Powered down." "0: Powered,1: Powered down"
bitfld.long 0x0 3. "PDEN_IRC_OSC,IRC oscillator output. 0 = Powered; 1 = Powered down." "0: Powered,1: Powered down"
line.long 0x4 "PDRUNCFGSET,Set bits in PDRUNCFG"
hexmask.long 0x4 0.--31. 1. "PD_SET,Writing ones to this register sets the corresponding bit or bits in the PDRUNCFG register  if they are implemented. Bits that do not correspond to defined bits in PDRUNCFG are reserved and only zeroes should be written to them."
line.long 0x8 "PDRUNCFGCLR,Clear bits in PDRUNCFG"
hexmask.long 0x8 0.--31. 1. "PD_CLR,Writing ones to this register clears the corresponding bit or bits in the PDRUNCFG register  if they are implemented. Bits that do not correspond to defined bits in PDRUNCFG are reserved and only zeroes should be written to them."
group.long 0x240++0x7
line.long 0x0 "STARTER0,Start logic n wake-up enable register"
bitfld.long 0x0 31. "MAILBOX,Mailbox interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x0 29. "RTC,RTC interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled." "0: Wake-up disabled,1: Wake-up enabled"
newline
bitfld.long 0x0 28. "ADC0_THCMP,ADC0 threshold and error interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x0 27. "ADC0_SEQB,ADC0 sequence B interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only." "0: Wake-up disabled,1: Wake-up enabled"
newline
bitfld.long 0x0 26. "ADC0_SEQA,ADC0 sequence A interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x0 25. "SPI1,SPI1 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Peripheral interrupt." "0: Wake-up disabled,1: Wake-up enabled"
newline
bitfld.long 0x0 24. "SPI0,SPI0 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Peripheral interrupt." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x0 23. "I2C2,I2C2 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Peripheral interrupt." "0: Wake-up disabled,1: Wake-up enabled"
newline
bitfld.long 0x0 22. "I2C1,I2C1 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Peripheral interrupt." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x0 21. "I2C0,I2C0 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Peripheral interrupt." "0: Wake-up disabled,1: Wake-up enabled"
newline
bitfld.long 0x0 20. "USART3,USART2 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Peripheral interrupt." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x0 19. "USART2,USART2 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Peripheral interrupt." "0: Wake-up disabled,1: Wake-up enabled"
newline
bitfld.long 0x0 18. "USART1,USART1 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Peripheral interrupt." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x0 17. "USART0,USART0 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Peripheral interrupt." "0: Wake-up disabled,1: Wake-up enabled"
newline
bitfld.long 0x0 16. "SCT0,SCT0 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x0 15. "CT32B4,CT32B 4 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only." "0: Wake-up disabled,1: Wake-up enabled"
newline
bitfld.long 0x0 14. "CT32B3,CT32B 3 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x0 13. "CT32B2,CT32B 2 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only." "0: Wake-up disabled,1: Wake-up enabled"
newline
bitfld.long 0x0 12. "CT32B1,CT32B 1 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x0 11. "CT32B0,CT32B 0 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only." "0: Wake-up disabled,1: Wake-up enabled"
newline
bitfld.long 0x0 10. "MRT,Multi-Rate Timer wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Typically used in sleep mode only." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x0 9. "UTICK,Micro-tick Timer wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled." "0: Wake-up disabled,1: Wake-up enabled"
newline
bitfld.long 0x0 8. "PINT3,GPIO pin interrupt 3 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x0 7. "PINT2,GPIO pin interrupt 2 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match." "0: Wake-up disabled,1: Wake-up enabled"
newline
bitfld.long 0x0 6. "PINT1,GPIO pin interrupt 1 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x0 5. "PINT0,GPIO pin interrupt 0 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match." "0: Wake-up disabled,1: Wake-up enabled"
newline
bitfld.long 0x0 4. "GINT0,Group interrupt 0 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x0 3. "DMA,DMA wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Typically used in sleep mode only." "0: Wake-up disabled,1: Wake-up enabled"
newline
bitfld.long 0x0 1. "BOD,BOD interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x0 0. "WWDT,WWDT interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled." "0: Wake-up disabled,1: Wake-up enabled"
line.long 0x4 "STARTER1,Start logic n wake-up enable register"
bitfld.long 0x4 8. "RIT,Repetitive Interrupt Timer interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Typically used in sleep mode only." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x4 4. "PINT7,GPIO pin interrupt 7 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match." "0: Wake-up disabled,1: Wake-up enabled"
newline
bitfld.long 0x4 3. "PINT6,GPIO pin interrupt 6 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x4 2. "PINT5,GPIO pin interrupt 5 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match." "0: Wake-up disabled,1: Wake-up enabled"
newline
bitfld.long 0x4 1. "PINT4,GPIO pin interrupt 4 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x4 0. "GINT1,Group interrupt 0 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled." "0: Wake-up disabled,1: Wake-up enabled"
endif
sif (cpuis("LPC54101*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x248)++0x3
line.long 0x0 "STARTERSET[$1],Set bits in STARTERP n"
hexmask.long 0x0 0.--31. 1. "START_SET,Writing ones to this register sets the corresponding bit or bits in the STARTERP n register  if they are implemented. Bits that do not correspond to defined bits in STARTERP0 are reserved and only zeroes should be written to them."
repeat.end
endif
sif (cpuis("LPC54101*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x250)++0x3
line.long 0x0 "STARTERCLR[$1],Clear bits in STARTER n"
hexmask.long 0x0 0.--31. 1. "START_CLR,Writing ones to this register clears the corresponding bit or bits in the STARTERP n register  if they are implemented. Bits that do not correspond to defined bits in STARTERP0 are reserved and only zeroes should be written to them."
repeat.end
group.long 0x300++0xF
line.long 0x0 "CPUCTRL,CPU Control for multiple processors"
bitfld.long 0x0 6. "POWERCPU,Identifies the owner of reduced power mode control: which CPU can cause the device to enter Sleep  Deep Sleep  Power-down  and Deep Power-down modes." "0: M0+. Cortex-M0+ is the owner of reduced power..,1: M4. Cortex-M4 is the owner of reduced power mode.."
bitfld.long 0x0 5. "CM0RSTEN,Cortex-M0+ reset." "0: Disabled. The Cortex-M0+ is not being reset.,1: Enabled. The Cortex-M0+ is being reset."
newline
bitfld.long 0x0 4. "CM4RSTEN,Cortex-M4 reset." "0: Disabled. The Cortex-M4 is not being reset.,1: Enabled. The Cortex-M4 is being reset."
bitfld.long 0x0 3. "CM0CLKEN,Cortex-M0+ clock enable." "0: Disabled. The Cortex-M0+ clock is not enabled.,1: Enabled. The Cortex-M0+ clock is enabled."
newline
bitfld.long 0x0 2. "CM4CLKEN,Cortex-M4 clock enable." "0: Disabled. The Cortex-M4 clock is not enabled.,1: Enabled. The Cortex-M4 clock is enabled."
bitfld.long 0x0 0. "MASTERCPU,Determines which CPU is considered the master. The master CPU cannot have its clock turned off via the related CMnCLKEN bit or be reset via the related CMxRSTEN in this register. The slave CPU wakes up briefly following device reset  then goes.." "0: M0+. Cortex-M0+ is the master CPU.,1: M4. Cortex-M4 is the master CPU."
line.long 0x4 "CPBOOT,Coprocessor Boot Address"
hexmask.long 0x4 0.--31. 1. "BOOTADDR,Slave processor boot address."
line.long 0x8 "CPSTACK,Coprocessor Stack Address"
hexmask.long 0x8 0.--31. 1. "STACKADDR,Slave processor stack address."
line.long 0xC "CPSTAT,Coprocessor Status"
bitfld.long 0xC 3. "CM0LOCKUP,When 1  the Cortex-M0+ CPU is in lockup." "0,1"
bitfld.long 0xC 2. "CM4LOCKUP,When 1  the Cortex-M4 CPU is in lockup." "0,1"
newline
bitfld.long 0xC 1. "CM0SLEEPING,When 1  the Cortex-M0+ CPU is sleeping." "0,1"
bitfld.long 0xC 0. "CM4SLEEPING,When 1  the Cortex-M4 CPU is sleeping." "0,1"
group.long 0x3F4++0xB
line.long 0x0 "JTAGIDCODE,JTAG ID code register"
hexmask.long 0x0 0.--31. 1. "JTAGID,JTAG ID code."
line.long 0x4 "DEVICE_ID0,Part ID register"
hexmask.long 0x4 0.--31. 1. "PARTID,Part ID"
line.long 0x8 "DEVICE_ID1,Part ID register"
hexmask.long 0x8 0.--31. 1. "REVID,Revision."
group.long 0x2C044++0x3
line.long 0x0 "BODCTRL,Brown-Out Detect control"
bitfld.long 0x0 7. "BODINTSTAT,BOD interrupt status" "0,1"
bitfld.long 0x0 6. "BODRSTSTAT,BOD reset status" "0,1"
newline
bitfld.long 0x0 5. "BODINTENA,BOD interrupt enable" "0: Disable interrupt function.,1: Enable reset function."
bitfld.long 0x0 3.--4. "BODINTLEV,BOD interrupt level" "0: Level 0: 2.05 V,1: Level 1: 2.45 V,2: Level 2: 2.75 V,3: Level 3: 3.05 V"
newline
bitfld.long 0x0 2. "BODRSTENA,BOD reset enable" "0: Disable reset function.,1: Enable reset function."
bitfld.long 0x0 0.--1. "BODRSTLEV,BOD reset level" "0: Level 0: 1.5 V,1: Level 1: 1.85 V,2: Level 2: 2.0 V,3: Level 3: 2.3 V"
endif
sif (cpuis("LPC54102*"))
group.long 0x0++0x7
line.long 0x0 "SYSMEMREMAP,System memory remap"
bitfld.long 0x0 0.--1. "MAP,System memory remap. Value 0x3 is reserved." "0: Boot Loader Mode. Interrupt vectors are..,1: User RAM Mode. Interrupt vectors are re-mapped..,2: User Flash Mode. Interrupt vectors are not..,?"
line.long 0x4 "AHBMATPRIO,AHB multilayer matrix priority control"
bitfld.long 0x4 16.--17. "PRI_M0,Cortex-M0+ bus priority." "0,1,2,3"
bitfld.long 0x4 14.--15. "PRI_FIFO,System FIFO bus priority" "0,1,2,3"
newline
bitfld.long 0x4 8.--9. "PRI_DMA,DMA controller priority." "0,1,2,3"
bitfld.long 0x4 4.--5. "PRI_SYS,System bus priority." "0,1,2,3"
newline
bitfld.long 0x4 2.--3. "PRI_DCODE,D-Code bus priority." "0,1,2,3"
bitfld.long 0x4 0.--1. "PRI_ICODE,I-Code bus priority. Should be lower than PRI_DCODE for proper operation." "0,1,2,3"
group.long 0x14++0x3
line.long 0x0 "SYSTCKCAL,System tick counter calibration"
bitfld.long 0x0 25. "NOREF,Initial value for the Systick timer." "0,1"
bitfld.long 0x0 24. "SKEW,Initial value for the Systick timer." "0,1"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "CAL,System tick timer calibration value."
group.long 0x1C++0x7
line.long 0x0 "NMISRC,NMI Source Select"
bitfld.long 0x0 31. "NMIENM4,Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQM4." "0,1"
bitfld.long 0x0 30. "NMIENM0,Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQM0." "0,1"
newline
hexmask.long.byte 0x0 8.--13. 1. "IRQM0,The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the Cortex-M0+  if enabled by NMIENM0."
hexmask.long.byte 0x0 0.--5. 1. "IRQM4,The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the Cortex-M4  if enabled by NMIENM4."
line.long 0x4 "ASYNCAPBCTRL,Asynchronous APB Control"
bitfld.long 0x4 0. "ENABLE,Enables the asynchronous APB bridge and subsystem." "0: Disabled. Asynchronous APB bridge is disabled.,1: Enabled. Asynchronous APB bridge is enabled."
group.long 0x40++0xB
line.long 0x0 "SYSRSTSTAT,System reset status register"
bitfld.long 0x0 4. "SYSRST,Status of the software system reset" "0: No System reset detected,1: System reset detected. Writing a one clears this.."
bitfld.long 0x0 3. "BOD,Status of the Brown-out detect reset" "0: No BOD reset detected,1: BOD reset detected. Writing a one clears this.."
newline
bitfld.long 0x0 2. "WDT,Status of the Watchdog reset" "0: No WDT reset detected,1: WDT reset detected. Writing a one clears this.."
bitfld.long 0x0 1. "EXTRST,Status of the external RESET pin. External reset status." "0: No reset event detected.,1: Reset detected. Writing a one clears this reset."
newline
bitfld.long 0x0 0. "POR,POR reset status" "0: No POR detected,1: POR detected. Writing a one clears this reset."
line.long 0x4 "PRESETCTRL0,Peripheral reset control n"
bitfld.long 0x4 27. "ADC0_RST,ADC0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 22. "WWDT_RST,Watchdog timer reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 21. "CRC_RST,CRC generator reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 20. "DMA_RST,DMA reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 19. "GINT_RST,Grouped interrupt (GINT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 18. "PINT_RST,Pin interrupt (PINT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 15. "GPIO1_RST,GPIO1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 14. "GPIO0_RST,GPIO0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 13. "IOCON_RST,IOCON reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 11. "MUX_RST,Input mux reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 8. "FMC_RST,Flash accelerator reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 7. "FLASH_RST,Flash controller reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
line.long 0x8 "PRESETCTRL1,Peripheral reset control n"
bitfld.long 0x8 27. "CT32B4_RST,CT32B 4 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x8 26. "CT32B3_RST,CT32B 3 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x8 22. "CT32B2_RST,CT32B 2 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x8 10. "UTICK_RST,Micro-tick Timer reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x8 9. "FIFO_RST,System FIFO reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x8 2. "SCT0_RST,State configurable timer 0 (SCT0) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x8 1. "RIT_RST,Repetitive interrupt timer (RIT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x8 0. "MRT_RST,Multi-rate timer (MRT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
endif
sif (cpuis("LPC54102*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x4C)++0x3
line.long 0x0 "PRESETCTRLSET[$1],Set bits in PRESETCTRL n"
hexmask.long 0x0 0.--31. 1. "RST_SET,Writing ones to this register sets the corresponding bit or bits in the PRESETCTRL n register  if they are implemented. Bits that do not correspond to defined bits in PRESETCTRL0 are reserved and only zeroes should be written to them."
repeat.end
endif
sif (cpuis("LPC54102*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x54)++0x3
line.long 0x0 "PRESETCTRLCLR[$1],Clear bits in PRESETCTRL n"
hexmask.long 0x0 0.--31. 1. "RST_CLR,Writing ones to this register clears the corresponding bit or bits in the PRESETCTRL n register  if they are implemented. Bits that do not correspond to defined bits in PRESETCTRL0 are reserved and only zeroes should be written to them."
repeat.end
group.long 0x5C++0x7
line.long 0x0 "PIOPORCAP0,POR captured PIO status 0"
hexmask.long 0x0 0.--31. 1. "PIOPORSTAT,State of PIO0_31 through PIO0_0 at power-on reset"
line.long 0x4 "PIOPORCAP1,POR captured PIO status 1"
hexmask.long 0x4 0.--31. 1. "PIOPORSTAT,State of PIO1_31 through PIO1_0 at power-on reset"
group.long 0x68++0x7
line.long 0x0 "PIORESCAP0,Reset captured PIO status 0"
hexmask.long 0x0 0.--31. 1. "PIORESSTAT,State of PIO0_31 through PIO0_0 for resets other than power-on reset."
line.long 0x4 "PIORESCAP1,Reset captured PIO status 1"
hexmask.long 0x4 0.--31. 1. "PIORESSTAT,State of PIO1_31 through PIO1_0 for resets other than power-on reset."
group.long 0x80++0x7
line.long 0x0 "MAINCLKSELA,Main clock source select A"
bitfld.long 0x0 0.--1. "SEL,Clock source for main clock source selector A" "0: IRC Oscillator,1: CLKIN,2: Watchdog oscillator,?"
line.long 0x4 "MAINCLKSELB,Main clock source select B"
bitfld.long 0x4 0.--1. "SEL,Clock source for main clock source selector B. Selects the clock source for the main clock." "0: MAINCLKSELA. Use the clock source selected in..,1: System PLL input.,2: System PLL output.,3: RTC osc output. RTC oscillator 32 kHz output."
group.long 0x8C++0x3
line.long 0x0 "ADCCLKSEL,ADC clock source select"
bitfld.long 0x0 0.--1. "SEL,ADC clock source." "0: Main clock,1: System PLL output,2: IRC Oscillator,?"
group.long 0x94++0x7
line.long 0x0 "CLKOUTSELA,CLKOUT clock source select A"
bitfld.long 0x0 0.--1. "SEL,CLKOUT clock source" "0: Main clock,1: CLKIN,2: Watchdog oscillator,3: IRC oscillator"
line.long 0x4 "CLKOUTSELB,CLKOUT clock source select B"
bitfld.long 0x4 0.--1. "SEL,CLKOUT clock source" "0: CLKOUTSELA. Clock source selected in the..,?,?,3: RTC 32 kHz clock"
group.long 0xA0++0x3
line.long 0x0 "SYSPLLCLKSEL,PLL clock source select"
bitfld.long 0x0 0.--1. "SEL,System PLL clock source" "0: IRC Oscillator,1: CLKIN,2: Watchdog oscillator,3: RTC 32 kHz clock"
group.long 0xC0++0x7
line.long 0x0 "AHBCLKCTRL0,AHB Clock control n"
bitfld.long 0x0 27. "ADC0,Enables the clock for the ADC0 register interface. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 26. "MAILBOX,Enables the clock for the Mailbox. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 23. "RTC,Enables the clock for the RTC. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 22. "WWDT,Enables the clock for the Watchdog Timer. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 21. "CRC,Enables the clock for the CRC engine. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 20. "DMA,Enables the clock for the DMA controller. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 19. "GINT,Enables the clock for the grouped pin interrupt block. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 18. "PINT,Enables the clock for the pin interrupt block.0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 15. "GPIO1,Enables the clock for the GPIO1 port registers. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 14. "GPIO0,Enables the clock for the GPIO0 port registers. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 13. "IOCON,Enables the clock for the IOCON block. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 11. "INPUTMUX,Enables the clock for the input muxes. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 8. "FMC,Enables the clock for the Flash accelerator. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 7. "FLASH,Enables the clock for the flash controller. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 4. "SRAM2,Enables the clock for SRAM2. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 3. "SRAM1,Enables the clock for SRAM1. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 1. "ROM,Enables the clock for the Boot ROM. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
line.long 0x4 "AHBCLKCTRL1,AHB Clock control n"
bitfld.long 0x4 27. "CT32B4,Enables the clock for CT32B 4. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 26. "CT32B3,Enables the clock for CT32B 3. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 22. "CT32B2,Enables the clock for CT32B 2. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 10. "UTICK,Enables the clock for the Micro-tick Timer. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 9. "FIFO,Enables the clock for system FIFOs. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 2. "SCT0,Enables the clock for SCT0. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 1. "RIT,Enables the clock for the repetitive interrupt timer. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 0. "MRT,Enables the clock for the Multi-Rate Timer. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
endif
sif (cpuis("LPC54102*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0xC8)++0x3
line.long 0x0 "AHBCLKCTRLSET[$1],Set bits in AHBCLKCTRL n"
hexmask.long 0x0 0.--31. 1. "CLK_SET,Writing ones to this register sets the corresponding bit or bits in the AHBCLKCTRL0 register  if they are implemented. Bits that do not correspond to defined bits in AHBCLKCTRL0 are reserved and only zeroes should be written to them."
repeat.end
endif
sif (cpuis("LPC54102*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0xD0)++0x3
line.long 0x0 "AHBCLKCTRLCLR[$1],Clear bits in AHBCLKCTRL n"
hexmask.long 0x0 0.--31. 1. "CLK_CLR,Writing ones to this register clears the corresponding bit or bits in the AHBCLKCTRL0 register  if they are implemented. Bits that do not correspond to defined bits in AHBCLKCTRL0 are reserved and only zeroes should be written to them."
repeat.end
group.long 0xE0++0x7
line.long 0x0 "SYSTICKCLKDIV,SYSTICK clock divider"
hexmask.long.byte 0x0 0.--7. 1. "DIV,SYSTICK clock divider value. 0: Disable SYSTICK timer clock. 1: Divide by 1. to 255: Divide by 255."
line.long 0x4 "TRACECLKDIV,TRACE clock divider"
hexmask.long.byte 0x4 0.--7. 1. "DIV,TRACE clock divider value. 0: Disable TRACE clock. 1: Divide by 1. to 255: Divide by 255."
group.long 0x100++0x3
line.long 0x0 "AHBCLKDIV,System clock divider"
hexmask.long.byte 0x0 0.--7. 1. "DIV,System AHB clock divider value. 0: System clock disabled. 1: Divide by 1. to 255: Divide by 255."
group.long 0x108++0x7
line.long 0x0 "ADCCLKDIV,ADC clock divider"
hexmask.long.byte 0x0 0.--7. 1. "DIV,ADC clock divider value. 0: Disable ADC clock. 1: Divide by 1. to 255: Divide by 255."
line.long 0x4 "CLKOUTDIV,CLKOUT clock divider"
hexmask.long.byte 0x4 0.--7. 1. "DIV,CLKOUT clock divider value. 0: Disable CLKOUT clock divider. 1: Divide by 1. to 255: Divide by 255."
group.long 0x120++0x7
line.long 0x0 "FREQMECTRL,Frequency measure register"
bitfld.long 0x0 31. "PROG,Set this bit to one to initiate a frequency measurement cycle. Hardware clears this bit when the measurement cycle has completed and there is valid capture data in the CAPVAL field (bits 13:0)." "0,1"
hexmask.long.word 0x0 0.--13. 1. "CAPVAL,Stores the capture result which is used to calculate the frequency of the target clock. This field is read-only."
line.long 0x4 "FLASHCFG,Flash wait states configuration"
hexmask.long.byte 0x4 12.--15. 1. "FLASHTIM,Flash memory access time. FLASHTIM +1 is equal to the number of system clocks used for flash access."
bitfld.long 0x4 6. "PREFOVR,Prefetch override." "0,1"
newline
bitfld.long 0x4 5. "PREFEN,Prefetch enable." "0,1"
bitfld.long 0x4 4. "ACCEL,Acceleration enable." "0,1"
newline
bitfld.long 0x4 2.--3. "DATACFG,Data read configuration. This field determines how flash accelerator buffers are used for data accesses." "0,1,2,3"
bitfld.long 0x4 0.--1. "FETCHCFG,Instruction fetch configuration. This field determines how flash accelerator buffers are used for instruction fetches." "0,1,2,3"
group.long 0x148++0x3
line.long 0x0 "FIFOCTRL,Serial interface FIFO enables"
bitfld.long 0x0 13. "SPI1RXFIFOEN,SPI1 receiver FIFO enable" "0,1"
bitfld.long 0x0 12. "SPI0RXFIFOEN,SPI0 receiver FIFO enable" "0,1"
newline
bitfld.long 0x0 11. "U3RXFIFOEN,USART3 receiver FIFO enable" "0,1"
bitfld.long 0x0 10. "U2RXFIFOEN,USART2 receiver FIFO enable" "0,1"
newline
bitfld.long 0x0 9. "U1RXFIFOEN,USART1 receiver FIFO enable" "0,1"
bitfld.long 0x0 8. "U0RXFIFOEN,USART0 receiver FIFO enable" "0,1"
newline
bitfld.long 0x0 5. "SPI1TXFIFOEN,SPI1 transmitter FIFO enable" "0,1"
bitfld.long 0x0 4. "SPI0TXFIFOEN,SPI0 transmitter FIFO enable" "0,1"
newline
bitfld.long 0x0 3. "U3TXFIFOEN,USART3 transmitter FIFO enable" "0,1"
bitfld.long 0x0 2. "U2TXFIFOEN,USART2 transmitter FIFO enable" "0,1"
newline
bitfld.long 0x0 1. "U1TXFIFOEN,USART1 transmitter FIFO enable" "0,1"
bitfld.long 0x0 0. "U0TXFIFOEN,USART0 transmitter FIFO enable" "0,1"
group.long 0x184++0x3
line.long 0x0 "IRCCTRL,IRC oscillator control"
hexmask.long.byte 0x0 0.--7. 1. "TRIM,Trim value"
group.long 0x190++0x3
line.long 0x0 "RTCOSCCTRL,RTC oscillator 32 kHz output control"
bitfld.long 0x0 0. "EN,RTC 32 kHz clock enable." "0: Disabled. RTC clock off.,1: Enabled. RTC clock on."
group.long 0x1B0++0x17
line.long 0x0 "SYSPLLCTRL,PLL control"
bitfld.long 0x0 20. "DIRECTO,PLL0 direct output enable" "0: Disabled. The PLL output divider (P divider) is..,1: Enabled. The PLL output divider (P divider) is.."
bitfld.long 0x0 19. "DIRECTI,PLL0 direct input enable" "0: Disabled. The PLL input divider (N divider)..,1: Enabled. The PLL input divider (N divider) is.."
newline
bitfld.long 0x0 18. "BANDSEL,PLL filter control. Set this bit to one when the SSGC is disabled or at low frequencies." "0: SSCG control. The PLL filter uses the parameters..,1: MDEC control. The PLL filter uses the.."
bitfld.long 0x0 17. "UPLIMOFF,Enable spread spectrum/fractional mode" "0: Normal mode.,1: SSGC mode. Spread spectrum/fractional mode."
newline
bitfld.long 0x0 16. "BYPASSCCODIV2,Bypass feedback clock divide by 2." "0: Divide by 2. The CCO feedback clock is divided..,1: Bypass. The CCO feedback clock is divided only.."
bitfld.long 0x0 15. "BYPASS,PLL bypass control" "0: Disabled. PLL CCO is used to create the PLL..,1: Enabled. PLL is bypassed the PLL input clock is.."
newline
hexmask.long.byte 0x0 10.--14. 1. "SELP,Bandwidth select P value"
hexmask.long.byte 0x0 4.--9. 1. "SELI,Bandwidth select I value"
newline
hexmask.long.byte 0x0 0.--3. 1. "SELR,Bandwidth select R value"
line.long 0x4 "SYSPLLSTAT,PLL status"
bitfld.long 0x4 0. "LOCK,PLL0 lock indicator" "0,1"
line.long 0x8 "SYSPLLNDEC,PLL N decoder"
bitfld.long 0x8 10. "NREQ,NDEC reload request. When a 1 is written to this bit  the NDEC value is loaded into the PLL. Must be cleared by software for any subsequent load  or the PLL can be powered down and back up via the PDEN_SYS_PLL bit in the PDRUNCFG register if the.." "0,1"
hexmask.long.word 0x8 0.--9. 1. "NDEC,Decoded N-divider coefficient value"
line.long 0xC "SYSPLLPDEC,PLL P decoder"
bitfld.long 0xC 7. "PREQ,PDEC reload request. When a 1 is written to this bit  the PDEC value is loaded into the PLL. Must be cleared by software for any subsequent load  or the PLL can be powered down and back up via the PDEN_SYS_PLL bit in the PDRUNCFG register if the.." "0,1"
hexmask.long.byte 0xC 0.--6. 1. "PDEC,Decoded P-divider coefficient value"
line.long 0x10 "SYSPLLSSCTRL0,PLL spread spectrum control 0"
bitfld.long 0x10 18. "SEL_EXT,Select spread spectrum mode." "0: Spread spectrum mode. Spread spectrum mode..,1: MDEC enabled. Spread spectrum clock generator.."
bitfld.long 0x10 17. "MREQ,MDEC reload request. When a 1 is written to this bit  the MDEC value is loaded into the PLL. Must be cleared by software for any subsequent load  or the PLL can be powered down and back up via the PDEN_SYS_PLL bit in the PDRUNCFG register if the.." "0,1"
newline
hexmask.long.tbyte 0x10 0.--16. 1. "MDEC,Decoded M-divider coefficient value"
line.long 0x14 "SYSPLLSSCTRL1,PLL spread spectrum control 1"
bitfld.long 0x14 29. "DITHER,Select modulation frequency." "0: Fixed. Fixed modulation frequency.,1: Dither. Randomly dither between two modulation.."
bitfld.long 0x14 28. "PD,Power down." "0: Enabled. Spread spectrum controller is enabled,1: Disabled. Spread spectrum controller is disabled"
newline
bitfld.long 0x14 26.--27. "MC,Modulation waveform control 0 = no compensation Compensation for low pass filtering of the PLL to get a triangular modulation at the output of the PLL  giving a flat frequency spectrum. 0b00 => no compensation 0b10 => recommended setting 0b11 => max." "0: no compensation,?,2: recommended setting,3: max"
bitfld.long 0x14 23.--25. "MR,Programmable frequency modulation depth deltafmodpk-pk = Fref x k/Fcco = k/MDdec 0 = no spread 0b000 => k = 0 (no spread spectrum) 0b001 => k = 1 0b010 => k = 1.5 0b011 => k = 2 0b100 => k = 3 0b101 => k = 4 0b110 => k = 6 0b111 => k = 8" "0: k = 0,1: k = 1,2: k = 1,3: k = 2,4: k = 3,5: k = 4,6: k = 6,7: k = 8"
newline
bitfld.long 0x14 20.--22. "MF,Programmable modulation frequency fm = Fref/Nss with Fref = Fin/N 0b000 => Nss = 512 (fm = 3.9 - 7.8 kHz) 0b001 => Nss = 384 (fm = 5.2 - 10.4 kHz) 0b010 => Nss = 256 (fm = 7.8 - 15.6 kHz) 0b011 => Nss = 128 (fm = 15.6 - 31.3 kHz) 0b100 => Nss = 64 (fm.." "0: Nss = 512,1: Nss = 384,2: Nss = 256,3: Nss = 128,4: Nss = 64,5: Nss = 32,6: Nss = 24,7: Nss = 16"
bitfld.long 0x14 19. "MDREQ,MD reload request. When a 1 is written to this bit  the MD value is loaded into the PLL. This bit is cleared when the load is complete." "0,1"
newline
hexmask.long.tbyte 0x14 0.--18. 1. "MD,M- divider value with fraction. MD[18:11] : integer portion of the feedback divider value. MD[10:0] : fractional portion of the feedback divider value."
group.long 0x210++0xB
line.long 0x0 "PDRUNCFG,Power configuration register"
bitfld.long 0x0 24. "PDEN_32K_OSC,32 kHz RTC oscillator. 0 = Powered; 1 = Powered down." "0: Powered,1: Powered down"
bitfld.long 0x0 23. "PDEN_VREFP,Vrefp to the ADC  must be enabled for the ADC to work. Also see bit 19. 0 = Powered; 1 = Powered down." "0: Powered,1: Powered down"
newline
bitfld.long 0x0 22. "PDEN_SYS_PLL,PLL0. 0 = Powered; 1 = Powered down." "0: Powered,1: Powered down"
bitfld.long 0x0 20. "PDEN_WDT_OSC,Watchdog oscillator. 0 = Powered; 1 = Powered down." "0: Powered,1: Powered down"
newline
bitfld.long 0x0 19. "PDEN_VDDA,Vdda to the ADC  must be enabled for the ADC to work. Also see bit 23. 0 = Powered; 1 = Powered down." "0: Powered,1: Powered down"
bitfld.long 0x0 17. "PDEN_ROM,ROM. 0 = Powered; 1 = Powered down." "0: Powered,1: Powered down"
newline
bitfld.long 0x0 16. "PDEN_SRAM2,SRAM2 (undedicated 8 kB RAM). 0 = Powered; 1 = Powered down." "0: Powered,1: Powered down"
bitfld.long 0x0 15. "PDEN_SRAM1,SRAM1. 0 = Powered; 1 = Powered down." "0: Powered,1: Powered down"
newline
bitfld.long 0x0 14. "PDEN_SRAM0B,Remaining portion of SRAM0). 0 = Powered; 1 = Powered down." "0: Powered,1: Powered down"
bitfld.long 0x0 13. "PDEN_SRAM0A,First 8 kB of SRAM0). 0 = Powered; 1 = Powered down." "0: Powered,1: Powered down"
newline
bitfld.long 0x0 10. "PDEN_ADC0,ADC0. 0 = Powered; 1 = Powered down." "0: Powered,1: Powered down"
bitfld.long 0x0 8. "PDEN_BOD_INTR,Brown-out Detect interrupt. 0 = Powered; 1 = Powered down." "0: Powered,1: Powered down"
newline
bitfld.long 0x0 7. "PDEN_BOD_RST,Brown-out Detect reset. 0 = Powered; 1 = Powered down." "0: Powered,1: Powered down"
bitfld.long 0x0 5. "PDEN_FLASH,Flash memory. 0 = Powered; 1 = Powered down." "0: Powered,1: Powered down"
newline
bitfld.long 0x0 4. "PDEN_IRC,IRC oscillator. 0 = Powered; 1 = Powered down." "0: Powered,1: Powered down"
bitfld.long 0x0 3. "PDEN_IRC_OSC,IRC oscillator output. 0 = Powered; 1 = Powered down." "0: Powered,1: Powered down"
line.long 0x4 "PDRUNCFGSET,Set bits in PDRUNCFG"
hexmask.long 0x4 0.--31. 1. "PD_SET,Writing ones to this register sets the corresponding bit or bits in the PDRUNCFG register  if they are implemented. Bits that do not correspond to defined bits in PDRUNCFG are reserved and only zeroes should be written to them."
line.long 0x8 "PDRUNCFGCLR,Clear bits in PDRUNCFG"
hexmask.long 0x8 0.--31. 1. "PD_CLR,Writing ones to this register clears the corresponding bit or bits in the PDRUNCFG register  if they are implemented. Bits that do not correspond to defined bits in PDRUNCFG are reserved and only zeroes should be written to them."
group.long 0x240++0x7
line.long 0x0 "STARTER0,Start logic n wake-up enable register"
bitfld.long 0x0 31. "MAILBOX,Mailbox interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x0 29. "RTC,RTC interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled." "0: Wake-up disabled,1: Wake-up enabled"
newline
bitfld.long 0x0 28. "ADC0_THCMP,ADC0 threshold and error interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x0 27. "ADC0_SEQB,ADC0 sequence B interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only." "0: Wake-up disabled,1: Wake-up enabled"
newline
bitfld.long 0x0 26. "ADC0_SEQA,ADC0 sequence A interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x0 25. "SPI1,SPI1 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Peripheral interrupt." "0: Wake-up disabled,1: Wake-up enabled"
newline
bitfld.long 0x0 24. "SPI0,SPI0 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Peripheral interrupt." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x0 23. "I2C2,I2C2 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Peripheral interrupt." "0: Wake-up disabled,1: Wake-up enabled"
newline
bitfld.long 0x0 22. "I2C1,I2C1 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Peripheral interrupt." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x0 21. "I2C0,I2C0 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Peripheral interrupt." "0: Wake-up disabled,1: Wake-up enabled"
newline
bitfld.long 0x0 20. "USART3,USART2 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Peripheral interrupt." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x0 19. "USART2,USART2 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Peripheral interrupt." "0: Wake-up disabled,1: Wake-up enabled"
newline
bitfld.long 0x0 18. "USART1,USART1 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Peripheral interrupt." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x0 17. "USART0,USART0 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Peripheral interrupt." "0: Wake-up disabled,1: Wake-up enabled"
newline
bitfld.long 0x0 16. "SCT0,SCT0 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x0 15. "CT32B4,CT32B 4 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only." "0: Wake-up disabled,1: Wake-up enabled"
newline
bitfld.long 0x0 14. "CT32B3,CT32B 3 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x0 13. "CT32B2,CT32B 2 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only." "0: Wake-up disabled,1: Wake-up enabled"
newline
bitfld.long 0x0 12. "CT32B1,CT32B 1 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x0 11. "CT32B0,CT32B 0 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only." "0: Wake-up disabled,1: Wake-up enabled"
newline
bitfld.long 0x0 10. "MRT,Multi-Rate Timer wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Typically used in sleep mode only." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x0 9. "UTICK,Micro-tick Timer wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled." "0: Wake-up disabled,1: Wake-up enabled"
newline
bitfld.long 0x0 8. "PINT3,GPIO pin interrupt 3 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x0 7. "PINT2,GPIO pin interrupt 2 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match." "0: Wake-up disabled,1: Wake-up enabled"
newline
bitfld.long 0x0 6. "PINT1,GPIO pin interrupt 1 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x0 5. "PINT0,GPIO pin interrupt 0 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match." "0: Wake-up disabled,1: Wake-up enabled"
newline
bitfld.long 0x0 4. "GINT0,Group interrupt 0 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x0 3. "DMA,DMA wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Typically used in sleep mode only." "0: Wake-up disabled,1: Wake-up enabled"
newline
bitfld.long 0x0 1. "BOD,BOD interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x0 0. "WWDT,WWDT interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled." "0: Wake-up disabled,1: Wake-up enabled"
line.long 0x4 "STARTER1,Start logic n wake-up enable register"
bitfld.long 0x4 8. "RIT,Repetitive Interrupt Timer interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Typically used in sleep mode only." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x4 4. "PINT7,GPIO pin interrupt 7 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match." "0: Wake-up disabled,1: Wake-up enabled"
newline
bitfld.long 0x4 3. "PINT6,GPIO pin interrupt 6 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x4 2. "PINT5,GPIO pin interrupt 5 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match." "0: Wake-up disabled,1: Wake-up enabled"
newline
bitfld.long 0x4 1. "PINT4,GPIO pin interrupt 4 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x4 0. "GINT1,Group interrupt 0 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled." "0: Wake-up disabled,1: Wake-up enabled"
endif
sif (cpuis("LPC54102*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x248)++0x3
line.long 0x0 "STARTERSET[$1],Set bits in STARTERP n"
hexmask.long 0x0 0.--31. 1. "START_SET,Writing ones to this register sets the corresponding bit or bits in the STARTERP n register  if they are implemented. Bits that do not correspond to defined bits in STARTERP0 are reserved and only zeroes should be written to them."
repeat.end
endif
sif (cpuis("LPC54102*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x250)++0x3
line.long 0x0 "STARTERCLR[$1],Clear bits in STARTER n"
hexmask.long 0x0 0.--31. 1. "START_CLR,Writing ones to this register clears the corresponding bit or bits in the STARTERP n register  if they are implemented. Bits that do not correspond to defined bits in STARTERP0 are reserved and only zeroes should be written to them."
repeat.end
group.long 0x300++0xF
line.long 0x0 "CPUCTRL,CPU Control for multiple processors"
bitfld.long 0x0 6. "POWERCPU,Identifies the owner of reduced power mode control: which CPU can cause the device to enter Sleep  Deep Sleep  Power-down  and Deep Power-down modes." "0: M0+. Cortex-M0+ is the owner of reduced power..,1: M4. Cortex-M4 is the owner of reduced power mode.."
bitfld.long 0x0 5. "CM0RSTEN,Cortex-M0+ reset." "0: Disabled. The Cortex-M0+ is not being reset.,1: Enabled. The Cortex-M0+ is being reset."
newline
bitfld.long 0x0 4. "CM4RSTEN,Cortex-M4 reset." "0: Disabled. The Cortex-M4 is not being reset.,1: Enabled. The Cortex-M4 is being reset."
bitfld.long 0x0 3. "CM0CLKEN,Cortex-M0+ clock enable." "0: Disabled. The Cortex-M0+ clock is not enabled.,1: Enabled. The Cortex-M0+ clock is enabled."
newline
bitfld.long 0x0 2. "CM4CLKEN,Cortex-M4 clock enable." "0: Disabled. The Cortex-M4 clock is not enabled.,1: Enabled. The Cortex-M4 clock is enabled."
bitfld.long 0x0 0. "MASTERCPU,Determines which CPU is considered the master. The master CPU cannot have its clock turned off via the related CMnCLKEN bit or be reset via the related CMxRSTEN in this register. The slave CPU wakes up briefly following device reset  then goes.." "0: M0+. Cortex-M0+ is the master CPU.,1: M4. Cortex-M4 is the master CPU."
line.long 0x4 "CPBOOT,Coprocessor Boot Address"
hexmask.long 0x4 0.--31. 1. "BOOTADDR,Slave processor boot address."
line.long 0x8 "CPSTACK,Coprocessor Stack Address"
hexmask.long 0x8 0.--31. 1. "STACKADDR,Slave processor stack address."
line.long 0xC "CPSTAT,Coprocessor Status"
bitfld.long 0xC 3. "CM0LOCKUP,When 1  the Cortex-M0+ CPU is in lockup." "0,1"
bitfld.long 0xC 2. "CM4LOCKUP,When 1  the Cortex-M4 CPU is in lockup." "0,1"
newline
bitfld.long 0xC 1. "CM0SLEEPING,When 1  the Cortex-M0+ CPU is sleeping." "0,1"
bitfld.long 0xC 0. "CM4SLEEPING,When 1  the Cortex-M4 CPU is sleeping." "0,1"
group.long 0x3F4++0xB
line.long 0x0 "JTAGIDCODE,JTAG ID code register"
hexmask.long 0x0 0.--31. 1. "JTAGID,JTAG ID code."
line.long 0x4 "DEVICE_ID0,Part ID register"
hexmask.long 0x4 0.--31. 1. "PARTID,Part ID"
line.long 0x8 "DEVICE_ID1,Part ID register"
hexmask.long 0x8 0.--31. 1. "REVID,Revision."
group.long 0x2C044++0x3
line.long 0x0 "BODCTRL,Brown-Out Detect control"
bitfld.long 0x0 7. "BODINTSTAT,BOD interrupt status" "0,1"
bitfld.long 0x0 6. "BODRSTSTAT,BOD reset status" "0,1"
newline
bitfld.long 0x0 5. "BODINTENA,BOD interrupt enable" "0: Disable interrupt function.,1: Enable reset function."
bitfld.long 0x0 3.--4. "BODINTLEV,BOD interrupt level" "0: Level 0: 2.05 V,1: Level 1: 2.45 V,2: Level 2: 2.75 V,3: Level 3: 3.05 V"
newline
bitfld.long 0x0 2. "BODRSTENA,BOD reset enable" "0: Disable reset function.,1: Enable reset function."
bitfld.long 0x0 0.--1. "BODRSTLEV,BOD reset level" "0: Level 0: 1.5 V,1: Level 1: 1.85 V,2: Level 2: 2.0 V,3: Level 3: 2.3 V"
endif
sif (cpuis("LPC54113*"))
group.long 0x0++0x3
line.long 0x0 "SYSMEMREMAP,System Remap register"
group.long 0x10++0x3
line.long 0x0 "AHBMATPRIO,AHB multilayer matrix priority control"
bitfld.long 0x0 10.--11. "PRI_DMA,DMA controller priority." "0,1,2,3"
bitfld.long 0x0 8.--9. "PRI_USB,USB interface priority." "0,1,2,3"
newline
bitfld.long 0x0 6.--7. "PRI_M0,Cortex-M0+ bus priority. Present on selected devices." "0,1,2,3"
bitfld.long 0x0 4.--5. "PRI_SYS,Cortex M4 System bus priority." "0,1,2,3"
newline
bitfld.long 0x0 2.--3. "PRI_DCODE,Cortex M4 D-Code bus priority." "0,1,2,3"
bitfld.long 0x0 0.--1. "PRI_ICODE,Cortex-M4 I-Code bus priority. Should typically be lower than PRI_DCODE for best operation." "0,1,2,3"
group.long 0x40++0x3
line.long 0x0 "SYSTCKCAL,System tick counter calibration"
bitfld.long 0x0 25. "NOREF,Initial value for the Systick timer." "0,1"
bitfld.long 0x0 24. "SKEW,Initial value for the Systick timer." "0,1"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "CAL,System tick timer calibration value."
group.long 0x48++0x7
line.long 0x0 "NMISRC,NMI Source Select"
bitfld.long 0x0 31. "NMIENM4,Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQM4." "0,1"
bitfld.long 0x0 30. "NMIENM0,Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQM0. Present on selected devices." "0,1"
newline
hexmask.long.byte 0x0 8.--13. 1. "IRQM0,The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the Cortex-M0+  if enabled by NMIENM0. Present on selected devices."
hexmask.long.byte 0x0 0.--5. 1. "IRQM4,The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the Cortex-M4  if enabled by NMIENM4."
line.long 0x4 "ASYNCAPBCTRL,Asynchronous APB Control"
bitfld.long 0x4 0. "ENABLE,Enables the asynchronous APB bridge and subsystem." "0: Disabled. Asynchronous APB bridge is disabled.,1: Enabled. Asynchronous APB bridge is enabled."
endif
sif (cpuis("LPC54113*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0xC0)++0x3
line.long 0x0 "PIOPORCAP[$1],POR captured value of port n"
hexmask.long 0x0 0.--31. 1. "PIOPORCAP,State of PIOn_31 through PIOn_0 at power-on reset"
repeat.end
endif
sif (cpuis("LPC54113*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0xD0)++0x3
line.long 0x0 "PIORESCAP[$1],Reset captured value of port n"
hexmask.long 0x0 0.--31. 1. "PIORESCAP,State of PIOn_31 through PIOn_0 for resets other than POR."
repeat.end
group.long 0x100++0x7
line.long 0x0 "PRESETCTRL0,Peripheral reset control n"
bitfld.long 0x0 27. "ADC0_RST,ADC0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 22. "WWDT_RST,Watchdog timer reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x0 21. "CRC_RST,CRC generator reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 20. "DMA0_RST,DMA0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x0 19. "GINT_RST,Grouped interrupt (GINT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 18. "PINT_RST,Pin interrupt (PINT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x0 15. "GPIO1_RST,GPIO1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 14. "GPIO0_RST,GPIO0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x0 13. "IOCON_RST,IOCON reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 11. "MUX_RST,Input mux reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x0 8. "FMC_RST,Flash accelerator reset control. Note that the FMC must not be reset while executing from flash  and must be reconfigured after reset. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 7. "FLASH_RST,Flash controller reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
line.long 0x4 "PRESETCTRL1,Peripheral reset control n"
bitfld.long 0x4 27. "CTIMER1_RST,CTIMER1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 26. "CTIMER0_RST,CTIMER0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 25. "USB0_RST,USB0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 22. "CTIMER2_RST,CTIMER2 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function" "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 19. "DMIC0_RST,Digital microphone interface reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 18. "FC7_RST,Flexcomm 7 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 17. "FC6_RST,Flexcomm 6 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 16. "FC5_RST,Flexcomm 5 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 15. "FC4_RST,Flexcomm 4 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 14. "FC3_RST,Flexcomm 3 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 13. "FC2_RST,Flexcomm 2 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 12. "FC1_RST,Flexcomm 1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 11. "FC0_RST,Flexcomm 0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 10. "UTICK0_RST,Micro-tick Timer reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 2. "SCT0_RST,State configurable timer 0 (SCT0) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 0. "MRT0_RST,Multi-rate timer (MRT0) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
endif
sif (cpuis("LPC54113*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x120)++0x3
line.long 0x0 "PRESETCTRLSET[$1],Set bits in PRESETCTRLn"
hexmask.long 0x0 0.--31. 1. "RST_SET,Writing ones to this register sets the corresponding bit or bits in the PRESETCTRLn register  if they are implemented. Bits that do not correspond to defined bits in PRESETCTRLn are reserved and only zeroes should be written to them."
repeat.end
endif
sif (cpuis("LPC54113*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x140)++0x3
line.long 0x0 "PRESETCTRLCLR[$1],Clear bits in PRESETCTRLn"
hexmask.long 0x0 0.--31. 1. "RST_CLR,Writing ones to this register clears the corresponding bit or bits in the PRESETCTRLn register  if they are implemented. Bits that do not correspond to defined bits in PRESETCTRLn are reserved and only zeroes should be written to them."
repeat.end
group.long 0x1F0++0x3
line.long 0x0 "SYSRSTSTAT,System reset status register"
bitfld.long 0x0 4. "SYSRST,Status of the software system reset" "0: No System reset detected,1: System reset detected. Writing a one clears this.."
bitfld.long 0x0 3. "BOD,Status of the Brown-out detect reset" "0: No BOD reset detected,1: BOD reset detected. Writing a one clears this.."
newline
bitfld.long 0x0 2. "WDT,Status of the Watchdog reset" "0: No WDT reset detected,1: WDT reset detected. Writing a one clears this.."
bitfld.long 0x0 1. "EXTRST,Status of the external RESET pin. External reset status" "0: No reset event detected.,1: Reset detected. Writing a one clears this reset."
newline
bitfld.long 0x0 0. "POR,POR reset status" "0: No POR detected,1: POR detected. Writing a one clears this reset."
group.long 0x200++0x7
line.long 0x0 "AHBCLKCTRL0,AHB Clock control n"
bitfld.long 0x0 27. "ADC0,Enables the clock for the ADC0 register interface. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 26. "MAILBOX,Enables the clock for the Mailbox. 0 = Disable; 1 = Enable. Present on selected devices" "0: Disable,1: Enable"
newline
bitfld.long 0x0 23. "RTC,Enables the bus clock for the RTC. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 22. "WWDT,Enables the clock for the Watchdog Timer. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 21. "CRC,Enables the clock for the CRC engine. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 20. "DMA0,Enables the clock for the DMA0 controller. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 19. "GINT,Enables the clock for the grouped pin interrupt block. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 18. "PINT,Enables the clock for the pin interrupt block.0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 15. "GPIO1,Enables the clock for the GPIO1 port registers. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 14. "GPIO0,Enables the clock for the GPIO0 port registers. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 13. "IOCON,Enables the clock for the IOCON block. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 11. "INPUTMUX,Enables the clock for the input muxes. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 8. "FMC,Enables the clock for the Flash accelerator. 0 = Disable; 1 = Enable. This clock is needed if the flash is being read." "0: Disable,1: Enable"
bitfld.long 0x0 7. "FLASH,Enables the clock for the flash controller. 0 = Disable; 1 = Enable. This clock is needed for flash programming  not for flash read." "0: Disable,1: Enable"
newline
bitfld.long 0x0 4. "SRAM2,Enables the clock for SRAM2. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 3. "SRAM1,Enables the clock for SRAM1. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 1. "ROM,Enables the clock for the Boot ROM. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
line.long 0x4 "AHBCLKCTRL1,AHB Clock control n"
bitfld.long 0x4 27. "CTIMER1,Enables the clock for timer CTIMER1. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 26. "CTIMER0,Enables the clock for timer CTIMER0. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 25. "USB0,Enables the clock for the USB0 interface. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 22. "CTIMER2,Enables the clock for CTIMER 2. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 19. "DMIC0,Enables the clock for the digital microphone interface. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 18. "FLEXCOMM7,Enables the clock for Flexcomm 7. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
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bitfld.long 0x4 17. "FLEXCOMM6,Enables the clock for Flexcomm 6. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 16. "FLEXCOMM5,Enables the clock for Flexcomm 5. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
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bitfld.long 0x4 15. "FLEXCOMM4,Enables the clock for Flexcomm 4. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 14. "FLEXCOMM3,Enables the clock for Flexcomm 3. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
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bitfld.long 0x4 13. "FLEXCOMM2,Enables the clock for Flexcomm 2. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 12. "FLEXCOMM1,Enables the clock for Flexcomm 1. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 11. "FLEXCOMM0,Enables the clock for Flexcomm 0. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 10. "UTICK0,Enables the clock for the Micro-tick Timer. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 2. "SCT0,Enables the clock for SCT0. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 0. "MRT0,Enables the clock for the Multi-Rate Timer. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
endif
sif (cpuis("LPC54113*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x220)++0x3
line.long 0x0 "AHBCLKCTRLSET[$1],Set bits in AHBCLKCTRLn"
hexmask.long 0x0 0.--31. 1. "CLK_SET,Writing ones to this register sets the corresponding bit or bits in the AHBCLKCTRLn register  if they are implemented. Bits that do not correspond to defined bits in AHBCLKCTRLn are reserved and only zeroes should be written to them."
repeat.end
endif
sif (cpuis("LPC54113*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x240)++0x3
line.long 0x0 "AHBCLKCTRLCLR[$1],Clear bits in AHBCLKCTRLn"
hexmask.long 0x0 0.--31. 1. "CLK_CLR,Writing ones to this register clears the corresponding bit or bits in the AHBCLKCTRLn register  if they are implemented. Bits that do not correspond to defined bits in AHBCLKCTRLn are reserved and only zeroes should be written to them."
repeat.end
group.long 0x280++0xB
line.long 0x0 "MAINCLKSELA,Main clock source select A"
bitfld.long 0x0 0.--1. "SEL,Clock source for main clock source selector A" "0: FRO 12 MHz (fro_12m),1: CLKIN (clk_in),2: Watchdog oscillator (wdt_clk),3: FRO 96 or 48 MHz (fro_hf)"
line.long 0x4 "MAINCLKSELB,Main clock source select B"
bitfld.long 0x4 0.--1. "SEL,Clock source for main clock source selector B. Selects the clock source for the main clock." "0: MAINCLKSELA. Use the clock source selected in..,?,2: System PLL output (pll_clk),3: RTC oscillator 32 kHz output (32k_clk)"
line.long 0x8 "CLKOUTSELA,CLKOUT clock source select A"
bitfld.long 0x8 0.--2. "SEL,CLKOUT clock source selection" "0: Main clock (main_clk),1: CLKIN (clk_in),2: Watchdog oscillator (wdt_clk),3: FRO 96 or 48 MHz (fro_hf),4: PLL output (pll_clk),5: FRO 12 MHz (fro_12m),6: RTC oscillator 32 kHz output (32k_clk),7: None this may be selected in order to reduce.."
group.long 0x290++0x3
line.long 0x0 "SYSPLLCLKSEL,PLL clock source select"
bitfld.long 0x0 0.--2. "SEL,System PLL clock source selection" "0: FRO 12 MHz (fro_12m),1: CLKIN (clk_in),2: Watchdog oscillator (wdt_clk),3: RTC 32 kHz clock (32k_clk),?,?,?,7: None this may be selected in order to reduce.."
group.long 0x2A0++0xB
line.long 0x0 "SPIFICLKSEL,SPIFI clock source select"
bitfld.long 0x0 0.--2. "SEL,System PLL clock source selection" "0: Main clock (main_clk),1: System PLL output (pll_clk),?,3: FRO 96 or 48 MHz (fro_hf),?,?,?,7: None this may be selected in order to reduce.."
line.long 0x4 "ADCCLKSEL,ADC clock source select"
bitfld.long 0x4 0.--2. "SEL,ADC clock source selection" "0: Main clock (main_clk),1: System PLL output (pll_clk),2: FRO 96 or 48 MHz (fro_hf),?,?,?,?,7: None this may be selected in order to reduce.."
line.long 0x8 "USBCLKSEL,USB clock source select"
bitfld.long 0x8 0.--2. "SEL,USB device clock source selection" "0: FRO 96 or 48 MHz (fro_hf),1: System PLL output (pll_clk),2: Main clock (main_clk),?,?,?,?,7: None this may be selected in order to reduce.."
endif
sif (cpuis("LPC54113*"))
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2B0)++0x3
line.long 0x0 "FXCOMCLKSEL[$1],Flexcomm 0 clock source select"
bitfld.long 0x0 0.--2. "SEL,Flexcomm clock source selection. One per Flexcomm." "0: FRO 12 MHz (fro_12m),1: FRO 96 or 48 MHz (fro_hf),2: System PLL output (pll_clk),3: MCLK pin input when selected in IOCON (mclk_in),4: FRG clock the output of the fractional rate..,?,?,7: None this may be selected in order to reduce.."
repeat.end
group.long 0x2E0++0x3
line.long 0x0 "MCLKCLKSEL,MCLK clock source select"
bitfld.long 0x0 0.--2. "SEL,MCLK source select. This may be used by Flexcomms that support I2S  and/or by the digital microphone subsystem." "0: FRO 96 or 48 MHz (fro_hf),1: System PLL output (pll_clk),2: Main clock (main_clk),?,?,?,?,7: None this may be selected in order to reduce.."
group.long 0x2E8++0x7
line.long 0x0 "FRGCLKSEL,Fractional Rate Generator clock source select"
bitfld.long 0x0 0.--2. "SEL,Fractional Rate Generator clock source select." "0: Main clock (main_clk),1: System PLL output (pll_clk),2: FRO 12 MHz (fro_12m),3: FRO 96 or 48 MHz (fro_hf),?,?,?,7: None this may be selected in order to reduce.."
line.long 0x4 "DMICCLKSEL,Digital microphone (D-Mic) subsystem clock select"
bitfld.long 0x4 0.--2. "SEL,D-Mic subsystem clock source select." "0: FRO 12 MHz (fro_12m),1: FRO 96 or 48 MHz (fro_hf),2: System PLL output (pll_clk),3: MCLK pin input when selected in IOCON (mclk_in),4: Main clock (main_clk),5: Watchdog oscillator (wdt_clk),?,7: None this may be selected in order to reduce.."
group.long 0x300++0x7
line.long 0x0 "SYSTICKCLKDIV,SYSTICK clock divider"
bitfld.long 0x0 30. "HALT,Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output." "0,1"
bitfld.long 0x0 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count." "0,1"
newline
hexmask.long.byte 0x0 0.--7. 1. "DIV,Clock divider value. 0: Divide by 1 up to 255: Divide by 256."
line.long 0x4 "TRACECLKDIV,Trace clock divider"
bitfld.long 0x4 30. "HALT,Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output." "0,1"
bitfld.long 0x4 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count." "0,1"
newline
hexmask.long.byte 0x4 0.--7. 1. "DIV,Clock divider value. 0: Divide by 1 up to 255: Divide by 256."
group.long 0x380++0x7
line.long 0x0 "AHBCLKDIV,AHB clock divider"
bitfld.long 0x0 30. "HALT,Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output." "0,1"
bitfld.long 0x0 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count." "0,1"
newline
hexmask.long.byte 0x0 0.--7. 1. "DIV,Clock divider value. 0: Divide by 1 up to 255: Divide by 256."
line.long 0x4 "CLKOUTDIV,CLKOUT clock divider"
bitfld.long 0x4 30. "HALT,Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output." "0,1"
bitfld.long 0x4 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count." "0,1"
newline
hexmask.long.byte 0x4 0.--7. 1. "DIV,Clock divider value. 0: Divide by 1 up to 255: Divide by 256."
group.long 0x390++0xB
line.long 0x0 "SPIFICLKDIV,SPIFI clock divider"
bitfld.long 0x0 30. "HALT,Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output." "0,1"
bitfld.long 0x0 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count." "0,1"
newline
hexmask.long.byte 0x0 0.--7. 1. "DIV,Clock divider value. 0: Divide by 1 up to 255: Divide by 256."
line.long 0x4 "ADCCLKDIV,ADC clock divider"
bitfld.long 0x4 30. "HALT,Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output." "0,1"
bitfld.long 0x4 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count." "0,1"
newline
hexmask.long.byte 0x4 0.--7. 1. "DIV,Clock divider value. 0: Divide by 1 up to 255: Divide by 256."
line.long 0x8 "USBCLKDIV,USB clock divider"
bitfld.long 0x8 30. "HALT,Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output." "0,1"
bitfld.long 0x8 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count." "0,1"
newline
hexmask.long.byte 0x8 0.--7. 1. "DIV,Clock divider value. 0: Divide by 1 up to 255: Divide by 256."
group.long 0x3A0++0x3
line.long 0x0 "FRGCTRL,Fractional rate divider"
hexmask.long.byte 0x0 8.--15. 1. "MULT,Numerator of the fractional divider. MULT is equal to the programmed value."
hexmask.long.byte 0x0 0.--7. 1. "DIV,Denominator of the fractional divider. DIV is equal to the programmed value +1. Always set to 0xFF to use with the fractional baud rate generator."
group.long 0x3A8++0x7
line.long 0x0 "DMICCLKDIV,DMIC clock divider"
bitfld.long 0x0 30. "HALT,Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output." "0,1"
bitfld.long 0x0 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count." "0,1"
newline
hexmask.long.byte 0x0 0.--7. 1. "DIV,Clock divider value. 0: Divide by 1 up to 255: Divide by 256."
line.long 0x4 "MCLKDIV,I2S MCLK clock divider"
bitfld.long 0x4 30. "HALT,Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output." "0,1"
bitfld.long 0x4 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count." "0,1"
newline
hexmask.long.byte 0x4 0.--7. 1. "DIV,Clock divider value. 0: Divide by 1 up to 255: Divide by 256."
group.long 0x400++0x3
line.long 0x0 "FLASHCFG,Flash wait states configuration"
hexmask.long.byte 0x0 12.--15. 1. "FLASHTIM,Flash memory access time. The number of system clocks used for flash accesses is equal to FLASHTIM +1."
bitfld.long 0x0 6. "PREFOVR,Prefetch override. This bit only applies when PREFEN = 1 and a buffered instruction is completing for which the next flash line is not already buffered or being prefetched." "0: Any previously initiated prefetch will be..,1: Any previously initiated prefetch will be.."
newline
bitfld.long 0x0 5. "PREFEN,Prefetch enable." "0: No instruction prefetch is performed.,1: If the FETCHCFG field is not 0 the next flash.."
bitfld.long 0x0 4. "ACCEL,Acceleration enable." "0: Flash acceleration is disabled. Every flash read..,1: Flash acceleration is enabled. Performance is.."
newline
bitfld.long 0x0 2.--3. "DATACFG,Data read configuration. This field determines how flash accelerator buffers are used for data accesses." "0: Data accesses from flash are not buffered. Every..,1: One buffer is used for all data accesses.,2: All buffers may be used for data accesses.,?"
bitfld.long 0x0 0.--1. "FETCHCFG,Instruction fetch configuration. This field determines how flash accelerator buffers are used for instruction fetches." "0: Instruction fetches from flash are not buffered.,1: One buffer is used for all instruction fetches.,2: All buffers may be used for instruction fetches.,?"
group.long 0x40C++0x7
line.long 0x0 "USBCLKCTRL,USB clock control"
bitfld.long 0x0 1. "POL_CLK,USB_NEED_CLK polarity for triggering the USB wake-up interrupt" "0: Falling edge of the USB_NEED_CLK triggers the..,1: Rising edge of the USB_NEED_CLK triggers the USB.."
line.long 0x4 "USBCLKSTAT,USB clock status"
bitfld.long 0x4 0. "NEED_CLKST,USB_NEED_CLK signal status" "0: Low,1: High"
group.long 0x418++0x3
line.long 0x0 "FREQMECTRL,Frequency measure register"
bitfld.long 0x0 31. "PROG,Set this bit to one to initiate a frequency measurement cycle. Hardware clears this bit when the measurement cycle has completed and there is valid capture data in the CAPVAL field (bits 13:0)." "0,1"
hexmask.long.word 0x0 0.--13. 1. "CAPVAL,Stores the capture result which is used to calculate the frequency of the target clock. This field is read-only."
group.long 0x420++0x3
line.long 0x0 "MCLKIO,MCLK input/output control"
bitfld.long 0x0 0. "DIR,MCLK direction control." "0: The MCLK function is an input.,1: The MCLK function is an output."
group.long 0x500++0x3
line.long 0x0 "FROCTRL,FRO oscillator control"
bitfld.long 0x0 31. "WRTRIM,Write Trim value. Must be written to 1 to modify the SEL or TRIM fields  during the same write. This bit always reads as 0." "0,1"
bitfld.long 0x0 30. "HSPDCLK,High speed clock disable. Allows disabling the highs-speed FRO output if it is not needed." "0: The high-speed FRO output is disabled.,1: The selected high-speed FRO output (48 MHz or 96.."
newline
bitfld.long 0x0 25. "USBMODCHG,USB Mode value Change flag. When 1  indicates that the USB trim is currently being updated (or is still starting up) and software should wait to read FREQTRIM. Update occurs at most once per millisecond." "0,1"
bitfld.long 0x0 24. "USBCLKADJ,USB clock adjust mode." "0: Normal operation.,1: Automatic USB rate adjustment mode. If the USB.."
newline
hexmask.long.byte 0x0 16.--23. 1. "FREQTRIM,Frequency trim. Boot code configures this to a device-specific factory trim value for the 96 MHz FRO. If USBCLKADJ = 1  this field is read-only and provides the value resulting from USB rate adjustment. See the USBMODCFG flag regarding reading.."
bitfld.long 0x0 14. "SEL,Select the fro_hf output frequency. This bit can only be changed by software when the WRTRIM bit = 1. Note that the factory trim values are for the 96 MHz FRO only." "0: 48 MHz,1: 96 MHz"
newline
hexmask.long.word 0x0 0.--13. 1. "TRIM,This value is factory trimmed to account for bias and temperature compensation. The value should not be changed by software. Also see the WRTRIM bit description."
group.long 0x508++0x7
line.long 0x0 "WDTOSCCTRL,Watchdog oscillator control"
hexmask.long.byte 0x0 5.--9. 1. "FREQSEL,Frequency select. Selects the frequency of the oscillator. 0x00 = invalid setting when watchdog oscillator is running 0x01 = 0.4 MHz 0x02 = 0.6 MHz 0x03 = 0.75 MHz 0x04 = 0.9 MHz 0x05 = 1.0 MHz 0x06 = 1.2 MHz 0x07 = 1.3 MHz 0x08 = 1.4 MHz 0x09 =.."
hexmask.long.byte 0x0 0.--4. 1. "DIVSEL,Divider select. Selects the value of the divider that adjusts the output of the oscillator. 0x00 = divide by 2 0x01 = divide by 4 0x02 = divide by 6 up to 0x1E = divide by 62 0x1F = divide by 64"
line.long 0x4 "RTCOSCCTRL,RTC oscillator 32 kHz output control"
bitfld.long 0x4 0. "EN,RTC 32 kHz clock enable." "0: Disabled. RTC clock off.,1: Enabled. RTC clock on."
group.long 0x580++0x3
line.long 0x0 "SYSPLLCTRL,PLL control"
bitfld.long 0x0 20. "DIRECTO,PLL0 direct output enable." "0: Disabled. The PLL output divider (P divider) is..,1: Enabled. The PLL output divider (P divider) is.."
bitfld.long 0x0 19. "DIRECTI,PLL0 direct input enable" "0: Disabled. The PLL input divider (N divider)..,1: Enabled. The PLL input divider (N divider) is.."
newline
bitfld.long 0x0 18. "BANDSEL,PLL filter control. Set this bit to one when the spread spectrum controller is disabled or at low frequencies. For spread spectrum mode: SEL_EXT = 0  BANDSEL = 0  and UPLIMOFF = 1." "0: SSCG control. The PLL filter uses the parameters..,1: MDEC control. The PLL filter uses the.."
bitfld.long 0x0 17. "UPLIMOFF,Disable upper frequency limiter." "0: Normal mode.,1: Upper frequency limiter disabled."
newline
bitfld.long 0x0 16. "BYPASSCCODIV2,Bypass feedback clock divide by 2." "0: Divide by 2. The CCO feedback clock is divided..,1: Bypass. The CCO feedback clock is divided only.."
bitfld.long 0x0 15. "BYPASS,PLL bypass control." "0: Bypass disabled. PLL CCO is sent to the PLL..,1: Bypass enabled. PLL input clock is sent directly.."
newline
hexmask.long.byte 0x0 10.--14. 1. "SELP,Bandwidth select P value"
hexmask.long.byte 0x0 4.--9. 1. "SELI,Bandwidth select I value."
newline
hexmask.long.byte 0x0 0.--3. 1. "SELR,Bandwidth select R value"
rgroup.long 0x584++0x3
line.long 0x0 "SYSPLLSTAT,PLL status"
bitfld.long 0x0 0. "LOCK,PLL0 lock indicator" "0,1"
group.long 0x588++0xF
line.long 0x0 "SYSPLLNDEC,PLL N decoder"
bitfld.long 0x0 10. "NREQ,NDEC reload request. When a 1 is written to this bit  the NDEC value is loaded into the PLL. Must be cleared by software for any subsequent load  or the PLL can be powered down and back up via the PDEN_SYS_PLL bit in the PDRUNCFG register if the.." "0,1"
hexmask.long.word 0x0 0.--9. 1. "NDEC,Decoded N-divider coefficient value."
line.long 0x4 "SYSPLLPDEC,PLL P decoder"
bitfld.long 0x4 7. "PREQ,PDEC reload request. When a 1 is written to this bit  the PDEC value is loaded into the PLL. Must be cleared by software for any subsequent load  or the PLL can be powered down and back up via the PDEN_SYS_PLL bit in the PDRUNCFG register if the.." "0,1"
hexmask.long.byte 0x4 0.--6. 1. "PDEC,Decoded P-divider coefficient value."
line.long 0x8 "SYSPLLSSCTRL0,PLL spread spectrum control 0"
bitfld.long 0x8 18. "SEL_EXT,Select spread spectrum mode. Selects the source of the feedback divider value. For normal mode  this must be the value from the MDEC field in this register. For spread spectrum mode: SEL_EXT = 0  BANDSEL = 0  and UPLIMOFF = 1." "0,1"
bitfld.long 0x8 17. "MREQ,MDEC reload request. When a 1 is written to this bit  the MDEC value is loaded into the PLL. Must be cleared by software for any subsequent load  or the PLL can be powered down and back up via the PDEN_SYS_PLL bit in the PDRUNCFG register if the.." "0,1"
newline
hexmask.long.tbyte 0x8 0.--16. 1. "MDEC,Decoded M-divider coefficient value."
line.long 0xC "SYSPLLSSCTRL1,PLL spread spectrum control 1"
bitfld.long 0xC 29. "DITHER,Select modulation frequency." "0: Fixed. Fixed modulation frequency.,1: Dither. Randomly dither between two modulation.."
bitfld.long 0xC 28. "PD,Spread spectrum power-down." "0: Enabled. Spread spectrum controller is enabled,1: Disabled. Spread spectrum controller is disabled."
newline
bitfld.long 0xC 26.--27. "MC,Modulation waveform control. 0 = no compensation. Compensation for low pass filtering of the PLL to get a triangular modulation at the output of the PLL  giving a flat frequency spectrum. 0b00 => no compensation 0b10 => recommended setting 0b11 =>.." "0: no compensation,?,2: recommended setting,3: max"
bitfld.long 0xC 23.--25. "MR,Programmable frequency modulation depth. 0 = no spread. _fmodpk-pk = Fref x k/Fcco = k/MDdec 0b000 -> k = 0 (no spread spectrum) 0b001 => k _ 1 0b010 => k _ 1.5 0b011 => k _ 2 0b100 => k _ 3 0b101 => k _ 4 0b110 => k _ 6 0b111 => k _ 8" "0: k = 0,1: k _ 1,2: k _ 1,3: k _ 2,4: k _ 3,5: k _ 4,6: k _ 6,7: k _ 8"
newline
bitfld.long 0xC 20.--22. "MF,Programmable modulation frequency fm = Fref/Nss with Fref = Fin/N 0b000 => Nss = 512 (fm _ 3.9 - 7.8 kHz) 0b001 => Nss _ 384 (fm _ 5.2 - 10.4 kHz) 0b010 => Nss = 256 (fm _ 7.8 - 15.6 kHz) 0b011 => Nss = 128 (fm _ 15.6 - 31.3 kHz) 0b100 => Nss = 64 (fm.." "0: Nss = 512,1: Nss _ 384,2: Nss = 256,3: Nss = 128,4: Nss = 64,5: Nss = 32,6: Nss _ 24,7: Nss = 16"
bitfld.long 0xC 19. "MDREQ,MD reload request. When a 1 is written to this bit  the MD value is loaded into the PLL. This bit is cleared when the load is complete" "0,1"
newline
hexmask.long.tbyte 0xC 0.--18. 1. "MD,M- divider value with fraction. MD[18:11]: integer portion of the feedback divider value. MD[10:0]: fractional portion of the feedback divider value. In fractional mode  fcco = (2 - BYPASSCCODIV2) x (MD x 2^-11) x Fref"
group.long 0x600++0x7
line.long 0x0 "PDSLEEPCFG0,Sleep configuration register n"
hexmask.long 0x0 0.--31. 1. "PD_SLEEP,See bit descriptions in the PDRUNCFGn register."
line.long 0x4 "PDSLEEPCFG1,Sleep configuration register n"
hexmask.long 0x4 0.--31. 1. "PD_SLEEP,See bit descriptions in the PDRUNCFGn register."
group.long 0x610++0x7
line.long 0x0 "PDRUNCFG0,Power configuration register n"
bitfld.long 0x0 25. "PD_FLASH_BG,Part of flash power control." "0,1"
bitfld.long 0x0 23. "PDEN_VREFP,Vrefp to the ADC  must be enabled for the ADC to work. Also see bit 19. 0 = Powered; 1 = Powered down." "0: Powered,1: Powered down"
newline
bitfld.long 0x0 22. "PDEN_SYS_PLL,PLL0. 0 = Powered; 1 = Powered down." "0: Powered,1: Powered down"
bitfld.long 0x0 21. "PDEN_USB_PHY,USB pin interface. 0 = Powered; 1 = Powered down." "0: Powered,1: Powered down"
newline
bitfld.long 0x0 20. "PDEN_WDT_OSC,Watchdog oscillator. 0 = Powered; 1 = Powered down." "0: Powered,1: Powered down"
bitfld.long 0x0 19. "PDEN_VDDA,Vdda to the ADC  must be enabled for the ADC to work. Also see bit 23. 0 = Powered; 1 = Powered down." "0: Powered,1: Powered down"
newline
bitfld.long 0x0 18. "PD_VDDHV_ENA,Part of flash power control." "0,1"
bitfld.long 0x0 17. "PDEN_ROM,ROM. 0 = Powered; 1 = Powered down." "0: Powered,1: Powered down"
newline
bitfld.long 0x0 16. "PDEN_SRAMX,SRAMX. 0 = Powered; 1 = Powered down." "0: Powered,1: Powered down"
bitfld.long 0x0 15. "PDEN_SRAM2,SRAM2. 0 = Powered; 1 = Powered down." "0: Powered,1: Powered down"
newline
bitfld.long 0x0 14. "PDEN_SRAM1,SRAM1. 0 = Powered; 1 = Powered down." "0: Powered,1: Powered down"
bitfld.long 0x0 13. "PDEN_SRAM0,SRAM0. 0 = Powered; 1 = Powered down." "0: Powered,1: Powered down"
newline
bitfld.long 0x0 12. "LP_VDDFLASH,Part of flash power control." "0,1"
bitfld.long 0x0 11. "PD_VDDFLASH,Part of flash power control." "0,1"
newline
bitfld.long 0x0 10. "PDEN_ADC0,ADC0. 0 = Powered; 1 = Powered down." "0: Powered,1: Powered down"
bitfld.long 0x0 8. "PDEN_BOD_INTR,Brown-out Detect interrupt. 0 = Powered; 1 = Powered down." "0: Powered,1: Powered down"
newline
bitfld.long 0x0 7. "PDEN_BOD_RST,Brown-out Detect reset. 0 = Powered; 1 = Powered down." "0: Powered,1: Powered down"
bitfld.long 0x0 6. "PDEN_TS,Temp sensor. 0 = Powered; 1 = Powered down." "0: Powered,1: Powered down"
newline
bitfld.long 0x0 5. "PD_FLASH,Part of flash power control." "0,1"
bitfld.long 0x0 4. "PDEN_FRO,FRO oscillator. 0 = Powered; 1 = Powered down." "0: Powered,1: Powered down"
line.long 0x4 "PDRUNCFG1,Power configuration register n"
bitfld.long 0x4 29. "SEL_ALT_FLASH_IBG,Part of flash power control." "0,1"
bitfld.long 0x4 28. "PD_ALT_FLASH_IBG,Part of flash power control." "0,1"
endif
sif (cpuis("LPC54113*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x620)++0x3
line.long 0x0 "PDRUNCFGSET[$1],Set bits in PDRUNCFGn"
hexmask.long 0x0 0.--31. 1. "PD_SET,Writing ones to this register sets the corresponding bit or bits in the PDRUNCFG register  if they are implemented. Bits that do not correspond to defined bits in PDRUNCFG are reserved and only zeroes should be written to them."
repeat.end
endif
sif (cpuis("LPC54113*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x630)++0x3
line.long 0x0 "PDRUNCFGCLR[$1],Clear bits in PDRUNCFGn"
hexmask.long 0x0 0.--31. 1. "PD_CLR,Writing ones to this register clears the corresponding bit or bits in the PDRUNCFG register  if they are implemented. Bits that do not correspond to defined bits in PDRUNCFG are reserved and only zeroes should be written to them."
repeat.end
group.long 0x680++0x7
line.long 0x0 "STARTERP0,Start logic n wake-up enable register"
bitfld.long 0x0 31. "MAILBOX,Mailbox interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.At least one CPU must be running in order for a mailbox interrupt to occur. Present on selected devices." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x0 29. "RTC,RTC interrupt alarm and wake-up timer. 0 = Wake-up disabled. 1 = Wake-up enabled." "0: Wake-up disabled,1: Wake-up enabled"
newline
bitfld.long 0x0 28. "USB0,USB0 function interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x0 27. "USB0_NEEDCLK,USB0 activity interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled." "0: Wake-up disabled,1: Wake-up enabled"
newline
bitfld.long 0x0 25. "DMIC0,Digital microphone interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x0 24. "ADC0_THCMP,ADC0 threshold and error interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only since the peripheral clock must be running for it to function." "0: Wake-up disabled,1: Wake-up enabled"
newline
bitfld.long 0x0 23. "ADC0_SEQB,ADC0 sequence B interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only since the peripheral clock must be running for it to function." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x0 22. "ADC0_SEQA,ADC0 sequence A interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only since the peripheral clock must be running for it to function." "0: Wake-up disabled,1: Wake-up enabled"
newline
bitfld.long 0x0 21. "FLEXCOMM7,Flexcomm7 peripheral interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x0 20. "FLEXCOMM6,Flexcomm6 peripheral interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled." "0: Wake-up disabled,1: Wake-up enabled"
newline
bitfld.long 0x0 19. "FLEXCOMM5,Flexcomm5 peripheral interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x0 18. "FLEXCOMM4,Flexcomm4 peripheral interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled." "0: Wake-up disabled,1: Wake-up enabled"
newline
bitfld.long 0x0 17. "FLEXCOMM3,Flexcomm3 peripheral interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x0 16. "FLEXCOMM2,Flexcomm2 peripheral interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled." "0: Wake-up disabled,1: Wake-up enabled"
newline
bitfld.long 0x0 15. "FLEXCOMM1,Flexcomm1 peripheral interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x0 14. "FLEXCOMM0,Flexcomm0 peripheral interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled." "0: Wake-up disabled,1: Wake-up enabled"
newline
bitfld.long 0x0 13. "CTIMER3,Standard counter/timer CTIMER3 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only since the peripheral clock must be running for it to function." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x0 12. "SCT0,SCT0 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only since the peripheral clock must be running for it to function." "0: Wake-up disabled,1: Wake-up enabled"
newline
bitfld.long 0x0 11. "CTIMER1,Standard counter/timer CTIMER1 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only since the peripheral clock must be running for it to function." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x0 10. "CTIMER0,Standard counter/timer CTIMER0 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only since the peripheral clock must be running for it to function." "0: Wake-up disabled,1: Wake-up enabled"
newline
bitfld.long 0x0 9. "MRT0,Multi-Rate Timer wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Typically used in sleep mode only since the peripheral clock must be running for it to function." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x0 8. "UTICK0,Micro-tick Timer wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled." "0: Wake-up disabled,1: Wake-up enabled"
newline
bitfld.long 0x0 7. "PIN_INT3,GPIO pin interrupt 3 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x0 6. "PIN_INT2,GPIO pin interrupt 2 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match." "0: Wake-up disabled,1: Wake-up enabled"
newline
bitfld.long 0x0 5. "PIN_INT1,GPIO pin interrupt 1 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x0 4. "PIN_INT0,GPIO pin interrupt 0 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match." "0: Wake-up disabled,1: Wake-up enabled"
newline
bitfld.long 0x0 3. "GINT1,Group interrupt 1 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x0 2. "GINT0,Group interrupt 0 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled." "0: Wake-up disabled,1: Wake-up enabled"
newline
bitfld.long 0x0 1. "DMA0,DMA0 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Typically used in sleep mode only since the peripheral clock must be running for it to function." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x0 0. "WDT_BOD,WWDT and BOD interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled." "0: Wake-up disabled,1: Wake-up enabled"
line.long 0x4 "STARTERP1,Start logic n wake-up enable register"
bitfld.long 0x4 5. "CTIMER4,Standard counter/timer CTIMER4 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only since the peripheral clock must be running for it to function." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x4 4. "CTIMER2,Standard counter/timer CTIMER2 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only since the peripheral clock must be running for it to function." "0: Wake-up disabled,1: Wake-up enabled"
newline
bitfld.long 0x4 3. "PINT7,GPIO pin interrupt 7 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x4 2. "PINT6,GPIO pin interrupt 6 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match." "0: Wake-up disabled,1: Wake-up enabled"
newline
bitfld.long 0x4 1. "PINT5,GPIO pin interrupt 5 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x4 0. "PINT4,GPIO pin interrupt 4 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match." "0: Wake-up disabled,1: Wake-up enabled"
group.long 0x780++0x3
line.long 0x0 "HWWAKE,Configures special cases of hardware wake-up"
bitfld.long 0x0 3. "WAKEDMA,Wake for DMA. When 1  DMA being busy will cause peripheral clocking to remain running until DMA completes. This is generally used in conjunction with bit 1 and/or 2 in order to prevent peripheral clocking from being shut down as soon as the cause.." "0,1"
bitfld.long 0x0 2. "WAKEDMIC,Wake for Digital Microphone. When 1  the digital microphone input FIFO reaching the level specified by TRIGLVL of either channel will cause peripheral clocking to wake up temporarily while the related status is asserted." "0,1"
newline
bitfld.long 0x0 1. "FCWAKE,Wake for Flexcomms. When 1  any Flexcomm FIFO reaching the level specified by its own TXLVL will cause peripheral clocking to wake up temporarily while the related status is asserted." "0,1"
bitfld.long 0x0 0. "FORCEWAKE,Force peripheral clocking to stay on during Deep Sleep and Power-down modes. When 1  clocking to peripherals is prevented from being shut down when the CPU enters Deep Sleep and Power-down modes. This is intended to allow a coprocessor to.." "0,1"
group.long 0x800++0xB
line.long 0x0 "CPUCTRL,CPU Control for multiple processors"
bitfld.long 0x0 6. "POWERCPU,Identifies the owner of reduced power mode control: which CPU can cause the device to enter Deep Sleep  Power-down  and Deep Power-down modes." "0: M0+. Cortex-M0+ is the owner of reduced power..,1: M4. Cortex-M4 is the owner of reduced power mode.."
bitfld.long 0x0 5. "CM0RSTEN,Cortex-M0+ reset." "0: Disabled. The Cortex-M0+ is not being reset.,1: Enabled. The Cortex-M0+ is being reset."
newline
bitfld.long 0x0 4. "CM4RSTEN,Cortex-M4 reset." "0: Disabled. The Cortex-M4 is not being reset.,1: Enabled. The Cortex-M4 is being reset."
bitfld.long 0x0 3. "CM0CLKEN,Cortex-M0+ clock enable" "0: Disabled. The Cortex-M0+ clock is not enabled.,1: Enabled. The Cortex-M0+ clock is enabled."
newline
bitfld.long 0x0 2. "CM4CLKEN,Cortex-M4 clock enable" "0: Disabled. The Cortex-M4 clock is not enabled,1: Enabled. The Cortex-M4 clock is enabled."
bitfld.long 0x0 0. "MASTERCPU,Indicates which CPU is considered the master. This is factory set assign the Cortex-M4 as the master. The master CPU cannot have its clock turned off via the related CMnCLKEN bit or be reset via the related CMxRSTEN in this register. The slave.." "0: M0+. Cortex-M0+ is the master CPU.,1: M4. Cortex-M4 is the master CPU."
line.long 0x4 "CPBOOT,Coprocessor Boot Address"
hexmask.long 0x4 0.--31. 1. "BOOTADDR,Slave processor boot address"
line.long 0x8 "CPSTACK,Coprocessor Stack Address"
hexmask.long 0x8 0.--31. 1. "STACKADDR,Slave processor stack address"
rgroup.long 0x80C++0x3
line.long 0x0 "CPSTAT,Coprocessor Status"
bitfld.long 0x0 3. "CM0LOCKUP,When 1  the Cortex-M0+ CPU is in lockup." "0,1"
bitfld.long 0x0 2. "CM4LOCKUP,When 1  the Cortex-M4 CPU is in lockup" "0,1"
newline
bitfld.long 0x0 1. "CM0SLEEPING,When 1  the Cortex-M0+ CPU is sleeping" "0,1"
bitfld.long 0x0 0. "CM4SLEEPING,When 1  the Cortex-M4 CPU is sleeping" "0,1"
group.long 0xE04++0x3
line.long 0x0 "AUTOCGOR,Auto Clock-Gate Override Register"
bitfld.long 0x0 3. "RAM2,When 1  automatic clock gating for RAM2 is turned off." "0,1"
bitfld.long 0x0 2. "RAM1,When 1  automatic clock gating for RAM1 is turned off." "0,1"
newline
bitfld.long 0x0 1. "RAM0X,When 1  automatic clock gating for RAMX and RAM0 are turned off." "0,1"
rgroup.long 0xFF4++0xB
line.long 0x0 "JTAGIDCODE,JTAG ID code register"
hexmask.long 0x0 0.--31. 1. "JTAGID,JTAG ID code."
line.long 0x4 "DEVICE_ID0,Part ID register"
hexmask.long 0x4 0.--31. 1. "PARTID,Part ID"
line.long 0x8 "DEVICE_ID1,Boot ROM and die revision register"
hexmask.long 0x8 0.--31. 1. "REVID,Revision."
group.long 0x20044++0x3
line.long 0x0 "BODCTRL,Brown-Out Detect control"
bitfld.long 0x0 7. "BODINTSTAT,BOD interrupt status. When 1  a BOD interrupt has occurred. Cleared by writing 1 to this bit." "0,1"
bitfld.long 0x0 6. "BODRSTSTAT,BOD reset status. When 1  a BOD reset has occurred. Cleared by writing 1 to this bit." "0,1"
newline
bitfld.long 0x0 5. "BODINTENA,BOD interrupt enable" "0: Disable interrupt function.,1: Enable interrupt function."
bitfld.long 0x0 3.--4. "BODINTLEV,BOD interrupt level" "0: Level 0: 2.05 V,1: Level 1: 2.45 V,2: Level 2: 2.75 V,3: Level 3: 3.05 V"
newline
bitfld.long 0x0 2. "BODRSTENA,BOD reset enable" "0: Disable reset function.,1: Enable reset function."
bitfld.long 0x0 0.--1. "BODRSTLEV,BOD reset level" "0: Level 0: 1.5 V,1: Level 1: 1.85 V,2: Level 2: 2.0 V,3: Level 3: 2.3 V"
endif
sif (cpuis("LPC54114*"))
group.long 0x0++0x3
line.long 0x0 "SYSMEMREMAP,System Remap register"
group.long 0x10++0x3
line.long 0x0 "AHBMATPRIO,AHB multilayer matrix priority control"
bitfld.long 0x0 10.--11. "PRI_DMA,DMA controller priority." "0,1,2,3"
bitfld.long 0x0 8.--9. "PRI_USB,USB interface priority." "0,1,2,3"
newline
bitfld.long 0x0 6.--7. "PRI_M0,Cortex-M0+ bus priority. Present on selected devices." "0,1,2,3"
bitfld.long 0x0 4.--5. "PRI_SYS,Cortex M4 System bus priority." "0,1,2,3"
newline
bitfld.long 0x0 2.--3. "PRI_DCODE,Cortex M4 D-Code bus priority." "0,1,2,3"
bitfld.long 0x0 0.--1. "PRI_ICODE,Cortex-M4 I-Code bus priority. Should typically be lower than PRI_DCODE for best operation." "0,1,2,3"
group.long 0x40++0x3
line.long 0x0 "SYSTCKCAL,System tick counter calibration"
bitfld.long 0x0 25. "NOREF,Initial value for the Systick timer." "0,1"
bitfld.long 0x0 24. "SKEW,Initial value for the Systick timer." "0,1"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "CAL,System tick timer calibration value."
group.long 0x48++0x7
line.long 0x0 "NMISRC,NMI Source Select"
bitfld.long 0x0 31. "NMIENM4,Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQM4." "0,1"
bitfld.long 0x0 30. "NMIENM0,Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQM0. Present on selected devices." "0,1"
newline
hexmask.long.byte 0x0 8.--13. 1. "IRQM0,The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the Cortex-M0+  if enabled by NMIENM0. Present on selected devices."
hexmask.long.byte 0x0 0.--5. 1. "IRQM4,The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the Cortex-M4  if enabled by NMIENM4."
line.long 0x4 "ASYNCAPBCTRL,Asynchronous APB Control"
bitfld.long 0x4 0. "ENABLE,Enables the asynchronous APB bridge and subsystem." "0: Disabled. Asynchronous APB bridge is disabled.,1: Enabled. Asynchronous APB bridge is enabled."
endif
sif (cpuis("LPC54114*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0xC0)++0x3
line.long 0x0 "PIOPORCAP[$1],POR captured value of port n"
hexmask.long 0x0 0.--31. 1. "PIOPORCAP,State of PIOn_31 through PIOn_0 at power-on reset"
repeat.end
endif
sif (cpuis("LPC54114*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0xD0)++0x3
line.long 0x0 "PIORESCAP[$1],Reset captured value of port n"
hexmask.long 0x0 0.--31. 1. "PIORESCAP,State of PIOn_31 through PIOn_0 for resets other than POR."
repeat.end
group.long 0x100++0x7
line.long 0x0 "PRESETCTRL0,Peripheral reset control n"
bitfld.long 0x0 27. "ADC0_RST,ADC0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 22. "WWDT_RST,Watchdog timer reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x0 21. "CRC_RST,CRC generator reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 20. "DMA0_RST,DMA0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x0 19. "GINT_RST,Grouped interrupt (GINT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 18. "PINT_RST,Pin interrupt (PINT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x0 15. "GPIO1_RST,GPIO1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 14. "GPIO0_RST,GPIO0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x0 13. "IOCON_RST,IOCON reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 11. "MUX_RST,Input mux reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x0 8. "FMC_RST,Flash accelerator reset control. Note that the FMC must not be reset while executing from flash  and must be reconfigured after reset. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 7. "FLASH_RST,Flash controller reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
line.long 0x4 "PRESETCTRL1,Peripheral reset control n"
bitfld.long 0x4 27. "CTIMER1_RST,CTIMER1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 26. "CTIMER0_RST,CTIMER0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 25. "USB0_RST,USB0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 22. "CTIMER2_RST,CTIMER2 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function" "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 19. "DMIC0_RST,Digital microphone interface reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 18. "FC7_RST,Flexcomm 7 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 17. "FC6_RST,Flexcomm 6 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 16. "FC5_RST,Flexcomm 5 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 15. "FC4_RST,Flexcomm 4 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 14. "FC3_RST,Flexcomm 3 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 13. "FC2_RST,Flexcomm 2 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 12. "FC1_RST,Flexcomm 1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 11. "FC0_RST,Flexcomm 0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 10. "UTICK0_RST,Micro-tick Timer reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 2. "SCT0_RST,State configurable timer 0 (SCT0) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 0. "MRT0_RST,Multi-rate timer (MRT0) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
endif
sif (cpuis("LPC54114*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x120)++0x3
line.long 0x0 "PRESETCTRLSET[$1],Set bits in PRESETCTRLn"
hexmask.long 0x0 0.--31. 1. "RST_SET,Writing ones to this register sets the corresponding bit or bits in the PRESETCTRLn register  if they are implemented. Bits that do not correspond to defined bits in PRESETCTRLn are reserved and only zeroes should be written to them."
repeat.end
endif
sif (cpuis("LPC54114*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x140)++0x3
line.long 0x0 "PRESETCTRLCLR[$1],Clear bits in PRESETCTRLn"
hexmask.long 0x0 0.--31. 1. "RST_CLR,Writing ones to this register clears the corresponding bit or bits in the PRESETCTRLn register  if they are implemented. Bits that do not correspond to defined bits in PRESETCTRLn are reserved and only zeroes should be written to them."
repeat.end
group.long 0x1F0++0x3
line.long 0x0 "SYSRSTSTAT,System reset status register"
bitfld.long 0x0 4. "SYSRST,Status of the software system reset" "0: No System reset detected,1: System reset detected. Writing a one clears this.."
bitfld.long 0x0 3. "BOD,Status of the Brown-out detect reset" "0: No BOD reset detected,1: BOD reset detected. Writing a one clears this.."
newline
bitfld.long 0x0 2. "WDT,Status of the Watchdog reset" "0: No WDT reset detected,1: WDT reset detected. Writing a one clears this.."
bitfld.long 0x0 1. "EXTRST,Status of the external RESET pin. External reset status" "0: No reset event detected.,1: Reset detected. Writing a one clears this reset."
newline
bitfld.long 0x0 0. "POR,POR reset status" "0: No POR detected,1: POR detected. Writing a one clears this reset."
group.long 0x200++0x7
line.long 0x0 "AHBCLKCTRL0,AHB Clock control n"
bitfld.long 0x0 27. "ADC0,Enables the clock for the ADC0 register interface. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 26. "MAILBOX,Enables the clock for the Mailbox. 0 = Disable; 1 = Enable. Present on selected devices" "0: Disable,1: Enable"
newline
bitfld.long 0x0 23. "RTC,Enables the bus clock for the RTC. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 22. "WWDT,Enables the clock for the Watchdog Timer. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 21. "CRC,Enables the clock for the CRC engine. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 20. "DMA0,Enables the clock for the DMA0 controller. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 19. "GINT,Enables the clock for the grouped pin interrupt block. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 18. "PINT,Enables the clock for the pin interrupt block.0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 15. "GPIO1,Enables the clock for the GPIO1 port registers. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 14. "GPIO0,Enables the clock for the GPIO0 port registers. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 13. "IOCON,Enables the clock for the IOCON block. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 11. "INPUTMUX,Enables the clock for the input muxes. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 8. "FMC,Enables the clock for the Flash accelerator. 0 = Disable; 1 = Enable. This clock is needed if the flash is being read." "0: Disable,1: Enable"
bitfld.long 0x0 7. "FLASH,Enables the clock for the flash controller. 0 = Disable; 1 = Enable. This clock is needed for flash programming  not for flash read." "0: Disable,1: Enable"
newline
bitfld.long 0x0 4. "SRAM2,Enables the clock for SRAM2. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 3. "SRAM1,Enables the clock for SRAM1. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 1. "ROM,Enables the clock for the Boot ROM. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
line.long 0x4 "AHBCLKCTRL1,AHB Clock control n"
bitfld.long 0x4 27. "CTIMER1,Enables the clock for timer CTIMER1. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 26. "CTIMER0,Enables the clock for timer CTIMER0. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 25. "USB0,Enables the clock for the USB0 interface. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 22. "CTIMER2,Enables the clock for CTIMER 2. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 19. "DMIC0,Enables the clock for the digital microphone interface. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 18. "FLEXCOMM7,Enables the clock for Flexcomm 7. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 17. "FLEXCOMM6,Enables the clock for Flexcomm 6. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 16. "FLEXCOMM5,Enables the clock for Flexcomm 5. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 15. "FLEXCOMM4,Enables the clock for Flexcomm 4. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 14. "FLEXCOMM3,Enables the clock for Flexcomm 3. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 13. "FLEXCOMM2,Enables the clock for Flexcomm 2. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 12. "FLEXCOMM1,Enables the clock for Flexcomm 1. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 11. "FLEXCOMM0,Enables the clock for Flexcomm 0. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 10. "UTICK0,Enables the clock for the Micro-tick Timer. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 2. "SCT0,Enables the clock for SCT0. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 0. "MRT0,Enables the clock for the Multi-Rate Timer. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
endif
sif (cpuis("LPC54114*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x220)++0x3
line.long 0x0 "AHBCLKCTRLSET[$1],Set bits in AHBCLKCTRLn"
hexmask.long 0x0 0.--31. 1. "CLK_SET,Writing ones to this register sets the corresponding bit or bits in the AHBCLKCTRLn register  if they are implemented. Bits that do not correspond to defined bits in AHBCLKCTRLn are reserved and only zeroes should be written to them."
repeat.end
endif
sif (cpuis("LPC54114*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x240)++0x3
line.long 0x0 "AHBCLKCTRLCLR[$1],Clear bits in AHBCLKCTRLn"
hexmask.long 0x0 0.--31. 1. "CLK_CLR,Writing ones to this register clears the corresponding bit or bits in the AHBCLKCTRLn register  if they are implemented. Bits that do not correspond to defined bits in AHBCLKCTRLn are reserved and only zeroes should be written to them."
repeat.end
group.long 0x280++0xB
line.long 0x0 "MAINCLKSELA,Main clock source select A"
bitfld.long 0x0 0.--1. "SEL,Clock source for main clock source selector A" "0: FRO 12 MHz (fro_12m),1: CLKIN (clk_in),2: Watchdog oscillator (wdt_clk),3: FRO 96 or 48 MHz (fro_hf)"
line.long 0x4 "MAINCLKSELB,Main clock source select B"
bitfld.long 0x4 0.--1. "SEL,Clock source for main clock source selector B. Selects the clock source for the main clock." "0: MAINCLKSELA. Use the clock source selected in..,?,2: System PLL output (pll_clk),3: RTC oscillator 32 kHz output (32k_clk)"
line.long 0x8 "CLKOUTSELA,CLKOUT clock source select A"
bitfld.long 0x8 0.--2. "SEL,CLKOUT clock source selection" "0: Main clock (main_clk),1: CLKIN (clk_in),2: Watchdog oscillator (wdt_clk),3: FRO 96 or 48 MHz (fro_hf),4: PLL output (pll_clk),5: FRO 12 MHz (fro_12m),6: RTC oscillator 32 kHz output (32k_clk),7: None this may be selected in order to reduce.."
group.long 0x290++0x3
line.long 0x0 "SYSPLLCLKSEL,PLL clock source select"
bitfld.long 0x0 0.--2. "SEL,System PLL clock source selection" "0: FRO 12 MHz (fro_12m),1: CLKIN (clk_in),2: Watchdog oscillator (wdt_clk),3: RTC 32 kHz clock (32k_clk),?,?,?,7: None this may be selected in order to reduce.."
group.long 0x2A0++0xB
line.long 0x0 "SPIFICLKSEL,SPIFI clock source select"
bitfld.long 0x0 0.--2. "SEL,System PLL clock source selection" "0: Main clock (main_clk),1: System PLL output (pll_clk),?,3: FRO 96 or 48 MHz (fro_hf),?,?,?,7: None this may be selected in order to reduce.."
line.long 0x4 "ADCCLKSEL,ADC clock source select"
bitfld.long 0x4 0.--2. "SEL,ADC clock source selection" "0: Main clock (main_clk),1: System PLL output (pll_clk),2: FRO 96 or 48 MHz (fro_hf),?,?,?,?,7: None this may be selected in order to reduce.."
line.long 0x8 "USBCLKSEL,USB clock source select"
bitfld.long 0x8 0.--2. "SEL,USB device clock source selection" "0: FRO 96 or 48 MHz (fro_hf),1: System PLL output (pll_clk),2: Main clock (main_clk),?,?,?,?,7: None this may be selected in order to reduce.."
endif
sif (cpuis("LPC54114*"))
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2B0)++0x3
line.long 0x0 "FXCOMCLKSEL[$1],Flexcomm 0 clock source select"
bitfld.long 0x0 0.--2. "SEL,Flexcomm clock source selection. One per Flexcomm." "0: FRO 12 MHz (fro_12m),1: FRO 96 or 48 MHz (fro_hf),2: System PLL output (pll_clk),3: MCLK pin input when selected in IOCON (mclk_in),4: FRG clock the output of the fractional rate..,?,?,7: None this may be selected in order to reduce.."
repeat.end
group.long 0x2E0++0x3
line.long 0x0 "MCLKCLKSEL,MCLK clock source select"
bitfld.long 0x0 0.--2. "SEL,MCLK source select. This may be used by Flexcomms that support I2S  and/or by the digital microphone subsystem." "0: FRO 96 or 48 MHz (fro_hf),1: System PLL output (pll_clk),2: Main clock (main_clk),?,?,?,?,7: None this may be selected in order to reduce.."
group.long 0x2E8++0x7
line.long 0x0 "FRGCLKSEL,Fractional Rate Generator clock source select"
bitfld.long 0x0 0.--2. "SEL,Fractional Rate Generator clock source select." "0: Main clock (main_clk),1: System PLL output (pll_clk),2: FRO 12 MHz (fro_12m),3: FRO 96 or 48 MHz (fro_hf),?,?,?,7: None this may be selected in order to reduce.."
line.long 0x4 "DMICCLKSEL,Digital microphone (D-Mic) subsystem clock select"
bitfld.long 0x4 0.--2. "SEL,D-Mic subsystem clock source select." "0: FRO 12 MHz (fro_12m),1: FRO 96 or 48 MHz (fro_hf),2: System PLL output (pll_clk),3: MCLK pin input when selected in IOCON (mclk_in),4: Main clock (main_clk),5: Watchdog oscillator (wdt_clk),?,7: None this may be selected in order to reduce.."
group.long 0x300++0x7
line.long 0x0 "SYSTICKCLKDIV,SYSTICK clock divider"
bitfld.long 0x0 30. "HALT,Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output." "0,1"
bitfld.long 0x0 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count." "0,1"
newline
hexmask.long.byte 0x0 0.--7. 1. "DIV,Clock divider value. 0: Divide by 1 up to 255: Divide by 256."
line.long 0x4 "TRACECLKDIV,Trace clock divider"
bitfld.long 0x4 30. "HALT,Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output." "0,1"
bitfld.long 0x4 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count." "0,1"
newline
hexmask.long.byte 0x4 0.--7. 1. "DIV,Clock divider value. 0: Divide by 1 up to 255: Divide by 256."
group.long 0x380++0x7
line.long 0x0 "AHBCLKDIV,AHB clock divider"
bitfld.long 0x0 30. "HALT,Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output." "0,1"
bitfld.long 0x0 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count." "0,1"
newline
hexmask.long.byte 0x0 0.--7. 1. "DIV,Clock divider value. 0: Divide by 1 up to 255: Divide by 256."
line.long 0x4 "CLKOUTDIV,CLKOUT clock divider"
bitfld.long 0x4 30. "HALT,Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output." "0,1"
bitfld.long 0x4 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count." "0,1"
newline
hexmask.long.byte 0x4 0.--7. 1. "DIV,Clock divider value. 0: Divide by 1 up to 255: Divide by 256."
group.long 0x390++0xB
line.long 0x0 "SPIFICLKDIV,SPIFI clock divider"
bitfld.long 0x0 30. "HALT,Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output." "0,1"
bitfld.long 0x0 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count." "0,1"
newline
hexmask.long.byte 0x0 0.--7. 1. "DIV,Clock divider value. 0: Divide by 1 up to 255: Divide by 256."
line.long 0x4 "ADCCLKDIV,ADC clock divider"
bitfld.long 0x4 30. "HALT,Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output." "0,1"
bitfld.long 0x4 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count." "0,1"
newline
hexmask.long.byte 0x4 0.--7. 1. "DIV,Clock divider value. 0: Divide by 1 up to 255: Divide by 256."
line.long 0x8 "USBCLKDIV,USB clock divider"
bitfld.long 0x8 30. "HALT,Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output." "0,1"
bitfld.long 0x8 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count." "0,1"
newline
hexmask.long.byte 0x8 0.--7. 1. "DIV,Clock divider value. 0: Divide by 1 up to 255: Divide by 256."
group.long 0x3A0++0x3
line.long 0x0 "FRGCTRL,Fractional rate divider"
hexmask.long.byte 0x0 8.--15. 1. "MULT,Numerator of the fractional divider. MULT is equal to the programmed value."
hexmask.long.byte 0x0 0.--7. 1. "DIV,Denominator of the fractional divider. DIV is equal to the programmed value +1. Always set to 0xFF to use with the fractional baud rate generator."
group.long 0x3A8++0x7
line.long 0x0 "DMICCLKDIV,DMIC clock divider"
bitfld.long 0x0 30. "HALT,Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output." "0,1"
bitfld.long 0x0 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count." "0,1"
newline
hexmask.long.byte 0x0 0.--7. 1. "DIV,Clock divider value. 0: Divide by 1 up to 255: Divide by 256."
line.long 0x4 "MCLKDIV,I2S MCLK clock divider"
bitfld.long 0x4 30. "HALT,Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output." "0,1"
bitfld.long 0x4 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count." "0,1"
newline
hexmask.long.byte 0x4 0.--7. 1. "DIV,Clock divider value. 0: Divide by 1 up to 255: Divide by 256."
group.long 0x400++0x3
line.long 0x0 "FLASHCFG,Flash wait states configuration"
hexmask.long.byte 0x0 12.--15. 1. "FLASHTIM,Flash memory access time. The number of system clocks used for flash accesses is equal to FLASHTIM +1."
bitfld.long 0x0 6. "PREFOVR,Prefetch override. This bit only applies when PREFEN = 1 and a buffered instruction is completing for which the next flash line is not already buffered or being prefetched." "0: Any previously initiated prefetch will be..,1: Any previously initiated prefetch will be.."
newline
bitfld.long 0x0 5. "PREFEN,Prefetch enable." "0: No instruction prefetch is performed.,1: If the FETCHCFG field is not 0 the next flash.."
bitfld.long 0x0 4. "ACCEL,Acceleration enable." "0: Flash acceleration is disabled. Every flash read..,1: Flash acceleration is enabled. Performance is.."
newline
bitfld.long 0x0 2.--3. "DATACFG,Data read configuration. This field determines how flash accelerator buffers are used for data accesses." "0: Data accesses from flash are not buffered. Every..,1: One buffer is used for all data accesses.,2: All buffers may be used for data accesses.,?"
bitfld.long 0x0 0.--1. "FETCHCFG,Instruction fetch configuration. This field determines how flash accelerator buffers are used for instruction fetches." "0: Instruction fetches from flash are not buffered.,1: One buffer is used for all instruction fetches.,2: All buffers may be used for instruction fetches.,?"
group.long 0x40C++0x7
line.long 0x0 "USBCLKCTRL,USB clock control"
bitfld.long 0x0 1. "POL_CLK,USB_NEED_CLK polarity for triggering the USB wake-up interrupt" "0: Falling edge of the USB_NEED_CLK triggers the..,1: Rising edge of the USB_NEED_CLK triggers the USB.."
line.long 0x4 "USBCLKSTAT,USB clock status"
bitfld.long 0x4 0. "NEED_CLKST,USB_NEED_CLK signal status" "0: Low,1: High"
group.long 0x418++0x3
line.long 0x0 "FREQMECTRL,Frequency measure register"
bitfld.long 0x0 31. "PROG,Set this bit to one to initiate a frequency measurement cycle. Hardware clears this bit when the measurement cycle has completed and there is valid capture data in the CAPVAL field (bits 13:0)." "0,1"
hexmask.long.word 0x0 0.--13. 1. "CAPVAL,Stores the capture result which is used to calculate the frequency of the target clock. This field is read-only."
group.long 0x420++0x3
line.long 0x0 "MCLKIO,MCLK input/output control"
bitfld.long 0x0 0. "DIR,MCLK direction control." "0: The MCLK function is an input.,1: The MCLK function is an output."
group.long 0x500++0x3
line.long 0x0 "FROCTRL,FRO oscillator control"
bitfld.long 0x0 31. "WRTRIM,Write Trim value. Must be written to 1 to modify the SEL or TRIM fields  during the same write. This bit always reads as 0." "0,1"
bitfld.long 0x0 30. "HSPDCLK,High speed clock disable. Allows disabling the highs-speed FRO output if it is not needed." "0: The high-speed FRO output is disabled.,1: The selected high-speed FRO output (48 MHz or 96.."
newline
bitfld.long 0x0 25. "USBMODCHG,USB Mode value Change flag. When 1  indicates that the USB trim is currently being updated (or is still starting up) and software should wait to read FREQTRIM. Update occurs at most once per millisecond." "0,1"
bitfld.long 0x0 24. "USBCLKADJ,USB clock adjust mode." "0: Normal operation.,1: Automatic USB rate adjustment mode. If the USB.."
newline
hexmask.long.byte 0x0 16.--23. 1. "FREQTRIM,Frequency trim. Boot code configures this to a device-specific factory trim value for the 96 MHz FRO. If USBCLKADJ = 1  this field is read-only and provides the value resulting from USB rate adjustment. See the USBMODCFG flag regarding reading.."
bitfld.long 0x0 14. "SEL,Select the fro_hf output frequency. This bit can only be changed by software when the WRTRIM bit = 1. Note that the factory trim values are for the 96 MHz FRO only." "0: 48 MHz,1: 96 MHz"
newline
hexmask.long.word 0x0 0.--13. 1. "TRIM,This value is factory trimmed to account for bias and temperature compensation. The value should not be changed by software. Also see the WRTRIM bit description."
group.long 0x508++0x7
line.long 0x0 "WDTOSCCTRL,Watchdog oscillator control"
hexmask.long.byte 0x0 5.--9. 1. "FREQSEL,Frequency select. Selects the frequency of the oscillator. 0x00 = invalid setting when watchdog oscillator is running 0x01 = 0.4 MHz 0x02 = 0.6 MHz 0x03 = 0.75 MHz 0x04 = 0.9 MHz 0x05 = 1.0 MHz 0x06 = 1.2 MHz 0x07 = 1.3 MHz 0x08 = 1.4 MHz 0x09 =.."
hexmask.long.byte 0x0 0.--4. 1. "DIVSEL,Divider select. Selects the value of the divider that adjusts the output of the oscillator. 0x00 = divide by 2 0x01 = divide by 4 0x02 = divide by 6 up to 0x1E = divide by 62 0x1F = divide by 64"
line.long 0x4 "RTCOSCCTRL,RTC oscillator 32 kHz output control"
bitfld.long 0x4 0. "EN,RTC 32 kHz clock enable." "0: Disabled. RTC clock off.,1: Enabled. RTC clock on."
group.long 0x580++0x3
line.long 0x0 "SYSPLLCTRL,PLL control"
bitfld.long 0x0 20. "DIRECTO,PLL0 direct output enable." "0: Disabled. The PLL output divider (P divider) is..,1: Enabled. The PLL output divider (P divider) is.."
bitfld.long 0x0 19. "DIRECTI,PLL0 direct input enable" "0: Disabled. The PLL input divider (N divider)..,1: Enabled. The PLL input divider (N divider) is.."
newline
bitfld.long 0x0 18. "BANDSEL,PLL filter control. Set this bit to one when the spread spectrum controller is disabled or at low frequencies. For spread spectrum mode: SEL_EXT = 0  BANDSEL = 0  and UPLIMOFF = 1." "0: SSCG control. The PLL filter uses the parameters..,1: MDEC control. The PLL filter uses the.."
bitfld.long 0x0 17. "UPLIMOFF,Disable upper frequency limiter." "0: Normal mode.,1: Upper frequency limiter disabled."
newline
bitfld.long 0x0 16. "BYPASSCCODIV2,Bypass feedback clock divide by 2." "0: Divide by 2. The CCO feedback clock is divided..,1: Bypass. The CCO feedback clock is divided only.."
bitfld.long 0x0 15. "BYPASS,PLL bypass control." "0: Bypass disabled. PLL CCO is sent to the PLL..,1: Bypass enabled. PLL input clock is sent directly.."
newline
hexmask.long.byte 0x0 10.--14. 1. "SELP,Bandwidth select P value"
hexmask.long.byte 0x0 4.--9. 1. "SELI,Bandwidth select I value."
newline
hexmask.long.byte 0x0 0.--3. 1. "SELR,Bandwidth select R value"
rgroup.long 0x584++0x3
line.long 0x0 "SYSPLLSTAT,PLL status"
bitfld.long 0x0 0. "LOCK,PLL0 lock indicator" "0,1"
group.long 0x588++0xF
line.long 0x0 "SYSPLLNDEC,PLL N decoder"
bitfld.long 0x0 10. "NREQ,NDEC reload request. When a 1 is written to this bit  the NDEC value is loaded into the PLL. Must be cleared by software for any subsequent load  or the PLL can be powered down and back up via the PDEN_SYS_PLL bit in the PDRUNCFG register if the.." "0,1"
hexmask.long.word 0x0 0.--9. 1. "NDEC,Decoded N-divider coefficient value."
line.long 0x4 "SYSPLLPDEC,PLL P decoder"
bitfld.long 0x4 7. "PREQ,PDEC reload request. When a 1 is written to this bit  the PDEC value is loaded into the PLL. Must be cleared by software for any subsequent load  or the PLL can be powered down and back up via the PDEN_SYS_PLL bit in the PDRUNCFG register if the.." "0,1"
hexmask.long.byte 0x4 0.--6. 1. "PDEC,Decoded P-divider coefficient value."
line.long 0x8 "SYSPLLSSCTRL0,PLL spread spectrum control 0"
bitfld.long 0x8 18. "SEL_EXT,Select spread spectrum mode. Selects the source of the feedback divider value. For normal mode  this must be the value from the MDEC field in this register. For spread spectrum mode: SEL_EXT = 0  BANDSEL = 0  and UPLIMOFF = 1." "0,1"
bitfld.long 0x8 17. "MREQ,MDEC reload request. When a 1 is written to this bit  the MDEC value is loaded into the PLL. Must be cleared by software for any subsequent load  or the PLL can be powered down and back up via the PDEN_SYS_PLL bit in the PDRUNCFG register if the.." "0,1"
newline
hexmask.long.tbyte 0x8 0.--16. 1. "MDEC,Decoded M-divider coefficient value."
line.long 0xC "SYSPLLSSCTRL1,PLL spread spectrum control 1"
bitfld.long 0xC 29. "DITHER,Select modulation frequency." "0: Fixed. Fixed modulation frequency.,1: Dither. Randomly dither between two modulation.."
bitfld.long 0xC 28. "PD,Spread spectrum power-down." "0: Enabled. Spread spectrum controller is enabled,1: Disabled. Spread spectrum controller is disabled."
newline
bitfld.long 0xC 26.--27. "MC,Modulation waveform control. 0 = no compensation. Compensation for low pass filtering of the PLL to get a triangular modulation at the output of the PLL  giving a flat frequency spectrum. 0b00 => no compensation 0b10 => recommended setting 0b11 =>.." "0: no compensation,?,2: recommended setting,3: max"
bitfld.long 0xC 23.--25. "MR,Programmable frequency modulation depth. 0 = no spread. _fmodpk-pk = Fref x k/Fcco = k/MDdec 0b000 -> k = 0 (no spread spectrum) 0b001 => k _ 1 0b010 => k _ 1.5 0b011 => k _ 2 0b100 => k _ 3 0b101 => k _ 4 0b110 => k _ 6 0b111 => k _ 8" "0: k = 0,1: k _ 1,2: k _ 1,3: k _ 2,4: k _ 3,5: k _ 4,6: k _ 6,7: k _ 8"
newline
bitfld.long 0xC 20.--22. "MF,Programmable modulation frequency fm = Fref/Nss with Fref = Fin/N 0b000 => Nss = 512 (fm _ 3.9 - 7.8 kHz) 0b001 => Nss _ 384 (fm _ 5.2 - 10.4 kHz) 0b010 => Nss = 256 (fm _ 7.8 - 15.6 kHz) 0b011 => Nss = 128 (fm _ 15.6 - 31.3 kHz) 0b100 => Nss = 64 (fm.." "0: Nss = 512,1: Nss _ 384,2: Nss = 256,3: Nss = 128,4: Nss = 64,5: Nss = 32,6: Nss _ 24,7: Nss = 16"
bitfld.long 0xC 19. "MDREQ,MD reload request. When a 1 is written to this bit  the MD value is loaded into the PLL. This bit is cleared when the load is complete" "0,1"
newline
hexmask.long.tbyte 0xC 0.--18. 1. "MD,M- divider value with fraction. MD[18:11]: integer portion of the feedback divider value. MD[10:0]: fractional portion of the feedback divider value. In fractional mode  fcco = (2 - BYPASSCCODIV2) x (MD x 2^-11) x Fref"
group.long 0x600++0x7
line.long 0x0 "PDSLEEPCFG0,Sleep configuration register n"
hexmask.long 0x0 0.--31. 1. "PD_SLEEP,See bit descriptions in the PDRUNCFGn register."
line.long 0x4 "PDSLEEPCFG1,Sleep configuration register n"
hexmask.long 0x4 0.--31. 1. "PD_SLEEP,See bit descriptions in the PDRUNCFGn register."
group.long 0x610++0x7
line.long 0x0 "PDRUNCFG0,Power configuration register n"
bitfld.long 0x0 25. "PD_FLASH_BG,Part of flash power control." "0,1"
bitfld.long 0x0 23. "PDEN_VREFP,Vrefp to the ADC  must be enabled for the ADC to work. Also see bit 19. 0 = Powered; 1 = Powered down." "0: Powered,1: Powered down"
newline
bitfld.long 0x0 22. "PDEN_SYS_PLL,PLL0. 0 = Powered; 1 = Powered down." "0: Powered,1: Powered down"
bitfld.long 0x0 21. "PDEN_USB_PHY,USB pin interface. 0 = Powered; 1 = Powered down." "0: Powered,1: Powered down"
newline
bitfld.long 0x0 20. "PDEN_WDT_OSC,Watchdog oscillator. 0 = Powered; 1 = Powered down." "0: Powered,1: Powered down"
bitfld.long 0x0 19. "PDEN_VDDA,Vdda to the ADC  must be enabled for the ADC to work. Also see bit 23. 0 = Powered; 1 = Powered down." "0: Powered,1: Powered down"
newline
bitfld.long 0x0 18. "PD_VDDHV_ENA,Part of flash power control." "0,1"
bitfld.long 0x0 17. "PDEN_ROM,ROM. 0 = Powered; 1 = Powered down." "0: Powered,1: Powered down"
newline
bitfld.long 0x0 16. "PDEN_SRAMX,SRAMX. 0 = Powered; 1 = Powered down." "0: Powered,1: Powered down"
bitfld.long 0x0 15. "PDEN_SRAM2,SRAM2. 0 = Powered; 1 = Powered down." "0: Powered,1: Powered down"
newline
bitfld.long 0x0 14. "PDEN_SRAM1,SRAM1. 0 = Powered; 1 = Powered down." "0: Powered,1: Powered down"
bitfld.long 0x0 13. "PDEN_SRAM0,SRAM0. 0 = Powered; 1 = Powered down." "0: Powered,1: Powered down"
newline
bitfld.long 0x0 12. "LP_VDDFLASH,Part of flash power control." "0,1"
bitfld.long 0x0 11. "PD_VDDFLASH,Part of flash power control." "0,1"
newline
bitfld.long 0x0 10. "PDEN_ADC0,ADC0. 0 = Powered; 1 = Powered down." "0: Powered,1: Powered down"
bitfld.long 0x0 8. "PDEN_BOD_INTR,Brown-out Detect interrupt. 0 = Powered; 1 = Powered down." "0: Powered,1: Powered down"
newline
bitfld.long 0x0 7. "PDEN_BOD_RST,Brown-out Detect reset. 0 = Powered; 1 = Powered down." "0: Powered,1: Powered down"
bitfld.long 0x0 6. "PDEN_TS,Temp sensor. 0 = Powered; 1 = Powered down." "0: Powered,1: Powered down"
newline
bitfld.long 0x0 5. "PD_FLASH,Part of flash power control." "0,1"
bitfld.long 0x0 4. "PDEN_FRO,FRO oscillator. 0 = Powered; 1 = Powered down." "0: Powered,1: Powered down"
line.long 0x4 "PDRUNCFG1,Power configuration register n"
bitfld.long 0x4 29. "SEL_ALT_FLASH_IBG,Part of flash power control." "0,1"
bitfld.long 0x4 28. "PD_ALT_FLASH_IBG,Part of flash power control." "0,1"
endif
sif (cpuis("LPC54114*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x620)++0x3
line.long 0x0 "PDRUNCFGSET[$1],Set bits in PDRUNCFGn"
hexmask.long 0x0 0.--31. 1. "PD_SET,Writing ones to this register sets the corresponding bit or bits in the PDRUNCFG register  if they are implemented. Bits that do not correspond to defined bits in PDRUNCFG are reserved and only zeroes should be written to them."
repeat.end
endif
sif (cpuis("LPC54114*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x630)++0x3
line.long 0x0 "PDRUNCFGCLR[$1],Clear bits in PDRUNCFGn"
hexmask.long 0x0 0.--31. 1. "PD_CLR,Writing ones to this register clears the corresponding bit or bits in the PDRUNCFG register  if they are implemented. Bits that do not correspond to defined bits in PDRUNCFG are reserved and only zeroes should be written to them."
repeat.end
group.long 0x680++0x7
line.long 0x0 "STARTERP0,Start logic n wake-up enable register"
bitfld.long 0x0 31. "MAILBOX,Mailbox interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.At least one CPU must be running in order for a mailbox interrupt to occur. Present on selected devices." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x0 29. "RTC,RTC interrupt alarm and wake-up timer. 0 = Wake-up disabled. 1 = Wake-up enabled." "0: Wake-up disabled,1: Wake-up enabled"
newline
bitfld.long 0x0 28. "USB0,USB0 function interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x0 27. "USB0_NEEDCLK,USB0 activity interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled." "0: Wake-up disabled,1: Wake-up enabled"
newline
bitfld.long 0x0 25. "DMIC0,Digital microphone interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x0 24. "ADC0_THCMP,ADC0 threshold and error interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only since the peripheral clock must be running for it to function." "0: Wake-up disabled,1: Wake-up enabled"
newline
bitfld.long 0x0 23. "ADC0_SEQB,ADC0 sequence B interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only since the peripheral clock must be running for it to function." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x0 22. "ADC0_SEQA,ADC0 sequence A interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only since the peripheral clock must be running for it to function." "0: Wake-up disabled,1: Wake-up enabled"
newline
bitfld.long 0x0 21. "FLEXCOMM7,Flexcomm7 peripheral interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x0 20. "FLEXCOMM6,Flexcomm6 peripheral interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled." "0: Wake-up disabled,1: Wake-up enabled"
newline
bitfld.long 0x0 19. "FLEXCOMM5,Flexcomm5 peripheral interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x0 18. "FLEXCOMM4,Flexcomm4 peripheral interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled." "0: Wake-up disabled,1: Wake-up enabled"
newline
bitfld.long 0x0 17. "FLEXCOMM3,Flexcomm3 peripheral interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x0 16. "FLEXCOMM2,Flexcomm2 peripheral interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled." "0: Wake-up disabled,1: Wake-up enabled"
newline
bitfld.long 0x0 15. "FLEXCOMM1,Flexcomm1 peripheral interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x0 14. "FLEXCOMM0,Flexcomm0 peripheral interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled." "0: Wake-up disabled,1: Wake-up enabled"
newline
bitfld.long 0x0 13. "CTIMER3,Standard counter/timer CTIMER3 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only since the peripheral clock must be running for it to function." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x0 12. "SCT0,SCT0 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only since the peripheral clock must be running for it to function." "0: Wake-up disabled,1: Wake-up enabled"
newline
bitfld.long 0x0 11. "CTIMER1,Standard counter/timer CTIMER1 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only since the peripheral clock must be running for it to function." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x0 10. "CTIMER0,Standard counter/timer CTIMER0 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only since the peripheral clock must be running for it to function." "0: Wake-up disabled,1: Wake-up enabled"
newline
bitfld.long 0x0 9. "MRT0,Multi-Rate Timer wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Typically used in sleep mode only since the peripheral clock must be running for it to function." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x0 8. "UTICK0,Micro-tick Timer wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled." "0: Wake-up disabled,1: Wake-up enabled"
newline
bitfld.long 0x0 7. "PIN_INT3,GPIO pin interrupt 3 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x0 6. "PIN_INT2,GPIO pin interrupt 2 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match." "0: Wake-up disabled,1: Wake-up enabled"
newline
bitfld.long 0x0 5. "PIN_INT1,GPIO pin interrupt 1 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x0 4. "PIN_INT0,GPIO pin interrupt 0 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match." "0: Wake-up disabled,1: Wake-up enabled"
newline
bitfld.long 0x0 3. "GINT1,Group interrupt 1 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x0 2. "GINT0,Group interrupt 0 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled." "0: Wake-up disabled,1: Wake-up enabled"
newline
bitfld.long 0x0 1. "DMA0,DMA0 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Typically used in sleep mode only since the peripheral clock must be running for it to function." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x0 0. "WDT_BOD,WWDT and BOD interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled." "0: Wake-up disabled,1: Wake-up enabled"
line.long 0x4 "STARTERP1,Start logic n wake-up enable register"
bitfld.long 0x4 5. "CTIMER4,Standard counter/timer CTIMER4 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only since the peripheral clock must be running for it to function." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x4 4. "CTIMER2,Standard counter/timer CTIMER2 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only since the peripheral clock must be running for it to function." "0: Wake-up disabled,1: Wake-up enabled"
newline
bitfld.long 0x4 3. "PINT7,GPIO pin interrupt 7 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x4 2. "PINT6,GPIO pin interrupt 6 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match." "0: Wake-up disabled,1: Wake-up enabled"
newline
bitfld.long 0x4 1. "PINT5,GPIO pin interrupt 5 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match." "0: Wake-up disabled,1: Wake-up enabled"
bitfld.long 0x4 0. "PINT4,GPIO pin interrupt 4 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match." "0: Wake-up disabled,1: Wake-up enabled"
group.long 0x780++0x3
line.long 0x0 "HWWAKE,Configures special cases of hardware wake-up"
bitfld.long 0x0 3. "WAKEDMA,Wake for DMA. When 1  DMA being busy will cause peripheral clocking to remain running until DMA completes. This is generally used in conjunction with bit 1 and/or 2 in order to prevent peripheral clocking from being shut down as soon as the cause.." "0,1"
bitfld.long 0x0 2. "WAKEDMIC,Wake for Digital Microphone. When 1  the digital microphone input FIFO reaching the level specified by TRIGLVL of either channel will cause peripheral clocking to wake up temporarily while the related status is asserted." "0,1"
newline
bitfld.long 0x0 1. "FCWAKE,Wake for Flexcomms. When 1  any Flexcomm FIFO reaching the level specified by its own TXLVL will cause peripheral clocking to wake up temporarily while the related status is asserted." "0,1"
bitfld.long 0x0 0. "FORCEWAKE,Force peripheral clocking to stay on during Deep Sleep and Power-down modes. When 1  clocking to peripherals is prevented from being shut down when the CPU enters Deep Sleep and Power-down modes. This is intended to allow a coprocessor to.." "0,1"
group.long 0x800++0xB
line.long 0x0 "CPUCTRL,CPU Control for multiple processors"
bitfld.long 0x0 6. "POWERCPU,Identifies the owner of reduced power mode control: which CPU can cause the device to enter Deep Sleep  Power-down  and Deep Power-down modes." "0: M0+. Cortex-M0+ is the owner of reduced power..,1: M4. Cortex-M4 is the owner of reduced power mode.."
bitfld.long 0x0 5. "CM0RSTEN,Cortex-M0+ reset." "0: Disabled. The Cortex-M0+ is not being reset.,1: Enabled. The Cortex-M0+ is being reset."
newline
bitfld.long 0x0 4. "CM4RSTEN,Cortex-M4 reset." "0: Disabled. The Cortex-M4 is not being reset.,1: Enabled. The Cortex-M4 is being reset."
bitfld.long 0x0 3. "CM0CLKEN,Cortex-M0+ clock enable" "0: Disabled. The Cortex-M0+ clock is not enabled.,1: Enabled. The Cortex-M0+ clock is enabled."
newline
bitfld.long 0x0 2. "CM4CLKEN,Cortex-M4 clock enable" "0: Disabled. The Cortex-M4 clock is not enabled,1: Enabled. The Cortex-M4 clock is enabled."
bitfld.long 0x0 0. "MASTERCPU,Indicates which CPU is considered the master. This is factory set assign the Cortex-M4 as the master. The master CPU cannot have its clock turned off via the related CMnCLKEN bit or be reset via the related CMxRSTEN in this register. The slave.." "0: M0+. Cortex-M0+ is the master CPU.,1: M4. Cortex-M4 is the master CPU."
line.long 0x4 "CPBOOT,Coprocessor Boot Address"
hexmask.long 0x4 0.--31. 1. "BOOTADDR,Slave processor boot address"
line.long 0x8 "CPSTACK,Coprocessor Stack Address"
hexmask.long 0x8 0.--31. 1. "STACKADDR,Slave processor stack address"
rgroup.long 0x80C++0x3
line.long 0x0 "CPSTAT,Coprocessor Status"
bitfld.long 0x0 3. "CM0LOCKUP,When 1  the Cortex-M0+ CPU is in lockup." "0,1"
bitfld.long 0x0 2. "CM4LOCKUP,When 1  the Cortex-M4 CPU is in lockup" "0,1"
newline
bitfld.long 0x0 1. "CM0SLEEPING,When 1  the Cortex-M0+ CPU is sleeping" "0,1"
bitfld.long 0x0 0. "CM4SLEEPING,When 1  the Cortex-M4 CPU is sleeping" "0,1"
group.long 0xE04++0x3
line.long 0x0 "AUTOCGOR,Auto Clock-Gate Override Register"
bitfld.long 0x0 3. "RAM2,When 1  automatic clock gating for RAM2 is turned off." "0,1"
bitfld.long 0x0 2. "RAM1,When 1  automatic clock gating for RAM1 is turned off." "0,1"
newline
bitfld.long 0x0 1. "RAM0X,When 1  automatic clock gating for RAMX and RAM0 are turned off." "0,1"
rgroup.long 0xFF4++0xB
line.long 0x0 "JTAGIDCODE,JTAG ID code register"
hexmask.long 0x0 0.--31. 1. "JTAGID,JTAG ID code."
line.long 0x4 "DEVICE_ID0,Part ID register"
hexmask.long 0x4 0.--31. 1. "PARTID,Part ID"
line.long 0x8 "DEVICE_ID1,Boot ROM and die revision register"
hexmask.long 0x8 0.--31. 1. "REVID,Revision."
group.long 0x20044++0x3
line.long 0x0 "BODCTRL,Brown-Out Detect control"
bitfld.long 0x0 7. "BODINTSTAT,BOD interrupt status. When 1  a BOD interrupt has occurred. Cleared by writing 1 to this bit." "0,1"
bitfld.long 0x0 6. "BODRSTSTAT,BOD reset status. When 1  a BOD reset has occurred. Cleared by writing 1 to this bit." "0,1"
newline
bitfld.long 0x0 5. "BODINTENA,BOD interrupt enable" "0: Disable interrupt function.,1: Enable interrupt function."
bitfld.long 0x0 3.--4. "BODINTLEV,BOD interrupt level" "0: Level 0: 2.05 V,1: Level 1: 2.45 V,2: Level 2: 2.75 V,3: Level 3: 3.05 V"
newline
bitfld.long 0x0 2. "BODRSTENA,BOD reset enable" "0: Disable reset function.,1: Enable reset function."
bitfld.long 0x0 0.--1. "BODRSTLEV,BOD reset level" "0: Level 0: 1.5 V,1: Level 1: 1.85 V,2: Level 2: 2.0 V,3: Level 3: 2.3 V"
endif
sif (cpuis("LPC54605*"))
group.long 0x10++0x3
line.long 0x0 "AHBMATPRIO,AHB multilayer matrix priority control"
bitfld.long 0x0 24.--25. "PRI_SHA,SHA priority." "0,1,2,3"
bitfld.long 0x0 22.--23. "PRI_MCAN2,MCAN2 priority." "0,1,2,3"
newline
bitfld.long 0x0 20.--21. "PRI_MCAN1,MCAN1 priority." "0,1,2,3"
bitfld.long 0x0 18.--19. "PRI_SDIO,SDIO priority." "0,1,2,3"
newline
bitfld.long 0x0 16.--17. "PRI_USB1,USB1 DMA priority." "0,1,2,3"
bitfld.long 0x0 14.--15. "PRI_USB0,USB0 DMA priority." "0,1,2,3"
newline
bitfld.long 0x0 12.--13. "PRI_LCD,LCD DMA priority." "0,1,2,3"
bitfld.long 0x0 10.--11. "PRI_ETH,Ethernet DMA priority." "0,1,2,3"
newline
hexmask.long.byte 0x0 6.--9. 1. "PRI_DMA,DMA controller priority."
bitfld.long 0x0 4.--5. "PRI_SYS,System bus priority." "0,1,2,3"
newline
bitfld.long 0x0 2.--3. "PRI_DCODE,D-Code bus priority." "0,1,2,3"
bitfld.long 0x0 0.--1. "PRI_ICODE,I-Code bus priority." "0,1,2,3"
group.long 0x40++0x3
line.long 0x0 "SYSTCKCAL,System tick counter calibration"
bitfld.long 0x0 25. "NOREF,Initial value for the Systick timer." "0,1"
bitfld.long 0x0 24. "SKEW,Initial value for the Systick timer." "0,1"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "CAL,System tick timer calibration value."
group.long 0x48++0x7
line.long 0x0 "NMISRC,NMI Source Select"
bitfld.long 0x0 31. "NMIENM4,Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQM4." "0,1"
hexmask.long.byte 0x0 0.--5. 1. "IRQM4,The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the Cortex-M4  if enabled by NMIENM4."
line.long 0x4 "ASYNCAPBCTRL,Asynchronous APB Control"
bitfld.long 0x4 0. "ENABLE,Enables the asynchronous APB bridge and subsystem." "0: Disabled. Asynchronous APB bridge is disabled.,1: Enabled. Asynchronous APB bridge is enabled."
endif
sif (cpuis("LPC54605*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0xC0)++0x3
line.long 0x0 "PIOPORCAP[$1],POR captured value of port n"
hexmask.long 0x0 0.--31. 1. "PIOPORCAP,State of PIOn_31 through PIOn_0 at power-on reset"
repeat.end
endif
sif (cpuis("LPC54605*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0xD0)++0x3
line.long 0x0 "PIORESCAP[$1],Reset captured value of port n"
hexmask.long 0x0 0.--31. 1. "PIORESCAP,State of PIOn_31 through PIOn_0 for resets other than POR."
repeat.end
group.long 0x100++0xB
line.long 0x0 "PRESETCTRL0,Peripheral reset control n"
bitfld.long 0x0 27. "ADC0_RST,ADC0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 22. "WWDT_RST,Watchdog timer reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x0 21. "CRC_RST,CRC generator reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 20. "DMA0_RST,DMA0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x0 19. "GINT_RST,Grouped interrupt (GINT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 18. "PINT_RST,Pin interrupt (PINT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x0 17. "GPIO3_RST,GPIO3 reset control." "0,1"
bitfld.long 0x0 16. "GPIO2_RST,GPIO2 reset control." "0,1"
newline
bitfld.long 0x0 15. "GPIO1_RST,GPIO1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 14. "GPIO0_RST,GPIO0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x0 13. "IOCON_RST,IOCON reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 11. "MUX_RST,Input mux reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x0 10. "SPIFI_RST,SPIFI reset control." "0,1"
bitfld.long 0x0 9. "EEPROM_RST,EEPROM reset control." "0,1"
newline
bitfld.long 0x0 8. "FMC_RST,Flash accelerator reset control. Note that the FMC must not be reset while executing from flash  and must be reconfigured after reset. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 7. "FLASH_RST,Flash controller reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
line.long 0x4 "PRESETCTRL1,Peripheral reset control n"
bitfld.long 0x4 27. "CTIMER1_RST,CTIMER1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 26. "CTIMER0_RST,CTIMER0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 25. "USB0D_RST,USB0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 22. "CTIMER2_RST,CTIMER2 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function" "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 19. "DMIC_RST,Digital microphone interface reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 18. "FC7_RST,Flexcomm 7 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 17. "FC6_RST,Flexcomm 6 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 16. "FC5_RST,Flexcomm 5 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 15. "FC4_RST,Flexcomm 4 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 14. "FC3_RST,Flexcomm 3 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 13. "FC2_RST,Flexcomm 2 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 12. "FC1_RST,Flexcomm 1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 11. "FC0_RST,Flexcomm 0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 10. "UTICK_RST,Micro-tick Timer reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 8. "MCAN1_RST,0 = Clear reset to this function." "0: Clear reset to this function,?"
bitfld.long 0x4 7. "MCAN0_RST,0 = Clear reset to this function." "0: Clear reset to this function,?"
newline
bitfld.long 0x4 2. "SCT0_RST,State configurable timer 0 (SCT0) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 0. "MRT_RST,Multi-rate timer (MRT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
line.long 0x8 "PRESETCTRL2,Peripheral reset control n"
bitfld.long 0x8 20. "SC1_RST,Smart card 1 reset control." "0,1"
bitfld.long 0x8 19. "SC0_RST,Smart card 0 reset control." "0,1"
newline
bitfld.long 0x8 18. "SHA_RST,SHA reset control." "0,1"
bitfld.long 0x8 17. "USB0HSL_RST,USB0 HOST slave reset control." "0,1"
newline
bitfld.long 0x8 16. "USB0HMR_RST,USB0 HOST master reset control." "0,1"
bitfld.long 0x8 15. "FC9_RST,Flexcomm 9 reset control." "0,1"
newline
bitfld.long 0x8 14. "FC8_RST,Flexcomm 8 reset control." "0,1"
bitfld.long 0x8 13. "RNG_RST,RNG reset control." "0,1"
newline
bitfld.long 0x8 12. "OTP_RST,OTP reset control." "0,1"
bitfld.long 0x8 11. "AES_RST,AES reset control." "0,1"
newline
bitfld.long 0x8 10. "GPIO5_RST,GPIO5 reset control." "0,1"
bitfld.long 0x8 9. "GPIO4_RST,GPIO4 reset control." "0,1"
newline
bitfld.long 0x8 8. "ETH_RST,Ethernet reset control." "0,1"
bitfld.long 0x8 7. "EMC_RESET,EMC reset control." "0,1"
newline
bitfld.long 0x8 6. "USB1RAM_RST,USB1 RAM reset control." "0,1"
bitfld.long 0x8 5. "USB1D_RST,USB1 Device reset control." "0,1"
newline
bitfld.long 0x8 4. "USB1H_RST,USB1 Host reset control." "0,1"
bitfld.long 0x8 3. "SDIO_RST,SDIO reset control." "0,1"
newline
bitfld.long 0x8 2. "LCD_RST,LCD reset control." "0,1"
endif
sif (cpuis("LPC54605*"))
repeat 3. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x120)++0x3
line.long 0x0 "PRESETCTRLSET[$1],Set bits in PRESETCTRLn"
hexmask.long 0x0 0.--31. 1. "RST_SET,Writing ones to this register sets the corresponding bit or bits in the PRESETCTRLn register  if they are implemented. Bits that do not correspond to defined bits in PRESETCTRLn are reserved and only zeroes should be written to them."
repeat.end
endif
sif (cpuis("LPC54605*"))
repeat 3. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x140)++0x3
line.long 0x0 "PRESETCTRLCLR[$1],Clear bits in PRESETCTRLn"
hexmask.long 0x0 0.--31. 1. "RST_CLR,Writing ones to this register clears the corresponding bit or bits in the PRESETCTRLn register  if they are implemented. Bits that do not correspond to defined bits in PRESETCTRLn are reserved and only zeroes should be written to them."
repeat.end
group.long 0x1F0++0x3
line.long 0x0 "SYSRSTSTAT,System reset status register"
bitfld.long 0x0 4. "SYSRST,Status of the software system reset" "0: No System reset detected,1: System reset detected. Writing a one clears this.."
bitfld.long 0x0 3. "BOD,Status of the Brown-out detect reset" "0: No BOD reset detected,1: BOD reset detected. Writing a one clears this.."
newline
bitfld.long 0x0 2. "WDT,Status of the Watchdog reset" "0: No WDT reset detected,1: WDT reset detected. Writing a one clears this.."
bitfld.long 0x0 1. "EXTRST,Status of the external RESET pin. External reset status" "0: No reset event detected.,1: Reset detected. Writing a one clears this reset."
newline
bitfld.long 0x0 0. "POR,POR reset status" "0: No POR detected,1: POR detected. Writing a one clears this reset."
group.long 0x200++0xB
line.long 0x0 "AHBCLKCTRL0,AHB Clock control n"
bitfld.long 0x0 27. "ADC0,Enables the clock for the ADC0 register interface." "0,1"
bitfld.long 0x0 23. "RTC,Enables the bus clock for the RTC. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 22. "WWDT,Enables the clock for the Watchdog Timer. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 21. "CRC,Enables the clock for the CRC engine. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 20. "DMA,Enables the clock for the DMA controller. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 19. "GINT,Enables the clock for the grouped pin interrupt block. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 18. "PINT,Enables the clock for the pin interrupt block.0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 17. "GPIO3,Enables the clock for the GPIO3 port registers." "0,1"
newline
bitfld.long 0x0 16. "GPIO2,Enables the clock for the GPIO2 port registers." "0,1"
bitfld.long 0x0 15. "GPIO1,Enables the clock for the GPIO1 port registers. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 14. "GPIO0,Enables the clock for the GPIO0 port registers. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 13. "IOCON,Enables the clock for the IOCON block. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 11. "INPUTMUX,Enables the clock for the input muxes. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 10. "SPIFI,Enables the clock for the SPIFI. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 9. "EEPROM,Enables the clock for EEPROM." "0,1"
bitfld.long 0x0 8. "FMC,Enables the clock for the Flash accelerator. 0 = Disable; 1 = Enable. This clock is needed if the flash is being read." "0: Disable,1: Enable"
newline
bitfld.long 0x0 7. "FLASH,Enables the clock for the flash controller. 0 = Disable; 1 = Enable. This clock is needed for flash programming  not for flash read." "0: Disable,1: Enable"
bitfld.long 0x0 5. "SRAM3,Enables the clock for SRAM3." "0,1"
newline
bitfld.long 0x0 4. "SRAM2,Enables the clock for SRAM2. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 3. "SRAM1,Enables the clock for SRAM1. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 1. "ROM,Enables the clock for the Boot ROM. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
line.long 0x4 "AHBCLKCTRL1,AHB Clock control n"
bitfld.long 0x4 27. "CTIMER1,Enables the clock for timer CTIMER1. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 26. "CTIMER0,Enables the clock for timer CTIMER0. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 25. "USB0D,Enables the clock for the USB0 device interface. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 22. "CTIMER2,Enables the clock for CTIMER 2. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 19. "DMIC,Enables the clock for the digital microphone interface. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 18. "FLEXCOMM7,Enables the clock for Flexcomm 7. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 17. "FLEXCOMM6,Enables the clock for Flexcomm 6. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 16. "FLEXCOMM5,Enables the clock for Flexcomm 5. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 15. "FLEXCOMM4,Enables the clock for Flexcomm 4. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 14. "FLEXCOMM3,Enables the clock for Flexcomm 3. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 13. "FLEXCOMM2,Enables the clock for Flexcomm 2. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 12. "FLEXCOMM1,Enables the clock for Flexcomm 1. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 11. "FLEXCOMM0,Enables the clock for Flexcomm 0. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 10. "UTICK,Enables the clock for the Micro-tick Timer. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 8. "MCAN1,Enables the clock for MCAN1." "0,1"
bitfld.long 0x4 7. "MCAN0,Enables the clock for MCAN0." "0,1"
newline
bitfld.long 0x4 2. "SCT0,Enables the clock for SCT0." "0,1"
bitfld.long 0x4 1. "RIT,Enables the clock for the Repetitive Interrupt Timer." "0,1"
newline
bitfld.long 0x4 0. "MRT,Enables the clock for the Multi-Rate Timer." "0,1"
line.long 0x8 "AHBCLKCTRL2,AHB Clock control n"
bitfld.long 0x8 20. "SC1,Enables the clock for the Smart card1 interface." "0,1"
bitfld.long 0x8 19. "SC0,Enables the clock for the Smart card0 interface." "0,1"
newline
bitfld.long 0x8 18. "SHA0,Enables the clock for the SHA interface." "0,1"
bitfld.long 0x8 17. "USB0HSL,Enables the clock for the USB host slave interface." "0,1"
newline
bitfld.long 0x8 16. "USB0HMR,Enables the clock for the USB host master interface." "0,1"
bitfld.long 0x8 15. "FLEXCOMM9,Enables the clock for the Flexcomm9 interface." "0,1"
newline
bitfld.long 0x8 14. "FLEXCOMM8,Enables the clock for the Flexcomm8 interface." "0,1"
bitfld.long 0x8 13. "RNG,Enables the clock for the RNG interface." "0,1"
newline
bitfld.long 0x8 12. "OTP,Enables the clock for the OTP interface." "0,1"
bitfld.long 0x8 11. "AES,Enables the clock for the AES interface." "0,1"
newline
bitfld.long 0x8 10. "GPIO5,Enables the clock for the GPIO5 interface." "0,1"
bitfld.long 0x8 9. "GPIO4,Enables the clock for the GPIO4 interface." "0,1"
newline
bitfld.long 0x8 8. "ETH,Enables the clock for the ethernet interface." "0,1"
bitfld.long 0x8 7. "EMC,Enables the clock for the EMC interface." "0,1"
newline
bitfld.long 0x8 6. "USB1RAM,Enables the clock for the USB1 RAM interface." "0,1"
bitfld.long 0x8 5. "USB1D,Enables the clock for the USB1 device interface." "0,1"
newline
bitfld.long 0x8 4. "USB1H,Enables the clock for the USB1 host interface." "0,1"
bitfld.long 0x8 3. "SDIO,Enables the clock for the SDIO interface." "0,1"
newline
bitfld.long 0x8 2. "LCD,Enables the clock for the LCD interface." "0,1"
endif
sif (cpuis("LPC54605*"))
repeat 3. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x220)++0x3
line.long 0x0 "AHBCLKCTRLSET[$1],Set bits in AHBCLKCTRLn"
hexmask.long 0x0 0.--31. 1. "CLK_SET,Writing ones to this register sets the corresponding bit or bits in the AHBCLKCTRLn register  if they are implemented. Bits that do not correspond to defined bits in AHBCLKCTRLn are reserved and only zeroes should be written to them."
repeat.end
endif
sif (cpuis("LPC54605*"))
repeat 3. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x240)++0x3
line.long 0x0 "AHBCLKCTRLCLR[$1],Clear bits in AHBCLKCTRLn"
hexmask.long 0x0 0.--31. 1. "CLK_CLR,Writing ones to this register clears the corresponding bit or bits in the AHBCLKCTRLn register  if they are implemented. Bits that do not correspond to defined bits in AHBCLKCTRLn are reserved and only zeroes should be written to them."
repeat.end
group.long 0x280++0xB
line.long 0x0 "MAINCLKSELA,Main clock source select A"
bitfld.long 0x0 0.--1. "SEL,Clock source for main clock source selector A" "0: FRO 12 MHz (fro_12m),1: CLKIN (clk_in),2: Watchdog oscillator (wdt_clk),3: FRO 96 or 48 MHz (fro_hf)"
line.long 0x4 "MAINCLKSELB,Main clock source select B"
bitfld.long 0x4 0.--1. "SEL,Clock source for main clock source selector B. Selects the clock source for the main clock." "0: MAINCLKSELA. Use the clock source selected in..,?,2: System PLL output (pll_clk),3: RTC oscillator 32 kHz output (32k_clk)"
line.long 0x8 "CLKOUTSELA,CLKOUT clock source select A"
bitfld.long 0x8 0.--2. "SEL,CLKOUT clock source selection" "0: Main clock (main_clk),1: CLKIN (clk_in),2: Watchdog oscillator (wdt_clk),3: FRO 96 or 48 MHz (fro_hf),4: PLL output (pll_clk),5: USB PLL clock (usb_pll_clk),6: Audio PLL clock (audio_pll_clk),7: RTC oscillator 32 kHz output (32k_clk)"
group.long 0x290++0x3
line.long 0x0 "SYSPLLCLKSEL,PLL clock source select"
bitfld.long 0x0 0.--2. "SEL,System PLL clock source selection." "0: FRO 12 MHz (fro_12m),1: CLKIN (clk_in),2: Watchdog oscillator (wdt_clk),3: RTC oscillator 32 kHz output (32k_clk),?,?,?,7: None this may be selected in order to reduce.."
group.long 0x298++0x3
line.long 0x0 "AUDPLLCLKSEL,Audio PLL clock source select"
bitfld.long 0x0 0.--2. "SEL,Audio PLL clock source selection." "0: FRO 12 MHz (fro_12m),1: CLKIN (clk_in),?,?,?,?,?,7: None this may be selected in order to reduce.."
group.long 0x2A0++0xF
line.long 0x0 "SPIFICLKSEL,SPIFI clock source select"
bitfld.long 0x0 0.--2. "SEL,System PLL clock source selection" "0: Main clock (main_clk),1: System PLL output (pll_clk),2: USB PLL clock (usb_pll_clk),3: FRO 96 or 48 MHz (fro_hf),4: Audio PLL clock (audio_pll_clk),?,?,7: None this may be selected in order to reduce.."
line.long 0x4 "ADCCLKSEL,ADC clock source select"
bitfld.long 0x4 0.--2. "SEL,ADC clock source selection" "0: FRO 96 or 48 MHz (fro_hf),1: System PLL output (pll_clk),2: USB PLL clock (usb_pll_clk),3: Audio PLL clock (audio_pll_clk),?,?,?,7: None this may be selected in order to reduce.."
line.long 0x8 "USB0CLKSEL,USB0 clock source select"
bitfld.long 0x8 0.--2. "SEL,USB0 device clock source selection." "0: FRO 96 or 48 MHz (fro_hf),1: System PLL output (pll_clk),2: USB PLL clock (usb_pll_clk),?,?,?,?,7: None this may be selected in order to reduce.."
line.long 0xC "USB1CLKSEL,USB1 clock source select"
bitfld.long 0xC 0.--2. "SEL,USB1 PHY clock source selection." "0: Main clock (main_clk),1: System PLL output (pll_clk),2: USB PLL clock (usb_pll_clk),?,?,?,?,7: None this may be selected in order to reduce.."
endif
sif (cpuis("LPC54605*"))
repeat 10. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2B0)++0x3
line.long 0x0 "FCLKSEL[$1],Flexcomm 0 clock source select"
bitfld.long 0x0 0.--2. "SEL,Flexcomm clock source selection. One per Flexcomm." "0: FRO 12 MHz (fro_12m),1: FRO HF DIV (fro_hf_div),2: Audio PLL clock (audio_pll_clk),3: MCLK pin input when selected in IOCON (mclk_in),4: FRG clock the output of the fractional rate..,?,?,7: None this may be selected in order to reduce.."
repeat.end
group.long 0x2E0++0x3
line.long 0x0 "MCLKCLKSEL,MCLK clock source select"
bitfld.long 0x0 0.--2. "SEL,MCLK source select. This may be used by Flexcomms that support I2S  and/or by the digital microphone subsystem." "0: FRO HF DIV (fro_hf_div),1: Audio PLL clock (audio_pll_clk),?,?,?,?,?,7: None this may be selected in order to reduce.."
group.long 0x2E8++0x13
line.long 0x0 "FRGCLKSEL,Fractional Rate Generator clock source select"
bitfld.long 0x0 0.--2. "SEL,Fractional Rate Generator clock source select." "0: Main clock (main_clk),1: System PLL output (pll_clk),2: FRO 12 MHz (fro_12m),3: FRO 96 or 48 MHz (fro_hf),?,?,?,7: None this may be selected in order to reduce.."
line.long 0x4 "DMICCLKSEL,Digital microphone (DMIC) subsystem clock select"
bitfld.long 0x4 0.--2. "SEL,DMIC (audio subsystem) clock source select." "0: FRO 12 MHz (fro_12m),1: FRO HF DIV (fro_hf_div),2: Audio PLL clock (audio_pll_clk),3: MCLK pin input when selected in IOCON (mclk_in),?,?,?,7: None this may be selected in order to reduce.."
line.long 0x8 "SCTCLKSEL,SCTimer/PWM clock source select"
bitfld.long 0x8 0.--2. "SEL,SCT clock source select." "0: Main clock (main_clk),1: System PLL output (pll_clk),2: FRO 96 or 48 MHz (fro_hf),3: Audio PLL clock (audio_pll_clk),?,?,?,7: None this may be selected in order to reduce.."
line.long 0xC "LCDCLKSEL,LCD clock source select"
bitfld.long 0xC 0.--1. "SEL,LCD clock source select." "0: Main clock (main_clk),1: LCDCLKIN (LCDCLK_EXT),2: FRO 96 or 48 MHz (fro_hf),3: None this may be selected in order to reduce.."
line.long 0x10 "SDIOCLKSEL,SDIO clock source select"
bitfld.long 0x10 0.--2. "SEL,SDIO clock source select." "0: Main clock (main_clk),1: System PLL output (pll_clk),2: USB PLL clock (usb_pll_clk),3: FRO 96 or 48 MHz (fro_hf),4: Audio PLL clock (audio_pll_clk),?,?,7: None this may be selected in order to reduce.."
group.long 0x300++0x17
line.long 0x0 "SYSTICKCLKDIV,SYSTICK clock divider"
bitfld.long 0x0 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x0 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x0 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count." "0,1"
hexmask.long.byte 0x0 0.--7. 1. "DIV,Clock divider value. 0: Divide by 1 up to 255: Divide by 256."
line.long 0x4 "ARMTRACECLKDIV,ARM Trace clock divider"
bitfld.long 0x4 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x4 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x4 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x4 0.--7. 1. "DIV,Clock divider value."
line.long 0x8 "CAN0CLKDIV,MCAN0 clock divider"
bitfld.long 0x8 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x8 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x8 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x8 0.--7. 1. "DIV,Clock divider value."
line.long 0xC "CAN1CLKDIV,MCAN1 clock divider"
bitfld.long 0xC 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0xC 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0xC 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count." "0,1"
hexmask.long.byte 0xC 0.--7. 1. "DIV,Clock divider value. 0: Divide by 1 up to 255: Divide by 256."
line.long 0x10 "SC0CLKDIV,Smartcard0 clock divider"
bitfld.long 0x10 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x10 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x10 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x10 0.--7. 1. "DIV,Clock divider value."
line.long 0x14 "SC1CLKDIV,Smartcard1 clock divider"
bitfld.long 0x14 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x14 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x14 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x14 0.--7. 1. "DIV,Clock divider value."
group.long 0x380++0xB
line.long 0x0 "AHBCLKDIV,AHB clock divider"
bitfld.long 0x0 31. "REQFLAG,Divider status flag." "0,1"
hexmask.long.byte 0x0 0.--7. 1. "DIV,Clock divider value. 0: Divide by 1 up to 255: Divide by 256."
line.long 0x4 "CLKOUTDIV,CLKOUT clock divider"
bitfld.long 0x4 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x4 30. "HALT,Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output." "0,1"
newline
bitfld.long 0x4 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count." "0,1"
hexmask.long.byte 0x4 0.--7. 1. "DIV,Clock divider value. 0: Divide by 1 up to 255: Divide by 256."
line.long 0x8 "FROHFCLKDIV,FROHF clock divider"
bitfld.long 0x8 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x8 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x8 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x8 0.--7. 1. "DIV,Clock divider value."
group.long 0x390++0x13
line.long 0x0 "SPIFICLKDIV,SPIFI clock divider"
bitfld.long 0x0 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x0 30. "HALT,Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output." "0,1"
newline
bitfld.long 0x0 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count." "0,1"
hexmask.long.byte 0x0 0.--7. 1. "DIV,Clock divider value."
line.long 0x4 "ADCCLKDIV,ADC clock divider"
bitfld.long 0x4 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x4 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x4 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x4 0.--7. 1. "DIV,Clock divider value."
line.long 0x8 "USB0CLKDIV,USB0 clock divider"
bitfld.long 0x8 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x8 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x8 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x8 0.--7. 1. "DIV,Clock divider value."
line.long 0xC "USB1CLKDIV,USB1 clock divider"
bitfld.long 0xC 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0xC 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0xC 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0xC 0.--7. 1. "DIV,Clock divider value."
line.long 0x10 "FRGCTRL,Fractional rate divider"
hexmask.long.byte 0x10 8.--15. 1. "MULT,Numerator of the fractional divider. MULT is equal to the programmed value."
hexmask.long.byte 0x10 0.--7. 1. "DIV,Denominator of the fractional divider. DIV is equal to the programmed value +1. Always set to 0xFF to use with the fractional baud rate generator."
group.long 0x3A8++0x17
line.long 0x0 "DMICCLKDIV,DMIC clock divider"
bitfld.long 0x0 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x0 30. "HALT,Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output." "0,1"
newline
bitfld.long 0x0 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count." "0,1"
hexmask.long.byte 0x0 0.--7. 1. "DIV,Clock divider value. 0: Divide by 1 up to 255: Divide by 256."
line.long 0x4 "MCLKDIV,I2S MCLK clock divider"
bitfld.long 0x4 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x4 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x4 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x4 0.--7. 1. "DIV,Clock divider value. 0: Divide by 1 up to 255: Divide by 256."
line.long 0x8 "LCDCLKDIV,LCD clock divider"
bitfld.long 0x8 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x8 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x8 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x8 0.--7. 1. "DIV,Clock divider value."
line.long 0xC "SCTCLKDIV,SCT/PWM clock divider"
bitfld.long 0xC 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0xC 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0xC 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0xC 0.--7. 1. "DIV,Clock divider value."
line.long 0x10 "EMCCLKDIV,EMC clock divider"
bitfld.long 0x10 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x10 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x10 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x10 0.--7. 1. "DIV,Clock divider value."
line.long 0x14 "SDIOCLKDIV,SDIO clock divider"
bitfld.long 0x14 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x14 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x14 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x14 0.--7. 1. "DIV,Clock divider value."
group.long 0x400++0x3
line.long 0x0 "FLASHCFG,Flash wait states configuration"
hexmask.long.byte 0x0 12.--15. 1. "FLASHTIM,Flash memory access time. The number of system clocks used for flash accesses is equal to FLASHTIM +1."
bitfld.long 0x0 6. "PREFOVR,Prefetch override. This bit only applies when PREFEN = 1 and a buffered instruction is completing for which the next flash line is not already buffered or being prefetched." "0: Any previously initiated prefetch will be..,1: Any previously initiated prefetch will be.."
newline
bitfld.long 0x0 5. "PREFEN,Prefetch enable." "0: No instruction prefetch is performed.,1: If the FETCHCFG field is not 0 the next flash.."
bitfld.long 0x0 4. "ACCEL,Acceleration enable." "0: Flash acceleration is disabled. Every flash read..,1: Flash acceleration is enabled. Performance is.."
newline
bitfld.long 0x0 2.--3. "DATACFG,Data read configuration. This field determines how flash accelerator buffers are used for data accesses." "0: Data accesses from flash are not buffered. Every..,1: One buffer is used for all data accesses.,2: All buffers may be used for data accesses.,?"
bitfld.long 0x0 0.--1. "FETCHCFG,Instruction fetch configuration. This field determines how flash accelerator buffers are used for instruction fetches." "0: Instruction fetches from flash are not buffered.,1: One buffer is used for all instruction fetches.,2: All buffers may be used for instruction fetches.,?"
group.long 0x40C++0x7
line.long 0x0 "USB0CLKCTRL,USB0 clock control"
bitfld.long 0x0 4. "PU_DISABLE,Internal pull-up disable control." "0,1"
bitfld.long 0x0 3. "POL_FS_HOST_CLK,USB0 Host USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt." "0,1"
newline
bitfld.long 0x0 2. "AP_FS_HOST_CLK,USB0 Host USB0_NEEDCLK signal control." "0,1"
bitfld.long 0x0 1. "POL_FS_DEV_CLK,USB0 Device USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt." "0,1"
newline
bitfld.long 0x0 0. "AP_FS_DEV_CLK,USB0 Device USB0_NEEDCLK signal control." "0,1"
line.long 0x4 "USB0CLKSTAT,USB0 clock status"
bitfld.long 0x4 1. "HOST_NEED_CLKST,USB0 Host USB0_NEEDCLK signal status." "0,1"
bitfld.long 0x4 0. "DEV_NEED_CLKST,USB0 Device USB0_NEEDCLK signal status." "0,1"
group.long 0x418++0x3
line.long 0x0 "FREQMECTRL,Frequency measure register"
bitfld.long 0x0 31. "PROG,Set this bit to one to initiate a frequency measurement cycle. Hardware clears this bit when the measurement cycle has completed and there is valid capture data in the CAPVAL field (bits 13:0)." "0,1"
hexmask.long.word 0x0 0.--13. 1. "CAPVAL,Stores the capture result which is used to calculate the frequency of the target clock. This field is read-only."
group.long 0x420++0xB
line.long 0x0 "MCLKIO,MCLK input/output control"
bitfld.long 0x0 0. "DIR,MCLK direction control." "0,1"
line.long 0x4 "USB1CLKCTRL,USB1 clock control"
bitfld.long 0x4 4. "HS_DEV_WAKEUP_N,External user wake-up signal for device mode; asserting this signal (active low) will result in exiting the low power mode; input to asynchronous control logic." "0,1"
bitfld.long 0x4 3. "POL_FS_HOST_CLK,USB1 Host need_clock polarity for triggering the USB1 wake-up interrupt." "0,1"
newline
bitfld.long 0x4 2. "AP_FS_HOST_CLK,USB1 Host need_clock signal control." "0,1"
bitfld.long 0x4 1. "POL_FS_DEV_CLK,USB1 Device need_clock polarity for triggering the USB1 wake-up interrupt." "0,1"
newline
bitfld.long 0x4 0. "AP_FS_DEV_CLK,USB1 Device need_clock signal control." "0,1"
line.long 0x8 "USB1CLKSTAT,USB1 clock status"
bitfld.long 0x8 1. "HOST_NEED_CLKST,USB1 Device host USB1_NEEDCLK signal status." "0,1"
bitfld.long 0x8 0. "DEV_NEED_CLKST,USB1 Device USB1_NEEDCLK signal status." "0,1"
group.long 0x444++0x13
line.long 0x0 "EMCSYSCTRL,EMC system control"
bitfld.long 0x0 3. "EMCFBCLKINSEL,External Memory Controller clock select." "0,1"
bitfld.long 0x0 2. "EMCBC,External Memory Controller burst control." "0,1"
newline
bitfld.long 0x0 1. "EMCRD,EMC Reset Disable." "0,1"
bitfld.long 0x0 0. "EMCSC,EMC Shift Control." "0,1"
line.long 0x4 "EMCDLYCTRL,EMC clock delay control"
hexmask.long.byte 0x4 8.--12. 1. "FBCLK_DELAY,Programmable delay value for the feedback clock that controls input data sampling."
hexmask.long.byte 0x4 0.--4. 1. "CMD_DELAY,Programmable delay value for EMC outputs in command delayed mode."
line.long 0x8 "EMCDLYCAL,EMC delay chain calibration control"
bitfld.long 0x8 15. "DONE,Measurement completion flag." "0,1"
bitfld.long 0x8 14. "START,Start control bit for the EMC calibration counter." "0,1"
newline
hexmask.long.byte 0x8 0.--7. 1. "CALVALUE,Returns the count of the approximately 50 MHz ring oscillator that occur during 32 clocks of the FRO 12 MHz."
line.long 0xC "ETHPHYSEL,Ethernet PHY Selection"
bitfld.long 0xC 2. "PHY_SEL,PHY interface select." "0,1"
line.long 0x10 "ETHSBDCTRL,Ethernet SBD flow control"
bitfld.long 0x10 0.--1. "SBD_CTRL,Sideband Flow Control." "0,1,2,3"
group.long 0x460++0x3
line.long 0x0 "SDIOCLKCTRL,SDIO CCLKIN phase and delay control"
bitfld.long 0x0 31. "CCLK_SAMPLE_DELAY_ACTIVE,Enables sample delay  as controlled by the CCLK_SAMPLE_DELAY field." "0,1"
hexmask.long.byte 0x0 24.--28. 1. "CCLK_SAMPLE_DELAY,Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in."
newline
bitfld.long 0x0 23. "CCLK_DRV_DELAY_ACTIVE,Enables drive delay  as controlled by the CCLK_DRV_DELAY field." "0,1"
hexmask.long.byte 0x0 16.--20. 1. "CCLK_DRV_DELAY,Programmable delay value by which cclk_in_drv is delayed with regard to cclk_in."
newline
bitfld.long 0x0 7. "PHASE_ACTIVE,sdio_clk by 2  before feeding into ccl_in  cclk_in_sample  and cclk_in_drv." "0,1"
bitfld.long 0x0 2.--3. "CCLK_SAMPLE_PHASE,Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in." "0,1,2,3"
newline
bitfld.long 0x0 0.--1. "CCLK_DRV_PHASE,Programmable delay value by which cclk_in_drv is phase-shifted with regard to cclk_in." "0,1,2,3"
group.long 0x500++0xF
line.long 0x0 "FROCTRL,FRO oscillator control"
bitfld.long 0x0 31. "WRTRIM,Write Trim value." "0,1"
bitfld.long 0x0 30. "HSPDCLK,High speed clock enable." "0,1"
newline
bitfld.long 0x0 25. "USBMODCHG,USB Mode value Change flag." "0,1"
bitfld.long 0x0 24. "USBCLKADJ,USB clock adjust mode." "0,1"
newline
hexmask.long.byte 0x0 16.--23. 1. "FREQTRIM,Frequency trim."
bitfld.long 0x0 14. "SEL,Select the FRO HF output frequency." "0,1"
newline
hexmask.long.word 0x0 0.--13. 1. "TRIM,This value is factory trimmed to account for bias and temperature compensation."
line.long 0x4 "SYSOSCCTRL,System oscillator control"
bitfld.long 0x4 1. "FREQRANGE,Determines frequency range for system oscillator." "0,1"
bitfld.long 0x4 0. "BYPASS,Bypass system oscillator." "0,1"
line.long 0x8 "WDTOSCCTRL,Watchdog oscillator control"
hexmask.long.byte 0x8 5.--9. 1. "FREQSEL,Frequency select."
hexmask.long.byte 0x8 0.--4. 1. "DIVSEL,Divider select."
line.long 0xC "RTCOSCCTRL,RTC oscillator 32 kHz output control"
bitfld.long 0xC 0. "EN,RTC 32 kHz clock enable." "0,1"
group.long 0x51C++0x7
line.long 0x0 "USBPLLCTRL,USB PLL control"
bitfld.long 0x0 14. "FBSEL,Feedback divider input clock control." "0,1"
bitfld.long 0x0 13. "BYPASS,Input clock bypass control." "0: CCO clock is sent to post dividers..,1: PLL input clock is sent to post dividers.."
newline
bitfld.long 0x0 12. "DIRECT,Direct CCO clock output control." "0: CCO Clock signal goes through post divider.,1: CCO Clock signal goes directly to output(s).."
bitfld.long 0x0 10.--11. "NSEL,PLL feedback Divider value." "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "PSEL,PLL Divider value." "0,1,2,3"
hexmask.long.byte 0x0 0.--7. 1. "MSEL,PLL feedback Divider value."
line.long 0x4 "USBPLLSTAT,USB PLL status"
bitfld.long 0x4 0. "LOCK,USBPLL lock indicator." "0,1"
group.long 0x580++0x13
line.long 0x0 "SYSPLLCTRL,System PLL control"
bitfld.long 0x0 20. "DIRECTO,PLL0 direct output enable." "0: Disabled. The PLL output divider (P divider) is..,1: Enabled. The PLL output divider (P divider) is.."
bitfld.long 0x0 19. "DIRECTI,PLL0 direct input enable." "0,1"
newline
bitfld.long 0x0 17. "UPLIMOFF,Disable upper frequency limiter." "0,1"
bitfld.long 0x0 15. "BYPASS,PLL bypass control." "0: Bypass disabled. PLL CCO is sent to the PLL..,1: Bypass enabled. PLL input clock is sent directly.."
newline
hexmask.long.byte 0x0 10.--14. 1. "SELP,Bandwidth select P value."
hexmask.long.byte 0x0 4.--9. 1. "SELI,Bandwidth select I value."
newline
hexmask.long.byte 0x0 0.--3. 1. "SELR,Bandwidth select R value."
line.long 0x4 "SYSPLLSTAT,PLL status"
bitfld.long 0x4 0. "LOCK,PLL lock indicator." "0,1"
line.long 0x8 "SYSPLLNDEC,PLL N divider"
bitfld.long 0x8 10. "NREQ,NDEC reload request." "0,1"
hexmask.long.word 0x8 0.--9. 1. "NDEC,Decoded N-divider coefficient value."
line.long 0xC "SYSPLLPDEC,PLL P divider"
bitfld.long 0xC 7. "PREQ,." "0,1"
hexmask.long.byte 0xC 0.--6. 1. "PDEC,Decoded P-divider coefficient value."
line.long 0x10 "SYSPLLMDEC,System PLL M divider"
bitfld.long 0x10 17. "MREQ,MDEC reload request." "0,1"
hexmask.long.tbyte 0x10 0.--16. 1. "MDEC,Decoded M-divider coefficient value."
group.long 0x5A0++0x17
line.long 0x0 "AUDPLLCTRL,Audio PLL control"
bitfld.long 0x0 20. "DIRECTO,PLL direct output enable" "0: Disabled. The PLL output divider (P divider) is..,1: Enabled. The PLL output divider (P divider) is.."
bitfld.long 0x0 19. "DIRECTI,PLL direct input enable." "0,1"
newline
bitfld.long 0x0 17. "UPLIMOFF,Disable upper frequency limiter." "0,1"
bitfld.long 0x0 15. "BYPASS,PLL bypass control." "0: Bypass disabled. PLL CCO is sent to the PLL..,1: Bypass enabled. PLL input clock is sent directly.."
newline
hexmask.long.byte 0x0 10.--14. 1. "SELP,."
hexmask.long.byte 0x0 4.--9. 1. "SELI,Bandwidth select I value."
newline
hexmask.long.byte 0x0 0.--3. 1. "SELR,Bandwidth select R value."
line.long 0x4 "AUDPLLSTAT,Audio PLL status"
bitfld.long 0x4 0. "LOCK,PLL lock indicator." "0,1"
line.long 0x8 "AUDPLLNDEC,Audio PLL N divider"
bitfld.long 0x8 10. "NREQ,NDEC reload request." "0,1"
hexmask.long.word 0x8 0.--9. 1. "NDEC,Decoded N-divider coefficient value."
line.long 0xC "AUDPLLPDEC,Audio PLL P divider"
bitfld.long 0xC 7. "PREQ,PDEC reload request." "0,1"
hexmask.long.byte 0xC 0.--6. 1. "PDEC,Decoded P-divider coefficient value."
line.long 0x10 "AUDPLLMDEC,Audio PLL M divider"
bitfld.long 0x10 17. "MREQ,MDEC reload request." "0,1"
hexmask.long.tbyte 0x10 0.--16. 1. "MDEC,Decoded M-divider coefficient value."
line.long 0x14 "AUDPLLFRAC,Audio PLL fractional divider control"
bitfld.long 0x14 23. "SEL_EXT,Select fractional divider." "0,1"
bitfld.long 0x14 22. "REQ,Writing 1 to REQ signal loads CTRL value into fractional wrapper modulator." "0,1"
newline
hexmask.long.tbyte 0x14 0.--21. 1. "CTRL,PLL fractional divider control word"
group.long 0x600++0x7
line.long 0x0 "PDSLEEPCFG0,Sleep configuration register"
bitfld.long 0x0 29. "PDEN_VD6,Power control for EEPROM." "0,1"
bitfld.long 0x0 28. "PDEN_VD5,Power control both USB0 PHY and USB1 PHY." "0,1"
newline
bitfld.long 0x0 27. "PDEN_VD4,Power control for all SRAMs and ROM." "0,1"
bitfld.long 0x0 26. "PDEN_VD3,Power control for all PLLs." "0,1"
newline
bitfld.long 0x0 23. "PDEN_VREFP,VREFP to the ADC must be enabled for the ADC to work (also enable/disable bit 9  10  and 19)." "0,1"
bitfld.long 0x0 22. "PDEN_SYS_PLL,System PLL (PLL0) power (also enable/disable bit 26)." "0,1"
newline
bitfld.long 0x0 21. "PDEN_USB0_PHY,USB0 PHY power (also enable/disable bit 28)." "0,1"
bitfld.long 0x0 20. "PDEN_WDT_OSC,Watchdog oscillator." "0,1"
newline
bitfld.long 0x0 19. "PDEN_VDDA,Vdda to the ADC  must be enabled for the ADC to work (also enable/disable bit 9  10  and 23)." "0,1"
bitfld.long 0x0 17. "PDEN_ROM,ROM (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 16. "PDEN_USB_RAM,PDEN_USB_SRAM controls USB_RAM (also enable/disable bit 27)." "0,1"
bitfld.long 0x0 15. "PDEN_SRAM1_2_3,PDEN_SRAM1_2_3 controls SRAM1  SRAM2  and SRAM3 (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 14. "PDEN_SRAM0,PDEN_SRAM0 controls SRAM0 (also enable/disable bit 27)." "0,1"
bitfld.long 0x0 13. "PDEN_SRAMX,PDEN_SRAMX controls SRAMX (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 10. "PDEN_ADC0,ADC power." "0,1"
bitfld.long 0x0 9. "PDEN_VD2_ANA,Analog supply for System Oscillator (also enable/disable bit 3 in PDRUNCFG1 register)  Temperature Sensor (also  enable/disable bit 6)  ADC (also  enable/disable bits 10  19  and 23)." "0,1"
newline
bitfld.long 0x0 8. "PDEN_BOD_INTR,Brown-out Detect interrupt." "0,1"
bitfld.long 0x0 7. "PDEN_BOD_RST,Brown-out Detect reset." "0,1"
newline
bitfld.long 0x0 6. "PDEN_TS,Temp sensor." "0,1"
bitfld.long 0x0 4. "PDEN_FRO,FRO oscillator." "0,1"
line.long 0x4 "PDSLEEPCFG1,Sleep configuration register"
bitfld.long 0x4 7. "PDEN_RNG,Random Number Generator Power." "0,1"
bitfld.long 0x4 5. "PDEN_EEPROM,EEPROM power (also  enable/disable bit 29 in PDRUNCFG0 register)." "0,1"
newline
bitfld.long 0x4 3. "PDEN_SYSOSC,System Oscillator Power (also  enable/disable bit 9 in PDRUNCFG0 register)." "0,1"
bitfld.long 0x4 2. "PDEN_AUD_PLL,Audio PLL (PLL2) power and fractional divider (also  enable/disable bit 26 in PDRUNCFG0 register)." "0,1"
newline
bitfld.long 0x4 1. "PDEN_USB1_PLL,USB PLL (PLL1) power (also  enable/disable bit 26 in PDRUNCFG0 register)." "0,1"
bitfld.long 0x4 0. "PDEN_USB1_PHY,USB1 high speed PHY (also  enable/disable bit 28 in PDRUNCFG0 register)." "0,1"
group.long 0x610++0x7
line.long 0x0 "PDRUNCFG0,Power configuration register"
bitfld.long 0x0 29. "PDEN_VD6,Power control for EEPROM." "0,1"
bitfld.long 0x0 28. "PDEN_VD5,Power control both USB0 PHY and USB1 PHY." "0,1"
newline
bitfld.long 0x0 27. "PDEN_VD4,Power control for all SRAMs and ROM." "0,1"
bitfld.long 0x0 26. "PDEN_VD3,Power control for all PLLs." "0,1"
newline
bitfld.long 0x0 23. "PDEN_VREFP,VREFP to the ADC must be enabled for the ADC to work (also enable/disable bit 9  10  and 19)." "0,1"
bitfld.long 0x0 22. "PDEN_SYS_PLL,System PLL (PLL0) power (also enable/disable bit 26)." "0,1"
newline
bitfld.long 0x0 21. "PDEN_USB0_PHY,USB0 PHY power (also enable/disable bit 28)." "0,1"
bitfld.long 0x0 20. "PDEN_WDT_OSC,Watchdog oscillator." "0,1"
newline
bitfld.long 0x0 19. "PDEN_VDDA,Vdda to the ADC  must be enabled for the ADC to work (also enable/disable bit 9  10  and 23)." "0,1"
bitfld.long 0x0 17. "PDEN_ROM,ROM (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 16. "PDEN_USB_RAM,PDEN_USB_SRAM controls USB_RAM (also enable/disable bit 27)." "0,1"
bitfld.long 0x0 15. "PDEN_SRAM1_2_3,PDEN_SRAM1_2_3 controls SRAM1  SRAM2  and SRAM3 (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 14. "PDEN_SRAM0,PDEN_SRAM0 controls SRAM0 (also enable/disable bit 27)." "0,1"
bitfld.long 0x0 13. "PDEN_SRAMX,PDEN_SRAMX controls SRAMX (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 10. "PDEN_ADC0,ADC power." "0,1"
bitfld.long 0x0 9. "PDEN_VD2_ANA,Analog supply for System Oscillator (also enable/disable bit 3 in PDRUNCFG1 register)  Temperature Sensor (also  enable/disable bit 6)  ADC (also  enable/disable bits 10  19  and 23)." "0,1"
newline
bitfld.long 0x0 8. "PDEN_BOD_INTR,Brown-out Detect interrupt." "0,1"
bitfld.long 0x0 7. "PDEN_BOD_RST,Brown-out Detect reset." "0,1"
newline
bitfld.long 0x0 6. "PDEN_TS,Temp sensor." "0,1"
bitfld.long 0x0 4. "PDEN_FRO,FRO oscillator." "0,1"
line.long 0x4 "PDRUNCFG1,Power configuration register"
bitfld.long 0x4 7. "PDEN_RNG,Random Number Generator Power." "0,1"
bitfld.long 0x4 5. "PDEN_EEPROM,EEPROM power (also  enable/disable bit 29 in PDRUNCFG0 register)." "0,1"
newline
bitfld.long 0x4 3. "PDEN_SYSOSC,System Oscillator Power (also  enable/disable bit 9 in PDRUNCFG0 register)." "0,1"
bitfld.long 0x4 2. "PDEN_AUD_PLL,Audio PLL (PLL2) power and fractional divider (also  enable/disable bit 26 in PDRUNCFG0 register)." "0,1"
newline
bitfld.long 0x4 1. "PDEN_USB1_PLL,USB PLL (PLL1) power (also  enable/disable bit 26 in PDRUNCFG0 register)." "0,1"
bitfld.long 0x4 0. "PDEN_USB1_PHY,USB1 high speed PHY (also  enable/disable bit 28 in PDRUNCFG0 register)." "0,1"
group.long 0x620++0x7
line.long 0x0 "PDRUNCFGSET0,Power configuration set register"
bitfld.long 0x0 29. "PDEN_VD6,Power control for EEPROM." "0,1"
bitfld.long 0x0 28. "PDEN_VD5,Power control both USB0 PHY and USB1 PHY." "0,1"
newline
bitfld.long 0x0 27. "PDEN_VD4,Power control for all SRAMs and ROM." "0,1"
bitfld.long 0x0 26. "PDEN_VD3,Power control for all PLLs." "0,1"
newline
bitfld.long 0x0 23. "PDEN_VREFP,VREFP to the ADC must be enabled for the ADC to work (also enable/disable bit 9  10  and 19)." "0,1"
bitfld.long 0x0 22. "PDEN_SYS_PLL,System PLL (PLL0) power (also enable/disable bit 26)." "0,1"
newline
bitfld.long 0x0 21. "PDEN_USB0_PHY,USB0 PHY power (also enable/disable bit 28)." "0,1"
bitfld.long 0x0 20. "PDEN_WDT_OSC,Watchdog oscillator." "0,1"
newline
bitfld.long 0x0 19. "PDEN_VDDA,Vdda to the ADC  must be enabled for the ADC to work (also enable/disable bit 9  10  and 23)." "0,1"
bitfld.long 0x0 17. "PDEN_ROM,ROM (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 16. "PDEN_USB_RAM,PDEN_USB_SRAM controls USB_RAM (also enable/disable bit 27)." "0,1"
bitfld.long 0x0 15. "PDEN_SRAM1_2_3,PDEN_SRAM1_2_3 controls SRAM1  SRAM2  and SRAM3 (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 14. "PDEN_SRAM0,PDEN_SRAM0 controls SRAM0 (also enable/disable bit 27)." "0,1"
bitfld.long 0x0 13. "PDEN_SRAMX,PDEN_SRAMX controls SRAMX (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 10. "PDEN_ADC0,ADC power." "0,1"
bitfld.long 0x0 9. "PDEN_VD2_ANA,Analog supply for System Oscillator (also enable/disable bit 3 in PDRUNCFG1 register)  Temperature Sensor (also  enable/disable bit 6)  ADC (also  enable/disable bits 10  19  and 23)." "0,1"
newline
bitfld.long 0x0 8. "PDEN_BOD_INTR,Brown-out Detect interrupt." "0,1"
bitfld.long 0x0 7. "PDEN_BOD_RST,Brown-out Detect reset." "0,1"
newline
bitfld.long 0x0 6. "PDEN_TS,Temp sensor." "0,1"
bitfld.long 0x0 4. "PDEN_FRO,FRO oscillator." "0,1"
line.long 0x4 "PDRUNCFGSET1,Power configuration set register"
bitfld.long 0x4 7. "PDEN_RNG,Random Number Generator Power." "0,1"
bitfld.long 0x4 5. "PDEN_EEPROM,EEPROM power (also  enable/disable bit 29 in PDRUNCFG0 register)." "0,1"
newline
bitfld.long 0x4 3. "PDEN_SYSOSC,System Oscillator Power (also  enable/disable bit 9 in PDRUNCFG0 register)." "0,1"
bitfld.long 0x4 2. "PDEN_AUD_PLL,Audio PLL (PLL2) power and fractional divider (also  enable/disable bit 26 in PDRUNCFG0 register)." "0,1"
newline
bitfld.long 0x4 1. "PDEN_USB1_PLL,USB PLL (PLL1) power (also  enable/disable bit 26 in PDRUNCFG0 register)." "0,1"
bitfld.long 0x4 0. "PDEN_USB1_PHY,USB1 high speed PHY (also  enable/disable bit 28 in PDRUNCFG0 register)." "0,1"
group.long 0x630++0x7
line.long 0x0 "PDRUNCFGCLR0,Power configuration clear register"
bitfld.long 0x0 29. "PDEN_VD6,Power control for EEPROM." "0,1"
bitfld.long 0x0 28. "PDEN_VD5,Power control both USB0 PHY and USB1 PHY." "0,1"
newline
bitfld.long 0x0 27. "PDEN_VD4,Power control for all SRAMs and ROM." "0,1"
bitfld.long 0x0 26. "PDEN_VD3,Power control for all PLLs." "0,1"
newline
bitfld.long 0x0 23. "PDEN_VREFP,VREFP to the ADC must be enabled for the ADC to work (also enable/disable bit 9  10  and 19)." "0,1"
bitfld.long 0x0 22. "PDEN_SYS_PLL,System PLL (PLL0) power (also enable/disable bit 26)." "0,1"
newline
bitfld.long 0x0 21. "PDEN_USB0_PHY,USB0 PHY power (also enable/disable bit 28)." "0,1"
bitfld.long 0x0 20. "PDEN_WDT_OSC,Watchdog oscillator." "0,1"
newline
bitfld.long 0x0 19. "PDEN_VDDA,Vdda to the ADC  must be enabled for the ADC to work (also enable/disable bit 9  10  and 23)." "0,1"
bitfld.long 0x0 17. "PDEN_ROM,ROM (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 16. "PDEN_USB_RAM,PDEN_USB_SRAM controls USB_RAM (also enable/disable bit 27)." "0,1"
bitfld.long 0x0 15. "PDEN_SRAM1_2_3,PDEN_SRAM1_2_3 controls SRAM1  SRAM2  and SRAM3 (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 14. "PDEN_SRAM0,PDEN_SRAM0 controls SRAM0 (also enable/disable bit 27)." "0,1"
bitfld.long 0x0 13. "PDEN_SRAMX,PDEN_SRAMX controls SRAMX (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 10. "PDEN_ADC0,ADC power." "0,1"
bitfld.long 0x0 9. "PDEN_VD2_ANA,Analog supply for System Oscillator (also enable/disable bit 3 in PDRUNCFG1 register)  Temperature Sensor (also  enable/disable bit 6)  ADC (also  enable/disable bits 10  19  and 23)." "0,1"
newline
bitfld.long 0x0 8. "PDEN_BOD_INTR,Brown-out Detect interrupt." "0,1"
bitfld.long 0x0 7. "PDEN_BOD_RST,Brown-out Detect reset." "0,1"
newline
bitfld.long 0x0 6. "PDEN_TS,Temp sensor." "0,1"
bitfld.long 0x0 4. "PDEN_FRO,FRO oscillator." "0,1"
line.long 0x4 "PDRUNCFGCLR1,Power configuration clear register"
bitfld.long 0x4 7. "PDEN_RNG,Random Number Generator Power." "0,1"
bitfld.long 0x4 5. "PDEN_EEPROM,EEPROM power (also  enable/disable bit 29 in PDRUNCFG0 register)." "0,1"
newline
bitfld.long 0x4 3. "PDEN_SYSOSC,System Oscillator Power (also  enable/disable bit 9 in PDRUNCFG0 register)." "0,1"
bitfld.long 0x4 2. "PDEN_AUD_PLL,Audio PLL (PLL2) power and fractional divider (also  enable/disable bit 26 in PDRUNCFG0 register)." "0,1"
newline
bitfld.long 0x4 1. "PDEN_USB1_PLL,USB PLL (PLL1) power (also  enable/disable bit 26 in PDRUNCFG0 register)." "0,1"
bitfld.long 0x4 0. "PDEN_USB1_PHY,USB1 high speed PHY (also  enable/disable bit 28 in PDRUNCFG0 register)." "0,1"
group.long 0x680++0x7
line.long 0x0 "STARTER0,Start logic 0 wake-up enable register"
bitfld.long 0x0 29. "RTC,RTC interrupt alarm and wake-up timer." "0,1"
bitfld.long 0x0 28. "USB0,USB function interrupt wake-up." "0,1"
newline
bitfld.long 0x0 27. "USB0_NEEDCLK,USB activity interrupt wake-up." "0,1"
bitfld.long 0x0 26. "HWVAD,Hardware voice activity detect interrupt wake-up." "0,1"
newline
bitfld.long 0x0 25. "DMIC,Digital microphone interrupt wake-up." "0,1"
bitfld.long 0x0 24. "ADC0_THCMP,ADC0 threshold and error interrupt wake-up." "0,1"
newline
bitfld.long 0x0 23. "ADC0_SEQB,ADC0 sequence B interrupt wake-up." "0,1"
bitfld.long 0x0 22. "ADC0_SEQA,ADC0 sequence A interrupt wake-up." "0,1"
newline
bitfld.long 0x0 21. "FLEXCOMM7,Flexcomm7 peripheral interrupt wake-up." "0,1"
bitfld.long 0x0 20. "FLEXCOMM6,Flexcomm6 peripheral interrupt wake-up." "0,1"
newline
bitfld.long 0x0 19. "FLEXCOMM5,Flexcomm5 peripheral interrupt wake-up." "0,1"
bitfld.long 0x0 18. "FLEXCOMM4,Flexcomm4 peripheral interrupt wake-up." "0,1"
newline
bitfld.long 0x0 17. "FLEXCOMM3,Flexcomm3 peripheral interrupt wake-up." "0,1"
bitfld.long 0x0 16. "FLEXCOMM2,Flexcomm2 peripheral interrupt wake-up." "0,1"
newline
bitfld.long 0x0 15. "FLEXCOMM1,Flexcomm1 peripheral interrupt wake-up." "0,1"
bitfld.long 0x0 14. "FLEXCOMM0,Flexcomm0 peripheral interrupt wake-up." "0,1"
newline
bitfld.long 0x0 13. "CTIMER3,Standard counter/timer CTIMER3 wake-up." "0,1"
bitfld.long 0x0 12. "SCT0,SCT0 wake-up." "0,1"
newline
bitfld.long 0x0 11. "CTIMER1,Standard counter/timer CTIMER1 wake-up." "0,1"
bitfld.long 0x0 10. "CTIMER0,Standard counter/timer CTIMER0 wake-up." "0,1"
newline
bitfld.long 0x0 9. "MRT,Multi-Rate Timer wake-up." "0,1"
bitfld.long 0x0 8. "UTICK,Micro-tick Timer wake-up." "0,1"
newline
bitfld.long 0x0 7. "PIN_INT3,GPIO pin interrupt 3 wake-up." "0,1"
bitfld.long 0x0 6. "PIN_INT2,GPIO pin interrupt 2 wake-up." "0,1"
newline
bitfld.long 0x0 5. "PIN_INT1,GPIO pin interrupt 1 wake-up." "0,1"
bitfld.long 0x0 4. "PIN_INT0,GPIO pin interrupt 0 wake-up." "0,1"
newline
bitfld.long 0x0 3. "GINT1,Group interrupt 1 wake-up." "0,1"
bitfld.long 0x0 2. "GINT0,Group interrupt 0 wake-up." "0,1"
newline
bitfld.long 0x0 1. "DMA,DMA wake-up." "0,1"
bitfld.long 0x0 0. "WDT_BOD,WWDT and BOD interrupt wake-up." "0,1"
line.long 0x4 "STARTER1,Start logic 0 wake-up enable register"
bitfld.long 0x4 24. "SMARTCARD1,Smart card 1 wake-up." "0,1"
bitfld.long 0x4 23. "SMARTCARD0,Smart card 0 wake-up." "0,1"
newline
bitfld.long 0x4 19. "ENET_INT0,Ethernet." "0,1"
bitfld.long 0x4 18. "ENET_INT2,Ethernet." "0,1"
newline
bitfld.long 0x4 17. "ENET_INT1,Ethernet." "0,1"
bitfld.long 0x4 16. "USB1_ACT,USB 1 activity wake-up." "0,1"
newline
bitfld.long 0x4 15. "USB1,USB 1 wake-up." "0,1"
bitfld.long 0x4 9. "FLEXCOMM9,Flexcomm Interface 9 wake-up." "0,1"
newline
bitfld.long 0x4 8. "FLEXCOMM8,Flexcomm Interface 8 wake-up." "0,1"
bitfld.long 0x4 7. "SPIFI,SPIFI interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled." "0: Wake-up disabled,1: Wake-up enabled"
newline
bitfld.long 0x4 5. "CTIMER4,Standard counter/timer CTIMER4 wake-up." "0,1"
bitfld.long 0x4 4. "CTIMER2,Standard counter/timer CTIMER2 wake-up." "0,1"
newline
bitfld.long 0x4 3. "PINT7,GPIO pin interrupt 7 wake-up." "0,1"
bitfld.long 0x4 2. "PINT6,GPIO pin interrupt 6 wake-up." "0,1"
newline
bitfld.long 0x4 1. "PINT5,GPIO pin interrupt 5 wake-up." "0,1"
bitfld.long 0x4 0. "PINT4,GPIO pin interrupt 4 wake-up." "0,1"
group.long 0x780++0x3
line.long 0x0 "HWWAKE,Configures special cases of hardware wake-up"
bitfld.long 0x0 3. "WAKEDMA,Wake for DMA. When 1  DMA being busy will cause peripheral clocking to remain running until DMA completes. This is generally used in conjunction with bit 1 and/or 2 in order to prevent peripheral clocking from being shut down as soon as the cause.." "0,1"
bitfld.long 0x0 2. "WAKEDMIC,Wake for Digital Microphone. When 1  the digital microphone input FIFO reaching the level specified by TRIGLVL of either channel will cause peripheral clocking to wake up temporarily while the related status is asserted." "0,1"
newline
bitfld.long 0x0 1. "FCWAKE,Wake for Flexcomms. When 1  any Flexcomm FIFO reaching the level specified by its own TXLVL will cause peripheral clocking to wake up temporarily while the related status is asserted." "0,1"
bitfld.long 0x0 0. "FORCEWAKE,Force peripheral clocking to stay on during Deep Sleep and Power-down modes. When 1  clocking to peripherals is prevented from being shut down when the CPU enters Deep Sleep and Power-down modes. This is intended to allow a coprocessor to.." "0,1"
group.long 0xE04++0x3
line.long 0x0 "AUTOCGOR,Auto Clock-Gate Override Register"
bitfld.long 0x0 4. "RAM3,When 1  automatic clock gating for RAM1 are turned off." "0,1"
bitfld.long 0x0 3. "RAM2,When 1  automatic clock gating for RAM1 are turned off." "0,1"
newline
bitfld.long 0x0 2. "RAM1,When 1  automatic clock gating for RAM1 are turned off." "0,1"
bitfld.long 0x0 1. "RAM0X,When 1  automatic clock gating for RAMX and RAM0 are turned off." "0,1"
rgroup.long 0xFF4++0xB
line.long 0x0 "JTAGIDCODE,JTAG ID code register"
hexmask.long 0x0 0.--31. 1. "JTAGID,JTAG ID code."
line.long 0x4 "DEVICE_ID0,Part ID register"
hexmask.long 0x4 0.--31. 1. "PARTID,Part ID"
line.long 0x8 "DEVICE_ID1,Boot ROM and die revision register"
hexmask.long 0x8 0.--31. 1. "REVID,Revision."
group.long 0x20044++0x3
line.long 0x0 "BODCTRL,Brown-Out Detect control"
bitfld.long 0x0 7. "BODINTSTAT,BOD interrupt status. When 1  a BOD interrupt has occurred. Cleared by writing 1 to this bit." "0,1"
bitfld.long 0x0 6. "BODRSTSTAT,BOD reset status. When 1  a BOD reset has occurred. Cleared by writing 1 to this bit." "0,1"
newline
bitfld.long 0x0 5. "BODINTENA,BOD interrupt enable" "0: Disable interrupt function.,1: Enable interrupt function."
bitfld.long 0x0 3.--4. "BODINTLEV,BOD interrupt level" "0: Level 0: 2.05 V,1: Level 1: 2.45 V,2: Level 2: 2.75 V,3: Level 3: 3.05 V"
newline
bitfld.long 0x0 2. "BODRSTENA,BOD reset enable" "0: Disable reset function.,1: Enable reset function."
bitfld.long 0x0 0.--1. "BODRSTLEV,BOD reset level" "0: Level 0: 1.5 V,1: Level 1: 1.85 V,2: Level 2: 2.0 V,3: Level 3: 2.3 V"
endif
sif (cpuis("LPC54606*"))
group.long 0x10++0x3
line.long 0x0 "AHBMATPRIO,AHB multilayer matrix priority control"
bitfld.long 0x0 24.--25. "PRI_SHA,SHA priority." "0,1,2,3"
bitfld.long 0x0 22.--23. "PRI_MCAN2,MCAN2 priority." "0,1,2,3"
newline
bitfld.long 0x0 20.--21. "PRI_MCAN1,MCAN1 priority." "0,1,2,3"
bitfld.long 0x0 18.--19. "PRI_SDIO,SDIO priority." "0,1,2,3"
newline
bitfld.long 0x0 16.--17. "PRI_USB1,USB1 DMA priority." "0,1,2,3"
bitfld.long 0x0 14.--15. "PRI_USB0,USB0 DMA priority." "0,1,2,3"
newline
bitfld.long 0x0 12.--13. "PRI_LCD,LCD DMA priority." "0,1,2,3"
bitfld.long 0x0 10.--11. "PRI_ETH,Ethernet DMA priority." "0,1,2,3"
newline
hexmask.long.byte 0x0 6.--9. 1. "PRI_DMA,DMA controller priority."
bitfld.long 0x0 4.--5. "PRI_SYS,System bus priority." "0,1,2,3"
newline
bitfld.long 0x0 2.--3. "PRI_DCODE,D-Code bus priority." "0,1,2,3"
bitfld.long 0x0 0.--1. "PRI_ICODE,I-Code bus priority." "0,1,2,3"
group.long 0x40++0x3
line.long 0x0 "SYSTCKCAL,System tick counter calibration"
bitfld.long 0x0 25. "NOREF,Initial value for the Systick timer." "0,1"
bitfld.long 0x0 24. "SKEW,Initial value for the Systick timer." "0,1"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "CAL,System tick timer calibration value."
group.long 0x48++0x7
line.long 0x0 "NMISRC,NMI Source Select"
bitfld.long 0x0 31. "NMIENM4,Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQM4." "0,1"
hexmask.long.byte 0x0 0.--5. 1. "IRQM4,The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the Cortex-M4  if enabled by NMIENM4."
line.long 0x4 "ASYNCAPBCTRL,Asynchronous APB Control"
bitfld.long 0x4 0. "ENABLE,Enables the asynchronous APB bridge and subsystem." "0: Disabled. Asynchronous APB bridge is disabled.,1: Enabled. Asynchronous APB bridge is enabled."
endif
sif (cpuis("LPC54606*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0xC0)++0x3
line.long 0x0 "PIOPORCAP[$1],POR captured value of port n"
hexmask.long 0x0 0.--31. 1. "PIOPORCAP,State of PIOn_31 through PIOn_0 at power-on reset"
repeat.end
endif
sif (cpuis("LPC54606*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0xD0)++0x3
line.long 0x0 "PIORESCAP[$1],Reset captured value of port n"
hexmask.long 0x0 0.--31. 1. "PIORESCAP,State of PIOn_31 through PIOn_0 for resets other than POR."
repeat.end
group.long 0x100++0xB
line.long 0x0 "PRESETCTRL0,Peripheral reset control n"
bitfld.long 0x0 27. "ADC0_RST,ADC0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 22. "WWDT_RST,Watchdog timer reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x0 21. "CRC_RST,CRC generator reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 20. "DMA0_RST,DMA0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x0 19. "GINT_RST,Grouped interrupt (GINT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 18. "PINT_RST,Pin interrupt (PINT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x0 17. "GPIO3_RST,GPIO3 reset control." "0,1"
bitfld.long 0x0 16. "GPIO2_RST,GPIO2 reset control." "0,1"
newline
bitfld.long 0x0 15. "GPIO1_RST,GPIO1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 14. "GPIO0_RST,GPIO0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x0 13. "IOCON_RST,IOCON reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 11. "MUX_RST,Input mux reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x0 10. "SPIFI_RST,SPIFI reset control." "0,1"
bitfld.long 0x0 9. "EEPROM_RST,EEPROM reset control." "0,1"
newline
bitfld.long 0x0 8. "FMC_RST,Flash accelerator reset control. Note that the FMC must not be reset while executing from flash  and must be reconfigured after reset. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 7. "FLASH_RST,Flash controller reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
line.long 0x4 "PRESETCTRL1,Peripheral reset control n"
bitfld.long 0x4 27. "CTIMER1_RST,CTIMER1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 26. "CTIMER0_RST,CTIMER0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 25. "USB0D_RST,USB0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 22. "CTIMER2_RST,CTIMER2 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function" "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 19. "DMIC_RST,Digital microphone interface reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 18. "FC7_RST,Flexcomm 7 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 17. "FC6_RST,Flexcomm 6 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 16. "FC5_RST,Flexcomm 5 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 15. "FC4_RST,Flexcomm 4 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 14. "FC3_RST,Flexcomm 3 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 13. "FC2_RST,Flexcomm 2 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 12. "FC1_RST,Flexcomm 1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 11. "FC0_RST,Flexcomm 0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 10. "UTICK_RST,Micro-tick Timer reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 8. "MCAN1_RST,0 = Clear reset to this function." "0: Clear reset to this function,?"
bitfld.long 0x4 7. "MCAN0_RST,0 = Clear reset to this function." "0: Clear reset to this function,?"
newline
bitfld.long 0x4 2. "SCT0_RST,State configurable timer 0 (SCT0) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 0. "MRT_RST,Multi-rate timer (MRT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
line.long 0x8 "PRESETCTRL2,Peripheral reset control n"
bitfld.long 0x8 20. "SC1_RST,Smart card 1 reset control." "0,1"
bitfld.long 0x8 19. "SC0_RST,Smart card 0 reset control." "0,1"
newline
bitfld.long 0x8 18. "SHA_RST,SHA reset control." "0,1"
bitfld.long 0x8 17. "USB0HSL_RST,USB0 HOST slave reset control." "0,1"
newline
bitfld.long 0x8 16. "USB0HMR_RST,USB0 HOST master reset control." "0,1"
bitfld.long 0x8 15. "FC9_RST,Flexcomm 9 reset control." "0,1"
newline
bitfld.long 0x8 14. "FC8_RST,Flexcomm 8 reset control." "0,1"
bitfld.long 0x8 13. "RNG_RST,RNG reset control." "0,1"
newline
bitfld.long 0x8 12. "OTP_RST,OTP reset control." "0,1"
bitfld.long 0x8 11. "AES_RST,AES reset control." "0,1"
newline
bitfld.long 0x8 10. "GPIO5_RST,GPIO5 reset control." "0,1"
bitfld.long 0x8 9. "GPIO4_RST,GPIO4 reset control." "0,1"
newline
bitfld.long 0x8 8. "ETH_RST,Ethernet reset control." "0,1"
bitfld.long 0x8 7. "EMC_RESET,EMC reset control." "0,1"
newline
bitfld.long 0x8 6. "USB1RAM_RST,USB1 RAM reset control." "0,1"
bitfld.long 0x8 5. "USB1D_RST,USB1 Device reset control." "0,1"
newline
bitfld.long 0x8 4. "USB1H_RST,USB1 Host reset control." "0,1"
bitfld.long 0x8 3. "SDIO_RST,SDIO reset control." "0,1"
newline
bitfld.long 0x8 2. "LCD_RST,LCD reset control." "0,1"
endif
sif (cpuis("LPC54606*"))
repeat 3. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x120)++0x3
line.long 0x0 "PRESETCTRLSET[$1],Set bits in PRESETCTRLn"
hexmask.long 0x0 0.--31. 1. "RST_SET,Writing ones to this register sets the corresponding bit or bits in the PRESETCTRLn register  if they are implemented. Bits that do not correspond to defined bits in PRESETCTRLn are reserved and only zeroes should be written to them."
repeat.end
endif
sif (cpuis("LPC54606*"))
repeat 3. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x140)++0x3
line.long 0x0 "PRESETCTRLCLR[$1],Clear bits in PRESETCTRLn"
hexmask.long 0x0 0.--31. 1. "RST_CLR,Writing ones to this register clears the corresponding bit or bits in the PRESETCTRLn register  if they are implemented. Bits that do not correspond to defined bits in PRESETCTRLn are reserved and only zeroes should be written to them."
repeat.end
group.long 0x1F0++0x3
line.long 0x0 "SYSRSTSTAT,System reset status register"
bitfld.long 0x0 4. "SYSRST,Status of the software system reset" "0: No System reset detected,1: System reset detected. Writing a one clears this.."
bitfld.long 0x0 3. "BOD,Status of the Brown-out detect reset" "0: No BOD reset detected,1: BOD reset detected. Writing a one clears this.."
newline
bitfld.long 0x0 2. "WDT,Status of the Watchdog reset" "0: No WDT reset detected,1: WDT reset detected. Writing a one clears this.."
bitfld.long 0x0 1. "EXTRST,Status of the external RESET pin. External reset status" "0: No reset event detected.,1: Reset detected. Writing a one clears this reset."
newline
bitfld.long 0x0 0. "POR,POR reset status" "0: No POR detected,1: POR detected. Writing a one clears this reset."
group.long 0x200++0xB
line.long 0x0 "AHBCLKCTRL0,AHB Clock control n"
bitfld.long 0x0 27. "ADC0,Enables the clock for the ADC0 register interface." "0,1"
bitfld.long 0x0 23. "RTC,Enables the bus clock for the RTC. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 22. "WWDT,Enables the clock for the Watchdog Timer. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 21. "CRC,Enables the clock for the CRC engine. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 20. "DMA,Enables the clock for the DMA controller. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 19. "GINT,Enables the clock for the grouped pin interrupt block. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 18. "PINT,Enables the clock for the pin interrupt block.0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 17. "GPIO3,Enables the clock for the GPIO3 port registers." "0,1"
newline
bitfld.long 0x0 16. "GPIO2,Enables the clock for the GPIO2 port registers." "0,1"
bitfld.long 0x0 15. "GPIO1,Enables the clock for the GPIO1 port registers. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 14. "GPIO0,Enables the clock for the GPIO0 port registers. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 13. "IOCON,Enables the clock for the IOCON block. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 11. "INPUTMUX,Enables the clock for the input muxes. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 10. "SPIFI,Enables the clock for the SPIFI. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 9. "EEPROM,Enables the clock for EEPROM." "0,1"
bitfld.long 0x0 8. "FMC,Enables the clock for the Flash accelerator. 0 = Disable; 1 = Enable. This clock is needed if the flash is being read." "0: Disable,1: Enable"
newline
bitfld.long 0x0 7. "FLASH,Enables the clock for the flash controller. 0 = Disable; 1 = Enable. This clock is needed for flash programming  not for flash read." "0: Disable,1: Enable"
bitfld.long 0x0 5. "SRAM3,Enables the clock for SRAM3." "0,1"
newline
bitfld.long 0x0 4. "SRAM2,Enables the clock for SRAM2. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 3. "SRAM1,Enables the clock for SRAM1. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 1. "ROM,Enables the clock for the Boot ROM. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
line.long 0x4 "AHBCLKCTRL1,AHB Clock control n"
bitfld.long 0x4 27. "CTIMER1,Enables the clock for timer CTIMER1. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 26. "CTIMER0,Enables the clock for timer CTIMER0. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 25. "USB0D,Enables the clock for the USB0 device interface. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 22. "CTIMER2,Enables the clock for CTIMER 2. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 19. "DMIC,Enables the clock for the digital microphone interface. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 18. "FLEXCOMM7,Enables the clock for Flexcomm 7. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 17. "FLEXCOMM6,Enables the clock for Flexcomm 6. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 16. "FLEXCOMM5,Enables the clock for Flexcomm 5. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 15. "FLEXCOMM4,Enables the clock for Flexcomm 4. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 14. "FLEXCOMM3,Enables the clock for Flexcomm 3. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 13. "FLEXCOMM2,Enables the clock for Flexcomm 2. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 12. "FLEXCOMM1,Enables the clock for Flexcomm 1. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 11. "FLEXCOMM0,Enables the clock for Flexcomm 0. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 10. "UTICK,Enables the clock for the Micro-tick Timer. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 8. "MCAN1,Enables the clock for MCAN1." "0,1"
bitfld.long 0x4 7. "MCAN0,Enables the clock for MCAN0." "0,1"
newline
bitfld.long 0x4 2. "SCT0,Enables the clock for SCT0." "0,1"
bitfld.long 0x4 1. "RIT,Enables the clock for the Repetitive Interrupt Timer." "0,1"
newline
bitfld.long 0x4 0. "MRT,Enables the clock for the Multi-Rate Timer." "0,1"
line.long 0x8 "AHBCLKCTRL2,AHB Clock control n"
bitfld.long 0x8 20. "SC1,Enables the clock for the Smart card1 interface." "0,1"
bitfld.long 0x8 19. "SC0,Enables the clock for the Smart card0 interface." "0,1"
newline
bitfld.long 0x8 18. "SHA0,Enables the clock for the SHA interface." "0,1"
bitfld.long 0x8 17. "USB0HSL,Enables the clock for the USB host slave interface." "0,1"
newline
bitfld.long 0x8 16. "USB0HMR,Enables the clock for the USB host master interface." "0,1"
bitfld.long 0x8 15. "FLEXCOMM9,Enables the clock for the Flexcomm9 interface." "0,1"
newline
bitfld.long 0x8 14. "FLEXCOMM8,Enables the clock for the Flexcomm8 interface." "0,1"
bitfld.long 0x8 13. "RNG,Enables the clock for the RNG interface." "0,1"
newline
bitfld.long 0x8 12. "OTP,Enables the clock for the OTP interface." "0,1"
bitfld.long 0x8 11. "AES,Enables the clock for the AES interface." "0,1"
newline
bitfld.long 0x8 10. "GPIO5,Enables the clock for the GPIO5 interface." "0,1"
bitfld.long 0x8 9. "GPIO4,Enables the clock for the GPIO4 interface." "0,1"
newline
bitfld.long 0x8 8. "ETH,Enables the clock for the ethernet interface." "0,1"
bitfld.long 0x8 7. "EMC,Enables the clock for the EMC interface." "0,1"
newline
bitfld.long 0x8 6. "USB1RAM,Enables the clock for the USB1 RAM interface." "0,1"
bitfld.long 0x8 5. "USB1D,Enables the clock for the USB1 device interface." "0,1"
newline
bitfld.long 0x8 4. "USB1H,Enables the clock for the USB1 host interface." "0,1"
bitfld.long 0x8 3. "SDIO,Enables the clock for the SDIO interface." "0,1"
newline
bitfld.long 0x8 2. "LCD,Enables the clock for the LCD interface." "0,1"
endif
sif (cpuis("LPC54606*"))
repeat 3. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x220)++0x3
line.long 0x0 "AHBCLKCTRLSET[$1],Set bits in AHBCLKCTRLn"
hexmask.long 0x0 0.--31. 1. "CLK_SET,Writing ones to this register sets the corresponding bit or bits in the AHBCLKCTRLn register  if they are implemented. Bits that do not correspond to defined bits in AHBCLKCTRLn are reserved and only zeroes should be written to them."
repeat.end
endif
sif (cpuis("LPC54606*"))
repeat 3. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x240)++0x3
line.long 0x0 "AHBCLKCTRLCLR[$1],Clear bits in AHBCLKCTRLn"
hexmask.long 0x0 0.--31. 1. "CLK_CLR,Writing ones to this register clears the corresponding bit or bits in the AHBCLKCTRLn register  if they are implemented. Bits that do not correspond to defined bits in AHBCLKCTRLn are reserved and only zeroes should be written to them."
repeat.end
group.long 0x280++0xB
line.long 0x0 "MAINCLKSELA,Main clock source select A"
bitfld.long 0x0 0.--1. "SEL,Clock source for main clock source selector A" "0: FRO 12 MHz (fro_12m),1: CLKIN (clk_in),2: Watchdog oscillator (wdt_clk),3: FRO 96 or 48 MHz (fro_hf)"
line.long 0x4 "MAINCLKSELB,Main clock source select B"
bitfld.long 0x4 0.--1. "SEL,Clock source for main clock source selector B. Selects the clock source for the main clock." "0: MAINCLKSELA. Use the clock source selected in..,?,2: System PLL output (pll_clk),3: RTC oscillator 32 kHz output (32k_clk)"
line.long 0x8 "CLKOUTSELA,CLKOUT clock source select A"
bitfld.long 0x8 0.--2. "SEL,CLKOUT clock source selection" "0: Main clock (main_clk),1: CLKIN (clk_in),2: Watchdog oscillator (wdt_clk),3: FRO 96 or 48 MHz (fro_hf),4: PLL output (pll_clk),5: USB PLL clock (usb_pll_clk),6: Audio PLL clock (audio_pll_clk),7: RTC oscillator 32 kHz output (32k_clk)"
group.long 0x290++0x3
line.long 0x0 "SYSPLLCLKSEL,PLL clock source select"
bitfld.long 0x0 0.--2. "SEL,System PLL clock source selection." "0: FRO 12 MHz (fro_12m),1: CLKIN (clk_in),2: Watchdog oscillator (wdt_clk),3: RTC oscillator 32 kHz output (32k_clk),?,?,?,7: None this may be selected in order to reduce.."
group.long 0x298++0x3
line.long 0x0 "AUDPLLCLKSEL,Audio PLL clock source select"
bitfld.long 0x0 0.--2. "SEL,Audio PLL clock source selection." "0: FRO 12 MHz (fro_12m),1: CLKIN (clk_in),?,?,?,?,?,7: None this may be selected in order to reduce.."
group.long 0x2A0++0xF
line.long 0x0 "SPIFICLKSEL,SPIFI clock source select"
bitfld.long 0x0 0.--2. "SEL,System PLL clock source selection" "0: Main clock (main_clk),1: System PLL output (pll_clk),2: USB PLL clock (usb_pll_clk),3: FRO 96 or 48 MHz (fro_hf),4: Audio PLL clock (audio_pll_clk),?,?,7: None this may be selected in order to reduce.."
line.long 0x4 "ADCCLKSEL,ADC clock source select"
bitfld.long 0x4 0.--2. "SEL,ADC clock source selection" "0: FRO 96 or 48 MHz (fro_hf),1: System PLL output (pll_clk),2: USB PLL clock (usb_pll_clk),3: Audio PLL clock (audio_pll_clk),?,?,?,7: None this may be selected in order to reduce.."
line.long 0x8 "USB0CLKSEL,USB0 clock source select"
bitfld.long 0x8 0.--2. "SEL,USB0 device clock source selection." "0: FRO 96 or 48 MHz (fro_hf),1: System PLL output (pll_clk),2: USB PLL clock (usb_pll_clk),?,?,?,?,7: None this may be selected in order to reduce.."
line.long 0xC "USB1CLKSEL,USB1 clock source select"
bitfld.long 0xC 0.--2. "SEL,USB1 PHY clock source selection." "0: Main clock (main_clk),1: System PLL output (pll_clk),2: USB PLL clock (usb_pll_clk),?,?,?,?,7: None this may be selected in order to reduce.."
endif
sif (cpuis("LPC54606*"))
repeat 10. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2B0)++0x3
line.long 0x0 "FCLKSEL[$1],Flexcomm 0 clock source select"
bitfld.long 0x0 0.--2. "SEL,Flexcomm clock source selection. One per Flexcomm." "0: FRO 12 MHz (fro_12m),1: FRO HF DIV (fro_hf_div),2: Audio PLL clock (audio_pll_clk),3: MCLK pin input when selected in IOCON (mclk_in),4: FRG clock the output of the fractional rate..,?,?,7: None this may be selected in order to reduce.."
repeat.end
group.long 0x2E0++0x3
line.long 0x0 "MCLKCLKSEL,MCLK clock source select"
bitfld.long 0x0 0.--2. "SEL,MCLK source select. This may be used by Flexcomms that support I2S  and/or by the digital microphone subsystem." "0: FRO HF DIV (fro_hf_div),1: Audio PLL clock (audio_pll_clk),?,?,?,?,?,7: None this may be selected in order to reduce.."
group.long 0x2E8++0x13
line.long 0x0 "FRGCLKSEL,Fractional Rate Generator clock source select"
bitfld.long 0x0 0.--2. "SEL,Fractional Rate Generator clock source select." "0: Main clock (main_clk),1: System PLL output (pll_clk),2: FRO 12 MHz (fro_12m),3: FRO 96 or 48 MHz (fro_hf),?,?,?,7: None this may be selected in order to reduce.."
line.long 0x4 "DMICCLKSEL,Digital microphone (DMIC) subsystem clock select"
bitfld.long 0x4 0.--2. "SEL,DMIC (audio subsystem) clock source select." "0: FRO 12 MHz (fro_12m),1: FRO HF DIV (fro_hf_div),2: Audio PLL clock (audio_pll_clk),3: MCLK pin input when selected in IOCON (mclk_in),?,?,?,7: None this may be selected in order to reduce.."
line.long 0x8 "SCTCLKSEL,SCTimer/PWM clock source select"
bitfld.long 0x8 0.--2. "SEL,SCT clock source select." "0: Main clock (main_clk),1: System PLL output (pll_clk),2: FRO 96 or 48 MHz (fro_hf),3: Audio PLL clock (audio_pll_clk),?,?,?,7: None this may be selected in order to reduce.."
line.long 0xC "LCDCLKSEL,LCD clock source select"
bitfld.long 0xC 0.--1. "SEL,LCD clock source select." "0: Main clock (main_clk),1: LCDCLKIN (LCDCLK_EXT),2: FRO 96 or 48 MHz (fro_hf),3: None this may be selected in order to reduce.."
line.long 0x10 "SDIOCLKSEL,SDIO clock source select"
bitfld.long 0x10 0.--2. "SEL,SDIO clock source select." "0: Main clock (main_clk),1: System PLL output (pll_clk),2: USB PLL clock (usb_pll_clk),3: FRO 96 or 48 MHz (fro_hf),4: Audio PLL clock (audio_pll_clk),?,?,7: None this may be selected in order to reduce.."
group.long 0x300++0x17
line.long 0x0 "SYSTICKCLKDIV,SYSTICK clock divider"
bitfld.long 0x0 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x0 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x0 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count." "0,1"
hexmask.long.byte 0x0 0.--7. 1. "DIV,Clock divider value. 0: Divide by 1 up to 255: Divide by 256."
line.long 0x4 "ARMTRACECLKDIV,ARM Trace clock divider"
bitfld.long 0x4 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x4 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x4 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x4 0.--7. 1. "DIV,Clock divider value."
line.long 0x8 "CAN0CLKDIV,MCAN0 clock divider"
bitfld.long 0x8 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x8 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x8 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x8 0.--7. 1. "DIV,Clock divider value."
line.long 0xC "CAN1CLKDIV,MCAN1 clock divider"
bitfld.long 0xC 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0xC 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0xC 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count." "0,1"
hexmask.long.byte 0xC 0.--7. 1. "DIV,Clock divider value. 0: Divide by 1 up to 255: Divide by 256."
line.long 0x10 "SC0CLKDIV,Smartcard0 clock divider"
bitfld.long 0x10 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x10 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x10 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x10 0.--7. 1. "DIV,Clock divider value."
line.long 0x14 "SC1CLKDIV,Smartcard1 clock divider"
bitfld.long 0x14 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x14 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x14 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x14 0.--7. 1. "DIV,Clock divider value."
group.long 0x380++0xB
line.long 0x0 "AHBCLKDIV,AHB clock divider"
bitfld.long 0x0 31. "REQFLAG,Divider status flag." "0,1"
hexmask.long.byte 0x0 0.--7. 1. "DIV,Clock divider value. 0: Divide by 1 up to 255: Divide by 256."
line.long 0x4 "CLKOUTDIV,CLKOUT clock divider"
bitfld.long 0x4 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x4 30. "HALT,Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output." "0,1"
newline
bitfld.long 0x4 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count." "0,1"
hexmask.long.byte 0x4 0.--7. 1. "DIV,Clock divider value. 0: Divide by 1 up to 255: Divide by 256."
line.long 0x8 "FROHFCLKDIV,FROHF clock divider"
bitfld.long 0x8 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x8 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x8 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x8 0.--7. 1. "DIV,Clock divider value."
group.long 0x390++0x13
line.long 0x0 "SPIFICLKDIV,SPIFI clock divider"
bitfld.long 0x0 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x0 30. "HALT,Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output." "0,1"
newline
bitfld.long 0x0 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count." "0,1"
hexmask.long.byte 0x0 0.--7. 1. "DIV,Clock divider value."
line.long 0x4 "ADCCLKDIV,ADC clock divider"
bitfld.long 0x4 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x4 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x4 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x4 0.--7. 1. "DIV,Clock divider value."
line.long 0x8 "USB0CLKDIV,USB0 clock divider"
bitfld.long 0x8 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x8 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x8 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x8 0.--7. 1. "DIV,Clock divider value."
line.long 0xC "USB1CLKDIV,USB1 clock divider"
bitfld.long 0xC 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0xC 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0xC 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0xC 0.--7. 1. "DIV,Clock divider value."
line.long 0x10 "FRGCTRL,Fractional rate divider"
hexmask.long.byte 0x10 8.--15. 1. "MULT,Numerator of the fractional divider. MULT is equal to the programmed value."
hexmask.long.byte 0x10 0.--7. 1. "DIV,Denominator of the fractional divider. DIV is equal to the programmed value +1. Always set to 0xFF to use with the fractional baud rate generator."
group.long 0x3A8++0x17
line.long 0x0 "DMICCLKDIV,DMIC clock divider"
bitfld.long 0x0 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x0 30. "HALT,Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output." "0,1"
newline
bitfld.long 0x0 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count." "0,1"
hexmask.long.byte 0x0 0.--7. 1. "DIV,Clock divider value. 0: Divide by 1 up to 255: Divide by 256."
line.long 0x4 "MCLKDIV,I2S MCLK clock divider"
bitfld.long 0x4 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x4 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x4 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x4 0.--7. 1. "DIV,Clock divider value. 0: Divide by 1 up to 255: Divide by 256."
line.long 0x8 "LCDCLKDIV,LCD clock divider"
bitfld.long 0x8 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x8 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x8 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x8 0.--7. 1. "DIV,Clock divider value."
line.long 0xC "SCTCLKDIV,SCT/PWM clock divider"
bitfld.long 0xC 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0xC 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0xC 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0xC 0.--7. 1. "DIV,Clock divider value."
line.long 0x10 "EMCCLKDIV,EMC clock divider"
bitfld.long 0x10 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x10 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x10 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x10 0.--7. 1. "DIV,Clock divider value."
line.long 0x14 "SDIOCLKDIV,SDIO clock divider"
bitfld.long 0x14 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x14 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x14 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x14 0.--7. 1. "DIV,Clock divider value."
group.long 0x400++0x3
line.long 0x0 "FLASHCFG,Flash wait states configuration"
hexmask.long.byte 0x0 12.--15. 1. "FLASHTIM,Flash memory access time. The number of system clocks used for flash accesses is equal to FLASHTIM +1."
bitfld.long 0x0 6. "PREFOVR,Prefetch override. This bit only applies when PREFEN = 1 and a buffered instruction is completing for which the next flash line is not already buffered or being prefetched." "0: Any previously initiated prefetch will be..,1: Any previously initiated prefetch will be.."
newline
bitfld.long 0x0 5. "PREFEN,Prefetch enable." "0: No instruction prefetch is performed.,1: If the FETCHCFG field is not 0 the next flash.."
bitfld.long 0x0 4. "ACCEL,Acceleration enable." "0: Flash acceleration is disabled. Every flash read..,1: Flash acceleration is enabled. Performance is.."
newline
bitfld.long 0x0 2.--3. "DATACFG,Data read configuration. This field determines how flash accelerator buffers are used for data accesses." "0: Data accesses from flash are not buffered. Every..,1: One buffer is used for all data accesses.,2: All buffers may be used for data accesses.,?"
bitfld.long 0x0 0.--1. "FETCHCFG,Instruction fetch configuration. This field determines how flash accelerator buffers are used for instruction fetches." "0: Instruction fetches from flash are not buffered.,1: One buffer is used for all instruction fetches.,2: All buffers may be used for instruction fetches.,?"
group.long 0x40C++0x7
line.long 0x0 "USB0CLKCTRL,USB0 clock control"
bitfld.long 0x0 4. "PU_DISABLE,Internal pull-up disable control." "0,1"
bitfld.long 0x0 3. "POL_FS_HOST_CLK,USB0 Host USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt." "0,1"
newline
bitfld.long 0x0 2. "AP_FS_HOST_CLK,USB0 Host USB0_NEEDCLK signal control." "0,1"
bitfld.long 0x0 1. "POL_FS_DEV_CLK,USB0 Device USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt." "0,1"
newline
bitfld.long 0x0 0. "AP_FS_DEV_CLK,USB0 Device USB0_NEEDCLK signal control." "0,1"
line.long 0x4 "USB0CLKSTAT,USB0 clock status"
bitfld.long 0x4 1. "HOST_NEED_CLKST,USB0 Host USB0_NEEDCLK signal status." "0,1"
bitfld.long 0x4 0. "DEV_NEED_CLKST,USB0 Device USB0_NEEDCLK signal status." "0,1"
group.long 0x418++0x3
line.long 0x0 "FREQMECTRL,Frequency measure register"
bitfld.long 0x0 31. "PROG,Set this bit to one to initiate a frequency measurement cycle. Hardware clears this bit when the measurement cycle has completed and there is valid capture data in the CAPVAL field (bits 13:0)." "0,1"
hexmask.long.word 0x0 0.--13. 1. "CAPVAL,Stores the capture result which is used to calculate the frequency of the target clock. This field is read-only."
group.long 0x420++0xB
line.long 0x0 "MCLKIO,MCLK input/output control"
bitfld.long 0x0 0. "DIR,MCLK direction control." "0,1"
line.long 0x4 "USB1CLKCTRL,USB1 clock control"
bitfld.long 0x4 4. "HS_DEV_WAKEUP_N,External user wake-up signal for device mode; asserting this signal (active low) will result in exiting the low power mode; input to asynchronous control logic." "0,1"
bitfld.long 0x4 3. "POL_FS_HOST_CLK,USB1 Host need_clock polarity for triggering the USB1 wake-up interrupt." "0,1"
newline
bitfld.long 0x4 2. "AP_FS_HOST_CLK,USB1 Host need_clock signal control." "0,1"
bitfld.long 0x4 1. "POL_FS_DEV_CLK,USB1 Device need_clock polarity for triggering the USB1 wake-up interrupt." "0,1"
newline
bitfld.long 0x4 0. "AP_FS_DEV_CLK,USB1 Device need_clock signal control." "0,1"
line.long 0x8 "USB1CLKSTAT,USB1 clock status"
bitfld.long 0x8 1. "HOST_NEED_CLKST,USB1 Device host USB1_NEEDCLK signal status." "0,1"
bitfld.long 0x8 0. "DEV_NEED_CLKST,USB1 Device USB1_NEEDCLK signal status." "0,1"
group.long 0x444++0x13
line.long 0x0 "EMCSYSCTRL,EMC system control"
bitfld.long 0x0 3. "EMCFBCLKINSEL,External Memory Controller clock select." "0,1"
bitfld.long 0x0 2. "EMCBC,External Memory Controller burst control." "0,1"
newline
bitfld.long 0x0 1. "EMCRD,EMC Reset Disable." "0,1"
bitfld.long 0x0 0. "EMCSC,EMC Shift Control." "0,1"
line.long 0x4 "EMCDLYCTRL,EMC clock delay control"
hexmask.long.byte 0x4 8.--12. 1. "FBCLK_DELAY,Programmable delay value for the feedback clock that controls input data sampling."
hexmask.long.byte 0x4 0.--4. 1. "CMD_DELAY,Programmable delay value for EMC outputs in command delayed mode."
line.long 0x8 "EMCDLYCAL,EMC delay chain calibration control"
bitfld.long 0x8 15. "DONE,Measurement completion flag." "0,1"
bitfld.long 0x8 14. "START,Start control bit for the EMC calibration counter." "0,1"
newline
hexmask.long.byte 0x8 0.--7. 1. "CALVALUE,Returns the count of the approximately 50 MHz ring oscillator that occur during 32 clocks of the FRO 12 MHz."
line.long 0xC "ETHPHYSEL,Ethernet PHY Selection"
bitfld.long 0xC 2. "PHY_SEL,PHY interface select." "0,1"
line.long 0x10 "ETHSBDCTRL,Ethernet SBD flow control"
bitfld.long 0x10 0.--1. "SBD_CTRL,Sideband Flow Control." "0,1,2,3"
group.long 0x460++0x3
line.long 0x0 "SDIOCLKCTRL,SDIO CCLKIN phase and delay control"
bitfld.long 0x0 31. "CCLK_SAMPLE_DELAY_ACTIVE,Enables sample delay  as controlled by the CCLK_SAMPLE_DELAY field." "0,1"
hexmask.long.byte 0x0 24.--28. 1. "CCLK_SAMPLE_DELAY,Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in."
newline
bitfld.long 0x0 23. "CCLK_DRV_DELAY_ACTIVE,Enables drive delay  as controlled by the CCLK_DRV_DELAY field." "0,1"
hexmask.long.byte 0x0 16.--20. 1. "CCLK_DRV_DELAY,Programmable delay value by which cclk_in_drv is delayed with regard to cclk_in."
newline
bitfld.long 0x0 7. "PHASE_ACTIVE,sdio_clk by 2  before feeding into ccl_in  cclk_in_sample  and cclk_in_drv." "0,1"
bitfld.long 0x0 2.--3. "CCLK_SAMPLE_PHASE,Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in." "0,1,2,3"
newline
bitfld.long 0x0 0.--1. "CCLK_DRV_PHASE,Programmable delay value by which cclk_in_drv is phase-shifted with regard to cclk_in." "0,1,2,3"
group.long 0x500++0xF
line.long 0x0 "FROCTRL,FRO oscillator control"
bitfld.long 0x0 31. "WRTRIM,Write Trim value." "0,1"
bitfld.long 0x0 30. "HSPDCLK,High speed clock enable." "0,1"
newline
bitfld.long 0x0 25. "USBMODCHG,USB Mode value Change flag." "0,1"
bitfld.long 0x0 24. "USBCLKADJ,USB clock adjust mode." "0,1"
newline
hexmask.long.byte 0x0 16.--23. 1. "FREQTRIM,Frequency trim."
bitfld.long 0x0 14. "SEL,Select the FRO HF output frequency." "0,1"
newline
hexmask.long.word 0x0 0.--13. 1. "TRIM,This value is factory trimmed to account for bias and temperature compensation."
line.long 0x4 "SYSOSCCTRL,System oscillator control"
bitfld.long 0x4 1. "FREQRANGE,Determines frequency range for system oscillator." "0,1"
bitfld.long 0x4 0. "BYPASS,Bypass system oscillator." "0,1"
line.long 0x8 "WDTOSCCTRL,Watchdog oscillator control"
hexmask.long.byte 0x8 5.--9. 1. "FREQSEL,Frequency select."
hexmask.long.byte 0x8 0.--4. 1. "DIVSEL,Divider select."
line.long 0xC "RTCOSCCTRL,RTC oscillator 32 kHz output control"
bitfld.long 0xC 0. "EN,RTC 32 kHz clock enable." "0,1"
group.long 0x51C++0x7
line.long 0x0 "USBPLLCTRL,USB PLL control"
bitfld.long 0x0 14. "FBSEL,Feedback divider input clock control." "0,1"
bitfld.long 0x0 13. "BYPASS,Input clock bypass control." "0: CCO clock is sent to post dividers..,1: PLL input clock is sent to post dividers.."
newline
bitfld.long 0x0 12. "DIRECT,Direct CCO clock output control." "0: CCO Clock signal goes through post divider.,1: CCO Clock signal goes directly to output(s).."
bitfld.long 0x0 10.--11. "NSEL,PLL feedback Divider value." "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "PSEL,PLL Divider value." "0,1,2,3"
hexmask.long.byte 0x0 0.--7. 1. "MSEL,PLL feedback Divider value."
line.long 0x4 "USBPLLSTAT,USB PLL status"
bitfld.long 0x4 0. "LOCK,USBPLL lock indicator." "0,1"
group.long 0x580++0x13
line.long 0x0 "SYSPLLCTRL,System PLL control"
bitfld.long 0x0 20. "DIRECTO,PLL0 direct output enable." "0: Disabled. The PLL output divider (P divider) is..,1: Enabled. The PLL output divider (P divider) is.."
bitfld.long 0x0 19. "DIRECTI,PLL0 direct input enable." "0,1"
newline
bitfld.long 0x0 17. "UPLIMOFF,Disable upper frequency limiter." "0,1"
bitfld.long 0x0 15. "BYPASS,PLL bypass control." "0: Bypass disabled. PLL CCO is sent to the PLL..,1: Bypass enabled. PLL input clock is sent directly.."
newline
hexmask.long.byte 0x0 10.--14. 1. "SELP,Bandwidth select P value."
hexmask.long.byte 0x0 4.--9. 1. "SELI,Bandwidth select I value."
newline
hexmask.long.byte 0x0 0.--3. 1. "SELR,Bandwidth select R value."
line.long 0x4 "SYSPLLSTAT,PLL status"
bitfld.long 0x4 0. "LOCK,PLL lock indicator." "0,1"
line.long 0x8 "SYSPLLNDEC,PLL N divider"
bitfld.long 0x8 10. "NREQ,NDEC reload request." "0,1"
hexmask.long.word 0x8 0.--9. 1. "NDEC,Decoded N-divider coefficient value."
line.long 0xC "SYSPLLPDEC,PLL P divider"
bitfld.long 0xC 7. "PREQ,." "0,1"
hexmask.long.byte 0xC 0.--6. 1. "PDEC,Decoded P-divider coefficient value."
line.long 0x10 "SYSPLLMDEC,System PLL M divider"
bitfld.long 0x10 17. "MREQ,MDEC reload request." "0,1"
hexmask.long.tbyte 0x10 0.--16. 1. "MDEC,Decoded M-divider coefficient value."
group.long 0x5A0++0x17
line.long 0x0 "AUDPLLCTRL,Audio PLL control"
bitfld.long 0x0 20. "DIRECTO,PLL direct output enable" "0: Disabled. The PLL output divider (P divider) is..,1: Enabled. The PLL output divider (P divider) is.."
bitfld.long 0x0 19. "DIRECTI,PLL direct input enable." "0,1"
newline
bitfld.long 0x0 17. "UPLIMOFF,Disable upper frequency limiter." "0,1"
bitfld.long 0x0 15. "BYPASS,PLL bypass control." "0: Bypass disabled. PLL CCO is sent to the PLL..,1: Bypass enabled. PLL input clock is sent directly.."
newline
hexmask.long.byte 0x0 10.--14. 1. "SELP,."
hexmask.long.byte 0x0 4.--9. 1. "SELI,Bandwidth select I value."
newline
hexmask.long.byte 0x0 0.--3. 1. "SELR,Bandwidth select R value."
line.long 0x4 "AUDPLLSTAT,Audio PLL status"
bitfld.long 0x4 0. "LOCK,PLL lock indicator." "0,1"
line.long 0x8 "AUDPLLNDEC,Audio PLL N divider"
bitfld.long 0x8 10. "NREQ,NDEC reload request." "0,1"
hexmask.long.word 0x8 0.--9. 1. "NDEC,Decoded N-divider coefficient value."
line.long 0xC "AUDPLLPDEC,Audio PLL P divider"
bitfld.long 0xC 7. "PREQ,PDEC reload request." "0,1"
hexmask.long.byte 0xC 0.--6. 1. "PDEC,Decoded P-divider coefficient value."
line.long 0x10 "AUDPLLMDEC,Audio PLL M divider"
bitfld.long 0x10 17. "MREQ,MDEC reload request." "0,1"
hexmask.long.tbyte 0x10 0.--16. 1. "MDEC,Decoded M-divider coefficient value."
line.long 0x14 "AUDPLLFRAC,Audio PLL fractional divider control"
bitfld.long 0x14 23. "SEL_EXT,Select fractional divider." "0,1"
bitfld.long 0x14 22. "REQ,Writing 1 to REQ signal loads CTRL value into fractional wrapper modulator." "0,1"
newline
hexmask.long.tbyte 0x14 0.--21. 1. "CTRL,PLL fractional divider control word"
group.long 0x600++0x7
line.long 0x0 "PDSLEEPCFG0,Sleep configuration register"
bitfld.long 0x0 29. "PDEN_VD6,Power control for EEPROM." "0,1"
bitfld.long 0x0 28. "PDEN_VD5,Power control both USB0 PHY and USB1 PHY." "0,1"
newline
bitfld.long 0x0 27. "PDEN_VD4,Power control for all SRAMs and ROM." "0,1"
bitfld.long 0x0 26. "PDEN_VD3,Power control for all PLLs." "0,1"
newline
bitfld.long 0x0 23. "PDEN_VREFP,VREFP to the ADC must be enabled for the ADC to work (also enable/disable bit 9  10  and 19)." "0,1"
bitfld.long 0x0 22. "PDEN_SYS_PLL,System PLL (PLL0) power (also enable/disable bit 26)." "0,1"
newline
bitfld.long 0x0 21. "PDEN_USB0_PHY,USB0 PHY power (also enable/disable bit 28)." "0,1"
bitfld.long 0x0 20. "PDEN_WDT_OSC,Watchdog oscillator." "0,1"
newline
bitfld.long 0x0 19. "PDEN_VDDA,Vdda to the ADC  must be enabled for the ADC to work (also enable/disable bit 9  10  and 23)." "0,1"
bitfld.long 0x0 17. "PDEN_ROM,ROM (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 16. "PDEN_USB_RAM,PDEN_USB_SRAM controls USB_RAM (also enable/disable bit 27)." "0,1"
bitfld.long 0x0 15. "PDEN_SRAM1_2_3,PDEN_SRAM1_2_3 controls SRAM1  SRAM2  and SRAM3 (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 14. "PDEN_SRAM0,PDEN_SRAM0 controls SRAM0 (also enable/disable bit 27)." "0,1"
bitfld.long 0x0 13. "PDEN_SRAMX,PDEN_SRAMX controls SRAMX (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 10. "PDEN_ADC0,ADC power." "0,1"
bitfld.long 0x0 9. "PDEN_VD2_ANA,Analog supply for System Oscillator (also enable/disable bit 3 in PDRUNCFG1 register)  Temperature Sensor (also  enable/disable bit 6)  ADC (also  enable/disable bits 10  19  and 23)." "0,1"
newline
bitfld.long 0x0 8. "PDEN_BOD_INTR,Brown-out Detect interrupt." "0,1"
bitfld.long 0x0 7. "PDEN_BOD_RST,Brown-out Detect reset." "0,1"
newline
bitfld.long 0x0 6. "PDEN_TS,Temp sensor." "0,1"
bitfld.long 0x0 4. "PDEN_FRO,FRO oscillator." "0,1"
line.long 0x4 "PDSLEEPCFG1,Sleep configuration register"
bitfld.long 0x4 7. "PDEN_RNG,Random Number Generator Power." "0,1"
bitfld.long 0x4 5. "PDEN_EEPROM,EEPROM power (also  enable/disable bit 29 in PDRUNCFG0 register)." "0,1"
newline
bitfld.long 0x4 3. "PDEN_SYSOSC,System Oscillator Power (also  enable/disable bit 9 in PDRUNCFG0 register)." "0,1"
bitfld.long 0x4 2. "PDEN_AUD_PLL,Audio PLL (PLL2) power and fractional divider (also  enable/disable bit 26 in PDRUNCFG0 register)." "0,1"
newline
bitfld.long 0x4 1. "PDEN_USB1_PLL,USB PLL (PLL1) power (also  enable/disable bit 26 in PDRUNCFG0 register)." "0,1"
bitfld.long 0x4 0. "PDEN_USB1_PHY,USB1 high speed PHY (also  enable/disable bit 28 in PDRUNCFG0 register)." "0,1"
group.long 0x610++0x7
line.long 0x0 "PDRUNCFG0,Power configuration register"
bitfld.long 0x0 29. "PDEN_VD6,Power control for EEPROM." "0,1"
bitfld.long 0x0 28. "PDEN_VD5,Power control both USB0 PHY and USB1 PHY." "0,1"
newline
bitfld.long 0x0 27. "PDEN_VD4,Power control for all SRAMs and ROM." "0,1"
bitfld.long 0x0 26. "PDEN_VD3,Power control for all PLLs." "0,1"
newline
bitfld.long 0x0 23. "PDEN_VREFP,VREFP to the ADC must be enabled for the ADC to work (also enable/disable bit 9  10  and 19)." "0,1"
bitfld.long 0x0 22. "PDEN_SYS_PLL,System PLL (PLL0) power (also enable/disable bit 26)." "0,1"
newline
bitfld.long 0x0 21. "PDEN_USB0_PHY,USB0 PHY power (also enable/disable bit 28)." "0,1"
bitfld.long 0x0 20. "PDEN_WDT_OSC,Watchdog oscillator." "0,1"
newline
bitfld.long 0x0 19. "PDEN_VDDA,Vdda to the ADC  must be enabled for the ADC to work (also enable/disable bit 9  10  and 23)." "0,1"
bitfld.long 0x0 17. "PDEN_ROM,ROM (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 16. "PDEN_USB_RAM,PDEN_USB_SRAM controls USB_RAM (also enable/disable bit 27)." "0,1"
bitfld.long 0x0 15. "PDEN_SRAM1_2_3,PDEN_SRAM1_2_3 controls SRAM1  SRAM2  and SRAM3 (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 14. "PDEN_SRAM0,PDEN_SRAM0 controls SRAM0 (also enable/disable bit 27)." "0,1"
bitfld.long 0x0 13. "PDEN_SRAMX,PDEN_SRAMX controls SRAMX (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 10. "PDEN_ADC0,ADC power." "0,1"
bitfld.long 0x0 9. "PDEN_VD2_ANA,Analog supply for System Oscillator (also enable/disable bit 3 in PDRUNCFG1 register)  Temperature Sensor (also  enable/disable bit 6)  ADC (also  enable/disable bits 10  19  and 23)." "0,1"
newline
bitfld.long 0x0 8. "PDEN_BOD_INTR,Brown-out Detect interrupt." "0,1"
bitfld.long 0x0 7. "PDEN_BOD_RST,Brown-out Detect reset." "0,1"
newline
bitfld.long 0x0 6. "PDEN_TS,Temp sensor." "0,1"
bitfld.long 0x0 4. "PDEN_FRO,FRO oscillator." "0,1"
line.long 0x4 "PDRUNCFG1,Power configuration register"
bitfld.long 0x4 7. "PDEN_RNG,Random Number Generator Power." "0,1"
bitfld.long 0x4 5. "PDEN_EEPROM,EEPROM power (also  enable/disable bit 29 in PDRUNCFG0 register)." "0,1"
newline
bitfld.long 0x4 3. "PDEN_SYSOSC,System Oscillator Power (also  enable/disable bit 9 in PDRUNCFG0 register)." "0,1"
bitfld.long 0x4 2. "PDEN_AUD_PLL,Audio PLL (PLL2) power and fractional divider (also  enable/disable bit 26 in PDRUNCFG0 register)." "0,1"
newline
bitfld.long 0x4 1. "PDEN_USB1_PLL,USB PLL (PLL1) power (also  enable/disable bit 26 in PDRUNCFG0 register)." "0,1"
bitfld.long 0x4 0. "PDEN_USB1_PHY,USB1 high speed PHY (also  enable/disable bit 28 in PDRUNCFG0 register)." "0,1"
group.long 0x620++0x7
line.long 0x0 "PDRUNCFGSET0,Power configuration set register"
bitfld.long 0x0 29. "PDEN_VD6,Power control for EEPROM." "0,1"
bitfld.long 0x0 28. "PDEN_VD5,Power control both USB0 PHY and USB1 PHY." "0,1"
newline
bitfld.long 0x0 27. "PDEN_VD4,Power control for all SRAMs and ROM." "0,1"
bitfld.long 0x0 26. "PDEN_VD3,Power control for all PLLs." "0,1"
newline
bitfld.long 0x0 23. "PDEN_VREFP,VREFP to the ADC must be enabled for the ADC to work (also enable/disable bit 9  10  and 19)." "0,1"
bitfld.long 0x0 22. "PDEN_SYS_PLL,System PLL (PLL0) power (also enable/disable bit 26)." "0,1"
newline
bitfld.long 0x0 21. "PDEN_USB0_PHY,USB0 PHY power (also enable/disable bit 28)." "0,1"
bitfld.long 0x0 20. "PDEN_WDT_OSC,Watchdog oscillator." "0,1"
newline
bitfld.long 0x0 19. "PDEN_VDDA,Vdda to the ADC  must be enabled for the ADC to work (also enable/disable bit 9  10  and 23)." "0,1"
bitfld.long 0x0 17. "PDEN_ROM,ROM (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 16. "PDEN_USB_RAM,PDEN_USB_SRAM controls USB_RAM (also enable/disable bit 27)." "0,1"
bitfld.long 0x0 15. "PDEN_SRAM1_2_3,PDEN_SRAM1_2_3 controls SRAM1  SRAM2  and SRAM3 (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 14. "PDEN_SRAM0,PDEN_SRAM0 controls SRAM0 (also enable/disable bit 27)." "0,1"
bitfld.long 0x0 13. "PDEN_SRAMX,PDEN_SRAMX controls SRAMX (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 10. "PDEN_ADC0,ADC power." "0,1"
bitfld.long 0x0 9. "PDEN_VD2_ANA,Analog supply for System Oscillator (also enable/disable bit 3 in PDRUNCFG1 register)  Temperature Sensor (also  enable/disable bit 6)  ADC (also  enable/disable bits 10  19  and 23)." "0,1"
newline
bitfld.long 0x0 8. "PDEN_BOD_INTR,Brown-out Detect interrupt." "0,1"
bitfld.long 0x0 7. "PDEN_BOD_RST,Brown-out Detect reset." "0,1"
newline
bitfld.long 0x0 6. "PDEN_TS,Temp sensor." "0,1"
bitfld.long 0x0 4. "PDEN_FRO,FRO oscillator." "0,1"
line.long 0x4 "PDRUNCFGSET1,Power configuration set register"
bitfld.long 0x4 7. "PDEN_RNG,Random Number Generator Power." "0,1"
bitfld.long 0x4 5. "PDEN_EEPROM,EEPROM power (also  enable/disable bit 29 in PDRUNCFG0 register)." "0,1"
newline
bitfld.long 0x4 3. "PDEN_SYSOSC,System Oscillator Power (also  enable/disable bit 9 in PDRUNCFG0 register)." "0,1"
bitfld.long 0x4 2. "PDEN_AUD_PLL,Audio PLL (PLL2) power and fractional divider (also  enable/disable bit 26 in PDRUNCFG0 register)." "0,1"
newline
bitfld.long 0x4 1. "PDEN_USB1_PLL,USB PLL (PLL1) power (also  enable/disable bit 26 in PDRUNCFG0 register)." "0,1"
bitfld.long 0x4 0. "PDEN_USB1_PHY,USB1 high speed PHY (also  enable/disable bit 28 in PDRUNCFG0 register)." "0,1"
group.long 0x630++0x7
line.long 0x0 "PDRUNCFGCLR0,Power configuration clear register"
bitfld.long 0x0 29. "PDEN_VD6,Power control for EEPROM." "0,1"
bitfld.long 0x0 28. "PDEN_VD5,Power control both USB0 PHY and USB1 PHY." "0,1"
newline
bitfld.long 0x0 27. "PDEN_VD4,Power control for all SRAMs and ROM." "0,1"
bitfld.long 0x0 26. "PDEN_VD3,Power control for all PLLs." "0,1"
newline
bitfld.long 0x0 23. "PDEN_VREFP,VREFP to the ADC must be enabled for the ADC to work (also enable/disable bit 9  10  and 19)." "0,1"
bitfld.long 0x0 22. "PDEN_SYS_PLL,System PLL (PLL0) power (also enable/disable bit 26)." "0,1"
newline
bitfld.long 0x0 21. "PDEN_USB0_PHY,USB0 PHY power (also enable/disable bit 28)." "0,1"
bitfld.long 0x0 20. "PDEN_WDT_OSC,Watchdog oscillator." "0,1"
newline
bitfld.long 0x0 19. "PDEN_VDDA,Vdda to the ADC  must be enabled for the ADC to work (also enable/disable bit 9  10  and 23)." "0,1"
bitfld.long 0x0 17. "PDEN_ROM,ROM (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 16. "PDEN_USB_RAM,PDEN_USB_SRAM controls USB_RAM (also enable/disable bit 27)." "0,1"
bitfld.long 0x0 15. "PDEN_SRAM1_2_3,PDEN_SRAM1_2_3 controls SRAM1  SRAM2  and SRAM3 (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 14. "PDEN_SRAM0,PDEN_SRAM0 controls SRAM0 (also enable/disable bit 27)." "0,1"
bitfld.long 0x0 13. "PDEN_SRAMX,PDEN_SRAMX controls SRAMX (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 10. "PDEN_ADC0,ADC power." "0,1"
bitfld.long 0x0 9. "PDEN_VD2_ANA,Analog supply for System Oscillator (also enable/disable bit 3 in PDRUNCFG1 register)  Temperature Sensor (also  enable/disable bit 6)  ADC (also  enable/disable bits 10  19  and 23)." "0,1"
newline
bitfld.long 0x0 8. "PDEN_BOD_INTR,Brown-out Detect interrupt." "0,1"
bitfld.long 0x0 7. "PDEN_BOD_RST,Brown-out Detect reset." "0,1"
newline
bitfld.long 0x0 6. "PDEN_TS,Temp sensor." "0,1"
bitfld.long 0x0 4. "PDEN_FRO,FRO oscillator." "0,1"
line.long 0x4 "PDRUNCFGCLR1,Power configuration clear register"
bitfld.long 0x4 7. "PDEN_RNG,Random Number Generator Power." "0,1"
bitfld.long 0x4 5. "PDEN_EEPROM,EEPROM power (also  enable/disable bit 29 in PDRUNCFG0 register)." "0,1"
newline
bitfld.long 0x4 3. "PDEN_SYSOSC,System Oscillator Power (also  enable/disable bit 9 in PDRUNCFG0 register)." "0,1"
bitfld.long 0x4 2. "PDEN_AUD_PLL,Audio PLL (PLL2) power and fractional divider (also  enable/disable bit 26 in PDRUNCFG0 register)." "0,1"
newline
bitfld.long 0x4 1. "PDEN_USB1_PLL,USB PLL (PLL1) power (also  enable/disable bit 26 in PDRUNCFG0 register)." "0,1"
bitfld.long 0x4 0. "PDEN_USB1_PHY,USB1 high speed PHY (also  enable/disable bit 28 in PDRUNCFG0 register)." "0,1"
group.long 0x680++0x7
line.long 0x0 "STARTER0,Start logic 0 wake-up enable register"
bitfld.long 0x0 29. "RTC,RTC interrupt alarm and wake-up timer." "0,1"
bitfld.long 0x0 28. "USB0,USB function interrupt wake-up." "0,1"
newline
bitfld.long 0x0 27. "USB0_NEEDCLK,USB activity interrupt wake-up." "0,1"
bitfld.long 0x0 26. "HWVAD,Hardware voice activity detect interrupt wake-up." "0,1"
newline
bitfld.long 0x0 25. "DMIC,Digital microphone interrupt wake-up." "0,1"
bitfld.long 0x0 24. "ADC0_THCMP,ADC0 threshold and error interrupt wake-up." "0,1"
newline
bitfld.long 0x0 23. "ADC0_SEQB,ADC0 sequence B interrupt wake-up." "0,1"
bitfld.long 0x0 22. "ADC0_SEQA,ADC0 sequence A interrupt wake-up." "0,1"
newline
bitfld.long 0x0 21. "FLEXCOMM7,Flexcomm7 peripheral interrupt wake-up." "0,1"
bitfld.long 0x0 20. "FLEXCOMM6,Flexcomm6 peripheral interrupt wake-up." "0,1"
newline
bitfld.long 0x0 19. "FLEXCOMM5,Flexcomm5 peripheral interrupt wake-up." "0,1"
bitfld.long 0x0 18. "FLEXCOMM4,Flexcomm4 peripheral interrupt wake-up." "0,1"
newline
bitfld.long 0x0 17. "FLEXCOMM3,Flexcomm3 peripheral interrupt wake-up." "0,1"
bitfld.long 0x0 16. "FLEXCOMM2,Flexcomm2 peripheral interrupt wake-up." "0,1"
newline
bitfld.long 0x0 15. "FLEXCOMM1,Flexcomm1 peripheral interrupt wake-up." "0,1"
bitfld.long 0x0 14. "FLEXCOMM0,Flexcomm0 peripheral interrupt wake-up." "0,1"
newline
bitfld.long 0x0 13. "CTIMER3,Standard counter/timer CTIMER3 wake-up." "0,1"
bitfld.long 0x0 12. "SCT0,SCT0 wake-up." "0,1"
newline
bitfld.long 0x0 11. "CTIMER1,Standard counter/timer CTIMER1 wake-up." "0,1"
bitfld.long 0x0 10. "CTIMER0,Standard counter/timer CTIMER0 wake-up." "0,1"
newline
bitfld.long 0x0 9. "MRT,Multi-Rate Timer wake-up." "0,1"
bitfld.long 0x0 8. "UTICK,Micro-tick Timer wake-up." "0,1"
newline
bitfld.long 0x0 7. "PIN_INT3,GPIO pin interrupt 3 wake-up." "0,1"
bitfld.long 0x0 6. "PIN_INT2,GPIO pin interrupt 2 wake-up." "0,1"
newline
bitfld.long 0x0 5. "PIN_INT1,GPIO pin interrupt 1 wake-up." "0,1"
bitfld.long 0x0 4. "PIN_INT0,GPIO pin interrupt 0 wake-up." "0,1"
newline
bitfld.long 0x0 3. "GINT1,Group interrupt 1 wake-up." "0,1"
bitfld.long 0x0 2. "GINT0,Group interrupt 0 wake-up." "0,1"
newline
bitfld.long 0x0 1. "DMA,DMA wake-up." "0,1"
bitfld.long 0x0 0. "WDT_BOD,WWDT and BOD interrupt wake-up." "0,1"
line.long 0x4 "STARTER1,Start logic 0 wake-up enable register"
bitfld.long 0x4 24. "SMARTCARD1,Smart card 1 wake-up." "0,1"
bitfld.long 0x4 23. "SMARTCARD0,Smart card 0 wake-up." "0,1"
newline
bitfld.long 0x4 19. "ENET_INT0,Ethernet." "0,1"
bitfld.long 0x4 18. "ENET_INT2,Ethernet." "0,1"
newline
bitfld.long 0x4 17. "ENET_INT1,Ethernet." "0,1"
bitfld.long 0x4 16. "USB1_ACT,USB 1 activity wake-up." "0,1"
newline
bitfld.long 0x4 15. "USB1,USB 1 wake-up." "0,1"
bitfld.long 0x4 9. "FLEXCOMM9,Flexcomm Interface 9 wake-up." "0,1"
newline
bitfld.long 0x4 8. "FLEXCOMM8,Flexcomm Interface 8 wake-up." "0,1"
bitfld.long 0x4 7. "SPIFI,SPIFI interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled." "0: Wake-up disabled,1: Wake-up enabled"
newline
bitfld.long 0x4 5. "CTIMER4,Standard counter/timer CTIMER4 wake-up." "0,1"
bitfld.long 0x4 4. "CTIMER2,Standard counter/timer CTIMER2 wake-up." "0,1"
newline
bitfld.long 0x4 3. "PINT7,GPIO pin interrupt 7 wake-up." "0,1"
bitfld.long 0x4 2. "PINT6,GPIO pin interrupt 6 wake-up." "0,1"
newline
bitfld.long 0x4 1. "PINT5,GPIO pin interrupt 5 wake-up." "0,1"
bitfld.long 0x4 0. "PINT4,GPIO pin interrupt 4 wake-up." "0,1"
group.long 0x780++0x3
line.long 0x0 "HWWAKE,Configures special cases of hardware wake-up"
bitfld.long 0x0 3. "WAKEDMA,Wake for DMA. When 1  DMA being busy will cause peripheral clocking to remain running until DMA completes. This is generally used in conjunction with bit 1 and/or 2 in order to prevent peripheral clocking from being shut down as soon as the cause.." "0,1"
bitfld.long 0x0 2. "WAKEDMIC,Wake for Digital Microphone. When 1  the digital microphone input FIFO reaching the level specified by TRIGLVL of either channel will cause peripheral clocking to wake up temporarily while the related status is asserted." "0,1"
newline
bitfld.long 0x0 1. "FCWAKE,Wake for Flexcomms. When 1  any Flexcomm FIFO reaching the level specified by its own TXLVL will cause peripheral clocking to wake up temporarily while the related status is asserted." "0,1"
bitfld.long 0x0 0. "FORCEWAKE,Force peripheral clocking to stay on during Deep Sleep and Power-down modes. When 1  clocking to peripherals is prevented from being shut down when the CPU enters Deep Sleep and Power-down modes. This is intended to allow a coprocessor to.." "0,1"
group.long 0xE04++0x3
line.long 0x0 "AUTOCGOR,Auto Clock-Gate Override Register"
bitfld.long 0x0 4. "RAM3,When 1  automatic clock gating for RAM1 are turned off." "0,1"
bitfld.long 0x0 3. "RAM2,When 1  automatic clock gating for RAM1 are turned off." "0,1"
newline
bitfld.long 0x0 2. "RAM1,When 1  automatic clock gating for RAM1 are turned off." "0,1"
bitfld.long 0x0 1. "RAM0X,When 1  automatic clock gating for RAMX and RAM0 are turned off." "0,1"
rgroup.long 0xFF4++0xB
line.long 0x0 "JTAGIDCODE,JTAG ID code register"
hexmask.long 0x0 0.--31. 1. "JTAGID,JTAG ID code."
line.long 0x4 "DEVICE_ID0,Part ID register"
hexmask.long 0x4 0.--31. 1. "PARTID,Part ID"
line.long 0x8 "DEVICE_ID1,Boot ROM and die revision register"
hexmask.long 0x8 0.--31. 1. "REVID,Revision."
group.long 0x20044++0x3
line.long 0x0 "BODCTRL,Brown-Out Detect control"
bitfld.long 0x0 7. "BODINTSTAT,BOD interrupt status. When 1  a BOD interrupt has occurred. Cleared by writing 1 to this bit." "0,1"
bitfld.long 0x0 6. "BODRSTSTAT,BOD reset status. When 1  a BOD reset has occurred. Cleared by writing 1 to this bit." "0,1"
newline
bitfld.long 0x0 5. "BODINTENA,BOD interrupt enable" "0: Disable interrupt function.,1: Enable interrupt function."
bitfld.long 0x0 3.--4. "BODINTLEV,BOD interrupt level" "0: Level 0: 2.05 V,1: Level 1: 2.45 V,2: Level 2: 2.75 V,3: Level 3: 3.05 V"
newline
bitfld.long 0x0 2. "BODRSTENA,BOD reset enable" "0: Disable reset function.,1: Enable reset function."
bitfld.long 0x0 0.--1. "BODRSTLEV,BOD reset level" "0: Level 0: 1.5 V,1: Level 1: 1.85 V,2: Level 2: 2.0 V,3: Level 3: 2.3 V"
endif
sif (cpuis("LPC54607*"))
group.long 0x10++0x3
line.long 0x0 "AHBMATPRIO,AHB multilayer matrix priority control"
bitfld.long 0x0 24.--25. "PRI_SHA,SHA priority." "0,1,2,3"
bitfld.long 0x0 22.--23. "PRI_MCAN2,MCAN2 priority." "0,1,2,3"
newline
bitfld.long 0x0 20.--21. "PRI_MCAN1,MCAN1 priority." "0,1,2,3"
bitfld.long 0x0 18.--19. "PRI_SDIO,SDIO priority." "0,1,2,3"
newline
bitfld.long 0x0 16.--17. "PRI_USB1,USB1 DMA priority." "0,1,2,3"
bitfld.long 0x0 14.--15. "PRI_USB0,USB0 DMA priority." "0,1,2,3"
newline
bitfld.long 0x0 12.--13. "PRI_LCD,LCD DMA priority." "0,1,2,3"
bitfld.long 0x0 10.--11. "PRI_ETH,Ethernet DMA priority." "0,1,2,3"
newline
hexmask.long.byte 0x0 6.--9. 1. "PRI_DMA,DMA controller priority."
bitfld.long 0x0 4.--5. "PRI_SYS,System bus priority." "0,1,2,3"
newline
bitfld.long 0x0 2.--3. "PRI_DCODE,D-Code bus priority." "0,1,2,3"
bitfld.long 0x0 0.--1. "PRI_ICODE,I-Code bus priority." "0,1,2,3"
group.long 0x40++0x3
line.long 0x0 "SYSTCKCAL,System tick counter calibration"
bitfld.long 0x0 25. "NOREF,Initial value for the Systick timer." "0,1"
bitfld.long 0x0 24. "SKEW,Initial value for the Systick timer." "0,1"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "CAL,System tick timer calibration value."
group.long 0x48++0x7
line.long 0x0 "NMISRC,NMI Source Select"
bitfld.long 0x0 31. "NMIENM4,Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQM4." "0,1"
hexmask.long.byte 0x0 0.--5. 1. "IRQM4,The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the Cortex-M4  if enabled by NMIENM4."
line.long 0x4 "ASYNCAPBCTRL,Asynchronous APB Control"
bitfld.long 0x4 0. "ENABLE,Enables the asynchronous APB bridge and subsystem." "0: Disabled. Asynchronous APB bridge is disabled.,1: Enabled. Asynchronous APB bridge is enabled."
endif
sif (cpuis("LPC54607*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0xC0)++0x3
line.long 0x0 "PIOPORCAP[$1],POR captured value of port n"
hexmask.long 0x0 0.--31. 1. "PIOPORCAP,State of PIOn_31 through PIOn_0 at power-on reset"
repeat.end
endif
sif (cpuis("LPC54607*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0xD0)++0x3
line.long 0x0 "PIORESCAP[$1],Reset captured value of port n"
hexmask.long 0x0 0.--31. 1. "PIORESCAP,State of PIOn_31 through PIOn_0 for resets other than POR."
repeat.end
group.long 0x100++0xB
line.long 0x0 "PRESETCTRL0,Peripheral reset control n"
bitfld.long 0x0 27. "ADC0_RST,ADC0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 22. "WWDT_RST,Watchdog timer reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x0 21. "CRC_RST,CRC generator reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 20. "DMA0_RST,DMA0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x0 19. "GINT_RST,Grouped interrupt (GINT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 18. "PINT_RST,Pin interrupt (PINT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x0 17. "GPIO3_RST,GPIO3 reset control." "0,1"
bitfld.long 0x0 16. "GPIO2_RST,GPIO2 reset control." "0,1"
newline
bitfld.long 0x0 15. "GPIO1_RST,GPIO1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 14. "GPIO0_RST,GPIO0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x0 13. "IOCON_RST,IOCON reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 11. "MUX_RST,Input mux reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x0 10. "SPIFI_RST,SPIFI reset control." "0,1"
bitfld.long 0x0 9. "EEPROM_RST,EEPROM reset control." "0,1"
newline
bitfld.long 0x0 8. "FMC_RST,Flash accelerator reset control. Note that the FMC must not be reset while executing from flash  and must be reconfigured after reset. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 7. "FLASH_RST,Flash controller reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
line.long 0x4 "PRESETCTRL1,Peripheral reset control n"
bitfld.long 0x4 27. "CTIMER1_RST,CTIMER1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 26. "CTIMER0_RST,CTIMER0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 25. "USB0D_RST,USB0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 22. "CTIMER2_RST,CTIMER2 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function" "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 19. "DMIC_RST,Digital microphone interface reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 18. "FC7_RST,Flexcomm 7 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 17. "FC6_RST,Flexcomm 6 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 16. "FC5_RST,Flexcomm 5 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 15. "FC4_RST,Flexcomm 4 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 14. "FC3_RST,Flexcomm 3 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 13. "FC2_RST,Flexcomm 2 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 12. "FC1_RST,Flexcomm 1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 11. "FC0_RST,Flexcomm 0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 10. "UTICK_RST,Micro-tick Timer reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 8. "MCAN1_RST,0 = Clear reset to this function." "0: Clear reset to this function,?"
bitfld.long 0x4 7. "MCAN0_RST,0 = Clear reset to this function." "0: Clear reset to this function,?"
newline
bitfld.long 0x4 2. "SCT0_RST,State configurable timer 0 (SCT0) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 0. "MRT_RST,Multi-rate timer (MRT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
line.long 0x8 "PRESETCTRL2,Peripheral reset control n"
bitfld.long 0x8 20. "SC1_RST,Smart card 1 reset control." "0,1"
bitfld.long 0x8 19. "SC0_RST,Smart card 0 reset control." "0,1"
newline
bitfld.long 0x8 18. "SHA_RST,SHA reset control." "0,1"
bitfld.long 0x8 17. "USB0HSL_RST,USB0 HOST slave reset control." "0,1"
newline
bitfld.long 0x8 16. "USB0HMR_RST,USB0 HOST master reset control." "0,1"
bitfld.long 0x8 15. "FC9_RST,Flexcomm 9 reset control." "0,1"
newline
bitfld.long 0x8 14. "FC8_RST,Flexcomm 8 reset control." "0,1"
bitfld.long 0x8 13. "RNG_RST,RNG reset control." "0,1"
newline
bitfld.long 0x8 12. "OTP_RST,OTP reset control." "0,1"
bitfld.long 0x8 11. "AES_RST,AES reset control." "0,1"
newline
bitfld.long 0x8 10. "GPIO5_RST,GPIO5 reset control." "0,1"
bitfld.long 0x8 9. "GPIO4_RST,GPIO4 reset control." "0,1"
newline
bitfld.long 0x8 8. "ETH_RST,Ethernet reset control." "0,1"
bitfld.long 0x8 7. "EMC_RESET,EMC reset control." "0,1"
newline
bitfld.long 0x8 6. "USB1RAM_RST,USB1 RAM reset control." "0,1"
bitfld.long 0x8 5. "USB1D_RST,USB1 Device reset control." "0,1"
newline
bitfld.long 0x8 4. "USB1H_RST,USB1 Host reset control." "0,1"
bitfld.long 0x8 3. "SDIO_RST,SDIO reset control." "0,1"
newline
bitfld.long 0x8 2. "LCD_RST,LCD reset control." "0,1"
endif
sif (cpuis("LPC54607*"))
repeat 3. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x120)++0x3
line.long 0x0 "PRESETCTRLSET[$1],Set bits in PRESETCTRLn"
hexmask.long 0x0 0.--31. 1. "RST_SET,Writing ones to this register sets the corresponding bit or bits in the PRESETCTRLn register  if they are implemented. Bits that do not correspond to defined bits in PRESETCTRLn are reserved and only zeroes should be written to them."
repeat.end
endif
sif (cpuis("LPC54607*"))
repeat 3. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x140)++0x3
line.long 0x0 "PRESETCTRLCLR[$1],Clear bits in PRESETCTRLn"
hexmask.long 0x0 0.--31. 1. "RST_CLR,Writing ones to this register clears the corresponding bit or bits in the PRESETCTRLn register  if they are implemented. Bits that do not correspond to defined bits in PRESETCTRLn are reserved and only zeroes should be written to them."
repeat.end
group.long 0x1F0++0x3
line.long 0x0 "SYSRSTSTAT,System reset status register"
bitfld.long 0x0 4. "SYSRST,Status of the software system reset" "0: No System reset detected,1: System reset detected. Writing a one clears this.."
bitfld.long 0x0 3. "BOD,Status of the Brown-out detect reset" "0: No BOD reset detected,1: BOD reset detected. Writing a one clears this.."
newline
bitfld.long 0x0 2. "WDT,Status of the Watchdog reset" "0: No WDT reset detected,1: WDT reset detected. Writing a one clears this.."
bitfld.long 0x0 1. "EXTRST,Status of the external RESET pin. External reset status" "0: No reset event detected.,1: Reset detected. Writing a one clears this reset."
newline
bitfld.long 0x0 0. "POR,POR reset status" "0: No POR detected,1: POR detected. Writing a one clears this reset."
group.long 0x200++0xB
line.long 0x0 "AHBCLKCTRL0,AHB Clock control n"
bitfld.long 0x0 27. "ADC0,Enables the clock for the ADC0 register interface." "0,1"
bitfld.long 0x0 23. "RTC,Enables the bus clock for the RTC. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 22. "WWDT,Enables the clock for the Watchdog Timer. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 21. "CRC,Enables the clock for the CRC engine. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 20. "DMA,Enables the clock for the DMA controller. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 19. "GINT,Enables the clock for the grouped pin interrupt block. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 18. "PINT,Enables the clock for the pin interrupt block.0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 17. "GPIO3,Enables the clock for the GPIO3 port registers." "0,1"
newline
bitfld.long 0x0 16. "GPIO2,Enables the clock for the GPIO2 port registers." "0,1"
bitfld.long 0x0 15. "GPIO1,Enables the clock for the GPIO1 port registers. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 14. "GPIO0,Enables the clock for the GPIO0 port registers. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 13. "IOCON,Enables the clock for the IOCON block. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 11. "INPUTMUX,Enables the clock for the input muxes. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 10. "SPIFI,Enables the clock for the SPIFI. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 9. "EEPROM,Enables the clock for EEPROM." "0,1"
bitfld.long 0x0 8. "FMC,Enables the clock for the Flash accelerator. 0 = Disable; 1 = Enable. This clock is needed if the flash is being read." "0: Disable,1: Enable"
newline
bitfld.long 0x0 7. "FLASH,Enables the clock for the flash controller. 0 = Disable; 1 = Enable. This clock is needed for flash programming  not for flash read." "0: Disable,1: Enable"
bitfld.long 0x0 5. "SRAM3,Enables the clock for SRAM3." "0,1"
newline
bitfld.long 0x0 4. "SRAM2,Enables the clock for SRAM2. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 3. "SRAM1,Enables the clock for SRAM1. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 1. "ROM,Enables the clock for the Boot ROM. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
line.long 0x4 "AHBCLKCTRL1,AHB Clock control n"
bitfld.long 0x4 27. "CTIMER1,Enables the clock for timer CTIMER1. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 26. "CTIMER0,Enables the clock for timer CTIMER0. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 25. "USB0D,Enables the clock for the USB0 device interface. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 22. "CTIMER2,Enables the clock for CTIMER 2. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 19. "DMIC,Enables the clock for the digital microphone interface. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 18. "FLEXCOMM7,Enables the clock for Flexcomm 7. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 17. "FLEXCOMM6,Enables the clock for Flexcomm 6. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 16. "FLEXCOMM5,Enables the clock for Flexcomm 5. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 15. "FLEXCOMM4,Enables the clock for Flexcomm 4. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 14. "FLEXCOMM3,Enables the clock for Flexcomm 3. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 13. "FLEXCOMM2,Enables the clock for Flexcomm 2. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 12. "FLEXCOMM1,Enables the clock for Flexcomm 1. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 11. "FLEXCOMM0,Enables the clock for Flexcomm 0. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 10. "UTICK,Enables the clock for the Micro-tick Timer. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 8. "MCAN1,Enables the clock for MCAN1." "0,1"
bitfld.long 0x4 7. "MCAN0,Enables the clock for MCAN0." "0,1"
newline
bitfld.long 0x4 2. "SCT0,Enables the clock for SCT0." "0,1"
bitfld.long 0x4 1. "RIT,Enables the clock for the Repetitive Interrupt Timer." "0,1"
newline
bitfld.long 0x4 0. "MRT,Enables the clock for the Multi-Rate Timer." "0,1"
line.long 0x8 "AHBCLKCTRL2,AHB Clock control n"
bitfld.long 0x8 20. "SC1,Enables the clock for the Smart card1 interface." "0,1"
bitfld.long 0x8 19. "SC0,Enables the clock for the Smart card0 interface." "0,1"
newline
bitfld.long 0x8 18. "SHA0,Enables the clock for the SHA interface." "0,1"
bitfld.long 0x8 17. "USB0HSL,Enables the clock for the USB host slave interface." "0,1"
newline
bitfld.long 0x8 16. "USB0HMR,Enables the clock for the USB host master interface." "0,1"
bitfld.long 0x8 15. "FLEXCOMM9,Enables the clock for the Flexcomm9 interface." "0,1"
newline
bitfld.long 0x8 14. "FLEXCOMM8,Enables the clock for the Flexcomm8 interface." "0,1"
bitfld.long 0x8 13. "RNG,Enables the clock for the RNG interface." "0,1"
newline
bitfld.long 0x8 12. "OTP,Enables the clock for the OTP interface." "0,1"
bitfld.long 0x8 11. "AES,Enables the clock for the AES interface." "0,1"
newline
bitfld.long 0x8 10. "GPIO5,Enables the clock for the GPIO5 interface." "0,1"
bitfld.long 0x8 9. "GPIO4,Enables the clock for the GPIO4 interface." "0,1"
newline
bitfld.long 0x8 8. "ETH,Enables the clock for the ethernet interface." "0,1"
bitfld.long 0x8 7. "EMC,Enables the clock for the EMC interface." "0,1"
newline
bitfld.long 0x8 6. "USB1RAM,Enables the clock for the USB1 RAM interface." "0,1"
bitfld.long 0x8 5. "USB1D,Enables the clock for the USB1 device interface." "0,1"
newline
bitfld.long 0x8 4. "USB1H,Enables the clock for the USB1 host interface." "0,1"
bitfld.long 0x8 3. "SDIO,Enables the clock for the SDIO interface." "0,1"
newline
bitfld.long 0x8 2. "LCD,Enables the clock for the LCD interface." "0,1"
endif
sif (cpuis("LPC54607*"))
repeat 3. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x220)++0x3
line.long 0x0 "AHBCLKCTRLSET[$1],Set bits in AHBCLKCTRLn"
hexmask.long 0x0 0.--31. 1. "CLK_SET,Writing ones to this register sets the corresponding bit or bits in the AHBCLKCTRLn register  if they are implemented. Bits that do not correspond to defined bits in AHBCLKCTRLn are reserved and only zeroes should be written to them."
repeat.end
endif
sif (cpuis("LPC54607*"))
repeat 3. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x240)++0x3
line.long 0x0 "AHBCLKCTRLCLR[$1],Clear bits in AHBCLKCTRLn"
hexmask.long 0x0 0.--31. 1. "CLK_CLR,Writing ones to this register clears the corresponding bit or bits in the AHBCLKCTRLn register  if they are implemented. Bits that do not correspond to defined bits in AHBCLKCTRLn are reserved and only zeroes should be written to them."
repeat.end
group.long 0x280++0xB
line.long 0x0 "MAINCLKSELA,Main clock source select A"
bitfld.long 0x0 0.--1. "SEL,Clock source for main clock source selector A" "0: FRO 12 MHz (fro_12m),1: CLKIN (clk_in),2: Watchdog oscillator (wdt_clk),3: FRO 96 or 48 MHz (fro_hf)"
line.long 0x4 "MAINCLKSELB,Main clock source select B"
bitfld.long 0x4 0.--1. "SEL,Clock source for main clock source selector B. Selects the clock source for the main clock." "0: MAINCLKSELA. Use the clock source selected in..,?,2: System PLL output (pll_clk),3: RTC oscillator 32 kHz output (32k_clk)"
line.long 0x8 "CLKOUTSELA,CLKOUT clock source select A"
bitfld.long 0x8 0.--2. "SEL,CLKOUT clock source selection" "0: Main clock (main_clk),1: CLKIN (clk_in),2: Watchdog oscillator (wdt_clk),3: FRO 96 or 48 MHz (fro_hf),4: PLL output (pll_clk),5: USB PLL clock (usb_pll_clk),6: Audio PLL clock (audio_pll_clk),7: RTC oscillator 32 kHz output (32k_clk)"
group.long 0x290++0x3
line.long 0x0 "SYSPLLCLKSEL,PLL clock source select"
bitfld.long 0x0 0.--2. "SEL,System PLL clock source selection." "0: FRO 12 MHz (fro_12m),1: CLKIN (clk_in),2: Watchdog oscillator (wdt_clk),3: RTC oscillator 32 kHz output (32k_clk),?,?,?,7: None this may be selected in order to reduce.."
group.long 0x298++0x3
line.long 0x0 "AUDPLLCLKSEL,Audio PLL clock source select"
bitfld.long 0x0 0.--2. "SEL,Audio PLL clock source selection." "0: FRO 12 MHz (fro_12m),1: CLKIN (clk_in),?,?,?,?,?,7: None this may be selected in order to reduce.."
group.long 0x2A0++0xF
line.long 0x0 "SPIFICLKSEL,SPIFI clock source select"
bitfld.long 0x0 0.--2. "SEL,System PLL clock source selection" "0: Main clock (main_clk),1: System PLL output (pll_clk),2: USB PLL clock (usb_pll_clk),3: FRO 96 or 48 MHz (fro_hf),4: Audio PLL clock (audio_pll_clk),?,?,7: None this may be selected in order to reduce.."
line.long 0x4 "ADCCLKSEL,ADC clock source select"
bitfld.long 0x4 0.--2. "SEL,ADC clock source selection" "0: FRO 96 or 48 MHz (fro_hf),1: System PLL output (pll_clk),2: USB PLL clock (usb_pll_clk),3: Audio PLL clock (audio_pll_clk),?,?,?,7: None this may be selected in order to reduce.."
line.long 0x8 "USB0CLKSEL,USB0 clock source select"
bitfld.long 0x8 0.--2. "SEL,USB0 device clock source selection." "0: FRO 96 or 48 MHz (fro_hf),1: System PLL output (pll_clk),2: USB PLL clock (usb_pll_clk),?,?,?,?,7: None this may be selected in order to reduce.."
line.long 0xC "USB1CLKSEL,USB1 clock source select"
bitfld.long 0xC 0.--2. "SEL,USB1 PHY clock source selection." "0: Main clock (main_clk),1: System PLL output (pll_clk),2: USB PLL clock (usb_pll_clk),?,?,?,?,7: None this may be selected in order to reduce.."
endif
sif (cpuis("LPC54607*"))
repeat 10. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2B0)++0x3
line.long 0x0 "FCLKSEL[$1],Flexcomm 0 clock source select"
bitfld.long 0x0 0.--2. "SEL,Flexcomm clock source selection. One per Flexcomm." "0: FRO 12 MHz (fro_12m),1: FRO HF DIV (fro_hf_div),2: Audio PLL clock (audio_pll_clk),3: MCLK pin input when selected in IOCON (mclk_in),4: FRG clock the output of the fractional rate..,?,?,7: None this may be selected in order to reduce.."
repeat.end
group.long 0x2E0++0x3
line.long 0x0 "MCLKCLKSEL,MCLK clock source select"
bitfld.long 0x0 0.--2. "SEL,MCLK source select. This may be used by Flexcomms that support I2S  and/or by the digital microphone subsystem." "0: FRO HF DIV (fro_hf_div),1: Audio PLL clock (audio_pll_clk),?,?,?,?,?,7: None this may be selected in order to reduce.."
group.long 0x2E8++0x13
line.long 0x0 "FRGCLKSEL,Fractional Rate Generator clock source select"
bitfld.long 0x0 0.--2. "SEL,Fractional Rate Generator clock source select." "0: Main clock (main_clk),1: System PLL output (pll_clk),2: FRO 12 MHz (fro_12m),3: FRO 96 or 48 MHz (fro_hf),?,?,?,7: None this may be selected in order to reduce.."
line.long 0x4 "DMICCLKSEL,Digital microphone (DMIC) subsystem clock select"
bitfld.long 0x4 0.--2. "SEL,DMIC (audio subsystem) clock source select." "0: FRO 12 MHz (fro_12m),1: FRO HF DIV (fro_hf_div),2: Audio PLL clock (audio_pll_clk),3: MCLK pin input when selected in IOCON (mclk_in),?,?,?,7: None this may be selected in order to reduce.."
line.long 0x8 "SCTCLKSEL,SCTimer/PWM clock source select"
bitfld.long 0x8 0.--2. "SEL,SCT clock source select." "0: Main clock (main_clk),1: System PLL output (pll_clk),2: FRO 96 or 48 MHz (fro_hf),3: Audio PLL clock (audio_pll_clk),?,?,?,7: None this may be selected in order to reduce.."
line.long 0xC "LCDCLKSEL,LCD clock source select"
bitfld.long 0xC 0.--1. "SEL,LCD clock source select." "0: Main clock (main_clk),1: LCDCLKIN (LCDCLK_EXT),2: FRO 96 or 48 MHz (fro_hf),3: None this may be selected in order to reduce.."
line.long 0x10 "SDIOCLKSEL,SDIO clock source select"
bitfld.long 0x10 0.--2. "SEL,SDIO clock source select." "0: Main clock (main_clk),1: System PLL output (pll_clk),2: USB PLL clock (usb_pll_clk),3: FRO 96 or 48 MHz (fro_hf),4: Audio PLL clock (audio_pll_clk),?,?,7: None this may be selected in order to reduce.."
group.long 0x300++0x17
line.long 0x0 "SYSTICKCLKDIV,SYSTICK clock divider"
bitfld.long 0x0 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x0 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x0 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count." "0,1"
hexmask.long.byte 0x0 0.--7. 1. "DIV,Clock divider value. 0: Divide by 1 up to 255: Divide by 256."
line.long 0x4 "ARMTRACECLKDIV,ARM Trace clock divider"
bitfld.long 0x4 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x4 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x4 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x4 0.--7. 1. "DIV,Clock divider value."
line.long 0x8 "CAN0CLKDIV,MCAN0 clock divider"
bitfld.long 0x8 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x8 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x8 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x8 0.--7. 1. "DIV,Clock divider value."
line.long 0xC "CAN1CLKDIV,MCAN1 clock divider"
bitfld.long 0xC 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0xC 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0xC 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count." "0,1"
hexmask.long.byte 0xC 0.--7. 1. "DIV,Clock divider value. 0: Divide by 1 up to 255: Divide by 256."
line.long 0x10 "SC0CLKDIV,Smartcard0 clock divider"
bitfld.long 0x10 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x10 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x10 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x10 0.--7. 1. "DIV,Clock divider value."
line.long 0x14 "SC1CLKDIV,Smartcard1 clock divider"
bitfld.long 0x14 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x14 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x14 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x14 0.--7. 1. "DIV,Clock divider value."
group.long 0x380++0xB
line.long 0x0 "AHBCLKDIV,AHB clock divider"
bitfld.long 0x0 31. "REQFLAG,Divider status flag." "0,1"
hexmask.long.byte 0x0 0.--7. 1. "DIV,Clock divider value. 0: Divide by 1 up to 255: Divide by 256."
line.long 0x4 "CLKOUTDIV,CLKOUT clock divider"
bitfld.long 0x4 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x4 30. "HALT,Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output." "0,1"
newline
bitfld.long 0x4 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count." "0,1"
hexmask.long.byte 0x4 0.--7. 1. "DIV,Clock divider value. 0: Divide by 1 up to 255: Divide by 256."
line.long 0x8 "FROHFCLKDIV,FROHF clock divider"
bitfld.long 0x8 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x8 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x8 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x8 0.--7. 1. "DIV,Clock divider value."
group.long 0x390++0x13
line.long 0x0 "SPIFICLKDIV,SPIFI clock divider"
bitfld.long 0x0 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x0 30. "HALT,Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output." "0,1"
newline
bitfld.long 0x0 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count." "0,1"
hexmask.long.byte 0x0 0.--7. 1. "DIV,Clock divider value."
line.long 0x4 "ADCCLKDIV,ADC clock divider"
bitfld.long 0x4 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x4 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x4 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x4 0.--7. 1. "DIV,Clock divider value."
line.long 0x8 "USB0CLKDIV,USB0 clock divider"
bitfld.long 0x8 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x8 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x8 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x8 0.--7. 1. "DIV,Clock divider value."
line.long 0xC "USB1CLKDIV,USB1 clock divider"
bitfld.long 0xC 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0xC 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0xC 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0xC 0.--7. 1. "DIV,Clock divider value."
line.long 0x10 "FRGCTRL,Fractional rate divider"
hexmask.long.byte 0x10 8.--15. 1. "MULT,Numerator of the fractional divider. MULT is equal to the programmed value."
hexmask.long.byte 0x10 0.--7. 1. "DIV,Denominator of the fractional divider. DIV is equal to the programmed value +1. Always set to 0xFF to use with the fractional baud rate generator."
group.long 0x3A8++0x17
line.long 0x0 "DMICCLKDIV,DMIC clock divider"
bitfld.long 0x0 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x0 30. "HALT,Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output." "0,1"
newline
bitfld.long 0x0 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count." "0,1"
hexmask.long.byte 0x0 0.--7. 1. "DIV,Clock divider value. 0: Divide by 1 up to 255: Divide by 256."
line.long 0x4 "MCLKDIV,I2S MCLK clock divider"
bitfld.long 0x4 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x4 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x4 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x4 0.--7. 1. "DIV,Clock divider value. 0: Divide by 1 up to 255: Divide by 256."
line.long 0x8 "LCDCLKDIV,LCD clock divider"
bitfld.long 0x8 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x8 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x8 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x8 0.--7. 1. "DIV,Clock divider value."
line.long 0xC "SCTCLKDIV,SCT/PWM clock divider"
bitfld.long 0xC 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0xC 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0xC 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0xC 0.--7. 1. "DIV,Clock divider value."
line.long 0x10 "EMCCLKDIV,EMC clock divider"
bitfld.long 0x10 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x10 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x10 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x10 0.--7. 1. "DIV,Clock divider value."
line.long 0x14 "SDIOCLKDIV,SDIO clock divider"
bitfld.long 0x14 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x14 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x14 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x14 0.--7. 1. "DIV,Clock divider value."
group.long 0x400++0x3
line.long 0x0 "FLASHCFG,Flash wait states configuration"
hexmask.long.byte 0x0 12.--15. 1. "FLASHTIM,Flash memory access time. The number of system clocks used for flash accesses is equal to FLASHTIM +1."
bitfld.long 0x0 6. "PREFOVR,Prefetch override. This bit only applies when PREFEN = 1 and a buffered instruction is completing for which the next flash line is not already buffered or being prefetched." "0: Any previously initiated prefetch will be..,1: Any previously initiated prefetch will be.."
newline
bitfld.long 0x0 5. "PREFEN,Prefetch enable." "0: No instruction prefetch is performed.,1: If the FETCHCFG field is not 0 the next flash.."
bitfld.long 0x0 4. "ACCEL,Acceleration enable." "0: Flash acceleration is disabled. Every flash read..,1: Flash acceleration is enabled. Performance is.."
newline
bitfld.long 0x0 2.--3. "DATACFG,Data read configuration. This field determines how flash accelerator buffers are used for data accesses." "0: Data accesses from flash are not buffered. Every..,1: One buffer is used for all data accesses.,2: All buffers may be used for data accesses.,?"
bitfld.long 0x0 0.--1. "FETCHCFG,Instruction fetch configuration. This field determines how flash accelerator buffers are used for instruction fetches." "0: Instruction fetches from flash are not buffered.,1: One buffer is used for all instruction fetches.,2: All buffers may be used for instruction fetches.,?"
group.long 0x40C++0x7
line.long 0x0 "USB0CLKCTRL,USB0 clock control"
bitfld.long 0x0 4. "PU_DISABLE,Internal pull-up disable control." "0,1"
bitfld.long 0x0 3. "POL_FS_HOST_CLK,USB0 Host USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt." "0,1"
newline
bitfld.long 0x0 2. "AP_FS_HOST_CLK,USB0 Host USB0_NEEDCLK signal control." "0,1"
bitfld.long 0x0 1. "POL_FS_DEV_CLK,USB0 Device USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt." "0,1"
newline
bitfld.long 0x0 0. "AP_FS_DEV_CLK,USB0 Device USB0_NEEDCLK signal control." "0,1"
line.long 0x4 "USB0CLKSTAT,USB0 clock status"
bitfld.long 0x4 1. "HOST_NEED_CLKST,USB0 Host USB0_NEEDCLK signal status." "0,1"
bitfld.long 0x4 0. "DEV_NEED_CLKST,USB0 Device USB0_NEEDCLK signal status." "0,1"
group.long 0x418++0x3
line.long 0x0 "FREQMECTRL,Frequency measure register"
bitfld.long 0x0 31. "PROG,Set this bit to one to initiate a frequency measurement cycle. Hardware clears this bit when the measurement cycle has completed and there is valid capture data in the CAPVAL field (bits 13:0)." "0,1"
hexmask.long.word 0x0 0.--13. 1. "CAPVAL,Stores the capture result which is used to calculate the frequency of the target clock. This field is read-only."
group.long 0x420++0xB
line.long 0x0 "MCLKIO,MCLK input/output control"
bitfld.long 0x0 0. "DIR,MCLK direction control." "0,1"
line.long 0x4 "USB1CLKCTRL,USB1 clock control"
bitfld.long 0x4 4. "HS_DEV_WAKEUP_N,External user wake-up signal for device mode; asserting this signal (active low) will result in exiting the low power mode; input to asynchronous control logic." "0,1"
bitfld.long 0x4 3. "POL_FS_HOST_CLK,USB1 Host need_clock polarity for triggering the USB1 wake-up interrupt." "0,1"
newline
bitfld.long 0x4 2. "AP_FS_HOST_CLK,USB1 Host need_clock signal control." "0,1"
bitfld.long 0x4 1. "POL_FS_DEV_CLK,USB1 Device need_clock polarity for triggering the USB1 wake-up interrupt." "0,1"
newline
bitfld.long 0x4 0. "AP_FS_DEV_CLK,USB1 Device need_clock signal control." "0,1"
line.long 0x8 "USB1CLKSTAT,USB1 clock status"
bitfld.long 0x8 1. "HOST_NEED_CLKST,USB1 Device host USB1_NEEDCLK signal status." "0,1"
bitfld.long 0x8 0. "DEV_NEED_CLKST,USB1 Device USB1_NEEDCLK signal status." "0,1"
group.long 0x444++0x13
line.long 0x0 "EMCSYSCTRL,EMC system control"
bitfld.long 0x0 3. "EMCFBCLKINSEL,External Memory Controller clock select." "0,1"
bitfld.long 0x0 2. "EMCBC,External Memory Controller burst control." "0,1"
newline
bitfld.long 0x0 1. "EMCRD,EMC Reset Disable." "0,1"
bitfld.long 0x0 0. "EMCSC,EMC Shift Control." "0,1"
line.long 0x4 "EMCDLYCTRL,EMC clock delay control"
hexmask.long.byte 0x4 8.--12. 1. "FBCLK_DELAY,Programmable delay value for the feedback clock that controls input data sampling."
hexmask.long.byte 0x4 0.--4. 1. "CMD_DELAY,Programmable delay value for EMC outputs in command delayed mode."
line.long 0x8 "EMCDLYCAL,EMC delay chain calibration control"
bitfld.long 0x8 15. "DONE,Measurement completion flag." "0,1"
bitfld.long 0x8 14. "START,Start control bit for the EMC calibration counter." "0,1"
newline
hexmask.long.byte 0x8 0.--7. 1. "CALVALUE,Returns the count of the approximately 50 MHz ring oscillator that occur during 32 clocks of the FRO 12 MHz."
line.long 0xC "ETHPHYSEL,Ethernet PHY Selection"
bitfld.long 0xC 2. "PHY_SEL,PHY interface select." "0,1"
line.long 0x10 "ETHSBDCTRL,Ethernet SBD flow control"
bitfld.long 0x10 0.--1. "SBD_CTRL,Sideband Flow Control." "0,1,2,3"
group.long 0x460++0x3
line.long 0x0 "SDIOCLKCTRL,SDIO CCLKIN phase and delay control"
bitfld.long 0x0 31. "CCLK_SAMPLE_DELAY_ACTIVE,Enables sample delay  as controlled by the CCLK_SAMPLE_DELAY field." "0,1"
hexmask.long.byte 0x0 24.--28. 1. "CCLK_SAMPLE_DELAY,Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in."
newline
bitfld.long 0x0 23. "CCLK_DRV_DELAY_ACTIVE,Enables drive delay  as controlled by the CCLK_DRV_DELAY field." "0,1"
hexmask.long.byte 0x0 16.--20. 1. "CCLK_DRV_DELAY,Programmable delay value by which cclk_in_drv is delayed with regard to cclk_in."
newline
bitfld.long 0x0 7. "PHASE_ACTIVE,sdio_clk by 2  before feeding into ccl_in  cclk_in_sample  and cclk_in_drv." "0,1"
bitfld.long 0x0 2.--3. "CCLK_SAMPLE_PHASE,Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in." "0,1,2,3"
newline
bitfld.long 0x0 0.--1. "CCLK_DRV_PHASE,Programmable delay value by which cclk_in_drv is phase-shifted with regard to cclk_in." "0,1,2,3"
group.long 0x500++0xF
line.long 0x0 "FROCTRL,FRO oscillator control"
bitfld.long 0x0 31. "WRTRIM,Write Trim value." "0,1"
bitfld.long 0x0 30. "HSPDCLK,High speed clock enable." "0,1"
newline
bitfld.long 0x0 25. "USBMODCHG,USB Mode value Change flag." "0,1"
bitfld.long 0x0 24. "USBCLKADJ,USB clock adjust mode." "0,1"
newline
hexmask.long.byte 0x0 16.--23. 1. "FREQTRIM,Frequency trim."
bitfld.long 0x0 14. "SEL,Select the FRO HF output frequency." "0,1"
newline
hexmask.long.word 0x0 0.--13. 1. "TRIM,This value is factory trimmed to account for bias and temperature compensation."
line.long 0x4 "SYSOSCCTRL,System oscillator control"
bitfld.long 0x4 1. "FREQRANGE,Determines frequency range for system oscillator." "0,1"
bitfld.long 0x4 0. "BYPASS,Bypass system oscillator." "0,1"
line.long 0x8 "WDTOSCCTRL,Watchdog oscillator control"
hexmask.long.byte 0x8 5.--9. 1. "FREQSEL,Frequency select."
hexmask.long.byte 0x8 0.--4. 1. "DIVSEL,Divider select."
line.long 0xC "RTCOSCCTRL,RTC oscillator 32 kHz output control"
bitfld.long 0xC 0. "EN,RTC 32 kHz clock enable." "0,1"
group.long 0x51C++0x7
line.long 0x0 "USBPLLCTRL,USB PLL control"
bitfld.long 0x0 14. "FBSEL,Feedback divider input clock control." "0,1"
bitfld.long 0x0 13. "BYPASS,Input clock bypass control." "0: CCO clock is sent to post dividers..,1: PLL input clock is sent to post dividers.."
newline
bitfld.long 0x0 12. "DIRECT,Direct CCO clock output control." "0: CCO Clock signal goes through post divider.,1: CCO Clock signal goes directly to output(s).."
bitfld.long 0x0 10.--11. "NSEL,PLL feedback Divider value." "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "PSEL,PLL Divider value." "0,1,2,3"
hexmask.long.byte 0x0 0.--7. 1. "MSEL,PLL feedback Divider value."
line.long 0x4 "USBPLLSTAT,USB PLL status"
bitfld.long 0x4 0. "LOCK,USBPLL lock indicator." "0,1"
group.long 0x580++0x13
line.long 0x0 "SYSPLLCTRL,System PLL control"
bitfld.long 0x0 20. "DIRECTO,PLL0 direct output enable." "0: Disabled. The PLL output divider (P divider) is..,1: Enabled. The PLL output divider (P divider) is.."
bitfld.long 0x0 19. "DIRECTI,PLL0 direct input enable." "0,1"
newline
bitfld.long 0x0 17. "UPLIMOFF,Disable upper frequency limiter." "0,1"
bitfld.long 0x0 15. "BYPASS,PLL bypass control." "0: Bypass disabled. PLL CCO is sent to the PLL..,1: Bypass enabled. PLL input clock is sent directly.."
newline
hexmask.long.byte 0x0 10.--14. 1. "SELP,Bandwidth select P value."
hexmask.long.byte 0x0 4.--9. 1. "SELI,Bandwidth select I value."
newline
hexmask.long.byte 0x0 0.--3. 1. "SELR,Bandwidth select R value."
line.long 0x4 "SYSPLLSTAT,PLL status"
bitfld.long 0x4 0. "LOCK,PLL lock indicator." "0,1"
line.long 0x8 "SYSPLLNDEC,PLL N divider"
bitfld.long 0x8 10. "NREQ,NDEC reload request." "0,1"
hexmask.long.word 0x8 0.--9. 1. "NDEC,Decoded N-divider coefficient value."
line.long 0xC "SYSPLLPDEC,PLL P divider"
bitfld.long 0xC 7. "PREQ,." "0,1"
hexmask.long.byte 0xC 0.--6. 1. "PDEC,Decoded P-divider coefficient value."
line.long 0x10 "SYSPLLMDEC,System PLL M divider"
bitfld.long 0x10 17. "MREQ,MDEC reload request." "0,1"
hexmask.long.tbyte 0x10 0.--16. 1. "MDEC,Decoded M-divider coefficient value."
group.long 0x5A0++0x17
line.long 0x0 "AUDPLLCTRL,Audio PLL control"
bitfld.long 0x0 20. "DIRECTO,PLL direct output enable" "0: Disabled. The PLL output divider (P divider) is..,1: Enabled. The PLL output divider (P divider) is.."
bitfld.long 0x0 19. "DIRECTI,PLL direct input enable." "0,1"
newline
bitfld.long 0x0 17. "UPLIMOFF,Disable upper frequency limiter." "0,1"
bitfld.long 0x0 15. "BYPASS,PLL bypass control." "0: Bypass disabled. PLL CCO is sent to the PLL..,1: Bypass enabled. PLL input clock is sent directly.."
newline
hexmask.long.byte 0x0 10.--14. 1. "SELP,."
hexmask.long.byte 0x0 4.--9. 1. "SELI,Bandwidth select I value."
newline
hexmask.long.byte 0x0 0.--3. 1. "SELR,Bandwidth select R value."
line.long 0x4 "AUDPLLSTAT,Audio PLL status"
bitfld.long 0x4 0. "LOCK,PLL lock indicator." "0,1"
line.long 0x8 "AUDPLLNDEC,Audio PLL N divider"
bitfld.long 0x8 10. "NREQ,NDEC reload request." "0,1"
hexmask.long.word 0x8 0.--9. 1. "NDEC,Decoded N-divider coefficient value."
line.long 0xC "AUDPLLPDEC,Audio PLL P divider"
bitfld.long 0xC 7. "PREQ,PDEC reload request." "0,1"
hexmask.long.byte 0xC 0.--6. 1. "PDEC,Decoded P-divider coefficient value."
line.long 0x10 "AUDPLLMDEC,Audio PLL M divider"
bitfld.long 0x10 17. "MREQ,MDEC reload request." "0,1"
hexmask.long.tbyte 0x10 0.--16. 1. "MDEC,Decoded M-divider coefficient value."
line.long 0x14 "AUDPLLFRAC,Audio PLL fractional divider control"
bitfld.long 0x14 23. "SEL_EXT,Select fractional divider." "0,1"
bitfld.long 0x14 22. "REQ,Writing 1 to REQ signal loads CTRL value into fractional wrapper modulator." "0,1"
newline
hexmask.long.tbyte 0x14 0.--21. 1. "CTRL,PLL fractional divider control word"
group.long 0x600++0x7
line.long 0x0 "PDSLEEPCFG0,Sleep configuration register"
bitfld.long 0x0 29. "PDEN_VD6,Power control for EEPROM." "0,1"
bitfld.long 0x0 28. "PDEN_VD5,Power control both USB0 PHY and USB1 PHY." "0,1"
newline
bitfld.long 0x0 27. "PDEN_VD4,Power control for all SRAMs and ROM." "0,1"
bitfld.long 0x0 26. "PDEN_VD3,Power control for all PLLs." "0,1"
newline
bitfld.long 0x0 23. "PDEN_VREFP,VREFP to the ADC must be enabled for the ADC to work (also enable/disable bit 9  10  and 19)." "0,1"
bitfld.long 0x0 22. "PDEN_SYS_PLL,System PLL (PLL0) power (also enable/disable bit 26)." "0,1"
newline
bitfld.long 0x0 21. "PDEN_USB0_PHY,USB0 PHY power (also enable/disable bit 28)." "0,1"
bitfld.long 0x0 20. "PDEN_WDT_OSC,Watchdog oscillator." "0,1"
newline
bitfld.long 0x0 19. "PDEN_VDDA,Vdda to the ADC  must be enabled for the ADC to work (also enable/disable bit 9  10  and 23)." "0,1"
bitfld.long 0x0 17. "PDEN_ROM,ROM (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 16. "PDEN_USB_RAM,PDEN_USB_SRAM controls USB_RAM (also enable/disable bit 27)." "0,1"
bitfld.long 0x0 15. "PDEN_SRAM1_2_3,PDEN_SRAM1_2_3 controls SRAM1  SRAM2  and SRAM3 (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 14. "PDEN_SRAM0,PDEN_SRAM0 controls SRAM0 (also enable/disable bit 27)." "0,1"
bitfld.long 0x0 13. "PDEN_SRAMX,PDEN_SRAMX controls SRAMX (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 10. "PDEN_ADC0,ADC power." "0,1"
bitfld.long 0x0 9. "PDEN_VD2_ANA,Analog supply for System Oscillator (also enable/disable bit 3 in PDRUNCFG1 register)  Temperature Sensor (also  enable/disable bit 6)  ADC (also  enable/disable bits 10  19  and 23)." "0,1"
newline
bitfld.long 0x0 8. "PDEN_BOD_INTR,Brown-out Detect interrupt." "0,1"
bitfld.long 0x0 7. "PDEN_BOD_RST,Brown-out Detect reset." "0,1"
newline
bitfld.long 0x0 6. "PDEN_TS,Temp sensor." "0,1"
bitfld.long 0x0 4. "PDEN_FRO,FRO oscillator." "0,1"
line.long 0x4 "PDSLEEPCFG1,Sleep configuration register"
bitfld.long 0x4 7. "PDEN_RNG,Random Number Generator Power." "0,1"
bitfld.long 0x4 5. "PDEN_EEPROM,EEPROM power (also  enable/disable bit 29 in PDRUNCFG0 register)." "0,1"
newline
bitfld.long 0x4 3. "PDEN_SYSOSC,System Oscillator Power (also  enable/disable bit 9 in PDRUNCFG0 register)." "0,1"
bitfld.long 0x4 2. "PDEN_AUD_PLL,Audio PLL (PLL2) power and fractional divider (also  enable/disable bit 26 in PDRUNCFG0 register)." "0,1"
newline
bitfld.long 0x4 1. "PDEN_USB1_PLL,USB PLL (PLL1) power (also  enable/disable bit 26 in PDRUNCFG0 register)." "0,1"
bitfld.long 0x4 0. "PDEN_USB1_PHY,USB1 high speed PHY (also  enable/disable bit 28 in PDRUNCFG0 register)." "0,1"
group.long 0x610++0x7
line.long 0x0 "PDRUNCFG0,Power configuration register"
bitfld.long 0x0 29. "PDEN_VD6,Power control for EEPROM." "0,1"
bitfld.long 0x0 28. "PDEN_VD5,Power control both USB0 PHY and USB1 PHY." "0,1"
newline
bitfld.long 0x0 27. "PDEN_VD4,Power control for all SRAMs and ROM." "0,1"
bitfld.long 0x0 26. "PDEN_VD3,Power control for all PLLs." "0,1"
newline
bitfld.long 0x0 23. "PDEN_VREFP,VREFP to the ADC must be enabled for the ADC to work (also enable/disable bit 9  10  and 19)." "0,1"
bitfld.long 0x0 22. "PDEN_SYS_PLL,System PLL (PLL0) power (also enable/disable bit 26)." "0,1"
newline
bitfld.long 0x0 21. "PDEN_USB0_PHY,USB0 PHY power (also enable/disable bit 28)." "0,1"
bitfld.long 0x0 20. "PDEN_WDT_OSC,Watchdog oscillator." "0,1"
newline
bitfld.long 0x0 19. "PDEN_VDDA,Vdda to the ADC  must be enabled for the ADC to work (also enable/disable bit 9  10  and 23)." "0,1"
bitfld.long 0x0 17. "PDEN_ROM,ROM (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 16. "PDEN_USB_RAM,PDEN_USB_SRAM controls USB_RAM (also enable/disable bit 27)." "0,1"
bitfld.long 0x0 15. "PDEN_SRAM1_2_3,PDEN_SRAM1_2_3 controls SRAM1  SRAM2  and SRAM3 (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 14. "PDEN_SRAM0,PDEN_SRAM0 controls SRAM0 (also enable/disable bit 27)." "0,1"
bitfld.long 0x0 13. "PDEN_SRAMX,PDEN_SRAMX controls SRAMX (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 10. "PDEN_ADC0,ADC power." "0,1"
bitfld.long 0x0 9. "PDEN_VD2_ANA,Analog supply for System Oscillator (also enable/disable bit 3 in PDRUNCFG1 register)  Temperature Sensor (also  enable/disable bit 6)  ADC (also  enable/disable bits 10  19  and 23)." "0,1"
newline
bitfld.long 0x0 8. "PDEN_BOD_INTR,Brown-out Detect interrupt." "0,1"
bitfld.long 0x0 7. "PDEN_BOD_RST,Brown-out Detect reset." "0,1"
newline
bitfld.long 0x0 6. "PDEN_TS,Temp sensor." "0,1"
bitfld.long 0x0 4. "PDEN_FRO,FRO oscillator." "0,1"
line.long 0x4 "PDRUNCFG1,Power configuration register"
bitfld.long 0x4 7. "PDEN_RNG,Random Number Generator Power." "0,1"
bitfld.long 0x4 5. "PDEN_EEPROM,EEPROM power (also  enable/disable bit 29 in PDRUNCFG0 register)." "0,1"
newline
bitfld.long 0x4 3. "PDEN_SYSOSC,System Oscillator Power (also  enable/disable bit 9 in PDRUNCFG0 register)." "0,1"
bitfld.long 0x4 2. "PDEN_AUD_PLL,Audio PLL (PLL2) power and fractional divider (also  enable/disable bit 26 in PDRUNCFG0 register)." "0,1"
newline
bitfld.long 0x4 1. "PDEN_USB1_PLL,USB PLL (PLL1) power (also  enable/disable bit 26 in PDRUNCFG0 register)." "0,1"
bitfld.long 0x4 0. "PDEN_USB1_PHY,USB1 high speed PHY (also  enable/disable bit 28 in PDRUNCFG0 register)." "0,1"
group.long 0x620++0x7
line.long 0x0 "PDRUNCFGSET0,Power configuration set register"
bitfld.long 0x0 29. "PDEN_VD6,Power control for EEPROM." "0,1"
bitfld.long 0x0 28. "PDEN_VD5,Power control both USB0 PHY and USB1 PHY." "0,1"
newline
bitfld.long 0x0 27. "PDEN_VD4,Power control for all SRAMs and ROM." "0,1"
bitfld.long 0x0 26. "PDEN_VD3,Power control for all PLLs." "0,1"
newline
bitfld.long 0x0 23. "PDEN_VREFP,VREFP to the ADC must be enabled for the ADC to work (also enable/disable bit 9  10  and 19)." "0,1"
bitfld.long 0x0 22. "PDEN_SYS_PLL,System PLL (PLL0) power (also enable/disable bit 26)." "0,1"
newline
bitfld.long 0x0 21. "PDEN_USB0_PHY,USB0 PHY power (also enable/disable bit 28)." "0,1"
bitfld.long 0x0 20. "PDEN_WDT_OSC,Watchdog oscillator." "0,1"
newline
bitfld.long 0x0 19. "PDEN_VDDA,Vdda to the ADC  must be enabled for the ADC to work (also enable/disable bit 9  10  and 23)." "0,1"
bitfld.long 0x0 17. "PDEN_ROM,ROM (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 16. "PDEN_USB_RAM,PDEN_USB_SRAM controls USB_RAM (also enable/disable bit 27)." "0,1"
bitfld.long 0x0 15. "PDEN_SRAM1_2_3,PDEN_SRAM1_2_3 controls SRAM1  SRAM2  and SRAM3 (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 14. "PDEN_SRAM0,PDEN_SRAM0 controls SRAM0 (also enable/disable bit 27)." "0,1"
bitfld.long 0x0 13. "PDEN_SRAMX,PDEN_SRAMX controls SRAMX (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 10. "PDEN_ADC0,ADC power." "0,1"
bitfld.long 0x0 9. "PDEN_VD2_ANA,Analog supply for System Oscillator (also enable/disable bit 3 in PDRUNCFG1 register)  Temperature Sensor (also  enable/disable bit 6)  ADC (also  enable/disable bits 10  19  and 23)." "0,1"
newline
bitfld.long 0x0 8. "PDEN_BOD_INTR,Brown-out Detect interrupt." "0,1"
bitfld.long 0x0 7. "PDEN_BOD_RST,Brown-out Detect reset." "0,1"
newline
bitfld.long 0x0 6. "PDEN_TS,Temp sensor." "0,1"
bitfld.long 0x0 4. "PDEN_FRO,FRO oscillator." "0,1"
line.long 0x4 "PDRUNCFGSET1,Power configuration set register"
bitfld.long 0x4 7. "PDEN_RNG,Random Number Generator Power." "0,1"
bitfld.long 0x4 5. "PDEN_EEPROM,EEPROM power (also  enable/disable bit 29 in PDRUNCFG0 register)." "0,1"
newline
bitfld.long 0x4 3. "PDEN_SYSOSC,System Oscillator Power (also  enable/disable bit 9 in PDRUNCFG0 register)." "0,1"
bitfld.long 0x4 2. "PDEN_AUD_PLL,Audio PLL (PLL2) power and fractional divider (also  enable/disable bit 26 in PDRUNCFG0 register)." "0,1"
newline
bitfld.long 0x4 1. "PDEN_USB1_PLL,USB PLL (PLL1) power (also  enable/disable bit 26 in PDRUNCFG0 register)." "0,1"
bitfld.long 0x4 0. "PDEN_USB1_PHY,USB1 high speed PHY (also  enable/disable bit 28 in PDRUNCFG0 register)." "0,1"
group.long 0x630++0x7
line.long 0x0 "PDRUNCFGCLR0,Power configuration clear register"
bitfld.long 0x0 29. "PDEN_VD6,Power control for EEPROM." "0,1"
bitfld.long 0x0 28. "PDEN_VD5,Power control both USB0 PHY and USB1 PHY." "0,1"
newline
bitfld.long 0x0 27. "PDEN_VD4,Power control for all SRAMs and ROM." "0,1"
bitfld.long 0x0 26. "PDEN_VD3,Power control for all PLLs." "0,1"
newline
bitfld.long 0x0 23. "PDEN_VREFP,VREFP to the ADC must be enabled for the ADC to work (also enable/disable bit 9  10  and 19)." "0,1"
bitfld.long 0x0 22. "PDEN_SYS_PLL,System PLL (PLL0) power (also enable/disable bit 26)." "0,1"
newline
bitfld.long 0x0 21. "PDEN_USB0_PHY,USB0 PHY power (also enable/disable bit 28)." "0,1"
bitfld.long 0x0 20. "PDEN_WDT_OSC,Watchdog oscillator." "0,1"
newline
bitfld.long 0x0 19. "PDEN_VDDA,Vdda to the ADC  must be enabled for the ADC to work (also enable/disable bit 9  10  and 23)." "0,1"
bitfld.long 0x0 17. "PDEN_ROM,ROM (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 16. "PDEN_USB_RAM,PDEN_USB_SRAM controls USB_RAM (also enable/disable bit 27)." "0,1"
bitfld.long 0x0 15. "PDEN_SRAM1_2_3,PDEN_SRAM1_2_3 controls SRAM1  SRAM2  and SRAM3 (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 14. "PDEN_SRAM0,PDEN_SRAM0 controls SRAM0 (also enable/disable bit 27)." "0,1"
bitfld.long 0x0 13. "PDEN_SRAMX,PDEN_SRAMX controls SRAMX (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 10. "PDEN_ADC0,ADC power." "0,1"
bitfld.long 0x0 9. "PDEN_VD2_ANA,Analog supply for System Oscillator (also enable/disable bit 3 in PDRUNCFG1 register)  Temperature Sensor (also  enable/disable bit 6)  ADC (also  enable/disable bits 10  19  and 23)." "0,1"
newline
bitfld.long 0x0 8. "PDEN_BOD_INTR,Brown-out Detect interrupt." "0,1"
bitfld.long 0x0 7. "PDEN_BOD_RST,Brown-out Detect reset." "0,1"
newline
bitfld.long 0x0 6. "PDEN_TS,Temp sensor." "0,1"
bitfld.long 0x0 4. "PDEN_FRO,FRO oscillator." "0,1"
line.long 0x4 "PDRUNCFGCLR1,Power configuration clear register"
bitfld.long 0x4 7. "PDEN_RNG,Random Number Generator Power." "0,1"
bitfld.long 0x4 5. "PDEN_EEPROM,EEPROM power (also  enable/disable bit 29 in PDRUNCFG0 register)." "0,1"
newline
bitfld.long 0x4 3. "PDEN_SYSOSC,System Oscillator Power (also  enable/disable bit 9 in PDRUNCFG0 register)." "0,1"
bitfld.long 0x4 2. "PDEN_AUD_PLL,Audio PLL (PLL2) power and fractional divider (also  enable/disable bit 26 in PDRUNCFG0 register)." "0,1"
newline
bitfld.long 0x4 1. "PDEN_USB1_PLL,USB PLL (PLL1) power (also  enable/disable bit 26 in PDRUNCFG0 register)." "0,1"
bitfld.long 0x4 0. "PDEN_USB1_PHY,USB1 high speed PHY (also  enable/disable bit 28 in PDRUNCFG0 register)." "0,1"
group.long 0x680++0x7
line.long 0x0 "STARTER0,Start logic 0 wake-up enable register"
bitfld.long 0x0 29. "RTC,RTC interrupt alarm and wake-up timer." "0,1"
bitfld.long 0x0 28. "USB0,USB function interrupt wake-up." "0,1"
newline
bitfld.long 0x0 27. "USB0_NEEDCLK,USB activity interrupt wake-up." "0,1"
bitfld.long 0x0 26. "HWVAD,Hardware voice activity detect interrupt wake-up." "0,1"
newline
bitfld.long 0x0 25. "DMIC,Digital microphone interrupt wake-up." "0,1"
bitfld.long 0x0 24. "ADC0_THCMP,ADC0 threshold and error interrupt wake-up." "0,1"
newline
bitfld.long 0x0 23. "ADC0_SEQB,ADC0 sequence B interrupt wake-up." "0,1"
bitfld.long 0x0 22. "ADC0_SEQA,ADC0 sequence A interrupt wake-up." "0,1"
newline
bitfld.long 0x0 21. "FLEXCOMM7,Flexcomm7 peripheral interrupt wake-up." "0,1"
bitfld.long 0x0 20. "FLEXCOMM6,Flexcomm6 peripheral interrupt wake-up." "0,1"
newline
bitfld.long 0x0 19. "FLEXCOMM5,Flexcomm5 peripheral interrupt wake-up." "0,1"
bitfld.long 0x0 18. "FLEXCOMM4,Flexcomm4 peripheral interrupt wake-up." "0,1"
newline
bitfld.long 0x0 17. "FLEXCOMM3,Flexcomm3 peripheral interrupt wake-up." "0,1"
bitfld.long 0x0 16. "FLEXCOMM2,Flexcomm2 peripheral interrupt wake-up." "0,1"
newline
bitfld.long 0x0 15. "FLEXCOMM1,Flexcomm1 peripheral interrupt wake-up." "0,1"
bitfld.long 0x0 14. "FLEXCOMM0,Flexcomm0 peripheral interrupt wake-up." "0,1"
newline
bitfld.long 0x0 13. "CTIMER3,Standard counter/timer CTIMER3 wake-up." "0,1"
bitfld.long 0x0 12. "SCT0,SCT0 wake-up." "0,1"
newline
bitfld.long 0x0 11. "CTIMER1,Standard counter/timer CTIMER1 wake-up." "0,1"
bitfld.long 0x0 10. "CTIMER0,Standard counter/timer CTIMER0 wake-up." "0,1"
newline
bitfld.long 0x0 9. "MRT,Multi-Rate Timer wake-up." "0,1"
bitfld.long 0x0 8. "UTICK,Micro-tick Timer wake-up." "0,1"
newline
bitfld.long 0x0 7. "PIN_INT3,GPIO pin interrupt 3 wake-up." "0,1"
bitfld.long 0x0 6. "PIN_INT2,GPIO pin interrupt 2 wake-up." "0,1"
newline
bitfld.long 0x0 5. "PIN_INT1,GPIO pin interrupt 1 wake-up." "0,1"
bitfld.long 0x0 4. "PIN_INT0,GPIO pin interrupt 0 wake-up." "0,1"
newline
bitfld.long 0x0 3. "GINT1,Group interrupt 1 wake-up." "0,1"
bitfld.long 0x0 2. "GINT0,Group interrupt 0 wake-up." "0,1"
newline
bitfld.long 0x0 1. "DMA,DMA wake-up." "0,1"
bitfld.long 0x0 0. "WDT_BOD,WWDT and BOD interrupt wake-up." "0,1"
line.long 0x4 "STARTER1,Start logic 0 wake-up enable register"
bitfld.long 0x4 24. "SMARTCARD1,Smart card 1 wake-up." "0,1"
bitfld.long 0x4 23. "SMARTCARD0,Smart card 0 wake-up." "0,1"
newline
bitfld.long 0x4 19. "ENET_INT0,Ethernet." "0,1"
bitfld.long 0x4 18. "ENET_INT2,Ethernet." "0,1"
newline
bitfld.long 0x4 17. "ENET_INT1,Ethernet." "0,1"
bitfld.long 0x4 16. "USB1_ACT,USB 1 activity wake-up." "0,1"
newline
bitfld.long 0x4 15. "USB1,USB 1 wake-up." "0,1"
bitfld.long 0x4 9. "FLEXCOMM9,Flexcomm Interface 9 wake-up." "0,1"
newline
bitfld.long 0x4 8. "FLEXCOMM8,Flexcomm Interface 8 wake-up." "0,1"
bitfld.long 0x4 7. "SPIFI,SPIFI interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled." "0: Wake-up disabled,1: Wake-up enabled"
newline
bitfld.long 0x4 5. "CTIMER4,Standard counter/timer CTIMER4 wake-up." "0,1"
bitfld.long 0x4 4. "CTIMER2,Standard counter/timer CTIMER2 wake-up." "0,1"
newline
bitfld.long 0x4 3. "PINT7,GPIO pin interrupt 7 wake-up." "0,1"
bitfld.long 0x4 2. "PINT6,GPIO pin interrupt 6 wake-up." "0,1"
newline
bitfld.long 0x4 1. "PINT5,GPIO pin interrupt 5 wake-up." "0,1"
bitfld.long 0x4 0. "PINT4,GPIO pin interrupt 4 wake-up." "0,1"
group.long 0x780++0x3
line.long 0x0 "HWWAKE,Configures special cases of hardware wake-up"
bitfld.long 0x0 3. "WAKEDMA,Wake for DMA. When 1  DMA being busy will cause peripheral clocking to remain running until DMA completes. This is generally used in conjunction with bit 1 and/or 2 in order to prevent peripheral clocking from being shut down as soon as the cause.." "0,1"
bitfld.long 0x0 2. "WAKEDMIC,Wake for Digital Microphone. When 1  the digital microphone input FIFO reaching the level specified by TRIGLVL of either channel will cause peripheral clocking to wake up temporarily while the related status is asserted." "0,1"
newline
bitfld.long 0x0 1. "FCWAKE,Wake for Flexcomms. When 1  any Flexcomm FIFO reaching the level specified by its own TXLVL will cause peripheral clocking to wake up temporarily while the related status is asserted." "0,1"
bitfld.long 0x0 0. "FORCEWAKE,Force peripheral clocking to stay on during Deep Sleep and Power-down modes. When 1  clocking to peripherals is prevented from being shut down when the CPU enters Deep Sleep and Power-down modes. This is intended to allow a coprocessor to.." "0,1"
group.long 0xE04++0x3
line.long 0x0 "AUTOCGOR,Auto Clock-Gate Override Register"
bitfld.long 0x0 4. "RAM3,When 1  automatic clock gating for RAM1 are turned off." "0,1"
bitfld.long 0x0 3. "RAM2,When 1  automatic clock gating for RAM1 are turned off." "0,1"
newline
bitfld.long 0x0 2. "RAM1,When 1  automatic clock gating for RAM1 are turned off." "0,1"
bitfld.long 0x0 1. "RAM0X,When 1  automatic clock gating for RAMX and RAM0 are turned off." "0,1"
rgroup.long 0xFF4++0xB
line.long 0x0 "JTAGIDCODE,JTAG ID code register"
hexmask.long 0x0 0.--31. 1. "JTAGID,JTAG ID code."
line.long 0x4 "DEVICE_ID0,Part ID register"
hexmask.long 0x4 0.--31. 1. "PARTID,Part ID"
line.long 0x8 "DEVICE_ID1,Boot ROM and die revision register"
hexmask.long 0x8 0.--31. 1. "REVID,Revision."
group.long 0x20044++0x3
line.long 0x0 "BODCTRL,Brown-Out Detect control"
bitfld.long 0x0 7. "BODINTSTAT,BOD interrupt status. When 1  a BOD interrupt has occurred. Cleared by writing 1 to this bit." "0,1"
bitfld.long 0x0 6. "BODRSTSTAT,BOD reset status. When 1  a BOD reset has occurred. Cleared by writing 1 to this bit." "0,1"
newline
bitfld.long 0x0 5. "BODINTENA,BOD interrupt enable" "0: Disable interrupt function.,1: Enable interrupt function."
bitfld.long 0x0 3.--4. "BODINTLEV,BOD interrupt level" "0: Level 0: 2.05 V,1: Level 1: 2.45 V,2: Level 2: 2.75 V,3: Level 3: 3.05 V"
newline
bitfld.long 0x0 2. "BODRSTENA,BOD reset enable" "0: Disable reset function.,1: Enable reset function."
bitfld.long 0x0 0.--1. "BODRSTLEV,BOD reset level" "0: Level 0: 1.5 V,1: Level 1: 1.85 V,2: Level 2: 2.0 V,3: Level 3: 2.3 V"
endif
sif (cpuis("LPC54608*"))
group.long 0x10++0x3
line.long 0x0 "AHBMATPRIO,AHB multilayer matrix priority control"
bitfld.long 0x0 24.--25. "PRI_SHA,SHA priority." "0,1,2,3"
bitfld.long 0x0 22.--23. "PRI_MCAN2,MCAN2 priority." "0,1,2,3"
newline
bitfld.long 0x0 20.--21. "PRI_MCAN1,MCAN1 priority." "0,1,2,3"
bitfld.long 0x0 18.--19. "PRI_SDIO,SDIO priority." "0,1,2,3"
newline
bitfld.long 0x0 16.--17. "PRI_USB1,USB1 DMA priority." "0,1,2,3"
bitfld.long 0x0 14.--15. "PRI_USB0,USB0 DMA priority." "0,1,2,3"
newline
bitfld.long 0x0 12.--13. "PRI_LCD,LCD DMA priority." "0,1,2,3"
bitfld.long 0x0 10.--11. "PRI_ETH,Ethernet DMA priority." "0,1,2,3"
newline
hexmask.long.byte 0x0 6.--9. 1. "PRI_DMA,DMA controller priority."
bitfld.long 0x0 4.--5. "PRI_SYS,System bus priority." "0,1,2,3"
newline
bitfld.long 0x0 2.--3. "PRI_DCODE,D-Code bus priority." "0,1,2,3"
bitfld.long 0x0 0.--1. "PRI_ICODE,I-Code bus priority." "0,1,2,3"
group.long 0x40++0x3
line.long 0x0 "SYSTCKCAL,System tick counter calibration"
bitfld.long 0x0 25. "NOREF,Initial value for the Systick timer." "0,1"
bitfld.long 0x0 24. "SKEW,Initial value for the Systick timer." "0,1"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "CAL,System tick timer calibration value."
group.long 0x48++0x7
line.long 0x0 "NMISRC,NMI Source Select"
bitfld.long 0x0 31. "NMIENM4,Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQM4." "0,1"
hexmask.long.byte 0x0 0.--5. 1. "IRQM4,The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the Cortex-M4  if enabled by NMIENM4."
line.long 0x4 "ASYNCAPBCTRL,Asynchronous APB Control"
bitfld.long 0x4 0. "ENABLE,Enables the asynchronous APB bridge and subsystem." "0: Disabled. Asynchronous APB bridge is disabled.,1: Enabled. Asynchronous APB bridge is enabled."
endif
sif (cpuis("LPC54608*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0xC0)++0x3
line.long 0x0 "PIOPORCAP[$1],POR captured value of port n"
hexmask.long 0x0 0.--31. 1. "PIOPORCAP,State of PIOn_31 through PIOn_0 at power-on reset"
repeat.end
endif
sif (cpuis("LPC54608*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0xD0)++0x3
line.long 0x0 "PIORESCAP[$1],Reset captured value of port n"
hexmask.long 0x0 0.--31. 1. "PIORESCAP,State of PIOn_31 through PIOn_0 for resets other than POR."
repeat.end
group.long 0x100++0xB
line.long 0x0 "PRESETCTRL0,Peripheral reset control n"
bitfld.long 0x0 27. "ADC0_RST,ADC0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 22. "WWDT_RST,Watchdog timer reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x0 21. "CRC_RST,CRC generator reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 20. "DMA0_RST,DMA0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x0 19. "GINT_RST,Grouped interrupt (GINT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 18. "PINT_RST,Pin interrupt (PINT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x0 17. "GPIO3_RST,GPIO3 reset control." "0,1"
bitfld.long 0x0 16. "GPIO2_RST,GPIO2 reset control." "0,1"
newline
bitfld.long 0x0 15. "GPIO1_RST,GPIO1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 14. "GPIO0_RST,GPIO0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x0 13. "IOCON_RST,IOCON reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 11. "MUX_RST,Input mux reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x0 10. "SPIFI_RST,SPIFI reset control." "0,1"
bitfld.long 0x0 9. "EEPROM_RST,EEPROM reset control." "0,1"
newline
bitfld.long 0x0 8. "FMC_RST,Flash accelerator reset control. Note that the FMC must not be reset while executing from flash  and must be reconfigured after reset. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 7. "FLASH_RST,Flash controller reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
line.long 0x4 "PRESETCTRL1,Peripheral reset control n"
bitfld.long 0x4 27. "CTIMER1_RST,CTIMER1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 26. "CTIMER0_RST,CTIMER0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 25. "USB0D_RST,USB0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 22. "CTIMER2_RST,CTIMER2 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function" "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 19. "DMIC_RST,Digital microphone interface reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 18. "FC7_RST,Flexcomm 7 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 17. "FC6_RST,Flexcomm 6 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 16. "FC5_RST,Flexcomm 5 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 15. "FC4_RST,Flexcomm 4 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 14. "FC3_RST,Flexcomm 3 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 13. "FC2_RST,Flexcomm 2 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 12. "FC1_RST,Flexcomm 1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 11. "FC0_RST,Flexcomm 0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 10. "UTICK_RST,Micro-tick Timer reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 8. "MCAN1_RST,0 = Clear reset to this function." "0: Clear reset to this function,?"
bitfld.long 0x4 7. "MCAN0_RST,0 = Clear reset to this function." "0: Clear reset to this function,?"
newline
bitfld.long 0x4 2. "SCT0_RST,State configurable timer 0 (SCT0) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 0. "MRT_RST,Multi-rate timer (MRT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
line.long 0x8 "PRESETCTRL2,Peripheral reset control n"
bitfld.long 0x8 20. "SC1_RST,Smart card 1 reset control." "0,1"
bitfld.long 0x8 19. "SC0_RST,Smart card 0 reset control." "0,1"
newline
bitfld.long 0x8 18. "SHA_RST,SHA reset control." "0,1"
bitfld.long 0x8 17. "USB0HSL_RST,USB0 HOST slave reset control." "0,1"
newline
bitfld.long 0x8 16. "USB0HMR_RST,USB0 HOST master reset control." "0,1"
bitfld.long 0x8 15. "FC9_RST,Flexcomm 9 reset control." "0,1"
newline
bitfld.long 0x8 14. "FC8_RST,Flexcomm 8 reset control." "0,1"
bitfld.long 0x8 13. "RNG_RST,RNG reset control." "0,1"
newline
bitfld.long 0x8 12. "OTP_RST,OTP reset control." "0,1"
bitfld.long 0x8 11. "AES_RST,AES reset control." "0,1"
newline
bitfld.long 0x8 10. "GPIO5_RST,GPIO5 reset control." "0,1"
bitfld.long 0x8 9. "GPIO4_RST,GPIO4 reset control." "0,1"
newline
bitfld.long 0x8 8. "ETH_RST,Ethernet reset control." "0,1"
bitfld.long 0x8 7. "EMC_RESET,EMC reset control." "0,1"
newline
bitfld.long 0x8 6. "USB1RAM_RST,USB1 RAM reset control." "0,1"
bitfld.long 0x8 5. "USB1D_RST,USB1 Device reset control." "0,1"
newline
bitfld.long 0x8 4. "USB1H_RST,USB1 Host reset control." "0,1"
bitfld.long 0x8 3. "SDIO_RST,SDIO reset control." "0,1"
newline
bitfld.long 0x8 2. "LCD_RST,LCD reset control." "0,1"
endif
sif (cpuis("LPC54608*"))
repeat 3. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x120)++0x3
line.long 0x0 "PRESETCTRLSET[$1],Set bits in PRESETCTRLn"
hexmask.long 0x0 0.--31. 1. "RST_SET,Writing ones to this register sets the corresponding bit or bits in the PRESETCTRLn register  if they are implemented. Bits that do not correspond to defined bits in PRESETCTRLn are reserved and only zeroes should be written to them."
repeat.end
endif
sif (cpuis("LPC54608*"))
repeat 3. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x140)++0x3
line.long 0x0 "PRESETCTRLCLR[$1],Clear bits in PRESETCTRLn"
hexmask.long 0x0 0.--31. 1. "RST_CLR,Writing ones to this register clears the corresponding bit or bits in the PRESETCTRLn register  if they are implemented. Bits that do not correspond to defined bits in PRESETCTRLn are reserved and only zeroes should be written to them."
repeat.end
group.long 0x1F0++0x3
line.long 0x0 "SYSRSTSTAT,System reset status register"
bitfld.long 0x0 4. "SYSRST,Status of the software system reset" "0: No System reset detected,1: System reset detected. Writing a one clears this.."
bitfld.long 0x0 3. "BOD,Status of the Brown-out detect reset" "0: No BOD reset detected,1: BOD reset detected. Writing a one clears this.."
newline
bitfld.long 0x0 2. "WDT,Status of the Watchdog reset" "0: No WDT reset detected,1: WDT reset detected. Writing a one clears this.."
bitfld.long 0x0 1. "EXTRST,Status of the external RESET pin. External reset status" "0: No reset event detected.,1: Reset detected. Writing a one clears this reset."
newline
bitfld.long 0x0 0. "POR,POR reset status" "0: No POR detected,1: POR detected. Writing a one clears this reset."
group.long 0x200++0xB
line.long 0x0 "AHBCLKCTRL0,AHB Clock control n"
bitfld.long 0x0 27. "ADC0,Enables the clock for the ADC0 register interface." "0,1"
bitfld.long 0x0 23. "RTC,Enables the bus clock for the RTC. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 22. "WWDT,Enables the clock for the Watchdog Timer. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 21. "CRC,Enables the clock for the CRC engine. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 20. "DMA,Enables the clock for the DMA controller. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 19. "GINT,Enables the clock for the grouped pin interrupt block. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 18. "PINT,Enables the clock for the pin interrupt block.0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 17. "GPIO3,Enables the clock for the GPIO3 port registers." "0,1"
newline
bitfld.long 0x0 16. "GPIO2,Enables the clock for the GPIO2 port registers." "0,1"
bitfld.long 0x0 15. "GPIO1,Enables the clock for the GPIO1 port registers. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 14. "GPIO0,Enables the clock for the GPIO0 port registers. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 13. "IOCON,Enables the clock for the IOCON block. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 11. "INPUTMUX,Enables the clock for the input muxes. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 10. "SPIFI,Enables the clock for the SPIFI. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 9. "EEPROM,Enables the clock for EEPROM." "0,1"
bitfld.long 0x0 8. "FMC,Enables the clock for the Flash accelerator. 0 = Disable; 1 = Enable. This clock is needed if the flash is being read." "0: Disable,1: Enable"
newline
bitfld.long 0x0 7. "FLASH,Enables the clock for the flash controller. 0 = Disable; 1 = Enable. This clock is needed for flash programming  not for flash read." "0: Disable,1: Enable"
bitfld.long 0x0 5. "SRAM3,Enables the clock for SRAM3." "0,1"
newline
bitfld.long 0x0 4. "SRAM2,Enables the clock for SRAM2. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 3. "SRAM1,Enables the clock for SRAM1. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 1. "ROM,Enables the clock for the Boot ROM. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
line.long 0x4 "AHBCLKCTRL1,AHB Clock control n"
bitfld.long 0x4 27. "CTIMER1,Enables the clock for timer CTIMER1. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 26. "CTIMER0,Enables the clock for timer CTIMER0. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 25. "USB0D,Enables the clock for the USB0 device interface. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 22. "CTIMER2,Enables the clock for CTIMER 2. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 19. "DMIC,Enables the clock for the digital microphone interface. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 18. "FLEXCOMM7,Enables the clock for Flexcomm 7. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 17. "FLEXCOMM6,Enables the clock for Flexcomm 6. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 16. "FLEXCOMM5,Enables the clock for Flexcomm 5. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 15. "FLEXCOMM4,Enables the clock for Flexcomm 4. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 14. "FLEXCOMM3,Enables the clock for Flexcomm 3. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 13. "FLEXCOMM2,Enables the clock for Flexcomm 2. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 12. "FLEXCOMM1,Enables the clock for Flexcomm 1. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 11. "FLEXCOMM0,Enables the clock for Flexcomm 0. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 10. "UTICK,Enables the clock for the Micro-tick Timer. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 8. "MCAN1,Enables the clock for MCAN1." "0,1"
bitfld.long 0x4 7. "MCAN0,Enables the clock for MCAN0." "0,1"
newline
bitfld.long 0x4 2. "SCT0,Enables the clock for SCT0." "0,1"
bitfld.long 0x4 1. "RIT,Enables the clock for the Repetitive Interrupt Timer." "0,1"
newline
bitfld.long 0x4 0. "MRT,Enables the clock for the Multi-Rate Timer." "0,1"
line.long 0x8 "AHBCLKCTRL2,AHB Clock control n"
bitfld.long 0x8 20. "SC1,Enables the clock for the Smart card1 interface." "0,1"
bitfld.long 0x8 19. "SC0,Enables the clock for the Smart card0 interface." "0,1"
newline
bitfld.long 0x8 18. "SHA0,Enables the clock for the SHA interface." "0,1"
bitfld.long 0x8 17. "USB0HSL,Enables the clock for the USB host slave interface." "0,1"
newline
bitfld.long 0x8 16. "USB0HMR,Enables the clock for the USB host master interface." "0,1"
bitfld.long 0x8 15. "FLEXCOMM9,Enables the clock for the Flexcomm9 interface." "0,1"
newline
bitfld.long 0x8 14. "FLEXCOMM8,Enables the clock for the Flexcomm8 interface." "0,1"
bitfld.long 0x8 13. "RNG,Enables the clock for the RNG interface." "0,1"
newline
bitfld.long 0x8 12. "OTP,Enables the clock for the OTP interface." "0,1"
bitfld.long 0x8 11. "AES,Enables the clock for the AES interface." "0,1"
newline
bitfld.long 0x8 10. "GPIO5,Enables the clock for the GPIO5 interface." "0,1"
bitfld.long 0x8 9. "GPIO4,Enables the clock for the GPIO4 interface." "0,1"
newline
bitfld.long 0x8 8. "ETH,Enables the clock for the ethernet interface." "0,1"
bitfld.long 0x8 7. "EMC,Enables the clock for the EMC interface." "0,1"
newline
bitfld.long 0x8 6. "USB1RAM,Enables the clock for the USB1 RAM interface." "0,1"
bitfld.long 0x8 5. "USB1D,Enables the clock for the USB1 device interface." "0,1"
newline
bitfld.long 0x8 4. "USB1H,Enables the clock for the USB1 host interface." "0,1"
bitfld.long 0x8 3. "SDIO,Enables the clock for the SDIO interface." "0,1"
newline
bitfld.long 0x8 2. "LCD,Enables the clock for the LCD interface." "0,1"
endif
sif (cpuis("LPC54608*"))
repeat 3. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x220)++0x3
line.long 0x0 "AHBCLKCTRLSET[$1],Set bits in AHBCLKCTRLn"
hexmask.long 0x0 0.--31. 1. "CLK_SET,Writing ones to this register sets the corresponding bit or bits in the AHBCLKCTRLn register  if they are implemented. Bits that do not correspond to defined bits in AHBCLKCTRLn are reserved and only zeroes should be written to them."
repeat.end
endif
sif (cpuis("LPC54608*"))
repeat 3. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x240)++0x3
line.long 0x0 "AHBCLKCTRLCLR[$1],Clear bits in AHBCLKCTRLn"
hexmask.long 0x0 0.--31. 1. "CLK_CLR,Writing ones to this register clears the corresponding bit or bits in the AHBCLKCTRLn register  if they are implemented. Bits that do not correspond to defined bits in AHBCLKCTRLn are reserved and only zeroes should be written to them."
repeat.end
group.long 0x280++0xB
line.long 0x0 "MAINCLKSELA,Main clock source select A"
bitfld.long 0x0 0.--1. "SEL,Clock source for main clock source selector A" "0: FRO 12 MHz (fro_12m),1: CLKIN (clk_in),2: Watchdog oscillator (wdt_clk),3: FRO 96 or 48 MHz (fro_hf)"
line.long 0x4 "MAINCLKSELB,Main clock source select B"
bitfld.long 0x4 0.--1. "SEL,Clock source for main clock source selector B. Selects the clock source for the main clock." "0: MAINCLKSELA. Use the clock source selected in..,?,2: System PLL output (pll_clk),3: RTC oscillator 32 kHz output (32k_clk)"
line.long 0x8 "CLKOUTSELA,CLKOUT clock source select A"
bitfld.long 0x8 0.--2. "SEL,CLKOUT clock source selection" "0: Main clock (main_clk),1: CLKIN (clk_in),2: Watchdog oscillator (wdt_clk),3: FRO 96 or 48 MHz (fro_hf),4: PLL output (pll_clk),5: USB PLL clock (usb_pll_clk),6: Audio PLL clock (audio_pll_clk),7: RTC oscillator 32 kHz output (32k_clk)"
group.long 0x290++0x3
line.long 0x0 "SYSPLLCLKSEL,PLL clock source select"
bitfld.long 0x0 0.--2. "SEL,System PLL clock source selection." "0: FRO 12 MHz (fro_12m),1: CLKIN (clk_in),2: Watchdog oscillator (wdt_clk),3: RTC oscillator 32 kHz output (32k_clk),?,?,?,7: None this may be selected in order to reduce.."
group.long 0x298++0x3
line.long 0x0 "AUDPLLCLKSEL,Audio PLL clock source select"
bitfld.long 0x0 0.--2. "SEL,Audio PLL clock source selection." "0: FRO 12 MHz (fro_12m),1: CLKIN (clk_in),?,?,?,?,?,7: None this may be selected in order to reduce.."
group.long 0x2A0++0xF
line.long 0x0 "SPIFICLKSEL,SPIFI clock source select"
bitfld.long 0x0 0.--2. "SEL,System PLL clock source selection" "0: Main clock (main_clk),1: System PLL output (pll_clk),2: USB PLL clock (usb_pll_clk),3: FRO 96 or 48 MHz (fro_hf),4: Audio PLL clock (audio_pll_clk),?,?,7: None this may be selected in order to reduce.."
line.long 0x4 "ADCCLKSEL,ADC clock source select"
bitfld.long 0x4 0.--2. "SEL,ADC clock source selection" "0: FRO 96 or 48 MHz (fro_hf),1: System PLL output (pll_clk),2: USB PLL clock (usb_pll_clk),3: Audio PLL clock (audio_pll_clk),?,?,?,7: None this may be selected in order to reduce.."
line.long 0x8 "USB0CLKSEL,USB0 clock source select"
bitfld.long 0x8 0.--2. "SEL,USB0 device clock source selection." "0: FRO 96 or 48 MHz (fro_hf),1: System PLL output (pll_clk),2: USB PLL clock (usb_pll_clk),?,?,?,?,7: None this may be selected in order to reduce.."
line.long 0xC "USB1CLKSEL,USB1 clock source select"
bitfld.long 0xC 0.--2. "SEL,USB1 PHY clock source selection." "0: Main clock (main_clk),1: System PLL output (pll_clk),2: USB PLL clock (usb_pll_clk),?,?,?,?,7: None this may be selected in order to reduce.."
endif
sif (cpuis("LPC54608*"))
repeat 10. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2B0)++0x3
line.long 0x0 "FCLKSEL[$1],Flexcomm 0 clock source select"
bitfld.long 0x0 0.--2. "SEL,Flexcomm clock source selection. One per Flexcomm." "0: FRO 12 MHz (fro_12m),1: FRO HF DIV (fro_hf_div),2: Audio PLL clock (audio_pll_clk),3: MCLK pin input when selected in IOCON (mclk_in),4: FRG clock the output of the fractional rate..,?,?,7: None this may be selected in order to reduce.."
repeat.end
group.long 0x2E0++0x3
line.long 0x0 "MCLKCLKSEL,MCLK clock source select"
bitfld.long 0x0 0.--2. "SEL,MCLK source select. This may be used by Flexcomms that support I2S  and/or by the digital microphone subsystem." "0: FRO HF DIV (fro_hf_div),1: Audio PLL clock (audio_pll_clk),?,?,?,?,?,7: None this may be selected in order to reduce.."
group.long 0x2E8++0x13
line.long 0x0 "FRGCLKSEL,Fractional Rate Generator clock source select"
bitfld.long 0x0 0.--2. "SEL,Fractional Rate Generator clock source select." "0: Main clock (main_clk),1: System PLL output (pll_clk),2: FRO 12 MHz (fro_12m),3: FRO 96 or 48 MHz (fro_hf),?,?,?,7: None this may be selected in order to reduce.."
line.long 0x4 "DMICCLKSEL,Digital microphone (DMIC) subsystem clock select"
bitfld.long 0x4 0.--2. "SEL,DMIC (audio subsystem) clock source select." "0: FRO 12 MHz (fro_12m),1: FRO HF DIV (fro_hf_div),2: Audio PLL clock (audio_pll_clk),3: MCLK pin input when selected in IOCON (mclk_in),?,?,?,7: None this may be selected in order to reduce.."
line.long 0x8 "SCTCLKSEL,SCTimer/PWM clock source select"
bitfld.long 0x8 0.--2. "SEL,SCT clock source select." "0: Main clock (main_clk),1: System PLL output (pll_clk),2: FRO 96 or 48 MHz (fro_hf),3: Audio PLL clock (audio_pll_clk),?,?,?,7: None this may be selected in order to reduce.."
line.long 0xC "LCDCLKSEL,LCD clock source select"
bitfld.long 0xC 0.--1. "SEL,LCD clock source select." "0: Main clock (main_clk),1: LCDCLKIN (LCDCLK_EXT),2: FRO 96 or 48 MHz (fro_hf),3: None this may be selected in order to reduce.."
line.long 0x10 "SDIOCLKSEL,SDIO clock source select"
bitfld.long 0x10 0.--2. "SEL,SDIO clock source select." "0: Main clock (main_clk),1: System PLL output (pll_clk),2: USB PLL clock (usb_pll_clk),3: FRO 96 or 48 MHz (fro_hf),4: Audio PLL clock (audio_pll_clk),?,?,7: None this may be selected in order to reduce.."
group.long 0x300++0x17
line.long 0x0 "SYSTICKCLKDIV,SYSTICK clock divider"
bitfld.long 0x0 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x0 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x0 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count." "0,1"
hexmask.long.byte 0x0 0.--7. 1. "DIV,Clock divider value. 0: Divide by 1 up to 255: Divide by 256."
line.long 0x4 "ARMTRACECLKDIV,ARM Trace clock divider"
bitfld.long 0x4 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x4 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x4 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x4 0.--7. 1. "DIV,Clock divider value."
line.long 0x8 "CAN0CLKDIV,MCAN0 clock divider"
bitfld.long 0x8 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x8 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x8 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x8 0.--7. 1. "DIV,Clock divider value."
line.long 0xC "CAN1CLKDIV,MCAN1 clock divider"
bitfld.long 0xC 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0xC 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0xC 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count." "0,1"
hexmask.long.byte 0xC 0.--7. 1. "DIV,Clock divider value. 0: Divide by 1 up to 255: Divide by 256."
line.long 0x10 "SC0CLKDIV,Smartcard0 clock divider"
bitfld.long 0x10 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x10 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x10 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x10 0.--7. 1. "DIV,Clock divider value."
line.long 0x14 "SC1CLKDIV,Smartcard1 clock divider"
bitfld.long 0x14 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x14 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x14 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x14 0.--7. 1. "DIV,Clock divider value."
group.long 0x380++0xB
line.long 0x0 "AHBCLKDIV,AHB clock divider"
bitfld.long 0x0 31. "REQFLAG,Divider status flag." "0,1"
hexmask.long.byte 0x0 0.--7. 1. "DIV,Clock divider value. 0: Divide by 1 up to 255: Divide by 256."
line.long 0x4 "CLKOUTDIV,CLKOUT clock divider"
bitfld.long 0x4 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x4 30. "HALT,Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output." "0,1"
newline
bitfld.long 0x4 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count." "0,1"
hexmask.long.byte 0x4 0.--7. 1. "DIV,Clock divider value. 0: Divide by 1 up to 255: Divide by 256."
line.long 0x8 "FROHFCLKDIV,FROHF clock divider"
bitfld.long 0x8 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x8 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x8 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x8 0.--7. 1. "DIV,Clock divider value."
group.long 0x390++0x13
line.long 0x0 "SPIFICLKDIV,SPIFI clock divider"
bitfld.long 0x0 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x0 30. "HALT,Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output." "0,1"
newline
bitfld.long 0x0 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count." "0,1"
hexmask.long.byte 0x0 0.--7. 1. "DIV,Clock divider value."
line.long 0x4 "ADCCLKDIV,ADC clock divider"
bitfld.long 0x4 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x4 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x4 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x4 0.--7. 1. "DIV,Clock divider value."
line.long 0x8 "USB0CLKDIV,USB0 clock divider"
bitfld.long 0x8 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x8 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x8 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x8 0.--7. 1. "DIV,Clock divider value."
line.long 0xC "USB1CLKDIV,USB1 clock divider"
bitfld.long 0xC 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0xC 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0xC 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0xC 0.--7. 1. "DIV,Clock divider value."
line.long 0x10 "FRGCTRL,Fractional rate divider"
hexmask.long.byte 0x10 8.--15. 1. "MULT,Numerator of the fractional divider. MULT is equal to the programmed value."
hexmask.long.byte 0x10 0.--7. 1. "DIV,Denominator of the fractional divider. DIV is equal to the programmed value +1. Always set to 0xFF to use with the fractional baud rate generator."
group.long 0x3A8++0x17
line.long 0x0 "DMICCLKDIV,DMIC clock divider"
bitfld.long 0x0 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x0 30. "HALT,Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output." "0,1"
newline
bitfld.long 0x0 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count." "0,1"
hexmask.long.byte 0x0 0.--7. 1. "DIV,Clock divider value. 0: Divide by 1 up to 255: Divide by 256."
line.long 0x4 "MCLKDIV,I2S MCLK clock divider"
bitfld.long 0x4 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x4 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x4 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x4 0.--7. 1. "DIV,Clock divider value. 0: Divide by 1 up to 255: Divide by 256."
line.long 0x8 "LCDCLKDIV,LCD clock divider"
bitfld.long 0x8 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x8 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x8 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x8 0.--7. 1. "DIV,Clock divider value."
line.long 0xC "SCTCLKDIV,SCT/PWM clock divider"
bitfld.long 0xC 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0xC 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0xC 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0xC 0.--7. 1. "DIV,Clock divider value."
line.long 0x10 "EMCCLKDIV,EMC clock divider"
bitfld.long 0x10 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x10 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x10 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x10 0.--7. 1. "DIV,Clock divider value."
line.long 0x14 "SDIOCLKDIV,SDIO clock divider"
bitfld.long 0x14 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x14 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x14 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x14 0.--7. 1. "DIV,Clock divider value."
group.long 0x400++0x3
line.long 0x0 "FLASHCFG,Flash wait states configuration"
hexmask.long.byte 0x0 12.--15. 1. "FLASHTIM,Flash memory access time. The number of system clocks used for flash accesses is equal to FLASHTIM +1."
bitfld.long 0x0 6. "PREFOVR,Prefetch override. This bit only applies when PREFEN = 1 and a buffered instruction is completing for which the next flash line is not already buffered or being prefetched." "0: Any previously initiated prefetch will be..,1: Any previously initiated prefetch will be.."
newline
bitfld.long 0x0 5. "PREFEN,Prefetch enable." "0: No instruction prefetch is performed.,1: If the FETCHCFG field is not 0 the next flash.."
bitfld.long 0x0 4. "ACCEL,Acceleration enable." "0: Flash acceleration is disabled. Every flash read..,1: Flash acceleration is enabled. Performance is.."
newline
bitfld.long 0x0 2.--3. "DATACFG,Data read configuration. This field determines how flash accelerator buffers are used for data accesses." "0: Data accesses from flash are not buffered. Every..,1: One buffer is used for all data accesses.,2: All buffers may be used for data accesses.,?"
bitfld.long 0x0 0.--1. "FETCHCFG,Instruction fetch configuration. This field determines how flash accelerator buffers are used for instruction fetches." "0: Instruction fetches from flash are not buffered.,1: One buffer is used for all instruction fetches.,2: All buffers may be used for instruction fetches.,?"
group.long 0x40C++0x7
line.long 0x0 "USB0CLKCTRL,USB0 clock control"
bitfld.long 0x0 4. "PU_DISABLE,Internal pull-up disable control." "0,1"
bitfld.long 0x0 3. "POL_FS_HOST_CLK,USB0 Host USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt." "0,1"
newline
bitfld.long 0x0 2. "AP_FS_HOST_CLK,USB0 Host USB0_NEEDCLK signal control." "0,1"
bitfld.long 0x0 1. "POL_FS_DEV_CLK,USB0 Device USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt." "0,1"
newline
bitfld.long 0x0 0. "AP_FS_DEV_CLK,USB0 Device USB0_NEEDCLK signal control." "0,1"
line.long 0x4 "USB0CLKSTAT,USB0 clock status"
bitfld.long 0x4 1. "HOST_NEED_CLKST,USB0 Host USB0_NEEDCLK signal status." "0,1"
bitfld.long 0x4 0. "DEV_NEED_CLKST,USB0 Device USB0_NEEDCLK signal status." "0,1"
group.long 0x418++0x3
line.long 0x0 "FREQMECTRL,Frequency measure register"
bitfld.long 0x0 31. "PROG,Set this bit to one to initiate a frequency measurement cycle. Hardware clears this bit when the measurement cycle has completed and there is valid capture data in the CAPVAL field (bits 13:0)." "0,1"
hexmask.long.word 0x0 0.--13. 1. "CAPVAL,Stores the capture result which is used to calculate the frequency of the target clock. This field is read-only."
group.long 0x420++0xB
line.long 0x0 "MCLKIO,MCLK input/output control"
bitfld.long 0x0 0. "DIR,MCLK direction control." "0,1"
line.long 0x4 "USB1CLKCTRL,USB1 clock control"
bitfld.long 0x4 4. "HS_DEV_WAKEUP_N,External user wake-up signal for device mode; asserting this signal (active low) will result in exiting the low power mode; input to asynchronous control logic." "0,1"
bitfld.long 0x4 3. "POL_FS_HOST_CLK,USB1 Host need_clock polarity for triggering the USB1 wake-up interrupt." "0,1"
newline
bitfld.long 0x4 2. "AP_FS_HOST_CLK,USB1 Host need_clock signal control." "0,1"
bitfld.long 0x4 1. "POL_FS_DEV_CLK,USB1 Device need_clock polarity for triggering the USB1 wake-up interrupt." "0,1"
newline
bitfld.long 0x4 0. "AP_FS_DEV_CLK,USB1 Device need_clock signal control." "0,1"
line.long 0x8 "USB1CLKSTAT,USB1 clock status"
bitfld.long 0x8 1. "HOST_NEED_CLKST,USB1 Device host USB1_NEEDCLK signal status." "0,1"
bitfld.long 0x8 0. "DEV_NEED_CLKST,USB1 Device USB1_NEEDCLK signal status." "0,1"
group.long 0x444++0x13
line.long 0x0 "EMCSYSCTRL,EMC system control"
bitfld.long 0x0 3. "EMCFBCLKINSEL,External Memory Controller clock select." "0,1"
bitfld.long 0x0 2. "EMCBC,External Memory Controller burst control." "0,1"
newline
bitfld.long 0x0 1. "EMCRD,EMC Reset Disable." "0,1"
bitfld.long 0x0 0. "EMCSC,EMC Shift Control." "0,1"
line.long 0x4 "EMCDLYCTRL,EMC clock delay control"
hexmask.long.byte 0x4 8.--12. 1. "FBCLK_DELAY,Programmable delay value for the feedback clock that controls input data sampling."
hexmask.long.byte 0x4 0.--4. 1. "CMD_DELAY,Programmable delay value for EMC outputs in command delayed mode."
line.long 0x8 "EMCDLYCAL,EMC delay chain calibration control"
bitfld.long 0x8 15. "DONE,Measurement completion flag." "0,1"
bitfld.long 0x8 14. "START,Start control bit for the EMC calibration counter." "0,1"
newline
hexmask.long.byte 0x8 0.--7. 1. "CALVALUE,Returns the count of the approximately 50 MHz ring oscillator that occur during 32 clocks of the FRO 12 MHz."
line.long 0xC "ETHPHYSEL,Ethernet PHY Selection"
bitfld.long 0xC 2. "PHY_SEL,PHY interface select." "0,1"
line.long 0x10 "ETHSBDCTRL,Ethernet SBD flow control"
bitfld.long 0x10 0.--1. "SBD_CTRL,Sideband Flow Control." "0,1,2,3"
group.long 0x460++0x3
line.long 0x0 "SDIOCLKCTRL,SDIO CCLKIN phase and delay control"
bitfld.long 0x0 31. "CCLK_SAMPLE_DELAY_ACTIVE,Enables sample delay  as controlled by the CCLK_SAMPLE_DELAY field." "0,1"
hexmask.long.byte 0x0 24.--28. 1. "CCLK_SAMPLE_DELAY,Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in."
newline
bitfld.long 0x0 23. "CCLK_DRV_DELAY_ACTIVE,Enables drive delay  as controlled by the CCLK_DRV_DELAY field." "0,1"
hexmask.long.byte 0x0 16.--20. 1. "CCLK_DRV_DELAY,Programmable delay value by which cclk_in_drv is delayed with regard to cclk_in."
newline
bitfld.long 0x0 7. "PHASE_ACTIVE,sdio_clk by 2  before feeding into ccl_in  cclk_in_sample  and cclk_in_drv." "0,1"
bitfld.long 0x0 2.--3. "CCLK_SAMPLE_PHASE,Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in." "0,1,2,3"
newline
bitfld.long 0x0 0.--1. "CCLK_DRV_PHASE,Programmable delay value by which cclk_in_drv is phase-shifted with regard to cclk_in." "0,1,2,3"
group.long 0x500++0xF
line.long 0x0 "FROCTRL,FRO oscillator control"
bitfld.long 0x0 31. "WRTRIM,Write Trim value." "0,1"
bitfld.long 0x0 30. "HSPDCLK,High speed clock enable." "0,1"
newline
bitfld.long 0x0 25. "USBMODCHG,USB Mode value Change flag." "0,1"
bitfld.long 0x0 24. "USBCLKADJ,USB clock adjust mode." "0,1"
newline
hexmask.long.byte 0x0 16.--23. 1. "FREQTRIM,Frequency trim."
bitfld.long 0x0 14. "SEL,Select the FRO HF output frequency." "0,1"
newline
hexmask.long.word 0x0 0.--13. 1. "TRIM,This value is factory trimmed to account for bias and temperature compensation."
line.long 0x4 "SYSOSCCTRL,System oscillator control"
bitfld.long 0x4 1. "FREQRANGE,Determines frequency range for system oscillator." "0,1"
bitfld.long 0x4 0. "BYPASS,Bypass system oscillator." "0,1"
line.long 0x8 "WDTOSCCTRL,Watchdog oscillator control"
hexmask.long.byte 0x8 5.--9. 1. "FREQSEL,Frequency select."
hexmask.long.byte 0x8 0.--4. 1. "DIVSEL,Divider select."
line.long 0xC "RTCOSCCTRL,RTC oscillator 32 kHz output control"
bitfld.long 0xC 0. "EN,RTC 32 kHz clock enable." "0,1"
group.long 0x51C++0x7
line.long 0x0 "USBPLLCTRL,USB PLL control"
bitfld.long 0x0 14. "FBSEL,Feedback divider input clock control." "0,1"
bitfld.long 0x0 13. "BYPASS,Input clock bypass control." "0: CCO clock is sent to post dividers..,1: PLL input clock is sent to post dividers.."
newline
bitfld.long 0x0 12. "DIRECT,Direct CCO clock output control." "0: CCO Clock signal goes through post divider.,1: CCO Clock signal goes directly to output(s).."
bitfld.long 0x0 10.--11. "NSEL,PLL feedback Divider value." "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "PSEL,PLL Divider value." "0,1,2,3"
hexmask.long.byte 0x0 0.--7. 1. "MSEL,PLL feedback Divider value."
line.long 0x4 "USBPLLSTAT,USB PLL status"
bitfld.long 0x4 0. "LOCK,USBPLL lock indicator." "0,1"
group.long 0x580++0x13
line.long 0x0 "SYSPLLCTRL,System PLL control"
bitfld.long 0x0 20. "DIRECTO,PLL0 direct output enable." "0: Disabled. The PLL output divider (P divider) is..,1: Enabled. The PLL output divider (P divider) is.."
bitfld.long 0x0 19. "DIRECTI,PLL0 direct input enable." "0,1"
newline
bitfld.long 0x0 17. "UPLIMOFF,Disable upper frequency limiter." "0,1"
bitfld.long 0x0 15. "BYPASS,PLL bypass control." "0: Bypass disabled. PLL CCO is sent to the PLL..,1: Bypass enabled. PLL input clock is sent directly.."
newline
hexmask.long.byte 0x0 10.--14. 1. "SELP,Bandwidth select P value."
hexmask.long.byte 0x0 4.--9. 1. "SELI,Bandwidth select I value."
newline
hexmask.long.byte 0x0 0.--3. 1. "SELR,Bandwidth select R value."
line.long 0x4 "SYSPLLSTAT,PLL status"
bitfld.long 0x4 0. "LOCK,PLL lock indicator." "0,1"
line.long 0x8 "SYSPLLNDEC,PLL N divider"
bitfld.long 0x8 10. "NREQ,NDEC reload request." "0,1"
hexmask.long.word 0x8 0.--9. 1. "NDEC,Decoded N-divider coefficient value."
line.long 0xC "SYSPLLPDEC,PLL P divider"
bitfld.long 0xC 7. "PREQ,." "0,1"
hexmask.long.byte 0xC 0.--6. 1. "PDEC,Decoded P-divider coefficient value."
line.long 0x10 "SYSPLLMDEC,System PLL M divider"
bitfld.long 0x10 17. "MREQ,MDEC reload request." "0,1"
hexmask.long.tbyte 0x10 0.--16. 1. "MDEC,Decoded M-divider coefficient value."
group.long 0x5A0++0x17
line.long 0x0 "AUDPLLCTRL,Audio PLL control"
bitfld.long 0x0 20. "DIRECTO,PLL direct output enable" "0: Disabled. The PLL output divider (P divider) is..,1: Enabled. The PLL output divider (P divider) is.."
bitfld.long 0x0 19. "DIRECTI,PLL direct input enable." "0,1"
newline
bitfld.long 0x0 17. "UPLIMOFF,Disable upper frequency limiter." "0,1"
bitfld.long 0x0 15. "BYPASS,PLL bypass control." "0: Bypass disabled. PLL CCO is sent to the PLL..,1: Bypass enabled. PLL input clock is sent directly.."
newline
hexmask.long.byte 0x0 10.--14. 1. "SELP,."
hexmask.long.byte 0x0 4.--9. 1. "SELI,Bandwidth select I value."
newline
hexmask.long.byte 0x0 0.--3. 1. "SELR,Bandwidth select R value."
line.long 0x4 "AUDPLLSTAT,Audio PLL status"
bitfld.long 0x4 0. "LOCK,PLL lock indicator." "0,1"
line.long 0x8 "AUDPLLNDEC,Audio PLL N divider"
bitfld.long 0x8 10. "NREQ,NDEC reload request." "0,1"
hexmask.long.word 0x8 0.--9. 1. "NDEC,Decoded N-divider coefficient value."
line.long 0xC "AUDPLLPDEC,Audio PLL P divider"
bitfld.long 0xC 7. "PREQ,PDEC reload request." "0,1"
hexmask.long.byte 0xC 0.--6. 1. "PDEC,Decoded P-divider coefficient value."
line.long 0x10 "AUDPLLMDEC,Audio PLL M divider"
bitfld.long 0x10 17. "MREQ,MDEC reload request." "0,1"
hexmask.long.tbyte 0x10 0.--16. 1. "MDEC,Decoded M-divider coefficient value."
line.long 0x14 "AUDPLLFRAC,Audio PLL fractional divider control"
bitfld.long 0x14 23. "SEL_EXT,Select fractional divider." "0,1"
bitfld.long 0x14 22. "REQ,Writing 1 to REQ signal loads CTRL value into fractional wrapper modulator." "0,1"
newline
hexmask.long.tbyte 0x14 0.--21. 1. "CTRL,PLL fractional divider control word"
group.long 0x600++0x7
line.long 0x0 "PDSLEEPCFG0,Sleep configuration register"
bitfld.long 0x0 29. "PDEN_VD6,Power control for EEPROM." "0,1"
bitfld.long 0x0 28. "PDEN_VD5,Power control both USB0 PHY and USB1 PHY." "0,1"
newline
bitfld.long 0x0 27. "PDEN_VD4,Power control for all SRAMs and ROM." "0,1"
bitfld.long 0x0 26. "PDEN_VD3,Power control for all PLLs." "0,1"
newline
bitfld.long 0x0 23. "PDEN_VREFP,VREFP to the ADC must be enabled for the ADC to work (also enable/disable bit 9  10  and 19)." "0,1"
bitfld.long 0x0 22. "PDEN_SYS_PLL,System PLL (PLL0) power (also enable/disable bit 26)." "0,1"
newline
bitfld.long 0x0 21. "PDEN_USB0_PHY,USB0 PHY power (also enable/disable bit 28)." "0,1"
bitfld.long 0x0 20. "PDEN_WDT_OSC,Watchdog oscillator." "0,1"
newline
bitfld.long 0x0 19. "PDEN_VDDA,Vdda to the ADC  must be enabled for the ADC to work (also enable/disable bit 9  10  and 23)." "0,1"
bitfld.long 0x0 17. "PDEN_ROM,ROM (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 16. "PDEN_USB_RAM,PDEN_USB_SRAM controls USB_RAM (also enable/disable bit 27)." "0,1"
bitfld.long 0x0 15. "PDEN_SRAM1_2_3,PDEN_SRAM1_2_3 controls SRAM1  SRAM2  and SRAM3 (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 14. "PDEN_SRAM0,PDEN_SRAM0 controls SRAM0 (also enable/disable bit 27)." "0,1"
bitfld.long 0x0 13. "PDEN_SRAMX,PDEN_SRAMX controls SRAMX (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 10. "PDEN_ADC0,ADC power." "0,1"
bitfld.long 0x0 9. "PDEN_VD2_ANA,Analog supply for System Oscillator (also enable/disable bit 3 in PDRUNCFG1 register)  Temperature Sensor (also  enable/disable bit 6)  ADC (also  enable/disable bits 10  19  and 23)." "0,1"
newline
bitfld.long 0x0 8. "PDEN_BOD_INTR,Brown-out Detect interrupt." "0,1"
bitfld.long 0x0 7. "PDEN_BOD_RST,Brown-out Detect reset." "0,1"
newline
bitfld.long 0x0 6. "PDEN_TS,Temp sensor." "0,1"
bitfld.long 0x0 4. "PDEN_FRO,FRO oscillator." "0,1"
line.long 0x4 "PDSLEEPCFG1,Sleep configuration register"
bitfld.long 0x4 7. "PDEN_RNG,Random Number Generator Power." "0,1"
bitfld.long 0x4 5. "PDEN_EEPROM,EEPROM power (also  enable/disable bit 29 in PDRUNCFG0 register)." "0,1"
newline
bitfld.long 0x4 3. "PDEN_SYSOSC,System Oscillator Power (also  enable/disable bit 9 in PDRUNCFG0 register)." "0,1"
bitfld.long 0x4 2. "PDEN_AUD_PLL,Audio PLL (PLL2) power and fractional divider (also  enable/disable bit 26 in PDRUNCFG0 register)." "0,1"
newline
bitfld.long 0x4 1. "PDEN_USB1_PLL,USB PLL (PLL1) power (also  enable/disable bit 26 in PDRUNCFG0 register)." "0,1"
bitfld.long 0x4 0. "PDEN_USB1_PHY,USB1 high speed PHY (also  enable/disable bit 28 in PDRUNCFG0 register)." "0,1"
group.long 0x610++0x7
line.long 0x0 "PDRUNCFG0,Power configuration register"
bitfld.long 0x0 29. "PDEN_VD6,Power control for EEPROM." "0,1"
bitfld.long 0x0 28. "PDEN_VD5,Power control both USB0 PHY and USB1 PHY." "0,1"
newline
bitfld.long 0x0 27. "PDEN_VD4,Power control for all SRAMs and ROM." "0,1"
bitfld.long 0x0 26. "PDEN_VD3,Power control for all PLLs." "0,1"
newline
bitfld.long 0x0 23. "PDEN_VREFP,VREFP to the ADC must be enabled for the ADC to work (also enable/disable bit 9  10  and 19)." "0,1"
bitfld.long 0x0 22. "PDEN_SYS_PLL,System PLL (PLL0) power (also enable/disable bit 26)." "0,1"
newline
bitfld.long 0x0 21. "PDEN_USB0_PHY,USB0 PHY power (also enable/disable bit 28)." "0,1"
bitfld.long 0x0 20. "PDEN_WDT_OSC,Watchdog oscillator." "0,1"
newline
bitfld.long 0x0 19. "PDEN_VDDA,Vdda to the ADC  must be enabled for the ADC to work (also enable/disable bit 9  10  and 23)." "0,1"
bitfld.long 0x0 17. "PDEN_ROM,ROM (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 16. "PDEN_USB_RAM,PDEN_USB_SRAM controls USB_RAM (also enable/disable bit 27)." "0,1"
bitfld.long 0x0 15. "PDEN_SRAM1_2_3,PDEN_SRAM1_2_3 controls SRAM1  SRAM2  and SRAM3 (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 14. "PDEN_SRAM0,PDEN_SRAM0 controls SRAM0 (also enable/disable bit 27)." "0,1"
bitfld.long 0x0 13. "PDEN_SRAMX,PDEN_SRAMX controls SRAMX (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 10. "PDEN_ADC0,ADC power." "0,1"
bitfld.long 0x0 9. "PDEN_VD2_ANA,Analog supply for System Oscillator (also enable/disable bit 3 in PDRUNCFG1 register)  Temperature Sensor (also  enable/disable bit 6)  ADC (also  enable/disable bits 10  19  and 23)." "0,1"
newline
bitfld.long 0x0 8. "PDEN_BOD_INTR,Brown-out Detect interrupt." "0,1"
bitfld.long 0x0 7. "PDEN_BOD_RST,Brown-out Detect reset." "0,1"
newline
bitfld.long 0x0 6. "PDEN_TS,Temp sensor." "0,1"
bitfld.long 0x0 4. "PDEN_FRO,FRO oscillator." "0,1"
line.long 0x4 "PDRUNCFG1,Power configuration register"
bitfld.long 0x4 7. "PDEN_RNG,Random Number Generator Power." "0,1"
bitfld.long 0x4 5. "PDEN_EEPROM,EEPROM power (also  enable/disable bit 29 in PDRUNCFG0 register)." "0,1"
newline
bitfld.long 0x4 3. "PDEN_SYSOSC,System Oscillator Power (also  enable/disable bit 9 in PDRUNCFG0 register)." "0,1"
bitfld.long 0x4 2. "PDEN_AUD_PLL,Audio PLL (PLL2) power and fractional divider (also  enable/disable bit 26 in PDRUNCFG0 register)." "0,1"
newline
bitfld.long 0x4 1. "PDEN_USB1_PLL,USB PLL (PLL1) power (also  enable/disable bit 26 in PDRUNCFG0 register)." "0,1"
bitfld.long 0x4 0. "PDEN_USB1_PHY,USB1 high speed PHY (also  enable/disable bit 28 in PDRUNCFG0 register)." "0,1"
group.long 0x620++0x7
line.long 0x0 "PDRUNCFGSET0,Power configuration set register"
bitfld.long 0x0 29. "PDEN_VD6,Power control for EEPROM." "0,1"
bitfld.long 0x0 28. "PDEN_VD5,Power control both USB0 PHY and USB1 PHY." "0,1"
newline
bitfld.long 0x0 27. "PDEN_VD4,Power control for all SRAMs and ROM." "0,1"
bitfld.long 0x0 26. "PDEN_VD3,Power control for all PLLs." "0,1"
newline
bitfld.long 0x0 23. "PDEN_VREFP,VREFP to the ADC must be enabled for the ADC to work (also enable/disable bit 9  10  and 19)." "0,1"
bitfld.long 0x0 22. "PDEN_SYS_PLL,System PLL (PLL0) power (also enable/disable bit 26)." "0,1"
newline
bitfld.long 0x0 21. "PDEN_USB0_PHY,USB0 PHY power (also enable/disable bit 28)." "0,1"
bitfld.long 0x0 20. "PDEN_WDT_OSC,Watchdog oscillator." "0,1"
newline
bitfld.long 0x0 19. "PDEN_VDDA,Vdda to the ADC  must be enabled for the ADC to work (also enable/disable bit 9  10  and 23)." "0,1"
bitfld.long 0x0 17. "PDEN_ROM,ROM (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 16. "PDEN_USB_RAM,PDEN_USB_SRAM controls USB_RAM (also enable/disable bit 27)." "0,1"
bitfld.long 0x0 15. "PDEN_SRAM1_2_3,PDEN_SRAM1_2_3 controls SRAM1  SRAM2  and SRAM3 (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 14. "PDEN_SRAM0,PDEN_SRAM0 controls SRAM0 (also enable/disable bit 27)." "0,1"
bitfld.long 0x0 13. "PDEN_SRAMX,PDEN_SRAMX controls SRAMX (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 10. "PDEN_ADC0,ADC power." "0,1"
bitfld.long 0x0 9. "PDEN_VD2_ANA,Analog supply for System Oscillator (also enable/disable bit 3 in PDRUNCFG1 register)  Temperature Sensor (also  enable/disable bit 6)  ADC (also  enable/disable bits 10  19  and 23)." "0,1"
newline
bitfld.long 0x0 8. "PDEN_BOD_INTR,Brown-out Detect interrupt." "0,1"
bitfld.long 0x0 7. "PDEN_BOD_RST,Brown-out Detect reset." "0,1"
newline
bitfld.long 0x0 6. "PDEN_TS,Temp sensor." "0,1"
bitfld.long 0x0 4. "PDEN_FRO,FRO oscillator." "0,1"
line.long 0x4 "PDRUNCFGSET1,Power configuration set register"
bitfld.long 0x4 7. "PDEN_RNG,Random Number Generator Power." "0,1"
bitfld.long 0x4 5. "PDEN_EEPROM,EEPROM power (also  enable/disable bit 29 in PDRUNCFG0 register)." "0,1"
newline
bitfld.long 0x4 3. "PDEN_SYSOSC,System Oscillator Power (also  enable/disable bit 9 in PDRUNCFG0 register)." "0,1"
bitfld.long 0x4 2. "PDEN_AUD_PLL,Audio PLL (PLL2) power and fractional divider (also  enable/disable bit 26 in PDRUNCFG0 register)." "0,1"
newline
bitfld.long 0x4 1. "PDEN_USB1_PLL,USB PLL (PLL1) power (also  enable/disable bit 26 in PDRUNCFG0 register)." "0,1"
bitfld.long 0x4 0. "PDEN_USB1_PHY,USB1 high speed PHY (also  enable/disable bit 28 in PDRUNCFG0 register)." "0,1"
group.long 0x630++0x7
line.long 0x0 "PDRUNCFGCLR0,Power configuration clear register"
bitfld.long 0x0 29. "PDEN_VD6,Power control for EEPROM." "0,1"
bitfld.long 0x0 28. "PDEN_VD5,Power control both USB0 PHY and USB1 PHY." "0,1"
newline
bitfld.long 0x0 27. "PDEN_VD4,Power control for all SRAMs and ROM." "0,1"
bitfld.long 0x0 26. "PDEN_VD3,Power control for all PLLs." "0,1"
newline
bitfld.long 0x0 23. "PDEN_VREFP,VREFP to the ADC must be enabled for the ADC to work (also enable/disable bit 9  10  and 19)." "0,1"
bitfld.long 0x0 22. "PDEN_SYS_PLL,System PLL (PLL0) power (also enable/disable bit 26)." "0,1"
newline
bitfld.long 0x0 21. "PDEN_USB0_PHY,USB0 PHY power (also enable/disable bit 28)." "0,1"
bitfld.long 0x0 20. "PDEN_WDT_OSC,Watchdog oscillator." "0,1"
newline
bitfld.long 0x0 19. "PDEN_VDDA,Vdda to the ADC  must be enabled for the ADC to work (also enable/disable bit 9  10  and 23)." "0,1"
bitfld.long 0x0 17. "PDEN_ROM,ROM (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 16. "PDEN_USB_RAM,PDEN_USB_SRAM controls USB_RAM (also enable/disable bit 27)." "0,1"
bitfld.long 0x0 15. "PDEN_SRAM1_2_3,PDEN_SRAM1_2_3 controls SRAM1  SRAM2  and SRAM3 (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 14. "PDEN_SRAM0,PDEN_SRAM0 controls SRAM0 (also enable/disable bit 27)." "0,1"
bitfld.long 0x0 13. "PDEN_SRAMX,PDEN_SRAMX controls SRAMX (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 10. "PDEN_ADC0,ADC power." "0,1"
bitfld.long 0x0 9. "PDEN_VD2_ANA,Analog supply for System Oscillator (also enable/disable bit 3 in PDRUNCFG1 register)  Temperature Sensor (also  enable/disable bit 6)  ADC (also  enable/disable bits 10  19  and 23)." "0,1"
newline
bitfld.long 0x0 8. "PDEN_BOD_INTR,Brown-out Detect interrupt." "0,1"
bitfld.long 0x0 7. "PDEN_BOD_RST,Brown-out Detect reset." "0,1"
newline
bitfld.long 0x0 6. "PDEN_TS,Temp sensor." "0,1"
bitfld.long 0x0 4. "PDEN_FRO,FRO oscillator." "0,1"
line.long 0x4 "PDRUNCFGCLR1,Power configuration clear register"
bitfld.long 0x4 7. "PDEN_RNG,Random Number Generator Power." "0,1"
bitfld.long 0x4 5. "PDEN_EEPROM,EEPROM power (also  enable/disable bit 29 in PDRUNCFG0 register)." "0,1"
newline
bitfld.long 0x4 3. "PDEN_SYSOSC,System Oscillator Power (also  enable/disable bit 9 in PDRUNCFG0 register)." "0,1"
bitfld.long 0x4 2. "PDEN_AUD_PLL,Audio PLL (PLL2) power and fractional divider (also  enable/disable bit 26 in PDRUNCFG0 register)." "0,1"
newline
bitfld.long 0x4 1. "PDEN_USB1_PLL,USB PLL (PLL1) power (also  enable/disable bit 26 in PDRUNCFG0 register)." "0,1"
bitfld.long 0x4 0. "PDEN_USB1_PHY,USB1 high speed PHY (also  enable/disable bit 28 in PDRUNCFG0 register)." "0,1"
group.long 0x680++0x7
line.long 0x0 "STARTER0,Start logic 0 wake-up enable register"
bitfld.long 0x0 29. "RTC,RTC interrupt alarm and wake-up timer." "0,1"
bitfld.long 0x0 28. "USB0,USB function interrupt wake-up." "0,1"
newline
bitfld.long 0x0 27. "USB0_NEEDCLK,USB activity interrupt wake-up." "0,1"
bitfld.long 0x0 26. "HWVAD,Hardware voice activity detect interrupt wake-up." "0,1"
newline
bitfld.long 0x0 25. "DMIC,Digital microphone interrupt wake-up." "0,1"
bitfld.long 0x0 24. "ADC0_THCMP,ADC0 threshold and error interrupt wake-up." "0,1"
newline
bitfld.long 0x0 23. "ADC0_SEQB,ADC0 sequence B interrupt wake-up." "0,1"
bitfld.long 0x0 22. "ADC0_SEQA,ADC0 sequence A interrupt wake-up." "0,1"
newline
bitfld.long 0x0 21. "FLEXCOMM7,Flexcomm7 peripheral interrupt wake-up." "0,1"
bitfld.long 0x0 20. "FLEXCOMM6,Flexcomm6 peripheral interrupt wake-up." "0,1"
newline
bitfld.long 0x0 19. "FLEXCOMM5,Flexcomm5 peripheral interrupt wake-up." "0,1"
bitfld.long 0x0 18. "FLEXCOMM4,Flexcomm4 peripheral interrupt wake-up." "0,1"
newline
bitfld.long 0x0 17. "FLEXCOMM3,Flexcomm3 peripheral interrupt wake-up." "0,1"
bitfld.long 0x0 16. "FLEXCOMM2,Flexcomm2 peripheral interrupt wake-up." "0,1"
newline
bitfld.long 0x0 15. "FLEXCOMM1,Flexcomm1 peripheral interrupt wake-up." "0,1"
bitfld.long 0x0 14. "FLEXCOMM0,Flexcomm0 peripheral interrupt wake-up." "0,1"
newline
bitfld.long 0x0 13. "CTIMER3,Standard counter/timer CTIMER3 wake-up." "0,1"
bitfld.long 0x0 12. "SCT0,SCT0 wake-up." "0,1"
newline
bitfld.long 0x0 11. "CTIMER1,Standard counter/timer CTIMER1 wake-up." "0,1"
bitfld.long 0x0 10. "CTIMER0,Standard counter/timer CTIMER0 wake-up." "0,1"
newline
bitfld.long 0x0 9. "MRT,Multi-Rate Timer wake-up." "0,1"
bitfld.long 0x0 8. "UTICK,Micro-tick Timer wake-up." "0,1"
newline
bitfld.long 0x0 7. "PIN_INT3,GPIO pin interrupt 3 wake-up." "0,1"
bitfld.long 0x0 6. "PIN_INT2,GPIO pin interrupt 2 wake-up." "0,1"
newline
bitfld.long 0x0 5. "PIN_INT1,GPIO pin interrupt 1 wake-up." "0,1"
bitfld.long 0x0 4. "PIN_INT0,GPIO pin interrupt 0 wake-up." "0,1"
newline
bitfld.long 0x0 3. "GINT1,Group interrupt 1 wake-up." "0,1"
bitfld.long 0x0 2. "GINT0,Group interrupt 0 wake-up." "0,1"
newline
bitfld.long 0x0 1. "DMA,DMA wake-up." "0,1"
bitfld.long 0x0 0. "WDT_BOD,WWDT and BOD interrupt wake-up." "0,1"
line.long 0x4 "STARTER1,Start logic 0 wake-up enable register"
bitfld.long 0x4 24. "SMARTCARD1,Smart card 1 wake-up." "0,1"
bitfld.long 0x4 23. "SMARTCARD0,Smart card 0 wake-up." "0,1"
newline
bitfld.long 0x4 19. "ENET_INT0,Ethernet." "0,1"
bitfld.long 0x4 18. "ENET_INT2,Ethernet." "0,1"
newline
bitfld.long 0x4 17. "ENET_INT1,Ethernet." "0,1"
bitfld.long 0x4 16. "USB1_ACT,USB 1 activity wake-up." "0,1"
newline
bitfld.long 0x4 15. "USB1,USB 1 wake-up." "0,1"
bitfld.long 0x4 9. "FLEXCOMM9,Flexcomm Interface 9 wake-up." "0,1"
newline
bitfld.long 0x4 8. "FLEXCOMM8,Flexcomm Interface 8 wake-up." "0,1"
bitfld.long 0x4 7. "SPIFI,SPIFI interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled." "0: Wake-up disabled,1: Wake-up enabled"
newline
bitfld.long 0x4 5. "CTIMER4,Standard counter/timer CTIMER4 wake-up." "0,1"
bitfld.long 0x4 4. "CTIMER2,Standard counter/timer CTIMER2 wake-up." "0,1"
newline
bitfld.long 0x4 3. "PINT7,GPIO pin interrupt 7 wake-up." "0,1"
bitfld.long 0x4 2. "PINT6,GPIO pin interrupt 6 wake-up." "0,1"
newline
bitfld.long 0x4 1. "PINT5,GPIO pin interrupt 5 wake-up." "0,1"
bitfld.long 0x4 0. "PINT4,GPIO pin interrupt 4 wake-up." "0,1"
group.long 0x780++0x3
line.long 0x0 "HWWAKE,Configures special cases of hardware wake-up"
bitfld.long 0x0 3. "WAKEDMA,Wake for DMA. When 1  DMA being busy will cause peripheral clocking to remain running until DMA completes. This is generally used in conjunction with bit 1 and/or 2 in order to prevent peripheral clocking from being shut down as soon as the cause.." "0,1"
bitfld.long 0x0 2. "WAKEDMIC,Wake for Digital Microphone. When 1  the digital microphone input FIFO reaching the level specified by TRIGLVL of either channel will cause peripheral clocking to wake up temporarily while the related status is asserted." "0,1"
newline
bitfld.long 0x0 1. "FCWAKE,Wake for Flexcomms. When 1  any Flexcomm FIFO reaching the level specified by its own TXLVL will cause peripheral clocking to wake up temporarily while the related status is asserted." "0,1"
bitfld.long 0x0 0. "FORCEWAKE,Force peripheral clocking to stay on during Deep Sleep and Power-down modes. When 1  clocking to peripherals is prevented from being shut down when the CPU enters Deep Sleep and Power-down modes. This is intended to allow a coprocessor to.." "0,1"
group.long 0xE04++0x3
line.long 0x0 "AUTOCGOR,Auto Clock-Gate Override Register"
bitfld.long 0x0 4. "RAM3,When 1  automatic clock gating for RAM1 are turned off." "0,1"
bitfld.long 0x0 3. "RAM2,When 1  automatic clock gating for RAM1 are turned off." "0,1"
newline
bitfld.long 0x0 2. "RAM1,When 1  automatic clock gating for RAM1 are turned off." "0,1"
bitfld.long 0x0 1. "RAM0X,When 1  automatic clock gating for RAMX and RAM0 are turned off." "0,1"
rgroup.long 0xFF4++0xB
line.long 0x0 "JTAGIDCODE,JTAG ID code register"
hexmask.long 0x0 0.--31. 1. "JTAGID,JTAG ID code."
line.long 0x4 "DEVICE_ID0,Part ID register"
hexmask.long 0x4 0.--31. 1. "PARTID,Part ID"
line.long 0x8 "DEVICE_ID1,Boot ROM and die revision register"
hexmask.long 0x8 0.--31. 1. "REVID,Revision."
group.long 0x20044++0x3
line.long 0x0 "BODCTRL,Brown-Out Detect control"
bitfld.long 0x0 7. "BODINTSTAT,BOD interrupt status. When 1  a BOD interrupt has occurred. Cleared by writing 1 to this bit." "0,1"
bitfld.long 0x0 6. "BODRSTSTAT,BOD reset status. When 1  a BOD reset has occurred. Cleared by writing 1 to this bit." "0,1"
newline
bitfld.long 0x0 5. "BODINTENA,BOD interrupt enable" "0: Disable interrupt function.,1: Enable interrupt function."
bitfld.long 0x0 3.--4. "BODINTLEV,BOD interrupt level" "0: Level 0: 2.05 V,1: Level 1: 2.45 V,2: Level 2: 2.75 V,3: Level 3: 3.05 V"
newline
bitfld.long 0x0 2. "BODRSTENA,BOD reset enable" "0: Disable reset function.,1: Enable reset function."
bitfld.long 0x0 0.--1. "BODRSTLEV,BOD reset level" "0: Level 0: 1.5 V,1: Level 1: 1.85 V,2: Level 2: 2.0 V,3: Level 3: 2.3 V"
endif
sif (cpuis("LPC54616*"))
group.long 0x10++0x3
line.long 0x0 "AHBMATPRIO,AHB multilayer matrix priority control"
bitfld.long 0x0 24.--25. "PRI_SHA,SHA priority." "0,1,2,3"
bitfld.long 0x0 22.--23. "PRI_MCAN2,MCAN2 priority." "0,1,2,3"
newline
bitfld.long 0x0 20.--21. "PRI_MCAN1,MCAN1 priority." "0,1,2,3"
bitfld.long 0x0 18.--19. "PRI_SDIO,SDIO priority." "0,1,2,3"
newline
bitfld.long 0x0 16.--17. "PRI_USB1,USB1 DMA priority." "0,1,2,3"
bitfld.long 0x0 14.--15. "PRI_USB0,USB0 DMA priority." "0,1,2,3"
newline
bitfld.long 0x0 12.--13. "PRI_LCD,LCD DMA priority." "0,1,2,3"
bitfld.long 0x0 10.--11. "PRI_ETH,Ethernet DMA priority." "0,1,2,3"
newline
hexmask.long.byte 0x0 6.--9. 1. "PRI_DMA,DMA controller priority."
bitfld.long 0x0 4.--5. "PRI_SYS,System bus priority." "0,1,2,3"
newline
bitfld.long 0x0 2.--3. "PRI_DCODE,D-Code bus priority." "0,1,2,3"
bitfld.long 0x0 0.--1. "PRI_ICODE,I-Code bus priority." "0,1,2,3"
group.long 0x40++0x3
line.long 0x0 "SYSTCKCAL,System tick counter calibration"
bitfld.long 0x0 25. "NOREF,Initial value for the Systick timer." "0,1"
bitfld.long 0x0 24. "SKEW,Initial value for the Systick timer." "0,1"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "CAL,System tick timer calibration value."
group.long 0x48++0x7
line.long 0x0 "NMISRC,NMI Source Select"
bitfld.long 0x0 31. "NMIENM4,Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQM4." "0,1"
hexmask.long.byte 0x0 0.--5. 1. "IRQM4,The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the Cortex-M4  if enabled by NMIENM4."
line.long 0x4 "ASYNCAPBCTRL,Asynchronous APB Control"
bitfld.long 0x4 0. "ENABLE,Enables the asynchronous APB bridge and subsystem." "0: Disabled. Asynchronous APB bridge is disabled.,1: Enabled. Asynchronous APB bridge is enabled."
endif
sif (cpuis("LPC54616*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0xC0)++0x3
line.long 0x0 "PIOPORCAP[$1],POR captured value of port n"
hexmask.long 0x0 0.--31. 1. "PIOPORCAP,State of PIOn_31 through PIOn_0 at power-on reset"
repeat.end
endif
sif (cpuis("LPC54616*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0xD0)++0x3
line.long 0x0 "PIORESCAP[$1],Reset captured value of port n"
hexmask.long 0x0 0.--31. 1. "PIORESCAP,State of PIOn_31 through PIOn_0 for resets other than POR."
repeat.end
group.long 0x100++0xB
line.long 0x0 "PRESETCTRL0,Peripheral reset control n"
bitfld.long 0x0 27. "ADC0_RST,ADC0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 22. "WWDT_RST,Watchdog timer reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x0 21. "CRC_RST,CRC generator reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 20. "DMA0_RST,DMA0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x0 19. "GINT_RST,Grouped interrupt (GINT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 18. "PINT_RST,Pin interrupt (PINT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x0 17. "GPIO3_RST,GPIO3 reset control." "0,1"
bitfld.long 0x0 16. "GPIO2_RST,GPIO2 reset control." "0,1"
newline
bitfld.long 0x0 15. "GPIO1_RST,GPIO1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 14. "GPIO0_RST,GPIO0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x0 13. "IOCON_RST,IOCON reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 11. "MUX_RST,Input mux reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x0 10. "SPIFI_RST,SPIFI reset control." "0,1"
bitfld.long 0x0 9. "EEPROM_RST,EEPROM reset control." "0,1"
newline
bitfld.long 0x0 8. "FMC_RST,Flash accelerator reset control. Note that the FMC must not be reset while executing from flash  and must be reconfigured after reset. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 7. "FLASH_RST,Flash controller reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
line.long 0x4 "PRESETCTRL1,Peripheral reset control n"
bitfld.long 0x4 27. "CTIMER1_RST,CTIMER1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 26. "CTIMER0_RST,CTIMER0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 25. "USB0D_RST,USB0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 22. "CTIMER2_RST,CTIMER2 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function" "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 19. "DMIC_RST,Digital microphone interface reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 18. "FC7_RST,Flexcomm 7 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 17. "FC6_RST,Flexcomm 6 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 16. "FC5_RST,Flexcomm 5 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 15. "FC4_RST,Flexcomm 4 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 14. "FC3_RST,Flexcomm 3 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 13. "FC2_RST,Flexcomm 2 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 12. "FC1_RST,Flexcomm 1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 11. "FC0_RST,Flexcomm 0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 10. "UTICK_RST,Micro-tick Timer reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 8. "MCAN1_RST,0 = Clear reset to this function." "0: Clear reset to this function,?"
bitfld.long 0x4 7. "MCAN0_RST,0 = Clear reset to this function." "0: Clear reset to this function,?"
newline
bitfld.long 0x4 2. "SCT0_RST,State configurable timer 0 (SCT0) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 0. "MRT_RST,Multi-rate timer (MRT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
line.long 0x8 "PRESETCTRL2,Peripheral reset control n"
bitfld.long 0x8 20. "SC1_RST,Smart card 1 reset control." "0,1"
bitfld.long 0x8 19. "SC0_RST,Smart card 0 reset control." "0,1"
newline
bitfld.long 0x8 18. "SHA_RST,SHA reset control." "0,1"
bitfld.long 0x8 17. "USB0HSL_RST,USB0 HOST slave reset control." "0,1"
newline
bitfld.long 0x8 16. "USB0HMR_RST,USB0 HOST master reset control." "0,1"
bitfld.long 0x8 15. "FC9_RST,Flexcomm 9 reset control." "0,1"
newline
bitfld.long 0x8 14. "FC8_RST,Flexcomm 8 reset control." "0,1"
bitfld.long 0x8 13. "RNG_RST,RNG reset control." "0,1"
newline
bitfld.long 0x8 12. "OTP_RST,OTP reset control." "0,1"
bitfld.long 0x8 11. "AES_RST,AES reset control." "0,1"
newline
bitfld.long 0x8 10. "GPIO5_RST,GPIO5 reset control." "0,1"
bitfld.long 0x8 9. "GPIO4_RST,GPIO4 reset control." "0,1"
newline
bitfld.long 0x8 8. "ETH_RST,Ethernet reset control." "0,1"
bitfld.long 0x8 7. "EMC_RESET,EMC reset control." "0,1"
newline
bitfld.long 0x8 6. "USB1RAM_RST,USB1 RAM reset control." "0,1"
bitfld.long 0x8 5. "USB1D_RST,USB1 Device reset control." "0,1"
newline
bitfld.long 0x8 4. "USB1H_RST,USB1 Host reset control." "0,1"
bitfld.long 0x8 3. "SDIO_RST,SDIO reset control." "0,1"
newline
bitfld.long 0x8 2. "LCD_RST,LCD reset control." "0,1"
endif
sif (cpuis("LPC54616*"))
repeat 3. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x120)++0x3
line.long 0x0 "PRESETCTRLSET[$1],Set bits in PRESETCTRLn"
hexmask.long 0x0 0.--31. 1. "RST_SET,Writing ones to this register sets the corresponding bit or bits in the PRESETCTRLn register  if they are implemented. Bits that do not correspond to defined bits in PRESETCTRLn are reserved and only zeroes should be written to them."
repeat.end
endif
sif (cpuis("LPC54616*"))
repeat 3. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x140)++0x3
line.long 0x0 "PRESETCTRLCLR[$1],Clear bits in PRESETCTRLn"
hexmask.long 0x0 0.--31. 1. "RST_CLR,Writing ones to this register clears the corresponding bit or bits in the PRESETCTRLn register  if they are implemented. Bits that do not correspond to defined bits in PRESETCTRLn are reserved and only zeroes should be written to them."
repeat.end
group.long 0x1F0++0x3
line.long 0x0 "SYSRSTSTAT,System reset status register"
bitfld.long 0x0 4. "SYSRST,Status of the software system reset" "0: No System reset detected,1: System reset detected. Writing a one clears this.."
bitfld.long 0x0 3. "BOD,Status of the Brown-out detect reset" "0: No BOD reset detected,1: BOD reset detected. Writing a one clears this.."
newline
bitfld.long 0x0 2. "WDT,Status of the Watchdog reset" "0: No WDT reset detected,1: WDT reset detected. Writing a one clears this.."
bitfld.long 0x0 1. "EXTRST,Status of the external RESET pin. External reset status" "0: No reset event detected.,1: Reset detected. Writing a one clears this reset."
newline
bitfld.long 0x0 0. "POR,POR reset status" "0: No POR detected,1: POR detected. Writing a one clears this reset."
group.long 0x200++0xB
line.long 0x0 "AHBCLKCTRL0,AHB Clock control n"
bitfld.long 0x0 27. "ADC0,Enables the clock for the ADC0 register interface." "0,1"
bitfld.long 0x0 23. "RTC,Enables the bus clock for the RTC. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 22. "WWDT,Enables the clock for the Watchdog Timer. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 21. "CRC,Enables the clock for the CRC engine. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 20. "DMA,Enables the clock for the DMA controller. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 19. "GINT,Enables the clock for the grouped pin interrupt block. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 18. "PINT,Enables the clock for the pin interrupt block.0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 17. "GPIO3,Enables the clock for the GPIO3 port registers." "0,1"
newline
bitfld.long 0x0 16. "GPIO2,Enables the clock for the GPIO2 port registers." "0,1"
bitfld.long 0x0 15. "GPIO1,Enables the clock for the GPIO1 port registers. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 14. "GPIO0,Enables the clock for the GPIO0 port registers. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 13. "IOCON,Enables the clock for the IOCON block. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 11. "INPUTMUX,Enables the clock for the input muxes. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 10. "SPIFI,Enables the clock for the SPIFI. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 9. "EEPROM,Enables the clock for EEPROM." "0,1"
bitfld.long 0x0 8. "FMC,Enables the clock for the Flash accelerator. 0 = Disable; 1 = Enable. This clock is needed if the flash is being read." "0: Disable,1: Enable"
newline
bitfld.long 0x0 7. "FLASH,Enables the clock for the flash controller. 0 = Disable; 1 = Enable. This clock is needed for flash programming  not for flash read." "0: Disable,1: Enable"
bitfld.long 0x0 5. "SRAM3,Enables the clock for SRAM3." "0,1"
newline
bitfld.long 0x0 4. "SRAM2,Enables the clock for SRAM2. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 3. "SRAM1,Enables the clock for SRAM1. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 1. "ROM,Enables the clock for the Boot ROM. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
line.long 0x4 "AHBCLKCTRL1,AHB Clock control n"
bitfld.long 0x4 27. "CTIMER1,Enables the clock for timer CTIMER1. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 26. "CTIMER0,Enables the clock for timer CTIMER0. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 25. "USB0D,Enables the clock for the USB0 device interface. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 22. "CTIMER2,Enables the clock for CTIMER 2. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 19. "DMIC,Enables the clock for the digital microphone interface. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 18. "FLEXCOMM7,Enables the clock for Flexcomm 7. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 17. "FLEXCOMM6,Enables the clock for Flexcomm 6. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 16. "FLEXCOMM5,Enables the clock for Flexcomm 5. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 15. "FLEXCOMM4,Enables the clock for Flexcomm 4. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 14. "FLEXCOMM3,Enables the clock for Flexcomm 3. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 13. "FLEXCOMM2,Enables the clock for Flexcomm 2. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 12. "FLEXCOMM1,Enables the clock for Flexcomm 1. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 11. "FLEXCOMM0,Enables the clock for Flexcomm 0. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 10. "UTICK,Enables the clock for the Micro-tick Timer. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 8. "MCAN1,Enables the clock for MCAN1." "0,1"
bitfld.long 0x4 7. "MCAN0,Enables the clock for MCAN0." "0,1"
newline
bitfld.long 0x4 2. "SCT0,Enables the clock for SCT0." "0,1"
bitfld.long 0x4 1. "RIT,Enables the clock for the Repetitive Interrupt Timer." "0,1"
newline
bitfld.long 0x4 0. "MRT,Enables the clock for the Multi-Rate Timer." "0,1"
line.long 0x8 "AHBCLKCTRL2,AHB Clock control n"
bitfld.long 0x8 20. "SC1,Enables the clock for the Smart card1 interface." "0,1"
bitfld.long 0x8 19. "SC0,Enables the clock for the Smart card0 interface." "0,1"
newline
bitfld.long 0x8 18. "SHA0,Enables the clock for the SHA interface." "0,1"
bitfld.long 0x8 17. "USB0HSL,Enables the clock for the USB host slave interface." "0,1"
newline
bitfld.long 0x8 16. "USB0HMR,Enables the clock for the USB host master interface." "0,1"
bitfld.long 0x8 15. "FLEXCOMM9,Enables the clock for the Flexcomm9 interface." "0,1"
newline
bitfld.long 0x8 14. "FLEXCOMM8,Enables the clock for the Flexcomm8 interface." "0,1"
bitfld.long 0x8 13. "RNG,Enables the clock for the RNG interface." "0,1"
newline
bitfld.long 0x8 12. "OTP,Enables the clock for the OTP interface." "0,1"
bitfld.long 0x8 11. "AES,Enables the clock for the AES interface." "0,1"
newline
bitfld.long 0x8 10. "GPIO5,Enables the clock for the GPIO5 interface." "0,1"
bitfld.long 0x8 9. "GPIO4,Enables the clock for the GPIO4 interface." "0,1"
newline
bitfld.long 0x8 8. "ETH,Enables the clock for the ethernet interface." "0,1"
bitfld.long 0x8 7. "EMC,Enables the clock for the EMC interface." "0,1"
newline
bitfld.long 0x8 6. "USB1RAM,Enables the clock for the USB1 RAM interface." "0,1"
bitfld.long 0x8 5. "USB1D,Enables the clock for the USB1 device interface." "0,1"
newline
bitfld.long 0x8 4. "USB1H,Enables the clock for the USB1 host interface." "0,1"
bitfld.long 0x8 3. "SDIO,Enables the clock for the SDIO interface." "0,1"
newline
bitfld.long 0x8 2. "LCD,Enables the clock for the LCD interface." "0,1"
endif
sif (cpuis("LPC54616*"))
repeat 3. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x220)++0x3
line.long 0x0 "AHBCLKCTRLSET[$1],Set bits in AHBCLKCTRLn"
hexmask.long 0x0 0.--31. 1. "CLK_SET,Writing ones to this register sets the corresponding bit or bits in the AHBCLKCTRLn register  if they are implemented. Bits that do not correspond to defined bits in AHBCLKCTRLn are reserved and only zeroes should be written to them."
repeat.end
endif
sif (cpuis("LPC54616*"))
repeat 3. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x240)++0x3
line.long 0x0 "AHBCLKCTRLCLR[$1],Clear bits in AHBCLKCTRLn"
hexmask.long 0x0 0.--31. 1. "CLK_CLR,Writing ones to this register clears the corresponding bit or bits in the AHBCLKCTRLn register  if they are implemented. Bits that do not correspond to defined bits in AHBCLKCTRLn are reserved and only zeroes should be written to them."
repeat.end
group.long 0x280++0xB
line.long 0x0 "MAINCLKSELA,Main clock source select A"
bitfld.long 0x0 0.--1. "SEL,Clock source for main clock source selector A" "0: FRO 12 MHz (fro_12m),1: CLKIN (clk_in),2: Watchdog oscillator (wdt_clk),3: FRO 96 or 48 MHz (fro_hf)"
line.long 0x4 "MAINCLKSELB,Main clock source select B"
bitfld.long 0x4 0.--1. "SEL,Clock source for main clock source selector B. Selects the clock source for the main clock." "0: MAINCLKSELA. Use the clock source selected in..,?,2: System PLL output (pll_clk),3: RTC oscillator 32 kHz output (32k_clk)"
line.long 0x8 "CLKOUTSELA,CLKOUT clock source select A"
bitfld.long 0x8 0.--2. "SEL,CLKOUT clock source selection" "0: Main clock (main_clk),1: CLKIN (clk_in),2: Watchdog oscillator (wdt_clk),3: FRO 96 or 48 MHz (fro_hf),4: PLL output (pll_clk),5: USB PLL clock (usb_pll_clk),6: Audio PLL clock (audio_pll_clk),7: RTC oscillator 32 kHz output (32k_clk)"
group.long 0x290++0x3
line.long 0x0 "SYSPLLCLKSEL,PLL clock source select"
bitfld.long 0x0 0.--2. "SEL,System PLL clock source selection." "0: FRO 12 MHz (fro_12m),1: CLKIN (clk_in),2: Watchdog oscillator (wdt_clk),3: RTC oscillator 32 kHz output (32k_clk),?,?,?,7: None this may be selected in order to reduce.."
group.long 0x298++0x3
line.long 0x0 "AUDPLLCLKSEL,Audio PLL clock source select"
bitfld.long 0x0 0.--2. "SEL,Audio PLL clock source selection." "0: FRO 12 MHz (fro_12m),1: CLKIN (clk_in),?,?,?,?,?,7: None this may be selected in order to reduce.."
group.long 0x2A0++0xF
line.long 0x0 "SPIFICLKSEL,SPIFI clock source select"
bitfld.long 0x0 0.--2. "SEL,System PLL clock source selection" "0: Main clock (main_clk),1: System PLL output (pll_clk),2: USB PLL clock (usb_pll_clk),3: FRO 96 or 48 MHz (fro_hf),4: Audio PLL clock (audio_pll_clk),?,?,7: None this may be selected in order to reduce.."
line.long 0x4 "ADCCLKSEL,ADC clock source select"
bitfld.long 0x4 0.--2. "SEL,ADC clock source selection" "0: FRO 96 or 48 MHz (fro_hf),1: System PLL output (pll_clk),2: USB PLL clock (usb_pll_clk),3: Audio PLL clock (audio_pll_clk),?,?,?,7: None this may be selected in order to reduce.."
line.long 0x8 "USB0CLKSEL,USB0 clock source select"
bitfld.long 0x8 0.--2. "SEL,USB0 device clock source selection." "0: FRO 96 or 48 MHz (fro_hf),1: System PLL output (pll_clk),2: USB PLL clock (usb_pll_clk),?,?,?,?,7: None this may be selected in order to reduce.."
line.long 0xC "USB1CLKSEL,USB1 clock source select"
bitfld.long 0xC 0.--2. "SEL,USB1 PHY clock source selection." "0: Main clock (main_clk),1: System PLL output (pll_clk),2: USB PLL clock (usb_pll_clk),?,?,?,?,7: None this may be selected in order to reduce.."
endif
sif (cpuis("LPC54616*"))
repeat 10. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2B0)++0x3
line.long 0x0 "FCLKSEL[$1],Flexcomm 0 clock source select"
bitfld.long 0x0 0.--2. "SEL,Flexcomm clock source selection. One per Flexcomm." "0: FRO 12 MHz (fro_12m),1: FRO HF DIV (fro_hf_div),2: Audio PLL clock (audio_pll_clk),3: MCLK pin input when selected in IOCON (mclk_in),4: FRG clock the output of the fractional rate..,?,?,7: None this may be selected in order to reduce.."
repeat.end
group.long 0x2E0++0x3
line.long 0x0 "MCLKCLKSEL,MCLK clock source select"
bitfld.long 0x0 0.--2. "SEL,MCLK source select. This may be used by Flexcomms that support I2S  and/or by the digital microphone subsystem." "0: FRO HF DIV (fro_hf_div),1: Audio PLL clock (audio_pll_clk),?,?,?,?,?,7: None this may be selected in order to reduce.."
group.long 0x2E8++0x13
line.long 0x0 "FRGCLKSEL,Fractional Rate Generator clock source select"
bitfld.long 0x0 0.--2. "SEL,Fractional Rate Generator clock source select." "0: Main clock (main_clk),1: System PLL output (pll_clk),2: FRO 12 MHz (fro_12m),3: FRO 96 or 48 MHz (fro_hf),?,?,?,7: None this may be selected in order to reduce.."
line.long 0x4 "DMICCLKSEL,Digital microphone (DMIC) subsystem clock select"
bitfld.long 0x4 0.--2. "SEL,DMIC (audio subsystem) clock source select." "0: FRO 12 MHz (fro_12m),1: FRO HF DIV (fro_hf_div),2: Audio PLL clock (audio_pll_clk),3: MCLK pin input when selected in IOCON (mclk_in),?,?,?,7: None this may be selected in order to reduce.."
line.long 0x8 "SCTCLKSEL,SCTimer/PWM clock source select"
bitfld.long 0x8 0.--2. "SEL,SCT clock source select." "0: Main clock (main_clk),1: System PLL output (pll_clk),2: FRO 96 or 48 MHz (fro_hf),3: Audio PLL clock (audio_pll_clk),?,?,?,7: None this may be selected in order to reduce.."
line.long 0xC "LCDCLKSEL,LCD clock source select"
bitfld.long 0xC 0.--1. "SEL,LCD clock source select." "0: Main clock (main_clk),1: LCDCLKIN (LCDCLK_EXT),2: FRO 96 or 48 MHz (fro_hf),3: None this may be selected in order to reduce.."
line.long 0x10 "SDIOCLKSEL,SDIO clock source select"
bitfld.long 0x10 0.--2. "SEL,SDIO clock source select." "0: Main clock (main_clk),1: System PLL output (pll_clk),2: USB PLL clock (usb_pll_clk),3: FRO 96 or 48 MHz (fro_hf),4: Audio PLL clock (audio_pll_clk),?,?,7: None this may be selected in order to reduce.."
group.long 0x300++0x17
line.long 0x0 "SYSTICKCLKDIV,SYSTICK clock divider"
bitfld.long 0x0 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x0 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x0 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count." "0,1"
hexmask.long.byte 0x0 0.--7. 1. "DIV,Clock divider value. 0: Divide by 1 up to 255: Divide by 256."
line.long 0x4 "ARMTRACECLKDIV,ARM Trace clock divider"
bitfld.long 0x4 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x4 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x4 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x4 0.--7. 1. "DIV,Clock divider value."
line.long 0x8 "CAN0CLKDIV,MCAN0 clock divider"
bitfld.long 0x8 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x8 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x8 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x8 0.--7. 1. "DIV,Clock divider value."
line.long 0xC "CAN1CLKDIV,MCAN1 clock divider"
bitfld.long 0xC 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0xC 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0xC 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count." "0,1"
hexmask.long.byte 0xC 0.--7. 1. "DIV,Clock divider value. 0: Divide by 1 up to 255: Divide by 256."
line.long 0x10 "SC0CLKDIV,Smartcard0 clock divider"
bitfld.long 0x10 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x10 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x10 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x10 0.--7. 1. "DIV,Clock divider value."
line.long 0x14 "SC1CLKDIV,Smartcard1 clock divider"
bitfld.long 0x14 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x14 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x14 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x14 0.--7. 1. "DIV,Clock divider value."
group.long 0x380++0xB
line.long 0x0 "AHBCLKDIV,AHB clock divider"
bitfld.long 0x0 31. "REQFLAG,Divider status flag." "0,1"
hexmask.long.byte 0x0 0.--7. 1. "DIV,Clock divider value. 0: Divide by 1 up to 255: Divide by 256."
line.long 0x4 "CLKOUTDIV,CLKOUT clock divider"
bitfld.long 0x4 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x4 30. "HALT,Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output." "0,1"
newline
bitfld.long 0x4 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count." "0,1"
hexmask.long.byte 0x4 0.--7. 1. "DIV,Clock divider value. 0: Divide by 1 up to 255: Divide by 256."
line.long 0x8 "FROHFCLKDIV,FROHF clock divider"
bitfld.long 0x8 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x8 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x8 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x8 0.--7. 1. "DIV,Clock divider value."
group.long 0x390++0x13
line.long 0x0 "SPIFICLKDIV,SPIFI clock divider"
bitfld.long 0x0 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x0 30. "HALT,Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output." "0,1"
newline
bitfld.long 0x0 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count." "0,1"
hexmask.long.byte 0x0 0.--7. 1. "DIV,Clock divider value."
line.long 0x4 "ADCCLKDIV,ADC clock divider"
bitfld.long 0x4 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x4 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x4 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x4 0.--7. 1. "DIV,Clock divider value."
line.long 0x8 "USB0CLKDIV,USB0 clock divider"
bitfld.long 0x8 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x8 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x8 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x8 0.--7. 1. "DIV,Clock divider value."
line.long 0xC "USB1CLKDIV,USB1 clock divider"
bitfld.long 0xC 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0xC 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0xC 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0xC 0.--7. 1. "DIV,Clock divider value."
line.long 0x10 "FRGCTRL,Fractional rate divider"
hexmask.long.byte 0x10 8.--15. 1. "MULT,Numerator of the fractional divider. MULT is equal to the programmed value."
hexmask.long.byte 0x10 0.--7. 1. "DIV,Denominator of the fractional divider. DIV is equal to the programmed value +1. Always set to 0xFF to use with the fractional baud rate generator."
group.long 0x3A8++0x17
line.long 0x0 "DMICCLKDIV,DMIC clock divider"
bitfld.long 0x0 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x0 30. "HALT,Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output." "0,1"
newline
bitfld.long 0x0 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count." "0,1"
hexmask.long.byte 0x0 0.--7. 1. "DIV,Clock divider value. 0: Divide by 1 up to 255: Divide by 256."
line.long 0x4 "MCLKDIV,I2S MCLK clock divider"
bitfld.long 0x4 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x4 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x4 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x4 0.--7. 1. "DIV,Clock divider value. 0: Divide by 1 up to 255: Divide by 256."
line.long 0x8 "LCDCLKDIV,LCD clock divider"
bitfld.long 0x8 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x8 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x8 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x8 0.--7. 1. "DIV,Clock divider value."
line.long 0xC "SCTCLKDIV,SCT/PWM clock divider"
bitfld.long 0xC 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0xC 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0xC 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0xC 0.--7. 1. "DIV,Clock divider value."
line.long 0x10 "EMCCLKDIV,EMC clock divider"
bitfld.long 0x10 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x10 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x10 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x10 0.--7. 1. "DIV,Clock divider value."
line.long 0x14 "SDIOCLKDIV,SDIO clock divider"
bitfld.long 0x14 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x14 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x14 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x14 0.--7. 1. "DIV,Clock divider value."
group.long 0x400++0x3
line.long 0x0 "FLASHCFG,Flash wait states configuration"
hexmask.long.byte 0x0 12.--15. 1. "FLASHTIM,Flash memory access time. The number of system clocks used for flash accesses is equal to FLASHTIM +1."
bitfld.long 0x0 6. "PREFOVR,Prefetch override. This bit only applies when PREFEN = 1 and a buffered instruction is completing for which the next flash line is not already buffered or being prefetched." "0: Any previously initiated prefetch will be..,1: Any previously initiated prefetch will be.."
newline
bitfld.long 0x0 5. "PREFEN,Prefetch enable." "0: No instruction prefetch is performed.,1: If the FETCHCFG field is not 0 the next flash.."
bitfld.long 0x0 4. "ACCEL,Acceleration enable." "0: Flash acceleration is disabled. Every flash read..,1: Flash acceleration is enabled. Performance is.."
newline
bitfld.long 0x0 2.--3. "DATACFG,Data read configuration. This field determines how flash accelerator buffers are used for data accesses." "0: Data accesses from flash are not buffered. Every..,1: One buffer is used for all data accesses.,2: All buffers may be used for data accesses.,?"
bitfld.long 0x0 0.--1. "FETCHCFG,Instruction fetch configuration. This field determines how flash accelerator buffers are used for instruction fetches." "0: Instruction fetches from flash are not buffered.,1: One buffer is used for all instruction fetches.,2: All buffers may be used for instruction fetches.,?"
group.long 0x40C++0x7
line.long 0x0 "USB0CLKCTRL,USB0 clock control"
bitfld.long 0x0 4. "PU_DISABLE,Internal pull-up disable control." "0,1"
bitfld.long 0x0 3. "POL_FS_HOST_CLK,USB0 Host USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt." "0,1"
newline
bitfld.long 0x0 2. "AP_FS_HOST_CLK,USB0 Host USB0_NEEDCLK signal control." "0,1"
bitfld.long 0x0 1. "POL_FS_DEV_CLK,USB0 Device USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt." "0,1"
newline
bitfld.long 0x0 0. "AP_FS_DEV_CLK,USB0 Device USB0_NEEDCLK signal control." "0,1"
line.long 0x4 "USB0CLKSTAT,USB0 clock status"
bitfld.long 0x4 1. "HOST_NEED_CLKST,USB0 Host USB0_NEEDCLK signal status." "0,1"
bitfld.long 0x4 0. "DEV_NEED_CLKST,USB0 Device USB0_NEEDCLK signal status." "0,1"
group.long 0x418++0x3
line.long 0x0 "FREQMECTRL,Frequency measure register"
bitfld.long 0x0 31. "PROG,Set this bit to one to initiate a frequency measurement cycle. Hardware clears this bit when the measurement cycle has completed and there is valid capture data in the CAPVAL field (bits 13:0)." "0,1"
hexmask.long.word 0x0 0.--13. 1. "CAPVAL,Stores the capture result which is used to calculate the frequency of the target clock. This field is read-only."
group.long 0x420++0xB
line.long 0x0 "MCLKIO,MCLK input/output control"
bitfld.long 0x0 0. "DIR,MCLK direction control." "0,1"
line.long 0x4 "USB1CLKCTRL,USB1 clock control"
bitfld.long 0x4 4. "HS_DEV_WAKEUP_N,External user wake-up signal for device mode; asserting this signal (active low) will result in exiting the low power mode; input to asynchronous control logic." "0,1"
bitfld.long 0x4 3. "POL_FS_HOST_CLK,USB1 Host need_clock polarity for triggering the USB1 wake-up interrupt." "0,1"
newline
bitfld.long 0x4 2. "AP_FS_HOST_CLK,USB1 Host need_clock signal control." "0,1"
bitfld.long 0x4 1. "POL_FS_DEV_CLK,USB1 Device need_clock polarity for triggering the USB1 wake-up interrupt." "0,1"
newline
bitfld.long 0x4 0. "AP_FS_DEV_CLK,USB1 Device need_clock signal control." "0,1"
line.long 0x8 "USB1CLKSTAT,USB1 clock status"
bitfld.long 0x8 1. "HOST_NEED_CLKST,USB1 Device host USB1_NEEDCLK signal status." "0,1"
bitfld.long 0x8 0. "DEV_NEED_CLKST,USB1 Device USB1_NEEDCLK signal status." "0,1"
group.long 0x444++0x13
line.long 0x0 "EMCSYSCTRL,EMC system control"
bitfld.long 0x0 3. "EMCFBCLKINSEL,External Memory Controller clock select." "0,1"
bitfld.long 0x0 2. "EMCBC,External Memory Controller burst control." "0,1"
newline
bitfld.long 0x0 1. "EMCRD,EMC Reset Disable." "0,1"
bitfld.long 0x0 0. "EMCSC,EMC Shift Control." "0,1"
line.long 0x4 "EMCDLYCTRL,EMC clock delay control"
hexmask.long.byte 0x4 8.--12. 1. "FBCLK_DELAY,Programmable delay value for the feedback clock that controls input data sampling."
hexmask.long.byte 0x4 0.--4. 1. "CMD_DELAY,Programmable delay value for EMC outputs in command delayed mode."
line.long 0x8 "EMCDLYCAL,EMC delay chain calibration control"
bitfld.long 0x8 15. "DONE,Measurement completion flag." "0,1"
bitfld.long 0x8 14. "START,Start control bit for the EMC calibration counter." "0,1"
newline
hexmask.long.byte 0x8 0.--7. 1. "CALVALUE,Returns the count of the approximately 50 MHz ring oscillator that occur during 32 clocks of the FRO 12 MHz."
line.long 0xC "ETHPHYSEL,Ethernet PHY Selection"
bitfld.long 0xC 2. "PHY_SEL,PHY interface select." "0,1"
line.long 0x10 "ETHSBDCTRL,Ethernet SBD flow control"
bitfld.long 0x10 0.--1. "SBD_CTRL,Sideband Flow Control." "0,1,2,3"
group.long 0x460++0x3
line.long 0x0 "SDIOCLKCTRL,SDIO CCLKIN phase and delay control"
bitfld.long 0x0 31. "CCLK_SAMPLE_DELAY_ACTIVE,Enables sample delay  as controlled by the CCLK_SAMPLE_DELAY field." "0,1"
hexmask.long.byte 0x0 24.--28. 1. "CCLK_SAMPLE_DELAY,Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in."
newline
bitfld.long 0x0 23. "CCLK_DRV_DELAY_ACTIVE,Enables drive delay  as controlled by the CCLK_DRV_DELAY field." "0,1"
hexmask.long.byte 0x0 16.--20. 1. "CCLK_DRV_DELAY,Programmable delay value by which cclk_in_drv is delayed with regard to cclk_in."
newline
bitfld.long 0x0 7. "PHASE_ACTIVE,sdio_clk by 2  before feeding into ccl_in  cclk_in_sample  and cclk_in_drv." "0,1"
bitfld.long 0x0 2.--3. "CCLK_SAMPLE_PHASE,Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in." "0,1,2,3"
newline
bitfld.long 0x0 0.--1. "CCLK_DRV_PHASE,Programmable delay value by which cclk_in_drv is phase-shifted with regard to cclk_in." "0,1,2,3"
group.long 0x500++0xF
line.long 0x0 "FROCTRL,FRO oscillator control"
bitfld.long 0x0 31. "WRTRIM,Write Trim value." "0,1"
bitfld.long 0x0 30. "HSPDCLK,High speed clock enable." "0,1"
newline
bitfld.long 0x0 25. "USBMODCHG,USB Mode value Change flag." "0,1"
bitfld.long 0x0 24. "USBCLKADJ,USB clock adjust mode." "0,1"
newline
hexmask.long.byte 0x0 16.--23. 1. "FREQTRIM,Frequency trim."
bitfld.long 0x0 14. "SEL,Select the FRO HF output frequency." "0,1"
newline
hexmask.long.word 0x0 0.--13. 1. "TRIM,This value is factory trimmed to account for bias and temperature compensation."
line.long 0x4 "SYSOSCCTRL,System oscillator control"
bitfld.long 0x4 1. "FREQRANGE,Determines frequency range for system oscillator." "0,1"
bitfld.long 0x4 0. "BYPASS,Bypass system oscillator." "0,1"
line.long 0x8 "WDTOSCCTRL,Watchdog oscillator control"
hexmask.long.byte 0x8 5.--9. 1. "FREQSEL,Frequency select."
hexmask.long.byte 0x8 0.--4. 1. "DIVSEL,Divider select."
line.long 0xC "RTCOSCCTRL,RTC oscillator 32 kHz output control"
bitfld.long 0xC 0. "EN,RTC 32 kHz clock enable." "0,1"
group.long 0x51C++0x7
line.long 0x0 "USBPLLCTRL,USB PLL control"
bitfld.long 0x0 14. "FBSEL,Feedback divider input clock control." "0,1"
bitfld.long 0x0 13. "BYPASS,Input clock bypass control." "0: CCO clock is sent to post dividers..,1: PLL input clock is sent to post dividers.."
newline
bitfld.long 0x0 12. "DIRECT,Direct CCO clock output control." "0: CCO Clock signal goes through post divider.,1: CCO Clock signal goes directly to output(s).."
bitfld.long 0x0 10.--11. "NSEL,PLL feedback Divider value." "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "PSEL,PLL Divider value." "0,1,2,3"
hexmask.long.byte 0x0 0.--7. 1. "MSEL,PLL feedback Divider value."
line.long 0x4 "USBPLLSTAT,USB PLL status"
bitfld.long 0x4 0. "LOCK,USBPLL lock indicator." "0,1"
group.long 0x580++0x13
line.long 0x0 "SYSPLLCTRL,System PLL control"
bitfld.long 0x0 20. "DIRECTO,PLL0 direct output enable." "0: Disabled. The PLL output divider (P divider) is..,1: Enabled. The PLL output divider (P divider) is.."
bitfld.long 0x0 19. "DIRECTI,PLL0 direct input enable." "0,1"
newline
bitfld.long 0x0 17. "UPLIMOFF,Disable upper frequency limiter." "0,1"
bitfld.long 0x0 15. "BYPASS,PLL bypass control." "0: Bypass disabled. PLL CCO is sent to the PLL..,1: Bypass enabled. PLL input clock is sent directly.."
newline
hexmask.long.byte 0x0 10.--14. 1. "SELP,Bandwidth select P value."
hexmask.long.byte 0x0 4.--9. 1. "SELI,Bandwidth select I value."
newline
hexmask.long.byte 0x0 0.--3. 1. "SELR,Bandwidth select R value."
line.long 0x4 "SYSPLLSTAT,PLL status"
bitfld.long 0x4 0. "LOCK,PLL lock indicator." "0,1"
line.long 0x8 "SYSPLLNDEC,PLL N divider"
bitfld.long 0x8 10. "NREQ,NDEC reload request." "0,1"
hexmask.long.word 0x8 0.--9. 1. "NDEC,Decoded N-divider coefficient value."
line.long 0xC "SYSPLLPDEC,PLL P divider"
bitfld.long 0xC 7. "PREQ,." "0,1"
hexmask.long.byte 0xC 0.--6. 1. "PDEC,Decoded P-divider coefficient value."
line.long 0x10 "SYSPLLMDEC,System PLL M divider"
bitfld.long 0x10 17. "MREQ,MDEC reload request." "0,1"
hexmask.long.tbyte 0x10 0.--16. 1. "MDEC,Decoded M-divider coefficient value."
group.long 0x5A0++0x17
line.long 0x0 "AUDPLLCTRL,Audio PLL control"
bitfld.long 0x0 20. "DIRECTO,PLL direct output enable" "0: Disabled. The PLL output divider (P divider) is..,1: Enabled. The PLL output divider (P divider) is.."
bitfld.long 0x0 19. "DIRECTI,PLL direct input enable." "0,1"
newline
bitfld.long 0x0 17. "UPLIMOFF,Disable upper frequency limiter." "0,1"
bitfld.long 0x0 15. "BYPASS,PLL bypass control." "0: Bypass disabled. PLL CCO is sent to the PLL..,1: Bypass enabled. PLL input clock is sent directly.."
newline
hexmask.long.byte 0x0 10.--14. 1. "SELP,."
hexmask.long.byte 0x0 4.--9. 1. "SELI,Bandwidth select I value."
newline
hexmask.long.byte 0x0 0.--3. 1. "SELR,Bandwidth select R value."
line.long 0x4 "AUDPLLSTAT,Audio PLL status"
bitfld.long 0x4 0. "LOCK,PLL lock indicator." "0,1"
line.long 0x8 "AUDPLLNDEC,Audio PLL N divider"
bitfld.long 0x8 10. "NREQ,NDEC reload request." "0,1"
hexmask.long.word 0x8 0.--9. 1. "NDEC,Decoded N-divider coefficient value."
line.long 0xC "AUDPLLPDEC,Audio PLL P divider"
bitfld.long 0xC 7. "PREQ,PDEC reload request." "0,1"
hexmask.long.byte 0xC 0.--6. 1. "PDEC,Decoded P-divider coefficient value."
line.long 0x10 "AUDPLLMDEC,Audio PLL M divider"
bitfld.long 0x10 17. "MREQ,MDEC reload request." "0,1"
hexmask.long.tbyte 0x10 0.--16. 1. "MDEC,Decoded M-divider coefficient value."
line.long 0x14 "AUDPLLFRAC,Audio PLL fractional divider control"
bitfld.long 0x14 23. "SEL_EXT,Select fractional divider." "0,1"
bitfld.long 0x14 22. "REQ,Writing 1 to REQ signal loads CTRL value into fractional wrapper modulator." "0,1"
newline
hexmask.long.tbyte 0x14 0.--21. 1. "CTRL,PLL fractional divider control word"
group.long 0x600++0x7
line.long 0x0 "PDSLEEPCFG0,Sleep configuration register"
bitfld.long 0x0 29. "PDEN_VD6,Power control for EEPROM." "0,1"
bitfld.long 0x0 28. "PDEN_VD5,Power control both USB0 PHY and USB1 PHY." "0,1"
newline
bitfld.long 0x0 27. "PDEN_VD4,Power control for all SRAMs and ROM." "0,1"
bitfld.long 0x0 26. "PDEN_VD3,Power control for all PLLs." "0,1"
newline
bitfld.long 0x0 23. "PDEN_VREFP,VREFP to the ADC must be enabled for the ADC to work (also enable/disable bit 9  10  and 19)." "0,1"
bitfld.long 0x0 22. "PDEN_SYS_PLL,System PLL (PLL0) power (also enable/disable bit 26)." "0,1"
newline
bitfld.long 0x0 21. "PDEN_USB0_PHY,USB0 PHY power (also enable/disable bit 28)." "0,1"
bitfld.long 0x0 20. "PDEN_WDT_OSC,Watchdog oscillator." "0,1"
newline
bitfld.long 0x0 19. "PDEN_VDDA,Vdda to the ADC  must be enabled for the ADC to work (also enable/disable bit 9  10  and 23)." "0,1"
bitfld.long 0x0 17. "PDEN_ROM,ROM (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 16. "PDEN_USB_RAM,PDEN_USB_SRAM controls USB_RAM (also enable/disable bit 27)." "0,1"
bitfld.long 0x0 15. "PDEN_SRAM1_2_3,PDEN_SRAM1_2_3 controls SRAM1  SRAM2  and SRAM3 (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 14. "PDEN_SRAM0,PDEN_SRAM0 controls SRAM0 (also enable/disable bit 27)." "0,1"
bitfld.long 0x0 13. "PDEN_SRAMX,PDEN_SRAMX controls SRAMX (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 10. "PDEN_ADC0,ADC power." "0,1"
bitfld.long 0x0 9. "PDEN_VD2_ANA,Analog supply for System Oscillator (also enable/disable bit 3 in PDRUNCFG1 register)  Temperature Sensor (also  enable/disable bit 6)  ADC (also  enable/disable bits 10  19  and 23)." "0,1"
newline
bitfld.long 0x0 8. "PDEN_BOD_INTR,Brown-out Detect interrupt." "0,1"
bitfld.long 0x0 7. "PDEN_BOD_RST,Brown-out Detect reset." "0,1"
newline
bitfld.long 0x0 6. "PDEN_TS,Temp sensor." "0,1"
bitfld.long 0x0 4. "PDEN_FRO,FRO oscillator." "0,1"
line.long 0x4 "PDSLEEPCFG1,Sleep configuration register"
bitfld.long 0x4 7. "PDEN_RNG,Random Number Generator Power." "0,1"
bitfld.long 0x4 5. "PDEN_EEPROM,EEPROM power (also  enable/disable bit 29 in PDRUNCFG0 register)." "0,1"
newline
bitfld.long 0x4 3. "PDEN_SYSOSC,System Oscillator Power (also  enable/disable bit 9 in PDRUNCFG0 register)." "0,1"
bitfld.long 0x4 2. "PDEN_AUD_PLL,Audio PLL (PLL2) power and fractional divider (also  enable/disable bit 26 in PDRUNCFG0 register)." "0,1"
newline
bitfld.long 0x4 1. "PDEN_USB1_PLL,USB PLL (PLL1) power (also  enable/disable bit 26 in PDRUNCFG0 register)." "0,1"
bitfld.long 0x4 0. "PDEN_USB1_PHY,USB1 high speed PHY (also  enable/disable bit 28 in PDRUNCFG0 register)." "0,1"
group.long 0x610++0x7
line.long 0x0 "PDRUNCFG0,Power configuration register"
bitfld.long 0x0 29. "PDEN_VD6,Power control for EEPROM." "0,1"
bitfld.long 0x0 28. "PDEN_VD5,Power control both USB0 PHY and USB1 PHY." "0,1"
newline
bitfld.long 0x0 27. "PDEN_VD4,Power control for all SRAMs and ROM." "0,1"
bitfld.long 0x0 26. "PDEN_VD3,Power control for all PLLs." "0,1"
newline
bitfld.long 0x0 23. "PDEN_VREFP,VREFP to the ADC must be enabled for the ADC to work (also enable/disable bit 9  10  and 19)." "0,1"
bitfld.long 0x0 22. "PDEN_SYS_PLL,System PLL (PLL0) power (also enable/disable bit 26)." "0,1"
newline
bitfld.long 0x0 21. "PDEN_USB0_PHY,USB0 PHY power (also enable/disable bit 28)." "0,1"
bitfld.long 0x0 20. "PDEN_WDT_OSC,Watchdog oscillator." "0,1"
newline
bitfld.long 0x0 19. "PDEN_VDDA,Vdda to the ADC  must be enabled for the ADC to work (also enable/disable bit 9  10  and 23)." "0,1"
bitfld.long 0x0 17. "PDEN_ROM,ROM (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 16. "PDEN_USB_RAM,PDEN_USB_SRAM controls USB_RAM (also enable/disable bit 27)." "0,1"
bitfld.long 0x0 15. "PDEN_SRAM1_2_3,PDEN_SRAM1_2_3 controls SRAM1  SRAM2  and SRAM3 (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 14. "PDEN_SRAM0,PDEN_SRAM0 controls SRAM0 (also enable/disable bit 27)." "0,1"
bitfld.long 0x0 13. "PDEN_SRAMX,PDEN_SRAMX controls SRAMX (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 10. "PDEN_ADC0,ADC power." "0,1"
bitfld.long 0x0 9. "PDEN_VD2_ANA,Analog supply for System Oscillator (also enable/disable bit 3 in PDRUNCFG1 register)  Temperature Sensor (also  enable/disable bit 6)  ADC (also  enable/disable bits 10  19  and 23)." "0,1"
newline
bitfld.long 0x0 8. "PDEN_BOD_INTR,Brown-out Detect interrupt." "0,1"
bitfld.long 0x0 7. "PDEN_BOD_RST,Brown-out Detect reset." "0,1"
newline
bitfld.long 0x0 6. "PDEN_TS,Temp sensor." "0,1"
bitfld.long 0x0 4. "PDEN_FRO,FRO oscillator." "0,1"
line.long 0x4 "PDRUNCFG1,Power configuration register"
bitfld.long 0x4 7. "PDEN_RNG,Random Number Generator Power." "0,1"
bitfld.long 0x4 5. "PDEN_EEPROM,EEPROM power (also  enable/disable bit 29 in PDRUNCFG0 register)." "0,1"
newline
bitfld.long 0x4 3. "PDEN_SYSOSC,System Oscillator Power (also  enable/disable bit 9 in PDRUNCFG0 register)." "0,1"
bitfld.long 0x4 2. "PDEN_AUD_PLL,Audio PLL (PLL2) power and fractional divider (also  enable/disable bit 26 in PDRUNCFG0 register)." "0,1"
newline
bitfld.long 0x4 1. "PDEN_USB1_PLL,USB PLL (PLL1) power (also  enable/disable bit 26 in PDRUNCFG0 register)." "0,1"
bitfld.long 0x4 0. "PDEN_USB1_PHY,USB1 high speed PHY (also  enable/disable bit 28 in PDRUNCFG0 register)." "0,1"
group.long 0x620++0x7
line.long 0x0 "PDRUNCFGSET0,Power configuration set register"
bitfld.long 0x0 29. "PDEN_VD6,Power control for EEPROM." "0,1"
bitfld.long 0x0 28. "PDEN_VD5,Power control both USB0 PHY and USB1 PHY." "0,1"
newline
bitfld.long 0x0 27. "PDEN_VD4,Power control for all SRAMs and ROM." "0,1"
bitfld.long 0x0 26. "PDEN_VD3,Power control for all PLLs." "0,1"
newline
bitfld.long 0x0 23. "PDEN_VREFP,VREFP to the ADC must be enabled for the ADC to work (also enable/disable bit 9  10  and 19)." "0,1"
bitfld.long 0x0 22. "PDEN_SYS_PLL,System PLL (PLL0) power (also enable/disable bit 26)." "0,1"
newline
bitfld.long 0x0 21. "PDEN_USB0_PHY,USB0 PHY power (also enable/disable bit 28)." "0,1"
bitfld.long 0x0 20. "PDEN_WDT_OSC,Watchdog oscillator." "0,1"
newline
bitfld.long 0x0 19. "PDEN_VDDA,Vdda to the ADC  must be enabled for the ADC to work (also enable/disable bit 9  10  and 23)." "0,1"
bitfld.long 0x0 17. "PDEN_ROM,ROM (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 16. "PDEN_USB_RAM,PDEN_USB_SRAM controls USB_RAM (also enable/disable bit 27)." "0,1"
bitfld.long 0x0 15. "PDEN_SRAM1_2_3,PDEN_SRAM1_2_3 controls SRAM1  SRAM2  and SRAM3 (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 14. "PDEN_SRAM0,PDEN_SRAM0 controls SRAM0 (also enable/disable bit 27)." "0,1"
bitfld.long 0x0 13. "PDEN_SRAMX,PDEN_SRAMX controls SRAMX (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 10. "PDEN_ADC0,ADC power." "0,1"
bitfld.long 0x0 9. "PDEN_VD2_ANA,Analog supply for System Oscillator (also enable/disable bit 3 in PDRUNCFG1 register)  Temperature Sensor (also  enable/disable bit 6)  ADC (also  enable/disable bits 10  19  and 23)." "0,1"
newline
bitfld.long 0x0 8. "PDEN_BOD_INTR,Brown-out Detect interrupt." "0,1"
bitfld.long 0x0 7. "PDEN_BOD_RST,Brown-out Detect reset." "0,1"
newline
bitfld.long 0x0 6. "PDEN_TS,Temp sensor." "0,1"
bitfld.long 0x0 4. "PDEN_FRO,FRO oscillator." "0,1"
line.long 0x4 "PDRUNCFGSET1,Power configuration set register"
bitfld.long 0x4 7. "PDEN_RNG,Random Number Generator Power." "0,1"
bitfld.long 0x4 5. "PDEN_EEPROM,EEPROM power (also  enable/disable bit 29 in PDRUNCFG0 register)." "0,1"
newline
bitfld.long 0x4 3. "PDEN_SYSOSC,System Oscillator Power (also  enable/disable bit 9 in PDRUNCFG0 register)." "0,1"
bitfld.long 0x4 2. "PDEN_AUD_PLL,Audio PLL (PLL2) power and fractional divider (also  enable/disable bit 26 in PDRUNCFG0 register)." "0,1"
newline
bitfld.long 0x4 1. "PDEN_USB1_PLL,USB PLL (PLL1) power (also  enable/disable bit 26 in PDRUNCFG0 register)." "0,1"
bitfld.long 0x4 0. "PDEN_USB1_PHY,USB1 high speed PHY (also  enable/disable bit 28 in PDRUNCFG0 register)." "0,1"
group.long 0x630++0x7
line.long 0x0 "PDRUNCFGCLR0,Power configuration clear register"
bitfld.long 0x0 29. "PDEN_VD6,Power control for EEPROM." "0,1"
bitfld.long 0x0 28. "PDEN_VD5,Power control both USB0 PHY and USB1 PHY." "0,1"
newline
bitfld.long 0x0 27. "PDEN_VD4,Power control for all SRAMs and ROM." "0,1"
bitfld.long 0x0 26. "PDEN_VD3,Power control for all PLLs." "0,1"
newline
bitfld.long 0x0 23. "PDEN_VREFP,VREFP to the ADC must be enabled for the ADC to work (also enable/disable bit 9  10  and 19)." "0,1"
bitfld.long 0x0 22. "PDEN_SYS_PLL,System PLL (PLL0) power (also enable/disable bit 26)." "0,1"
newline
bitfld.long 0x0 21. "PDEN_USB0_PHY,USB0 PHY power (also enable/disable bit 28)." "0,1"
bitfld.long 0x0 20. "PDEN_WDT_OSC,Watchdog oscillator." "0,1"
newline
bitfld.long 0x0 19. "PDEN_VDDA,Vdda to the ADC  must be enabled for the ADC to work (also enable/disable bit 9  10  and 23)." "0,1"
bitfld.long 0x0 17. "PDEN_ROM,ROM (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 16. "PDEN_USB_RAM,PDEN_USB_SRAM controls USB_RAM (also enable/disable bit 27)." "0,1"
bitfld.long 0x0 15. "PDEN_SRAM1_2_3,PDEN_SRAM1_2_3 controls SRAM1  SRAM2  and SRAM3 (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 14. "PDEN_SRAM0,PDEN_SRAM0 controls SRAM0 (also enable/disable bit 27)." "0,1"
bitfld.long 0x0 13. "PDEN_SRAMX,PDEN_SRAMX controls SRAMX (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 10. "PDEN_ADC0,ADC power." "0,1"
bitfld.long 0x0 9. "PDEN_VD2_ANA,Analog supply for System Oscillator (also enable/disable bit 3 in PDRUNCFG1 register)  Temperature Sensor (also  enable/disable bit 6)  ADC (also  enable/disable bits 10  19  and 23)." "0,1"
newline
bitfld.long 0x0 8. "PDEN_BOD_INTR,Brown-out Detect interrupt." "0,1"
bitfld.long 0x0 7. "PDEN_BOD_RST,Brown-out Detect reset." "0,1"
newline
bitfld.long 0x0 6. "PDEN_TS,Temp sensor." "0,1"
bitfld.long 0x0 4. "PDEN_FRO,FRO oscillator." "0,1"
line.long 0x4 "PDRUNCFGCLR1,Power configuration clear register"
bitfld.long 0x4 7. "PDEN_RNG,Random Number Generator Power." "0,1"
bitfld.long 0x4 5. "PDEN_EEPROM,EEPROM power (also  enable/disable bit 29 in PDRUNCFG0 register)." "0,1"
newline
bitfld.long 0x4 3. "PDEN_SYSOSC,System Oscillator Power (also  enable/disable bit 9 in PDRUNCFG0 register)." "0,1"
bitfld.long 0x4 2. "PDEN_AUD_PLL,Audio PLL (PLL2) power and fractional divider (also  enable/disable bit 26 in PDRUNCFG0 register)." "0,1"
newline
bitfld.long 0x4 1. "PDEN_USB1_PLL,USB PLL (PLL1) power (also  enable/disable bit 26 in PDRUNCFG0 register)." "0,1"
bitfld.long 0x4 0. "PDEN_USB1_PHY,USB1 high speed PHY (also  enable/disable bit 28 in PDRUNCFG0 register)." "0,1"
group.long 0x680++0x7
line.long 0x0 "STARTER0,Start logic 0 wake-up enable register"
bitfld.long 0x0 29. "RTC,RTC interrupt alarm and wake-up timer." "0,1"
bitfld.long 0x0 28. "USB0,USB function interrupt wake-up." "0,1"
newline
bitfld.long 0x0 27. "USB0_NEEDCLK,USB activity interrupt wake-up." "0,1"
bitfld.long 0x0 26. "HWVAD,Hardware voice activity detect interrupt wake-up." "0,1"
newline
bitfld.long 0x0 25. "DMIC,Digital microphone interrupt wake-up." "0,1"
bitfld.long 0x0 24. "ADC0_THCMP,ADC0 threshold and error interrupt wake-up." "0,1"
newline
bitfld.long 0x0 23. "ADC0_SEQB,ADC0 sequence B interrupt wake-up." "0,1"
bitfld.long 0x0 22. "ADC0_SEQA,ADC0 sequence A interrupt wake-up." "0,1"
newline
bitfld.long 0x0 21. "FLEXCOMM7,Flexcomm7 peripheral interrupt wake-up." "0,1"
bitfld.long 0x0 20. "FLEXCOMM6,Flexcomm6 peripheral interrupt wake-up." "0,1"
newline
bitfld.long 0x0 19. "FLEXCOMM5,Flexcomm5 peripheral interrupt wake-up." "0,1"
bitfld.long 0x0 18. "FLEXCOMM4,Flexcomm4 peripheral interrupt wake-up." "0,1"
newline
bitfld.long 0x0 17. "FLEXCOMM3,Flexcomm3 peripheral interrupt wake-up." "0,1"
bitfld.long 0x0 16. "FLEXCOMM2,Flexcomm2 peripheral interrupt wake-up." "0,1"
newline
bitfld.long 0x0 15. "FLEXCOMM1,Flexcomm1 peripheral interrupt wake-up." "0,1"
bitfld.long 0x0 14. "FLEXCOMM0,Flexcomm0 peripheral interrupt wake-up." "0,1"
newline
bitfld.long 0x0 13. "CTIMER3,Standard counter/timer CTIMER3 wake-up." "0,1"
bitfld.long 0x0 12. "SCT0,SCT0 wake-up." "0,1"
newline
bitfld.long 0x0 11. "CTIMER1,Standard counter/timer CTIMER1 wake-up." "0,1"
bitfld.long 0x0 10. "CTIMER0,Standard counter/timer CTIMER0 wake-up." "0,1"
newline
bitfld.long 0x0 9. "MRT,Multi-Rate Timer wake-up." "0,1"
bitfld.long 0x0 8. "UTICK,Micro-tick Timer wake-up." "0,1"
newline
bitfld.long 0x0 7. "PIN_INT3,GPIO pin interrupt 3 wake-up." "0,1"
bitfld.long 0x0 6. "PIN_INT2,GPIO pin interrupt 2 wake-up." "0,1"
newline
bitfld.long 0x0 5. "PIN_INT1,GPIO pin interrupt 1 wake-up." "0,1"
bitfld.long 0x0 4. "PIN_INT0,GPIO pin interrupt 0 wake-up." "0,1"
newline
bitfld.long 0x0 3. "GINT1,Group interrupt 1 wake-up." "0,1"
bitfld.long 0x0 2. "GINT0,Group interrupt 0 wake-up." "0,1"
newline
bitfld.long 0x0 1. "DMA,DMA wake-up." "0,1"
bitfld.long 0x0 0. "WDT_BOD,WWDT and BOD interrupt wake-up." "0,1"
line.long 0x4 "STARTER1,Start logic 0 wake-up enable register"
bitfld.long 0x4 24. "SMARTCARD1,Smart card 1 wake-up." "0,1"
bitfld.long 0x4 23. "SMARTCARD0,Smart card 0 wake-up." "0,1"
newline
bitfld.long 0x4 19. "ENET_INT0,Ethernet." "0,1"
bitfld.long 0x4 18. "ENET_INT2,Ethernet." "0,1"
newline
bitfld.long 0x4 17. "ENET_INT1,Ethernet." "0,1"
bitfld.long 0x4 16. "USB1_ACT,USB 1 activity wake-up." "0,1"
newline
bitfld.long 0x4 15. "USB1,USB 1 wake-up." "0,1"
bitfld.long 0x4 9. "FLEXCOMM9,Flexcomm Interface 9 wake-up." "0,1"
newline
bitfld.long 0x4 8. "FLEXCOMM8,Flexcomm Interface 8 wake-up." "0,1"
bitfld.long 0x4 7. "SPIFI,SPIFI interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled." "0: Wake-up disabled,1: Wake-up enabled"
newline
bitfld.long 0x4 5. "CTIMER4,Standard counter/timer CTIMER4 wake-up." "0,1"
bitfld.long 0x4 4. "CTIMER2,Standard counter/timer CTIMER2 wake-up." "0,1"
newline
bitfld.long 0x4 3. "PINT7,GPIO pin interrupt 7 wake-up." "0,1"
bitfld.long 0x4 2. "PINT6,GPIO pin interrupt 6 wake-up." "0,1"
newline
bitfld.long 0x4 1. "PINT5,GPIO pin interrupt 5 wake-up." "0,1"
bitfld.long 0x4 0. "PINT4,GPIO pin interrupt 4 wake-up." "0,1"
group.long 0x780++0x3
line.long 0x0 "HWWAKE,Configures special cases of hardware wake-up"
bitfld.long 0x0 3. "WAKEDMA,Wake for DMA. When 1  DMA being busy will cause peripheral clocking to remain running until DMA completes. This is generally used in conjunction with bit 1 and/or 2 in order to prevent peripheral clocking from being shut down as soon as the cause.." "0,1"
bitfld.long 0x0 2. "WAKEDMIC,Wake for Digital Microphone. When 1  the digital microphone input FIFO reaching the level specified by TRIGLVL of either channel will cause peripheral clocking to wake up temporarily while the related status is asserted." "0,1"
newline
bitfld.long 0x0 1. "FCWAKE,Wake for Flexcomms. When 1  any Flexcomm FIFO reaching the level specified by its own TXLVL will cause peripheral clocking to wake up temporarily while the related status is asserted." "0,1"
bitfld.long 0x0 0. "FORCEWAKE,Force peripheral clocking to stay on during Deep Sleep and Power-down modes. When 1  clocking to peripherals is prevented from being shut down when the CPU enters Deep Sleep and Power-down modes. This is intended to allow a coprocessor to.." "0,1"
group.long 0xE04++0x3
line.long 0x0 "AUTOCGOR,Auto Clock-Gate Override Register"
bitfld.long 0x0 4. "RAM3,When 1  automatic clock gating for RAM1 are turned off." "0,1"
bitfld.long 0x0 3. "RAM2,When 1  automatic clock gating for RAM1 are turned off." "0,1"
newline
bitfld.long 0x0 2. "RAM1,When 1  automatic clock gating for RAM1 are turned off." "0,1"
bitfld.long 0x0 1. "RAM0X,When 1  automatic clock gating for RAMX and RAM0 are turned off." "0,1"
rgroup.long 0xFF4++0xB
line.long 0x0 "JTAGIDCODE,JTAG ID code register"
hexmask.long 0x0 0.--31. 1. "JTAGID,JTAG ID code."
line.long 0x4 "DEVICE_ID0,Part ID register"
hexmask.long 0x4 0.--31. 1. "PARTID,Part ID"
line.long 0x8 "DEVICE_ID1,Boot ROM and die revision register"
hexmask.long 0x8 0.--31. 1. "REVID,Revision."
group.long 0x20044++0x3
line.long 0x0 "BODCTRL,Brown-Out Detect control"
bitfld.long 0x0 7. "BODINTSTAT,BOD interrupt status. When 1  a BOD interrupt has occurred. Cleared by writing 1 to this bit." "0,1"
bitfld.long 0x0 6. "BODRSTSTAT,BOD reset status. When 1  a BOD reset has occurred. Cleared by writing 1 to this bit." "0,1"
newline
bitfld.long 0x0 5. "BODINTENA,BOD interrupt enable" "0: Disable interrupt function.,1: Enable interrupt function."
bitfld.long 0x0 3.--4. "BODINTLEV,BOD interrupt level" "0: Level 0: 2.05 V,1: Level 1: 2.45 V,2: Level 2: 2.75 V,3: Level 3: 3.05 V"
newline
bitfld.long 0x0 2. "BODRSTENA,BOD reset enable" "0: Disable reset function.,1: Enable reset function."
bitfld.long 0x0 0.--1. "BODRSTLEV,BOD reset level" "0: Level 0: 1.5 V,1: Level 1: 1.85 V,2: Level 2: 2.0 V,3: Level 3: 2.3 V"
endif
sif (cpuis("LPC54618*"))
group.long 0x10++0x3
line.long 0x0 "AHBMATPRIO,AHB multilayer matrix priority control"
bitfld.long 0x0 24.--25. "PRI_SHA,SHA priority." "0,1,2,3"
bitfld.long 0x0 22.--23. "PRI_MCAN2,MCAN2 priority." "0,1,2,3"
newline
bitfld.long 0x0 20.--21. "PRI_MCAN1,MCAN1 priority." "0,1,2,3"
bitfld.long 0x0 18.--19. "PRI_SDIO,SDIO priority." "0,1,2,3"
newline
bitfld.long 0x0 16.--17. "PRI_USB1,USB1 DMA priority." "0,1,2,3"
bitfld.long 0x0 14.--15. "PRI_USB0,USB0 DMA priority." "0,1,2,3"
newline
bitfld.long 0x0 12.--13. "PRI_LCD,LCD DMA priority." "0,1,2,3"
bitfld.long 0x0 10.--11. "PRI_ETH,Ethernet DMA priority." "0,1,2,3"
newline
hexmask.long.byte 0x0 6.--9. 1. "PRI_DMA,DMA controller priority."
bitfld.long 0x0 4.--5. "PRI_SYS,System bus priority." "0,1,2,3"
newline
bitfld.long 0x0 2.--3. "PRI_DCODE,D-Code bus priority." "0,1,2,3"
bitfld.long 0x0 0.--1. "PRI_ICODE,I-Code bus priority." "0,1,2,3"
group.long 0x40++0x3
line.long 0x0 "SYSTCKCAL,System tick counter calibration"
bitfld.long 0x0 25. "NOREF,Initial value for the Systick timer." "0,1"
bitfld.long 0x0 24. "SKEW,Initial value for the Systick timer." "0,1"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "CAL,System tick timer calibration value."
group.long 0x48++0x7
line.long 0x0 "NMISRC,NMI Source Select"
bitfld.long 0x0 31. "NMIENM4,Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQM4." "0,1"
hexmask.long.byte 0x0 0.--5. 1. "IRQM4,The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the Cortex-M4  if enabled by NMIENM4."
line.long 0x4 "ASYNCAPBCTRL,Asynchronous APB Control"
bitfld.long 0x4 0. "ENABLE,Enables the asynchronous APB bridge and subsystem." "0: Disabled. Asynchronous APB bridge is disabled.,1: Enabled. Asynchronous APB bridge is enabled."
endif
sif (cpuis("LPC54618*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0xC0)++0x3
line.long 0x0 "PIOPORCAP[$1],POR captured value of port n"
hexmask.long 0x0 0.--31. 1. "PIOPORCAP,State of PIOn_31 through PIOn_0 at power-on reset"
repeat.end
endif
sif (cpuis("LPC54618*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0xD0)++0x3
line.long 0x0 "PIORESCAP[$1],Reset captured value of port n"
hexmask.long 0x0 0.--31. 1. "PIORESCAP,State of PIOn_31 through PIOn_0 for resets other than POR."
repeat.end
group.long 0x100++0xB
line.long 0x0 "PRESETCTRL0,Peripheral reset control n"
bitfld.long 0x0 27. "ADC0_RST,ADC0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 22. "WWDT_RST,Watchdog timer reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x0 21. "CRC_RST,CRC generator reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 20. "DMA0_RST,DMA0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x0 19. "GINT_RST,Grouped interrupt (GINT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 18. "PINT_RST,Pin interrupt (PINT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x0 17. "GPIO3_RST,GPIO3 reset control." "0,1"
bitfld.long 0x0 16. "GPIO2_RST,GPIO2 reset control." "0,1"
newline
bitfld.long 0x0 15. "GPIO1_RST,GPIO1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 14. "GPIO0_RST,GPIO0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x0 13. "IOCON_RST,IOCON reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 11. "MUX_RST,Input mux reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x0 10. "SPIFI_RST,SPIFI reset control." "0,1"
bitfld.long 0x0 9. "EEPROM_RST,EEPROM reset control." "0,1"
newline
bitfld.long 0x0 8. "FMC_RST,Flash accelerator reset control. Note that the FMC must not be reset while executing from flash  and must be reconfigured after reset. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 7. "FLASH_RST,Flash controller reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
line.long 0x4 "PRESETCTRL1,Peripheral reset control n"
bitfld.long 0x4 27. "CTIMER1_RST,CTIMER1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 26. "CTIMER0_RST,CTIMER0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 25. "USB0D_RST,USB0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 22. "CTIMER2_RST,CTIMER2 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function" "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 19. "DMIC_RST,Digital microphone interface reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 18. "FC7_RST,Flexcomm 7 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 17. "FC6_RST,Flexcomm 6 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 16. "FC5_RST,Flexcomm 5 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 15. "FC4_RST,Flexcomm 4 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 14. "FC3_RST,Flexcomm 3 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 13. "FC2_RST,Flexcomm 2 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 12. "FC1_RST,Flexcomm 1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 11. "FC0_RST,Flexcomm 0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 10. "UTICK_RST,Micro-tick Timer reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 8. "MCAN1_RST,0 = Clear reset to this function." "0: Clear reset to this function,?"
bitfld.long 0x4 7. "MCAN0_RST,0 = Clear reset to this function." "0: Clear reset to this function,?"
newline
bitfld.long 0x4 2. "SCT0_RST,State configurable timer 0 (SCT0) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 0. "MRT_RST,Multi-rate timer (MRT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
line.long 0x8 "PRESETCTRL2,Peripheral reset control n"
bitfld.long 0x8 20. "SC1_RST,Smart card 1 reset control." "0,1"
bitfld.long 0x8 19. "SC0_RST,Smart card 0 reset control." "0,1"
newline
bitfld.long 0x8 18. "SHA_RST,SHA reset control." "0,1"
bitfld.long 0x8 17. "USB0HSL_RST,USB0 HOST slave reset control." "0,1"
newline
bitfld.long 0x8 16. "USB0HMR_RST,USB0 HOST master reset control." "0,1"
bitfld.long 0x8 15. "FC9_RST,Flexcomm 9 reset control." "0,1"
newline
bitfld.long 0x8 14. "FC8_RST,Flexcomm 8 reset control." "0,1"
bitfld.long 0x8 13. "RNG_RST,RNG reset control." "0,1"
newline
bitfld.long 0x8 12. "OTP_RST,OTP reset control." "0,1"
bitfld.long 0x8 11. "AES_RST,AES reset control." "0,1"
newline
bitfld.long 0x8 10. "GPIO5_RST,GPIO5 reset control." "0,1"
bitfld.long 0x8 9. "GPIO4_RST,GPIO4 reset control." "0,1"
newline
bitfld.long 0x8 8. "ETH_RST,Ethernet reset control." "0,1"
bitfld.long 0x8 7. "EMC_RESET,EMC reset control." "0,1"
newline
bitfld.long 0x8 6. "USB1RAM_RST,USB1 RAM reset control." "0,1"
bitfld.long 0x8 5. "USB1D_RST,USB1 Device reset control." "0,1"
newline
bitfld.long 0x8 4. "USB1H_RST,USB1 Host reset control." "0,1"
bitfld.long 0x8 3. "SDIO_RST,SDIO reset control." "0,1"
newline
bitfld.long 0x8 2. "LCD_RST,LCD reset control." "0,1"
endif
sif (cpuis("LPC54618*"))
repeat 3. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x120)++0x3
line.long 0x0 "PRESETCTRLSET[$1],Set bits in PRESETCTRLn"
hexmask.long 0x0 0.--31. 1. "RST_SET,Writing ones to this register sets the corresponding bit or bits in the PRESETCTRLn register  if they are implemented. Bits that do not correspond to defined bits in PRESETCTRLn are reserved and only zeroes should be written to them."
repeat.end
endif
sif (cpuis("LPC54618*"))
repeat 3. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x140)++0x3
line.long 0x0 "PRESETCTRLCLR[$1],Clear bits in PRESETCTRLn"
hexmask.long 0x0 0.--31. 1. "RST_CLR,Writing ones to this register clears the corresponding bit or bits in the PRESETCTRLn register  if they are implemented. Bits that do not correspond to defined bits in PRESETCTRLn are reserved and only zeroes should be written to them."
repeat.end
group.long 0x1F0++0x3
line.long 0x0 "SYSRSTSTAT,System reset status register"
bitfld.long 0x0 4. "SYSRST,Status of the software system reset" "0: No System reset detected,1: System reset detected. Writing a one clears this.."
bitfld.long 0x0 3. "BOD,Status of the Brown-out detect reset" "0: No BOD reset detected,1: BOD reset detected. Writing a one clears this.."
newline
bitfld.long 0x0 2. "WDT,Status of the Watchdog reset" "0: No WDT reset detected,1: WDT reset detected. Writing a one clears this.."
bitfld.long 0x0 1. "EXTRST,Status of the external RESET pin. External reset status" "0: No reset event detected.,1: Reset detected. Writing a one clears this reset."
newline
bitfld.long 0x0 0. "POR,POR reset status" "0: No POR detected,1: POR detected. Writing a one clears this reset."
group.long 0x200++0xB
line.long 0x0 "AHBCLKCTRL0,AHB Clock control n"
bitfld.long 0x0 27. "ADC0,Enables the clock for the ADC0 register interface." "0,1"
bitfld.long 0x0 23. "RTC,Enables the bus clock for the RTC. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 22. "WWDT,Enables the clock for the Watchdog Timer. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 21. "CRC,Enables the clock for the CRC engine. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 20. "DMA,Enables the clock for the DMA controller. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 19. "GINT,Enables the clock for the grouped pin interrupt block. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 18. "PINT,Enables the clock for the pin interrupt block.0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 17. "GPIO3,Enables the clock for the GPIO3 port registers." "0,1"
newline
bitfld.long 0x0 16. "GPIO2,Enables the clock for the GPIO2 port registers." "0,1"
bitfld.long 0x0 15. "GPIO1,Enables the clock for the GPIO1 port registers. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 14. "GPIO0,Enables the clock for the GPIO0 port registers. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 13. "IOCON,Enables the clock for the IOCON block. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 11. "INPUTMUX,Enables the clock for the input muxes. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 10. "SPIFI,Enables the clock for the SPIFI. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 9. "EEPROM,Enables the clock for EEPROM." "0,1"
bitfld.long 0x0 8. "FMC,Enables the clock for the Flash accelerator. 0 = Disable; 1 = Enable. This clock is needed if the flash is being read." "0: Disable,1: Enable"
newline
bitfld.long 0x0 7. "FLASH,Enables the clock for the flash controller. 0 = Disable; 1 = Enable. This clock is needed for flash programming  not for flash read." "0: Disable,1: Enable"
bitfld.long 0x0 5. "SRAM3,Enables the clock for SRAM3." "0,1"
newline
bitfld.long 0x0 4. "SRAM2,Enables the clock for SRAM2. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 3. "SRAM1,Enables the clock for SRAM1. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 1. "ROM,Enables the clock for the Boot ROM. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
line.long 0x4 "AHBCLKCTRL1,AHB Clock control n"
bitfld.long 0x4 27. "CTIMER1,Enables the clock for timer CTIMER1. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 26. "CTIMER0,Enables the clock for timer CTIMER0. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 25. "USB0D,Enables the clock for the USB0 device interface. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 22. "CTIMER2,Enables the clock for CTIMER 2. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 19. "DMIC,Enables the clock for the digital microphone interface. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 18. "FLEXCOMM7,Enables the clock for Flexcomm 7. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 17. "FLEXCOMM6,Enables the clock for Flexcomm 6. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 16. "FLEXCOMM5,Enables the clock for Flexcomm 5. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 15. "FLEXCOMM4,Enables the clock for Flexcomm 4. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 14. "FLEXCOMM3,Enables the clock for Flexcomm 3. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 13. "FLEXCOMM2,Enables the clock for Flexcomm 2. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 12. "FLEXCOMM1,Enables the clock for Flexcomm 1. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 11. "FLEXCOMM0,Enables the clock for Flexcomm 0. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 10. "UTICK,Enables the clock for the Micro-tick Timer. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 8. "MCAN1,Enables the clock for MCAN1." "0,1"
bitfld.long 0x4 7. "MCAN0,Enables the clock for MCAN0." "0,1"
newline
bitfld.long 0x4 2. "SCT0,Enables the clock for SCT0." "0,1"
bitfld.long 0x4 1. "RIT,Enables the clock for the Repetitive Interrupt Timer." "0,1"
newline
bitfld.long 0x4 0. "MRT,Enables the clock for the Multi-Rate Timer." "0,1"
line.long 0x8 "AHBCLKCTRL2,AHB Clock control n"
bitfld.long 0x8 20. "SC1,Enables the clock for the Smart card1 interface." "0,1"
bitfld.long 0x8 19. "SC0,Enables the clock for the Smart card0 interface." "0,1"
newline
bitfld.long 0x8 18. "SHA0,Enables the clock for the SHA interface." "0,1"
bitfld.long 0x8 17. "USB0HSL,Enables the clock for the USB host slave interface." "0,1"
newline
bitfld.long 0x8 16. "USB0HMR,Enables the clock for the USB host master interface." "0,1"
bitfld.long 0x8 15. "FLEXCOMM9,Enables the clock for the Flexcomm9 interface." "0,1"
newline
bitfld.long 0x8 14. "FLEXCOMM8,Enables the clock for the Flexcomm8 interface." "0,1"
bitfld.long 0x8 13. "RNG,Enables the clock for the RNG interface." "0,1"
newline
bitfld.long 0x8 12. "OTP,Enables the clock for the OTP interface." "0,1"
bitfld.long 0x8 11. "AES,Enables the clock for the AES interface." "0,1"
newline
bitfld.long 0x8 10. "GPIO5,Enables the clock for the GPIO5 interface." "0,1"
bitfld.long 0x8 9. "GPIO4,Enables the clock for the GPIO4 interface." "0,1"
newline
bitfld.long 0x8 8. "ETH,Enables the clock for the ethernet interface." "0,1"
bitfld.long 0x8 7. "EMC,Enables the clock for the EMC interface." "0,1"
newline
bitfld.long 0x8 6. "USB1RAM,Enables the clock for the USB1 RAM interface." "0,1"
bitfld.long 0x8 5. "USB1D,Enables the clock for the USB1 device interface." "0,1"
newline
bitfld.long 0x8 4. "USB1H,Enables the clock for the USB1 host interface." "0,1"
bitfld.long 0x8 3. "SDIO,Enables the clock for the SDIO interface." "0,1"
newline
bitfld.long 0x8 2. "LCD,Enables the clock for the LCD interface." "0,1"
endif
sif (cpuis("LPC54618*"))
repeat 3. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x220)++0x3
line.long 0x0 "AHBCLKCTRLSET[$1],Set bits in AHBCLKCTRLn"
hexmask.long 0x0 0.--31. 1. "CLK_SET,Writing ones to this register sets the corresponding bit or bits in the AHBCLKCTRLn register  if they are implemented. Bits that do not correspond to defined bits in AHBCLKCTRLn are reserved and only zeroes should be written to them."
repeat.end
endif
sif (cpuis("LPC54618*"))
repeat 3. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x240)++0x3
line.long 0x0 "AHBCLKCTRLCLR[$1],Clear bits in AHBCLKCTRLn"
hexmask.long 0x0 0.--31. 1. "CLK_CLR,Writing ones to this register clears the corresponding bit or bits in the AHBCLKCTRLn register  if they are implemented. Bits that do not correspond to defined bits in AHBCLKCTRLn are reserved and only zeroes should be written to them."
repeat.end
group.long 0x280++0xB
line.long 0x0 "MAINCLKSELA,Main clock source select A"
bitfld.long 0x0 0.--1. "SEL,Clock source for main clock source selector A" "0: FRO 12 MHz (fro_12m),1: CLKIN (clk_in),2: Watchdog oscillator (wdt_clk),3: FRO 96 or 48 MHz (fro_hf)"
line.long 0x4 "MAINCLKSELB,Main clock source select B"
bitfld.long 0x4 0.--1. "SEL,Clock source for main clock source selector B. Selects the clock source for the main clock." "0: MAINCLKSELA. Use the clock source selected in..,?,2: System PLL output (pll_clk),3: RTC oscillator 32 kHz output (32k_clk)"
line.long 0x8 "CLKOUTSELA,CLKOUT clock source select A"
bitfld.long 0x8 0.--2. "SEL,CLKOUT clock source selection" "0: Main clock (main_clk),1: CLKIN (clk_in),2: Watchdog oscillator (wdt_clk),3: FRO 96 or 48 MHz (fro_hf),4: PLL output (pll_clk),5: USB PLL clock (usb_pll_clk),6: Audio PLL clock (audio_pll_clk),7: RTC oscillator 32 kHz output (32k_clk)"
group.long 0x290++0x3
line.long 0x0 "SYSPLLCLKSEL,PLL clock source select"
bitfld.long 0x0 0.--2. "SEL,System PLL clock source selection." "0: FRO 12 MHz (fro_12m),1: CLKIN (clk_in),2: Watchdog oscillator (wdt_clk),3: RTC oscillator 32 kHz output (32k_clk),?,?,?,7: None this may be selected in order to reduce.."
group.long 0x298++0x3
line.long 0x0 "AUDPLLCLKSEL,Audio PLL clock source select"
bitfld.long 0x0 0.--2. "SEL,Audio PLL clock source selection." "0: FRO 12 MHz (fro_12m),1: CLKIN (clk_in),?,?,?,?,?,7: None this may be selected in order to reduce.."
group.long 0x2A0++0xF
line.long 0x0 "SPIFICLKSEL,SPIFI clock source select"
bitfld.long 0x0 0.--2. "SEL,System PLL clock source selection" "0: Main clock (main_clk),1: System PLL output (pll_clk),2: USB PLL clock (usb_pll_clk),3: FRO 96 or 48 MHz (fro_hf),4: Audio PLL clock (audio_pll_clk),?,?,7: None this may be selected in order to reduce.."
line.long 0x4 "ADCCLKSEL,ADC clock source select"
bitfld.long 0x4 0.--2. "SEL,ADC clock source selection" "0: FRO 96 or 48 MHz (fro_hf),1: System PLL output (pll_clk),2: USB PLL clock (usb_pll_clk),3: Audio PLL clock (audio_pll_clk),?,?,?,7: None this may be selected in order to reduce.."
line.long 0x8 "USB0CLKSEL,USB0 clock source select"
bitfld.long 0x8 0.--2. "SEL,USB0 device clock source selection." "0: FRO 96 or 48 MHz (fro_hf),1: System PLL output (pll_clk),2: USB PLL clock (usb_pll_clk),?,?,?,?,7: None this may be selected in order to reduce.."
line.long 0xC "USB1CLKSEL,USB1 clock source select"
bitfld.long 0xC 0.--2. "SEL,USB1 PHY clock source selection." "0: Main clock (main_clk),1: System PLL output (pll_clk),2: USB PLL clock (usb_pll_clk),?,?,?,?,7: None this may be selected in order to reduce.."
endif
sif (cpuis("LPC54618*"))
repeat 10. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2B0)++0x3
line.long 0x0 "FCLKSEL[$1],Flexcomm 0 clock source select"
bitfld.long 0x0 0.--2. "SEL,Flexcomm clock source selection. One per Flexcomm." "0: FRO 12 MHz (fro_12m),1: FRO HF DIV (fro_hf_div),2: Audio PLL clock (audio_pll_clk),3: MCLK pin input when selected in IOCON (mclk_in),4: FRG clock the output of the fractional rate..,?,?,7: None this may be selected in order to reduce.."
repeat.end
group.long 0x2E0++0x3
line.long 0x0 "MCLKCLKSEL,MCLK clock source select"
bitfld.long 0x0 0.--2. "SEL,MCLK source select. This may be used by Flexcomms that support I2S  and/or by the digital microphone subsystem." "0: FRO HF DIV (fro_hf_div),1: Audio PLL clock (audio_pll_clk),?,?,?,?,?,7: None this may be selected in order to reduce.."
group.long 0x2E8++0x13
line.long 0x0 "FRGCLKSEL,Fractional Rate Generator clock source select"
bitfld.long 0x0 0.--2. "SEL,Fractional Rate Generator clock source select." "0: Main clock (main_clk),1: System PLL output (pll_clk),2: FRO 12 MHz (fro_12m),3: FRO 96 or 48 MHz (fro_hf),?,?,?,7: None this may be selected in order to reduce.."
line.long 0x4 "DMICCLKSEL,Digital microphone (DMIC) subsystem clock select"
bitfld.long 0x4 0.--2. "SEL,DMIC (audio subsystem) clock source select." "0: FRO 12 MHz (fro_12m),1: FRO HF DIV (fro_hf_div),2: Audio PLL clock (audio_pll_clk),3: MCLK pin input when selected in IOCON (mclk_in),?,?,?,7: None this may be selected in order to reduce.."
line.long 0x8 "SCTCLKSEL,SCTimer/PWM clock source select"
bitfld.long 0x8 0.--2. "SEL,SCT clock source select." "0: Main clock (main_clk),1: System PLL output (pll_clk),2: FRO 96 or 48 MHz (fro_hf),3: Audio PLL clock (audio_pll_clk),?,?,?,7: None this may be selected in order to reduce.."
line.long 0xC "LCDCLKSEL,LCD clock source select"
bitfld.long 0xC 0.--1. "SEL,LCD clock source select." "0: Main clock (main_clk),1: LCDCLKIN (LCDCLK_EXT),2: FRO 96 or 48 MHz (fro_hf),3: None this may be selected in order to reduce.."
line.long 0x10 "SDIOCLKSEL,SDIO clock source select"
bitfld.long 0x10 0.--2. "SEL,SDIO clock source select." "0: Main clock (main_clk),1: System PLL output (pll_clk),2: USB PLL clock (usb_pll_clk),3: FRO 96 or 48 MHz (fro_hf),4: Audio PLL clock (audio_pll_clk),?,?,7: None this may be selected in order to reduce.."
group.long 0x300++0x17
line.long 0x0 "SYSTICKCLKDIV,SYSTICK clock divider"
bitfld.long 0x0 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x0 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x0 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count." "0,1"
hexmask.long.byte 0x0 0.--7. 1. "DIV,Clock divider value. 0: Divide by 1 up to 255: Divide by 256."
line.long 0x4 "ARMTRACECLKDIV,ARM Trace clock divider"
bitfld.long 0x4 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x4 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x4 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x4 0.--7. 1. "DIV,Clock divider value."
line.long 0x8 "CAN0CLKDIV,MCAN0 clock divider"
bitfld.long 0x8 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x8 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x8 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x8 0.--7. 1. "DIV,Clock divider value."
line.long 0xC "CAN1CLKDIV,MCAN1 clock divider"
bitfld.long 0xC 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0xC 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0xC 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count." "0,1"
hexmask.long.byte 0xC 0.--7. 1. "DIV,Clock divider value. 0: Divide by 1 up to 255: Divide by 256."
line.long 0x10 "SC0CLKDIV,Smartcard0 clock divider"
bitfld.long 0x10 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x10 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x10 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x10 0.--7. 1. "DIV,Clock divider value."
line.long 0x14 "SC1CLKDIV,Smartcard1 clock divider"
bitfld.long 0x14 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x14 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x14 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x14 0.--7. 1. "DIV,Clock divider value."
group.long 0x380++0xB
line.long 0x0 "AHBCLKDIV,AHB clock divider"
bitfld.long 0x0 31. "REQFLAG,Divider status flag." "0,1"
hexmask.long.byte 0x0 0.--7. 1. "DIV,Clock divider value. 0: Divide by 1 up to 255: Divide by 256."
line.long 0x4 "CLKOUTDIV,CLKOUT clock divider"
bitfld.long 0x4 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x4 30. "HALT,Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output." "0,1"
newline
bitfld.long 0x4 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count." "0,1"
hexmask.long.byte 0x4 0.--7. 1. "DIV,Clock divider value. 0: Divide by 1 up to 255: Divide by 256."
line.long 0x8 "FROHFCLKDIV,FROHF clock divider"
bitfld.long 0x8 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x8 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x8 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x8 0.--7. 1. "DIV,Clock divider value."
group.long 0x390++0x13
line.long 0x0 "SPIFICLKDIV,SPIFI clock divider"
bitfld.long 0x0 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x0 30. "HALT,Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output." "0,1"
newline
bitfld.long 0x0 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count." "0,1"
hexmask.long.byte 0x0 0.--7. 1. "DIV,Clock divider value."
line.long 0x4 "ADCCLKDIV,ADC clock divider"
bitfld.long 0x4 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x4 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x4 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x4 0.--7. 1. "DIV,Clock divider value."
line.long 0x8 "USB0CLKDIV,USB0 clock divider"
bitfld.long 0x8 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x8 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x8 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x8 0.--7. 1. "DIV,Clock divider value."
line.long 0xC "USB1CLKDIV,USB1 clock divider"
bitfld.long 0xC 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0xC 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0xC 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0xC 0.--7. 1. "DIV,Clock divider value."
line.long 0x10 "FRGCTRL,Fractional rate divider"
hexmask.long.byte 0x10 8.--15. 1. "MULT,Numerator of the fractional divider. MULT is equal to the programmed value."
hexmask.long.byte 0x10 0.--7. 1. "DIV,Denominator of the fractional divider. DIV is equal to the programmed value +1. Always set to 0xFF to use with the fractional baud rate generator."
group.long 0x3A8++0x17
line.long 0x0 "DMICCLKDIV,DMIC clock divider"
bitfld.long 0x0 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x0 30. "HALT,Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output." "0,1"
newline
bitfld.long 0x0 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count." "0,1"
hexmask.long.byte 0x0 0.--7. 1. "DIV,Clock divider value. 0: Divide by 1 up to 255: Divide by 256."
line.long 0x4 "MCLKDIV,I2S MCLK clock divider"
bitfld.long 0x4 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x4 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x4 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x4 0.--7. 1. "DIV,Clock divider value. 0: Divide by 1 up to 255: Divide by 256."
line.long 0x8 "LCDCLKDIV,LCD clock divider"
bitfld.long 0x8 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x8 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x8 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x8 0.--7. 1. "DIV,Clock divider value."
line.long 0xC "SCTCLKDIV,SCT/PWM clock divider"
bitfld.long 0xC 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0xC 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0xC 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0xC 0.--7. 1. "DIV,Clock divider value."
line.long 0x10 "EMCCLKDIV,EMC clock divider"
bitfld.long 0x10 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x10 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x10 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x10 0.--7. 1. "DIV,Clock divider value."
line.long 0x14 "SDIOCLKDIV,SDIO clock divider"
bitfld.long 0x14 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x14 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x14 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x14 0.--7. 1. "DIV,Clock divider value."
group.long 0x400++0x3
line.long 0x0 "FLASHCFG,Flash wait states configuration"
hexmask.long.byte 0x0 12.--15. 1. "FLASHTIM,Flash memory access time. The number of system clocks used for flash accesses is equal to FLASHTIM +1."
bitfld.long 0x0 6. "PREFOVR,Prefetch override. This bit only applies when PREFEN = 1 and a buffered instruction is completing for which the next flash line is not already buffered or being prefetched." "0: Any previously initiated prefetch will be..,1: Any previously initiated prefetch will be.."
newline
bitfld.long 0x0 5. "PREFEN,Prefetch enable." "0: No instruction prefetch is performed.,1: If the FETCHCFG field is not 0 the next flash.."
bitfld.long 0x0 4. "ACCEL,Acceleration enable." "0: Flash acceleration is disabled. Every flash read..,1: Flash acceleration is enabled. Performance is.."
newline
bitfld.long 0x0 2.--3. "DATACFG,Data read configuration. This field determines how flash accelerator buffers are used for data accesses." "0: Data accesses from flash are not buffered. Every..,1: One buffer is used for all data accesses.,2: All buffers may be used for data accesses.,?"
bitfld.long 0x0 0.--1. "FETCHCFG,Instruction fetch configuration. This field determines how flash accelerator buffers are used for instruction fetches." "0: Instruction fetches from flash are not buffered.,1: One buffer is used for all instruction fetches.,2: All buffers may be used for instruction fetches.,?"
group.long 0x40C++0x7
line.long 0x0 "USB0CLKCTRL,USB0 clock control"
bitfld.long 0x0 4. "PU_DISABLE,Internal pull-up disable control." "0,1"
bitfld.long 0x0 3. "POL_FS_HOST_CLK,USB0 Host USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt." "0,1"
newline
bitfld.long 0x0 2. "AP_FS_HOST_CLK,USB0 Host USB0_NEEDCLK signal control." "0,1"
bitfld.long 0x0 1. "POL_FS_DEV_CLK,USB0 Device USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt." "0,1"
newline
bitfld.long 0x0 0. "AP_FS_DEV_CLK,USB0 Device USB0_NEEDCLK signal control." "0,1"
line.long 0x4 "USB0CLKSTAT,USB0 clock status"
bitfld.long 0x4 1. "HOST_NEED_CLKST,USB0 Host USB0_NEEDCLK signal status." "0,1"
bitfld.long 0x4 0. "DEV_NEED_CLKST,USB0 Device USB0_NEEDCLK signal status." "0,1"
group.long 0x418++0x3
line.long 0x0 "FREQMECTRL,Frequency measure register"
bitfld.long 0x0 31. "PROG,Set this bit to one to initiate a frequency measurement cycle. Hardware clears this bit when the measurement cycle has completed and there is valid capture data in the CAPVAL field (bits 13:0)." "0,1"
hexmask.long.word 0x0 0.--13. 1. "CAPVAL,Stores the capture result which is used to calculate the frequency of the target clock. This field is read-only."
group.long 0x420++0xB
line.long 0x0 "MCLKIO,MCLK input/output control"
bitfld.long 0x0 0. "DIR,MCLK direction control." "0,1"
line.long 0x4 "USB1CLKCTRL,USB1 clock control"
bitfld.long 0x4 4. "HS_DEV_WAKEUP_N,External user wake-up signal for device mode; asserting this signal (active low) will result in exiting the low power mode; input to asynchronous control logic." "0,1"
bitfld.long 0x4 3. "POL_FS_HOST_CLK,USB1 Host need_clock polarity for triggering the USB1 wake-up interrupt." "0,1"
newline
bitfld.long 0x4 2. "AP_FS_HOST_CLK,USB1 Host need_clock signal control." "0,1"
bitfld.long 0x4 1. "POL_FS_DEV_CLK,USB1 Device need_clock polarity for triggering the USB1 wake-up interrupt." "0,1"
newline
bitfld.long 0x4 0. "AP_FS_DEV_CLK,USB1 Device need_clock signal control." "0,1"
line.long 0x8 "USB1CLKSTAT,USB1 clock status"
bitfld.long 0x8 1. "HOST_NEED_CLKST,USB1 Device host USB1_NEEDCLK signal status." "0,1"
bitfld.long 0x8 0. "DEV_NEED_CLKST,USB1 Device USB1_NEEDCLK signal status." "0,1"
group.long 0x444++0x13
line.long 0x0 "EMCSYSCTRL,EMC system control"
bitfld.long 0x0 3. "EMCFBCLKINSEL,External Memory Controller clock select." "0,1"
bitfld.long 0x0 2. "EMCBC,External Memory Controller burst control." "0,1"
newline
bitfld.long 0x0 1. "EMCRD,EMC Reset Disable." "0,1"
bitfld.long 0x0 0. "EMCSC,EMC Shift Control." "0,1"
line.long 0x4 "EMCDLYCTRL,EMC clock delay control"
hexmask.long.byte 0x4 8.--12. 1. "FBCLK_DELAY,Programmable delay value for the feedback clock that controls input data sampling."
hexmask.long.byte 0x4 0.--4. 1. "CMD_DELAY,Programmable delay value for EMC outputs in command delayed mode."
line.long 0x8 "EMCDLYCAL,EMC delay chain calibration control"
bitfld.long 0x8 15. "DONE,Measurement completion flag." "0,1"
bitfld.long 0x8 14. "START,Start control bit for the EMC calibration counter." "0,1"
newline
hexmask.long.byte 0x8 0.--7. 1. "CALVALUE,Returns the count of the approximately 50 MHz ring oscillator that occur during 32 clocks of the FRO 12 MHz."
line.long 0xC "ETHPHYSEL,Ethernet PHY Selection"
bitfld.long 0xC 2. "PHY_SEL,PHY interface select." "0,1"
line.long 0x10 "ETHSBDCTRL,Ethernet SBD flow control"
bitfld.long 0x10 0.--1. "SBD_CTRL,Sideband Flow Control." "0,1,2,3"
group.long 0x460++0x3
line.long 0x0 "SDIOCLKCTRL,SDIO CCLKIN phase and delay control"
bitfld.long 0x0 31. "CCLK_SAMPLE_DELAY_ACTIVE,Enables sample delay  as controlled by the CCLK_SAMPLE_DELAY field." "0,1"
hexmask.long.byte 0x0 24.--28. 1. "CCLK_SAMPLE_DELAY,Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in."
newline
bitfld.long 0x0 23. "CCLK_DRV_DELAY_ACTIVE,Enables drive delay  as controlled by the CCLK_DRV_DELAY field." "0,1"
hexmask.long.byte 0x0 16.--20. 1. "CCLK_DRV_DELAY,Programmable delay value by which cclk_in_drv is delayed with regard to cclk_in."
newline
bitfld.long 0x0 7. "PHASE_ACTIVE,sdio_clk by 2  before feeding into ccl_in  cclk_in_sample  and cclk_in_drv." "0,1"
bitfld.long 0x0 2.--3. "CCLK_SAMPLE_PHASE,Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in." "0,1,2,3"
newline
bitfld.long 0x0 0.--1. "CCLK_DRV_PHASE,Programmable delay value by which cclk_in_drv is phase-shifted with regard to cclk_in." "0,1,2,3"
group.long 0x500++0xF
line.long 0x0 "FROCTRL,FRO oscillator control"
bitfld.long 0x0 31. "WRTRIM,Write Trim value." "0,1"
bitfld.long 0x0 30. "HSPDCLK,High speed clock enable." "0,1"
newline
bitfld.long 0x0 25. "USBMODCHG,USB Mode value Change flag." "0,1"
bitfld.long 0x0 24. "USBCLKADJ,USB clock adjust mode." "0,1"
newline
hexmask.long.byte 0x0 16.--23. 1. "FREQTRIM,Frequency trim."
bitfld.long 0x0 14. "SEL,Select the FRO HF output frequency." "0,1"
newline
hexmask.long.word 0x0 0.--13. 1. "TRIM,This value is factory trimmed to account for bias and temperature compensation."
line.long 0x4 "SYSOSCCTRL,System oscillator control"
bitfld.long 0x4 1. "FREQRANGE,Determines frequency range for system oscillator." "0,1"
bitfld.long 0x4 0. "BYPASS,Bypass system oscillator." "0,1"
line.long 0x8 "WDTOSCCTRL,Watchdog oscillator control"
hexmask.long.byte 0x8 5.--9. 1. "FREQSEL,Frequency select."
hexmask.long.byte 0x8 0.--4. 1. "DIVSEL,Divider select."
line.long 0xC "RTCOSCCTRL,RTC oscillator 32 kHz output control"
bitfld.long 0xC 0. "EN,RTC 32 kHz clock enable." "0,1"
group.long 0x51C++0x7
line.long 0x0 "USBPLLCTRL,USB PLL control"
bitfld.long 0x0 14. "FBSEL,Feedback divider input clock control." "0,1"
bitfld.long 0x0 13. "BYPASS,Input clock bypass control." "0: CCO clock is sent to post dividers..,1: PLL input clock is sent to post dividers.."
newline
bitfld.long 0x0 12. "DIRECT,Direct CCO clock output control." "0: CCO Clock signal goes through post divider.,1: CCO Clock signal goes directly to output(s).."
bitfld.long 0x0 10.--11. "NSEL,PLL feedback Divider value." "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "PSEL,PLL Divider value." "0,1,2,3"
hexmask.long.byte 0x0 0.--7. 1. "MSEL,PLL feedback Divider value."
line.long 0x4 "USBPLLSTAT,USB PLL status"
bitfld.long 0x4 0. "LOCK,USBPLL lock indicator." "0,1"
group.long 0x580++0x13
line.long 0x0 "SYSPLLCTRL,System PLL control"
bitfld.long 0x0 20. "DIRECTO,PLL0 direct output enable." "0: Disabled. The PLL output divider (P divider) is..,1: Enabled. The PLL output divider (P divider) is.."
bitfld.long 0x0 19. "DIRECTI,PLL0 direct input enable." "0,1"
newline
bitfld.long 0x0 17. "UPLIMOFF,Disable upper frequency limiter." "0,1"
bitfld.long 0x0 15. "BYPASS,PLL bypass control." "0: Bypass disabled. PLL CCO is sent to the PLL..,1: Bypass enabled. PLL input clock is sent directly.."
newline
hexmask.long.byte 0x0 10.--14. 1. "SELP,Bandwidth select P value."
hexmask.long.byte 0x0 4.--9. 1. "SELI,Bandwidth select I value."
newline
hexmask.long.byte 0x0 0.--3. 1. "SELR,Bandwidth select R value."
line.long 0x4 "SYSPLLSTAT,PLL status"
bitfld.long 0x4 0. "LOCK,PLL lock indicator." "0,1"
line.long 0x8 "SYSPLLNDEC,PLL N divider"
bitfld.long 0x8 10. "NREQ,NDEC reload request." "0,1"
hexmask.long.word 0x8 0.--9. 1. "NDEC,Decoded N-divider coefficient value."
line.long 0xC "SYSPLLPDEC,PLL P divider"
bitfld.long 0xC 7. "PREQ,." "0,1"
hexmask.long.byte 0xC 0.--6. 1. "PDEC,Decoded P-divider coefficient value."
line.long 0x10 "SYSPLLMDEC,System PLL M divider"
bitfld.long 0x10 17. "MREQ,MDEC reload request." "0,1"
hexmask.long.tbyte 0x10 0.--16. 1. "MDEC,Decoded M-divider coefficient value."
group.long 0x5A0++0x17
line.long 0x0 "AUDPLLCTRL,Audio PLL control"
bitfld.long 0x0 20. "DIRECTO,PLL direct output enable" "0: Disabled. The PLL output divider (P divider) is..,1: Enabled. The PLL output divider (P divider) is.."
bitfld.long 0x0 19. "DIRECTI,PLL direct input enable." "0,1"
newline
bitfld.long 0x0 17. "UPLIMOFF,Disable upper frequency limiter." "0,1"
bitfld.long 0x0 15. "BYPASS,PLL bypass control." "0: Bypass disabled. PLL CCO is sent to the PLL..,1: Bypass enabled. PLL input clock is sent directly.."
newline
hexmask.long.byte 0x0 10.--14. 1. "SELP,."
hexmask.long.byte 0x0 4.--9. 1. "SELI,Bandwidth select I value."
newline
hexmask.long.byte 0x0 0.--3. 1. "SELR,Bandwidth select R value."
line.long 0x4 "AUDPLLSTAT,Audio PLL status"
bitfld.long 0x4 0. "LOCK,PLL lock indicator." "0,1"
line.long 0x8 "AUDPLLNDEC,Audio PLL N divider"
bitfld.long 0x8 10. "NREQ,NDEC reload request." "0,1"
hexmask.long.word 0x8 0.--9. 1. "NDEC,Decoded N-divider coefficient value."
line.long 0xC "AUDPLLPDEC,Audio PLL P divider"
bitfld.long 0xC 7. "PREQ,PDEC reload request." "0,1"
hexmask.long.byte 0xC 0.--6. 1. "PDEC,Decoded P-divider coefficient value."
line.long 0x10 "AUDPLLMDEC,Audio PLL M divider"
bitfld.long 0x10 17. "MREQ,MDEC reload request." "0,1"
hexmask.long.tbyte 0x10 0.--16. 1. "MDEC,Decoded M-divider coefficient value."
line.long 0x14 "AUDPLLFRAC,Audio PLL fractional divider control"
bitfld.long 0x14 23. "SEL_EXT,Select fractional divider." "0,1"
bitfld.long 0x14 22. "REQ,Writing 1 to REQ signal loads CTRL value into fractional wrapper modulator." "0,1"
newline
hexmask.long.tbyte 0x14 0.--21. 1. "CTRL,PLL fractional divider control word"
group.long 0x600++0x7
line.long 0x0 "PDSLEEPCFG0,Sleep configuration register"
bitfld.long 0x0 29. "PDEN_VD6,Power control for EEPROM." "0,1"
bitfld.long 0x0 28. "PDEN_VD5,Power control both USB0 PHY and USB1 PHY." "0,1"
newline
bitfld.long 0x0 27. "PDEN_VD4,Power control for all SRAMs and ROM." "0,1"
bitfld.long 0x0 26. "PDEN_VD3,Power control for all PLLs." "0,1"
newline
bitfld.long 0x0 23. "PDEN_VREFP,VREFP to the ADC must be enabled for the ADC to work (also enable/disable bit 9  10  and 19)." "0,1"
bitfld.long 0x0 22. "PDEN_SYS_PLL,System PLL (PLL0) power (also enable/disable bit 26)." "0,1"
newline
bitfld.long 0x0 21. "PDEN_USB0_PHY,USB0 PHY power (also enable/disable bit 28)." "0,1"
bitfld.long 0x0 20. "PDEN_WDT_OSC,Watchdog oscillator." "0,1"
newline
bitfld.long 0x0 19. "PDEN_VDDA,Vdda to the ADC  must be enabled for the ADC to work (also enable/disable bit 9  10  and 23)." "0,1"
bitfld.long 0x0 17. "PDEN_ROM,ROM (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 16. "PDEN_USB_RAM,PDEN_USB_SRAM controls USB_RAM (also enable/disable bit 27)." "0,1"
bitfld.long 0x0 15. "PDEN_SRAM1_2_3,PDEN_SRAM1_2_3 controls SRAM1  SRAM2  and SRAM3 (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 14. "PDEN_SRAM0,PDEN_SRAM0 controls SRAM0 (also enable/disable bit 27)." "0,1"
bitfld.long 0x0 13. "PDEN_SRAMX,PDEN_SRAMX controls SRAMX (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 10. "PDEN_ADC0,ADC power." "0,1"
bitfld.long 0x0 9. "PDEN_VD2_ANA,Analog supply for System Oscillator (also enable/disable bit 3 in PDRUNCFG1 register)  Temperature Sensor (also  enable/disable bit 6)  ADC (also  enable/disable bits 10  19  and 23)." "0,1"
newline
bitfld.long 0x0 8. "PDEN_BOD_INTR,Brown-out Detect interrupt." "0,1"
bitfld.long 0x0 7. "PDEN_BOD_RST,Brown-out Detect reset." "0,1"
newline
bitfld.long 0x0 6. "PDEN_TS,Temp sensor." "0,1"
bitfld.long 0x0 4. "PDEN_FRO,FRO oscillator." "0,1"
line.long 0x4 "PDSLEEPCFG1,Sleep configuration register"
bitfld.long 0x4 7. "PDEN_RNG,Random Number Generator Power." "0,1"
bitfld.long 0x4 5. "PDEN_EEPROM,EEPROM power (also  enable/disable bit 29 in PDRUNCFG0 register)." "0,1"
newline
bitfld.long 0x4 3. "PDEN_SYSOSC,System Oscillator Power (also  enable/disable bit 9 in PDRUNCFG0 register)." "0,1"
bitfld.long 0x4 2. "PDEN_AUD_PLL,Audio PLL (PLL2) power and fractional divider (also  enable/disable bit 26 in PDRUNCFG0 register)." "0,1"
newline
bitfld.long 0x4 1. "PDEN_USB1_PLL,USB PLL (PLL1) power (also  enable/disable bit 26 in PDRUNCFG0 register)." "0,1"
bitfld.long 0x4 0. "PDEN_USB1_PHY,USB1 high speed PHY (also  enable/disable bit 28 in PDRUNCFG0 register)." "0,1"
group.long 0x610++0x7
line.long 0x0 "PDRUNCFG0,Power configuration register"
bitfld.long 0x0 29. "PDEN_VD6,Power control for EEPROM." "0,1"
bitfld.long 0x0 28. "PDEN_VD5,Power control both USB0 PHY and USB1 PHY." "0,1"
newline
bitfld.long 0x0 27. "PDEN_VD4,Power control for all SRAMs and ROM." "0,1"
bitfld.long 0x0 26. "PDEN_VD3,Power control for all PLLs." "0,1"
newline
bitfld.long 0x0 23. "PDEN_VREFP,VREFP to the ADC must be enabled for the ADC to work (also enable/disable bit 9  10  and 19)." "0,1"
bitfld.long 0x0 22. "PDEN_SYS_PLL,System PLL (PLL0) power (also enable/disable bit 26)." "0,1"
newline
bitfld.long 0x0 21. "PDEN_USB0_PHY,USB0 PHY power (also enable/disable bit 28)." "0,1"
bitfld.long 0x0 20. "PDEN_WDT_OSC,Watchdog oscillator." "0,1"
newline
bitfld.long 0x0 19. "PDEN_VDDA,Vdda to the ADC  must be enabled for the ADC to work (also enable/disable bit 9  10  and 23)." "0,1"
bitfld.long 0x0 17. "PDEN_ROM,ROM (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 16. "PDEN_USB_RAM,PDEN_USB_SRAM controls USB_RAM (also enable/disable bit 27)." "0,1"
bitfld.long 0x0 15. "PDEN_SRAM1_2_3,PDEN_SRAM1_2_3 controls SRAM1  SRAM2  and SRAM3 (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 14. "PDEN_SRAM0,PDEN_SRAM0 controls SRAM0 (also enable/disable bit 27)." "0,1"
bitfld.long 0x0 13. "PDEN_SRAMX,PDEN_SRAMX controls SRAMX (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 10. "PDEN_ADC0,ADC power." "0,1"
bitfld.long 0x0 9. "PDEN_VD2_ANA,Analog supply for System Oscillator (also enable/disable bit 3 in PDRUNCFG1 register)  Temperature Sensor (also  enable/disable bit 6)  ADC (also  enable/disable bits 10  19  and 23)." "0,1"
newline
bitfld.long 0x0 8. "PDEN_BOD_INTR,Brown-out Detect interrupt." "0,1"
bitfld.long 0x0 7. "PDEN_BOD_RST,Brown-out Detect reset." "0,1"
newline
bitfld.long 0x0 6. "PDEN_TS,Temp sensor." "0,1"
bitfld.long 0x0 4. "PDEN_FRO,FRO oscillator." "0,1"
line.long 0x4 "PDRUNCFG1,Power configuration register"
bitfld.long 0x4 7. "PDEN_RNG,Random Number Generator Power." "0,1"
bitfld.long 0x4 5. "PDEN_EEPROM,EEPROM power (also  enable/disable bit 29 in PDRUNCFG0 register)." "0,1"
newline
bitfld.long 0x4 3. "PDEN_SYSOSC,System Oscillator Power (also  enable/disable bit 9 in PDRUNCFG0 register)." "0,1"
bitfld.long 0x4 2. "PDEN_AUD_PLL,Audio PLL (PLL2) power and fractional divider (also  enable/disable bit 26 in PDRUNCFG0 register)." "0,1"
newline
bitfld.long 0x4 1. "PDEN_USB1_PLL,USB PLL (PLL1) power (also  enable/disable bit 26 in PDRUNCFG0 register)." "0,1"
bitfld.long 0x4 0. "PDEN_USB1_PHY,USB1 high speed PHY (also  enable/disable bit 28 in PDRUNCFG0 register)." "0,1"
group.long 0x620++0x7
line.long 0x0 "PDRUNCFGSET0,Power configuration set register"
bitfld.long 0x0 29. "PDEN_VD6,Power control for EEPROM." "0,1"
bitfld.long 0x0 28. "PDEN_VD5,Power control both USB0 PHY and USB1 PHY." "0,1"
newline
bitfld.long 0x0 27. "PDEN_VD4,Power control for all SRAMs and ROM." "0,1"
bitfld.long 0x0 26. "PDEN_VD3,Power control for all PLLs." "0,1"
newline
bitfld.long 0x0 23. "PDEN_VREFP,VREFP to the ADC must be enabled for the ADC to work (also enable/disable bit 9  10  and 19)." "0,1"
bitfld.long 0x0 22. "PDEN_SYS_PLL,System PLL (PLL0) power (also enable/disable bit 26)." "0,1"
newline
bitfld.long 0x0 21. "PDEN_USB0_PHY,USB0 PHY power (also enable/disable bit 28)." "0,1"
bitfld.long 0x0 20. "PDEN_WDT_OSC,Watchdog oscillator." "0,1"
newline
bitfld.long 0x0 19. "PDEN_VDDA,Vdda to the ADC  must be enabled for the ADC to work (also enable/disable bit 9  10  and 23)." "0,1"
bitfld.long 0x0 17. "PDEN_ROM,ROM (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 16. "PDEN_USB_RAM,PDEN_USB_SRAM controls USB_RAM (also enable/disable bit 27)." "0,1"
bitfld.long 0x0 15. "PDEN_SRAM1_2_3,PDEN_SRAM1_2_3 controls SRAM1  SRAM2  and SRAM3 (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 14. "PDEN_SRAM0,PDEN_SRAM0 controls SRAM0 (also enable/disable bit 27)." "0,1"
bitfld.long 0x0 13. "PDEN_SRAMX,PDEN_SRAMX controls SRAMX (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 10. "PDEN_ADC0,ADC power." "0,1"
bitfld.long 0x0 9. "PDEN_VD2_ANA,Analog supply for System Oscillator (also enable/disable bit 3 in PDRUNCFG1 register)  Temperature Sensor (also  enable/disable bit 6)  ADC (also  enable/disable bits 10  19  and 23)." "0,1"
newline
bitfld.long 0x0 8. "PDEN_BOD_INTR,Brown-out Detect interrupt." "0,1"
bitfld.long 0x0 7. "PDEN_BOD_RST,Brown-out Detect reset." "0,1"
newline
bitfld.long 0x0 6. "PDEN_TS,Temp sensor." "0,1"
bitfld.long 0x0 4. "PDEN_FRO,FRO oscillator." "0,1"
line.long 0x4 "PDRUNCFGSET1,Power configuration set register"
bitfld.long 0x4 7. "PDEN_RNG,Random Number Generator Power." "0,1"
bitfld.long 0x4 5. "PDEN_EEPROM,EEPROM power (also  enable/disable bit 29 in PDRUNCFG0 register)." "0,1"
newline
bitfld.long 0x4 3. "PDEN_SYSOSC,System Oscillator Power (also  enable/disable bit 9 in PDRUNCFG0 register)." "0,1"
bitfld.long 0x4 2. "PDEN_AUD_PLL,Audio PLL (PLL2) power and fractional divider (also  enable/disable bit 26 in PDRUNCFG0 register)." "0,1"
newline
bitfld.long 0x4 1. "PDEN_USB1_PLL,USB PLL (PLL1) power (also  enable/disable bit 26 in PDRUNCFG0 register)." "0,1"
bitfld.long 0x4 0. "PDEN_USB1_PHY,USB1 high speed PHY (also  enable/disable bit 28 in PDRUNCFG0 register)." "0,1"
group.long 0x630++0x7
line.long 0x0 "PDRUNCFGCLR0,Power configuration clear register"
bitfld.long 0x0 29. "PDEN_VD6,Power control for EEPROM." "0,1"
bitfld.long 0x0 28. "PDEN_VD5,Power control both USB0 PHY and USB1 PHY." "0,1"
newline
bitfld.long 0x0 27. "PDEN_VD4,Power control for all SRAMs and ROM." "0,1"
bitfld.long 0x0 26. "PDEN_VD3,Power control for all PLLs." "0,1"
newline
bitfld.long 0x0 23. "PDEN_VREFP,VREFP to the ADC must be enabled for the ADC to work (also enable/disable bit 9  10  and 19)." "0,1"
bitfld.long 0x0 22. "PDEN_SYS_PLL,System PLL (PLL0) power (also enable/disable bit 26)." "0,1"
newline
bitfld.long 0x0 21. "PDEN_USB0_PHY,USB0 PHY power (also enable/disable bit 28)." "0,1"
bitfld.long 0x0 20. "PDEN_WDT_OSC,Watchdog oscillator." "0,1"
newline
bitfld.long 0x0 19. "PDEN_VDDA,Vdda to the ADC  must be enabled for the ADC to work (also enable/disable bit 9  10  and 23)." "0,1"
bitfld.long 0x0 17. "PDEN_ROM,ROM (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 16. "PDEN_USB_RAM,PDEN_USB_SRAM controls USB_RAM (also enable/disable bit 27)." "0,1"
bitfld.long 0x0 15. "PDEN_SRAM1_2_3,PDEN_SRAM1_2_3 controls SRAM1  SRAM2  and SRAM3 (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 14. "PDEN_SRAM0,PDEN_SRAM0 controls SRAM0 (also enable/disable bit 27)." "0,1"
bitfld.long 0x0 13. "PDEN_SRAMX,PDEN_SRAMX controls SRAMX (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 10. "PDEN_ADC0,ADC power." "0,1"
bitfld.long 0x0 9. "PDEN_VD2_ANA,Analog supply for System Oscillator (also enable/disable bit 3 in PDRUNCFG1 register)  Temperature Sensor (also  enable/disable bit 6)  ADC (also  enable/disable bits 10  19  and 23)." "0,1"
newline
bitfld.long 0x0 8. "PDEN_BOD_INTR,Brown-out Detect interrupt." "0,1"
bitfld.long 0x0 7. "PDEN_BOD_RST,Brown-out Detect reset." "0,1"
newline
bitfld.long 0x0 6. "PDEN_TS,Temp sensor." "0,1"
bitfld.long 0x0 4. "PDEN_FRO,FRO oscillator." "0,1"
line.long 0x4 "PDRUNCFGCLR1,Power configuration clear register"
bitfld.long 0x4 7. "PDEN_RNG,Random Number Generator Power." "0,1"
bitfld.long 0x4 5. "PDEN_EEPROM,EEPROM power (also  enable/disable bit 29 in PDRUNCFG0 register)." "0,1"
newline
bitfld.long 0x4 3. "PDEN_SYSOSC,System Oscillator Power (also  enable/disable bit 9 in PDRUNCFG0 register)." "0,1"
bitfld.long 0x4 2. "PDEN_AUD_PLL,Audio PLL (PLL2) power and fractional divider (also  enable/disable bit 26 in PDRUNCFG0 register)." "0,1"
newline
bitfld.long 0x4 1. "PDEN_USB1_PLL,USB PLL (PLL1) power (also  enable/disable bit 26 in PDRUNCFG0 register)." "0,1"
bitfld.long 0x4 0. "PDEN_USB1_PHY,USB1 high speed PHY (also  enable/disable bit 28 in PDRUNCFG0 register)." "0,1"
group.long 0x680++0x7
line.long 0x0 "STARTER0,Start logic 0 wake-up enable register"
bitfld.long 0x0 29. "RTC,RTC interrupt alarm and wake-up timer." "0,1"
bitfld.long 0x0 28. "USB0,USB function interrupt wake-up." "0,1"
newline
bitfld.long 0x0 27. "USB0_NEEDCLK,USB activity interrupt wake-up." "0,1"
bitfld.long 0x0 26. "HWVAD,Hardware voice activity detect interrupt wake-up." "0,1"
newline
bitfld.long 0x0 25. "DMIC,Digital microphone interrupt wake-up." "0,1"
bitfld.long 0x0 24. "ADC0_THCMP,ADC0 threshold and error interrupt wake-up." "0,1"
newline
bitfld.long 0x0 23. "ADC0_SEQB,ADC0 sequence B interrupt wake-up." "0,1"
bitfld.long 0x0 22. "ADC0_SEQA,ADC0 sequence A interrupt wake-up." "0,1"
newline
bitfld.long 0x0 21. "FLEXCOMM7,Flexcomm7 peripheral interrupt wake-up." "0,1"
bitfld.long 0x0 20. "FLEXCOMM6,Flexcomm6 peripheral interrupt wake-up." "0,1"
newline
bitfld.long 0x0 19. "FLEXCOMM5,Flexcomm5 peripheral interrupt wake-up." "0,1"
bitfld.long 0x0 18. "FLEXCOMM4,Flexcomm4 peripheral interrupt wake-up." "0,1"
newline
bitfld.long 0x0 17. "FLEXCOMM3,Flexcomm3 peripheral interrupt wake-up." "0,1"
bitfld.long 0x0 16. "FLEXCOMM2,Flexcomm2 peripheral interrupt wake-up." "0,1"
newline
bitfld.long 0x0 15. "FLEXCOMM1,Flexcomm1 peripheral interrupt wake-up." "0,1"
bitfld.long 0x0 14. "FLEXCOMM0,Flexcomm0 peripheral interrupt wake-up." "0,1"
newline
bitfld.long 0x0 13. "CTIMER3,Standard counter/timer CTIMER3 wake-up." "0,1"
bitfld.long 0x0 12. "SCT0,SCT0 wake-up." "0,1"
newline
bitfld.long 0x0 11. "CTIMER1,Standard counter/timer CTIMER1 wake-up." "0,1"
bitfld.long 0x0 10. "CTIMER0,Standard counter/timer CTIMER0 wake-up." "0,1"
newline
bitfld.long 0x0 9. "MRT,Multi-Rate Timer wake-up." "0,1"
bitfld.long 0x0 8. "UTICK,Micro-tick Timer wake-up." "0,1"
newline
bitfld.long 0x0 7. "PIN_INT3,GPIO pin interrupt 3 wake-up." "0,1"
bitfld.long 0x0 6. "PIN_INT2,GPIO pin interrupt 2 wake-up." "0,1"
newline
bitfld.long 0x0 5. "PIN_INT1,GPIO pin interrupt 1 wake-up." "0,1"
bitfld.long 0x0 4. "PIN_INT0,GPIO pin interrupt 0 wake-up." "0,1"
newline
bitfld.long 0x0 3. "GINT1,Group interrupt 1 wake-up." "0,1"
bitfld.long 0x0 2. "GINT0,Group interrupt 0 wake-up." "0,1"
newline
bitfld.long 0x0 1. "DMA,DMA wake-up." "0,1"
bitfld.long 0x0 0. "WDT_BOD,WWDT and BOD interrupt wake-up." "0,1"
line.long 0x4 "STARTER1,Start logic 0 wake-up enable register"
bitfld.long 0x4 24. "SMARTCARD1,Smart card 1 wake-up." "0,1"
bitfld.long 0x4 23. "SMARTCARD0,Smart card 0 wake-up." "0,1"
newline
bitfld.long 0x4 19. "ENET_INT0,Ethernet." "0,1"
bitfld.long 0x4 18. "ENET_INT2,Ethernet." "0,1"
newline
bitfld.long 0x4 17. "ENET_INT1,Ethernet." "0,1"
bitfld.long 0x4 16. "USB1_ACT,USB 1 activity wake-up." "0,1"
newline
bitfld.long 0x4 15. "USB1,USB 1 wake-up." "0,1"
bitfld.long 0x4 9. "FLEXCOMM9,Flexcomm Interface 9 wake-up." "0,1"
newline
bitfld.long 0x4 8. "FLEXCOMM8,Flexcomm Interface 8 wake-up." "0,1"
bitfld.long 0x4 7. "SPIFI,SPIFI interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled." "0: Wake-up disabled,1: Wake-up enabled"
newline
bitfld.long 0x4 5. "CTIMER4,Standard counter/timer CTIMER4 wake-up." "0,1"
bitfld.long 0x4 4. "CTIMER2,Standard counter/timer CTIMER2 wake-up." "0,1"
newline
bitfld.long 0x4 3. "PINT7,GPIO pin interrupt 7 wake-up." "0,1"
bitfld.long 0x4 2. "PINT6,GPIO pin interrupt 6 wake-up." "0,1"
newline
bitfld.long 0x4 1. "PINT5,GPIO pin interrupt 5 wake-up." "0,1"
bitfld.long 0x4 0. "PINT4,GPIO pin interrupt 4 wake-up." "0,1"
group.long 0x780++0x3
line.long 0x0 "HWWAKE,Configures special cases of hardware wake-up"
bitfld.long 0x0 3. "WAKEDMA,Wake for DMA. When 1  DMA being busy will cause peripheral clocking to remain running until DMA completes. This is generally used in conjunction with bit 1 and/or 2 in order to prevent peripheral clocking from being shut down as soon as the cause.." "0,1"
bitfld.long 0x0 2. "WAKEDMIC,Wake for Digital Microphone. When 1  the digital microphone input FIFO reaching the level specified by TRIGLVL of either channel will cause peripheral clocking to wake up temporarily while the related status is asserted." "0,1"
newline
bitfld.long 0x0 1. "FCWAKE,Wake for Flexcomms. When 1  any Flexcomm FIFO reaching the level specified by its own TXLVL will cause peripheral clocking to wake up temporarily while the related status is asserted." "0,1"
bitfld.long 0x0 0. "FORCEWAKE,Force peripheral clocking to stay on during Deep Sleep and Power-down modes. When 1  clocking to peripherals is prevented from being shut down when the CPU enters Deep Sleep and Power-down modes. This is intended to allow a coprocessor to.." "0,1"
group.long 0xE04++0x3
line.long 0x0 "AUTOCGOR,Auto Clock-Gate Override Register"
bitfld.long 0x0 4. "RAM3,When 1  automatic clock gating for RAM1 are turned off." "0,1"
bitfld.long 0x0 3. "RAM2,When 1  automatic clock gating for RAM1 are turned off." "0,1"
newline
bitfld.long 0x0 2. "RAM1,When 1  automatic clock gating for RAM1 are turned off." "0,1"
bitfld.long 0x0 1. "RAM0X,When 1  automatic clock gating for RAMX and RAM0 are turned off." "0,1"
rgroup.long 0xFF4++0xB
line.long 0x0 "JTAGIDCODE,JTAG ID code register"
hexmask.long 0x0 0.--31. 1. "JTAGID,JTAG ID code."
line.long 0x4 "DEVICE_ID0,Part ID register"
hexmask.long 0x4 0.--31. 1. "PARTID,Part ID"
line.long 0x8 "DEVICE_ID1,Boot ROM and die revision register"
hexmask.long 0x8 0.--31. 1. "REVID,Revision."
group.long 0x20044++0x3
line.long 0x0 "BODCTRL,Brown-Out Detect control"
bitfld.long 0x0 7. "BODINTSTAT,BOD interrupt status. When 1  a BOD interrupt has occurred. Cleared by writing 1 to this bit." "0,1"
bitfld.long 0x0 6. "BODRSTSTAT,BOD reset status. When 1  a BOD reset has occurred. Cleared by writing 1 to this bit." "0,1"
newline
bitfld.long 0x0 5. "BODINTENA,BOD interrupt enable" "0: Disable interrupt function.,1: Enable interrupt function."
bitfld.long 0x0 3.--4. "BODINTLEV,BOD interrupt level" "0: Level 0: 2.05 V,1: Level 1: 2.45 V,2: Level 2: 2.75 V,3: Level 3: 3.05 V"
newline
bitfld.long 0x0 2. "BODRSTENA,BOD reset enable" "0: Disable reset function.,1: Enable reset function."
bitfld.long 0x0 0.--1. "BODRSTLEV,BOD reset level" "0: Level 0: 1.5 V,1: Level 1: 1.85 V,2: Level 2: 2.0 V,3: Level 3: 2.3 V"
endif
sif (cpuis("LPC54628*"))
group.long 0x10++0x3
line.long 0x0 "AHBMATPRIO,AHB multilayer matrix priority control"
bitfld.long 0x0 24.--25. "PRI_SHA,SHA priority." "0,1,2,3"
bitfld.long 0x0 22.--23. "PRI_MCAN2,MCAN2 priority." "0,1,2,3"
newline
bitfld.long 0x0 20.--21. "PRI_MCAN1,MCAN1 priority." "0,1,2,3"
bitfld.long 0x0 18.--19. "PRI_SDIO,SDIO priority." "0,1,2,3"
newline
bitfld.long 0x0 16.--17. "PRI_USB1,USB1 DMA priority." "0,1,2,3"
bitfld.long 0x0 14.--15. "PRI_USB0,USB0 DMA priority." "0,1,2,3"
newline
bitfld.long 0x0 12.--13. "PRI_LCD,LCD DMA priority." "0,1,2,3"
bitfld.long 0x0 10.--11. "PRI_ETH,Ethernet DMA priority." "0,1,2,3"
newline
hexmask.long.byte 0x0 6.--9. 1. "PRI_DMA,DMA controller priority."
bitfld.long 0x0 4.--5. "PRI_SYS,System bus priority." "0,1,2,3"
newline
bitfld.long 0x0 2.--3. "PRI_DCODE,D-Code bus priority." "0,1,2,3"
bitfld.long 0x0 0.--1. "PRI_ICODE,I-Code bus priority." "0,1,2,3"
group.long 0x40++0x3
line.long 0x0 "SYSTCKCAL,System tick counter calibration"
bitfld.long 0x0 25. "NOREF,Initial value for the Systick timer." "0,1"
bitfld.long 0x0 24. "SKEW,Initial value for the Systick timer." "0,1"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "CAL,System tick timer calibration value."
group.long 0x48++0x7
line.long 0x0 "NMISRC,NMI Source Select"
bitfld.long 0x0 31. "NMIENM4,Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQM4." "0,1"
hexmask.long.byte 0x0 0.--5. 1. "IRQM4,The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the Cortex-M4  if enabled by NMIENM4."
line.long 0x4 "ASYNCAPBCTRL,Asynchronous APB Control"
bitfld.long 0x4 0. "ENABLE,Enables the asynchronous APB bridge and subsystem." "0: Disabled. Asynchronous APB bridge is disabled.,1: Enabled. Asynchronous APB bridge is enabled."
endif
sif (cpuis("LPC54628*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0xC0)++0x3
line.long 0x0 "PIOPORCAP[$1],POR captured value of port n"
hexmask.long 0x0 0.--31. 1. "PIOPORCAP,State of PIOn_31 through PIOn_0 at power-on reset"
repeat.end
endif
sif (cpuis("LPC54628*"))
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0xD0)++0x3
line.long 0x0 "PIORESCAP[$1],Reset captured value of port n"
hexmask.long 0x0 0.--31. 1. "PIORESCAP,State of PIOn_31 through PIOn_0 for resets other than POR."
repeat.end
group.long 0x100++0xB
line.long 0x0 "PRESETCTRL0,Peripheral reset control n"
bitfld.long 0x0 27. "ADC0_RST,ADC0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 22. "WWDT_RST,Watchdog timer reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x0 21. "CRC_RST,CRC generator reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 20. "DMA0_RST,DMA0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x0 19. "GINT_RST,Grouped interrupt (GINT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 18. "PINT_RST,Pin interrupt (PINT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x0 17. "GPIO3_RST,GPIO3 reset control." "0,1"
bitfld.long 0x0 16. "GPIO2_RST,GPIO2 reset control." "0,1"
newline
bitfld.long 0x0 15. "GPIO1_RST,GPIO1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 14. "GPIO0_RST,GPIO0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x0 13. "IOCON_RST,IOCON reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 11. "MUX_RST,Input mux reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x0 10. "SPIFI_RST,SPIFI reset control." "0,1"
bitfld.long 0x0 9. "EEPROM_RST,EEPROM reset control." "0,1"
newline
bitfld.long 0x0 8. "FMC_RST,Flash accelerator reset control. Note that the FMC must not be reset while executing from flash  and must be reconfigured after reset. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x0 7. "FLASH_RST,Flash controller reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
line.long 0x4 "PRESETCTRL1,Peripheral reset control n"
bitfld.long 0x4 27. "CTIMER1_RST,CTIMER1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 26. "CTIMER0_RST,CTIMER0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 25. "USB0D_RST,USB0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 22. "CTIMER2_RST,CTIMER2 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function" "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 19. "DMIC_RST,Digital microphone interface reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 18. "FC7_RST,Flexcomm 7 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 17. "FC6_RST,Flexcomm 6 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 16. "FC5_RST,Flexcomm 5 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 15. "FC4_RST,Flexcomm 4 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 14. "FC3_RST,Flexcomm 3 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 13. "FC2_RST,Flexcomm 2 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 12. "FC1_RST,Flexcomm 1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 11. "FC0_RST,Flexcomm 0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 10. "UTICK_RST,Micro-tick Timer reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
newline
bitfld.long 0x4 8. "MCAN1_RST,0 = Clear reset to this function." "0: Clear reset to this function,?"
bitfld.long 0x4 7. "MCAN0_RST,0 = Clear reset to this function." "0: Clear reset to this function,?"
newline
bitfld.long 0x4 2. "SCT0_RST,State configurable timer 0 (SCT0) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
bitfld.long 0x4 0. "MRT_RST,Multi-rate timer (MRT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function." "0: Clear reset to this function,1: Assert reset to this function"
line.long 0x8 "PRESETCTRL2,Peripheral reset control n"
bitfld.long 0x8 20. "SC1_RST,Smart card 1 reset control." "0,1"
bitfld.long 0x8 19. "SC0_RST,Smart card 0 reset control." "0,1"
newline
bitfld.long 0x8 18. "SHA_RST,SHA reset control." "0,1"
bitfld.long 0x8 17. "USB0HSL_RST,USB0 HOST slave reset control." "0,1"
newline
bitfld.long 0x8 16. "USB0HMR_RST,USB0 HOST master reset control." "0,1"
bitfld.long 0x8 15. "FC9_RST,Flexcomm 9 reset control." "0,1"
newline
bitfld.long 0x8 14. "FC8_RST,Flexcomm 8 reset control." "0,1"
bitfld.long 0x8 13. "RNG_RST,RNG reset control." "0,1"
newline
bitfld.long 0x8 12. "OTP_RST,OTP reset control." "0,1"
bitfld.long 0x8 11. "AES_RST,AES reset control." "0,1"
newline
bitfld.long 0x8 10. "GPIO5_RST,GPIO5 reset control." "0,1"
bitfld.long 0x8 9. "GPIO4_RST,GPIO4 reset control." "0,1"
newline
bitfld.long 0x8 8. "ETH_RST,Ethernet reset control." "0,1"
bitfld.long 0x8 7. "EMC_RESET,EMC reset control." "0,1"
newline
bitfld.long 0x8 6. "USB1RAM_RST,USB1 RAM reset control." "0,1"
bitfld.long 0x8 5. "USB1D_RST,USB1 Device reset control." "0,1"
newline
bitfld.long 0x8 4. "USB1H_RST,USB1 Host reset control." "0,1"
bitfld.long 0x8 3. "SDIO_RST,SDIO reset control." "0,1"
newline
bitfld.long 0x8 2. "LCD_RST,LCD reset control." "0,1"
endif
sif (cpuis("LPC54628*"))
repeat 3. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x120)++0x3
line.long 0x0 "PRESETCTRLSET[$1],Set bits in PRESETCTRLn"
hexmask.long 0x0 0.--31. 1. "RST_SET,Writing ones to this register sets the corresponding bit or bits in the PRESETCTRLn register  if they are implemented. Bits that do not correspond to defined bits in PRESETCTRLn are reserved and only zeroes should be written to them."
repeat.end
endif
sif (cpuis("LPC54628*"))
repeat 3. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x140)++0x3
line.long 0x0 "PRESETCTRLCLR[$1],Clear bits in PRESETCTRLn"
hexmask.long 0x0 0.--31. 1. "RST_CLR,Writing ones to this register clears the corresponding bit or bits in the PRESETCTRLn register  if they are implemented. Bits that do not correspond to defined bits in PRESETCTRLn are reserved and only zeroes should be written to them."
repeat.end
group.long 0x1F0++0x3
line.long 0x0 "SYSRSTSTAT,System reset status register"
bitfld.long 0x0 4. "SYSRST,Status of the software system reset" "0: No System reset detected,1: System reset detected. Writing a one clears this.."
bitfld.long 0x0 3. "BOD,Status of the Brown-out detect reset" "0: No BOD reset detected,1: BOD reset detected. Writing a one clears this.."
newline
bitfld.long 0x0 2. "WDT,Status of the Watchdog reset" "0: No WDT reset detected,1: WDT reset detected. Writing a one clears this.."
bitfld.long 0x0 1. "EXTRST,Status of the external RESET pin. External reset status" "0: No reset event detected.,1: Reset detected. Writing a one clears this reset."
newline
bitfld.long 0x0 0. "POR,POR reset status" "0: No POR detected,1: POR detected. Writing a one clears this reset."
group.long 0x200++0xB
line.long 0x0 "AHBCLKCTRL0,AHB Clock control n"
bitfld.long 0x0 27. "ADC0,Enables the clock for the ADC0 register interface." "0,1"
bitfld.long 0x0 23. "RTC,Enables the bus clock for the RTC. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 22. "WWDT,Enables the clock for the Watchdog Timer. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 21. "CRC,Enables the clock for the CRC engine. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 20. "DMA,Enables the clock for the DMA controller. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 19. "GINT,Enables the clock for the grouped pin interrupt block. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 18. "PINT,Enables the clock for the pin interrupt block.0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 17. "GPIO3,Enables the clock for the GPIO3 port registers." "0,1"
newline
bitfld.long 0x0 16. "GPIO2,Enables the clock for the GPIO2 port registers." "0,1"
bitfld.long 0x0 15. "GPIO1,Enables the clock for the GPIO1 port registers. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 14. "GPIO0,Enables the clock for the GPIO0 port registers. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 13. "IOCON,Enables the clock for the IOCON block. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 11. "INPUTMUX,Enables the clock for the input muxes. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 10. "SPIFI,Enables the clock for the SPIFI. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 9. "EEPROM,Enables the clock for EEPROM." "0,1"
bitfld.long 0x0 8. "FMC,Enables the clock for the Flash accelerator. 0 = Disable; 1 = Enable. This clock is needed if the flash is being read." "0: Disable,1: Enable"
newline
bitfld.long 0x0 7. "FLASH,Enables the clock for the flash controller. 0 = Disable; 1 = Enable. This clock is needed for flash programming  not for flash read." "0: Disable,1: Enable"
bitfld.long 0x0 5. "SRAM3,Enables the clock for SRAM3." "0,1"
newline
bitfld.long 0x0 4. "SRAM2,Enables the clock for SRAM2. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x0 3. "SRAM1,Enables the clock for SRAM1. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x0 1. "ROM,Enables the clock for the Boot ROM. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
line.long 0x4 "AHBCLKCTRL1,AHB Clock control n"
bitfld.long 0x4 27. "CTIMER1,Enables the clock for timer CTIMER1. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 26. "CTIMER0,Enables the clock for timer CTIMER0. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 25. "USB0D,Enables the clock for the USB0 device interface. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 22. "CTIMER2,Enables the clock for CTIMER 2. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 19. "DMIC,Enables the clock for the digital microphone interface. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 18. "FLEXCOMM7,Enables the clock for Flexcomm 7. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 17. "FLEXCOMM6,Enables the clock for Flexcomm 6. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 16. "FLEXCOMM5,Enables the clock for Flexcomm 5. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 15. "FLEXCOMM4,Enables the clock for Flexcomm 4. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 14. "FLEXCOMM3,Enables the clock for Flexcomm 3. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 13. "FLEXCOMM2,Enables the clock for Flexcomm 2. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 12. "FLEXCOMM1,Enables the clock for Flexcomm 1. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 11. "FLEXCOMM0,Enables the clock for Flexcomm 0. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
bitfld.long 0x4 10. "UTICK,Enables the clock for the Micro-tick Timer. 0 = Disable; 1 = Enable." "0: Disable,1: Enable"
newline
bitfld.long 0x4 8. "MCAN1,Enables the clock for MCAN1." "0,1"
bitfld.long 0x4 7. "MCAN0,Enables the clock for MCAN0." "0,1"
newline
bitfld.long 0x4 2. "SCT0,Enables the clock for SCT0." "0,1"
bitfld.long 0x4 1. "RIT,Enables the clock for the Repetitive Interrupt Timer." "0,1"
newline
bitfld.long 0x4 0. "MRT,Enables the clock for the Multi-Rate Timer." "0,1"
line.long 0x8 "AHBCLKCTRL2,AHB Clock control n"
bitfld.long 0x8 20. "SC1,Enables the clock for the Smart card1 interface." "0,1"
bitfld.long 0x8 19. "SC0,Enables the clock for the Smart card0 interface." "0,1"
newline
bitfld.long 0x8 18. "SHA0,Enables the clock for the SHA interface." "0,1"
bitfld.long 0x8 17. "USB0HSL,Enables the clock for the USB host slave interface." "0,1"
newline
bitfld.long 0x8 16. "USB0HMR,Enables the clock for the USB host master interface." "0,1"
bitfld.long 0x8 15. "FLEXCOMM9,Enables the clock for the Flexcomm9 interface." "0,1"
newline
bitfld.long 0x8 14. "FLEXCOMM8,Enables the clock for the Flexcomm8 interface." "0,1"
bitfld.long 0x8 13. "RNG,Enables the clock for the RNG interface." "0,1"
newline
bitfld.long 0x8 12. "OTP,Enables the clock for the OTP interface." "0,1"
bitfld.long 0x8 11. "AES,Enables the clock for the AES interface." "0,1"
newline
bitfld.long 0x8 10. "GPIO5,Enables the clock for the GPIO5 interface." "0,1"
bitfld.long 0x8 9. "GPIO4,Enables the clock for the GPIO4 interface." "0,1"
newline
bitfld.long 0x8 8. "ETH,Enables the clock for the ethernet interface." "0,1"
bitfld.long 0x8 7. "EMC,Enables the clock for the EMC interface." "0,1"
newline
bitfld.long 0x8 6. "USB1RAM,Enables the clock for the USB1 RAM interface." "0,1"
bitfld.long 0x8 5. "USB1D,Enables the clock for the USB1 device interface." "0,1"
newline
bitfld.long 0x8 4. "USB1H,Enables the clock for the USB1 host interface." "0,1"
bitfld.long 0x8 3. "SDIO,Enables the clock for the SDIO interface." "0,1"
newline
bitfld.long 0x8 2. "LCD,Enables the clock for the LCD interface." "0,1"
endif
sif (cpuis("LPC54628*"))
repeat 3. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x220)++0x3
line.long 0x0 "AHBCLKCTRLSET[$1],Set bits in AHBCLKCTRLn"
hexmask.long 0x0 0.--31. 1. "CLK_SET,Writing ones to this register sets the corresponding bit or bits in the AHBCLKCTRLn register  if they are implemented. Bits that do not correspond to defined bits in AHBCLKCTRLn are reserved and only zeroes should be written to them."
repeat.end
endif
sif (cpuis("LPC54628*"))
repeat 3. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x240)++0x3
line.long 0x0 "AHBCLKCTRLCLR[$1],Clear bits in AHBCLKCTRLn"
hexmask.long 0x0 0.--31. 1. "CLK_CLR,Writing ones to this register clears the corresponding bit or bits in the AHBCLKCTRLn register  if they are implemented. Bits that do not correspond to defined bits in AHBCLKCTRLn are reserved and only zeroes should be written to them."
repeat.end
group.long 0x280++0xB
line.long 0x0 "MAINCLKSELA,Main clock source select A"
bitfld.long 0x0 0.--1. "SEL,Clock source for main clock source selector A" "0: FRO 12 MHz (fro_12m),1: CLKIN (clk_in),2: Watchdog oscillator (wdt_clk),3: FRO 96 or 48 MHz (fro_hf)"
line.long 0x4 "MAINCLKSELB,Main clock source select B"
bitfld.long 0x4 0.--1. "SEL,Clock source for main clock source selector B. Selects the clock source for the main clock." "0: MAINCLKSELA. Use the clock source selected in..,?,2: System PLL output (pll_clk),3: RTC oscillator 32 kHz output (32k_clk)"
line.long 0x8 "CLKOUTSELA,CLKOUT clock source select A"
bitfld.long 0x8 0.--2. "SEL,CLKOUT clock source selection" "0: Main clock (main_clk),1: CLKIN (clk_in),2: Watchdog oscillator (wdt_clk),3: FRO 96 or 48 MHz (fro_hf),4: PLL output (pll_clk),5: USB PLL clock (usb_pll_clk),6: Audio PLL clock (audio_pll_clk),7: RTC oscillator 32 kHz output (32k_clk)"
group.long 0x290++0x3
line.long 0x0 "SYSPLLCLKSEL,PLL clock source select"
bitfld.long 0x0 0.--2. "SEL,System PLL clock source selection." "0: FRO 12 MHz (fro_12m),1: CLKIN (clk_in),2: Watchdog oscillator (wdt_clk),3: RTC oscillator 32 kHz output (32k_clk),?,?,?,7: None this may be selected in order to reduce.."
group.long 0x298++0x3
line.long 0x0 "AUDPLLCLKSEL,Audio PLL clock source select"
bitfld.long 0x0 0.--2. "SEL,Audio PLL clock source selection." "0: FRO 12 MHz (fro_12m),1: CLKIN (clk_in),?,?,?,?,?,7: None this may be selected in order to reduce.."
group.long 0x2A0++0xF
line.long 0x0 "SPIFICLKSEL,SPIFI clock source select"
bitfld.long 0x0 0.--2. "SEL,System PLL clock source selection" "0: Main clock (main_clk),1: System PLL output (pll_clk),2: USB PLL clock (usb_pll_clk),3: FRO 96 or 48 MHz (fro_hf),4: Audio PLL clock (audio_pll_clk),?,?,7: None this may be selected in order to reduce.."
line.long 0x4 "ADCCLKSEL,ADC clock source select"
bitfld.long 0x4 0.--2. "SEL,ADC clock source selection" "0: FRO 96 or 48 MHz (fro_hf),1: System PLL output (pll_clk),2: USB PLL clock (usb_pll_clk),3: Audio PLL clock (audio_pll_clk),?,?,?,7: None this may be selected in order to reduce.."
line.long 0x8 "USB0CLKSEL,USB0 clock source select"
bitfld.long 0x8 0.--2. "SEL,USB0 device clock source selection." "0: FRO 96 or 48 MHz (fro_hf),1: System PLL output (pll_clk),2: USB PLL clock (usb_pll_clk),?,?,?,?,7: None this may be selected in order to reduce.."
line.long 0xC "USB1CLKSEL,USB1 clock source select"
bitfld.long 0xC 0.--2. "SEL,USB1 PHY clock source selection." "0: Main clock (main_clk),1: System PLL output (pll_clk),2: USB PLL clock (usb_pll_clk),?,?,?,?,7: None this may be selected in order to reduce.."
endif
sif (cpuis("LPC54628*"))
repeat 10. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2B0)++0x3
line.long 0x0 "FCLKSEL[$1],Flexcomm 0 clock source select"
bitfld.long 0x0 0.--2. "SEL,Flexcomm clock source selection. One per Flexcomm." "0: FRO 12 MHz (fro_12m),1: FRO HF DIV (fro_hf_div),2: Audio PLL clock (audio_pll_clk),3: MCLK pin input when selected in IOCON (mclk_in),4: FRG clock the output of the fractional rate..,?,?,7: None this may be selected in order to reduce.."
repeat.end
group.long 0x2E0++0x3
line.long 0x0 "MCLKCLKSEL,MCLK clock source select"
bitfld.long 0x0 0.--2. "SEL,MCLK source select. This may be used by Flexcomms that support I2S  and/or by the digital microphone subsystem." "0: FRO HF DIV (fro_hf_div),1: Audio PLL clock (audio_pll_clk),?,?,?,?,?,7: None this may be selected in order to reduce.."
group.long 0x2E8++0x13
line.long 0x0 "FRGCLKSEL,Fractional Rate Generator clock source select"
bitfld.long 0x0 0.--2. "SEL,Fractional Rate Generator clock source select." "0: Main clock (main_clk),1: System PLL output (pll_clk),2: FRO 12 MHz (fro_12m),3: FRO 96 or 48 MHz (fro_hf),?,?,?,7: None this may be selected in order to reduce.."
line.long 0x4 "DMICCLKSEL,Digital microphone (DMIC) subsystem clock select"
bitfld.long 0x4 0.--2. "SEL,DMIC (audio subsystem) clock source select." "0: FRO 12 MHz (fro_12m),1: FRO HF DIV (fro_hf_div),2: Audio PLL clock (audio_pll_clk),3: MCLK pin input when selected in IOCON (mclk_in),?,?,?,7: None this may be selected in order to reduce.."
line.long 0x8 "SCTCLKSEL,SCTimer/PWM clock source select"
bitfld.long 0x8 0.--2. "SEL,SCT clock source select." "0: Main clock (main_clk),1: System PLL output (pll_clk),2: FRO 96 or 48 MHz (fro_hf),3: Audio PLL clock (audio_pll_clk),?,?,?,7: None this may be selected in order to reduce.."
line.long 0xC "LCDCLKSEL,LCD clock source select"
bitfld.long 0xC 0.--1. "SEL,LCD clock source select." "0: Main clock (main_clk),1: LCDCLKIN (LCDCLK_EXT),2: FRO 96 or 48 MHz (fro_hf),3: None this may be selected in order to reduce.."
line.long 0x10 "SDIOCLKSEL,SDIO clock source select"
bitfld.long 0x10 0.--2. "SEL,SDIO clock source select." "0: Main clock (main_clk),1: System PLL output (pll_clk),2: USB PLL clock (usb_pll_clk),3: FRO 96 or 48 MHz (fro_hf),4: Audio PLL clock (audio_pll_clk),?,?,7: None this may be selected in order to reduce.."
group.long 0x300++0x17
line.long 0x0 "SYSTICKCLKDIV,SYSTICK clock divider"
bitfld.long 0x0 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x0 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x0 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count." "0,1"
hexmask.long.byte 0x0 0.--7. 1. "DIV,Clock divider value. 0: Divide by 1 up to 255: Divide by 256."
line.long 0x4 "ARMTRACECLKDIV,ARM Trace clock divider"
bitfld.long 0x4 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x4 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x4 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x4 0.--7. 1. "DIV,Clock divider value."
line.long 0x8 "CAN0CLKDIV,MCAN0 clock divider"
bitfld.long 0x8 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x8 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x8 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x8 0.--7. 1. "DIV,Clock divider value."
line.long 0xC "CAN1CLKDIV,MCAN1 clock divider"
bitfld.long 0xC 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0xC 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0xC 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count." "0,1"
hexmask.long.byte 0xC 0.--7. 1. "DIV,Clock divider value. 0: Divide by 1 up to 255: Divide by 256."
line.long 0x10 "SC0CLKDIV,Smartcard0 clock divider"
bitfld.long 0x10 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x10 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x10 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x10 0.--7. 1. "DIV,Clock divider value."
line.long 0x14 "SC1CLKDIV,Smartcard1 clock divider"
bitfld.long 0x14 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x14 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x14 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x14 0.--7. 1. "DIV,Clock divider value."
group.long 0x380++0xB
line.long 0x0 "AHBCLKDIV,AHB clock divider"
bitfld.long 0x0 31. "REQFLAG,Divider status flag." "0,1"
hexmask.long.byte 0x0 0.--7. 1. "DIV,Clock divider value. 0: Divide by 1 up to 255: Divide by 256."
line.long 0x4 "CLKOUTDIV,CLKOUT clock divider"
bitfld.long 0x4 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x4 30. "HALT,Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output." "0,1"
newline
bitfld.long 0x4 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count." "0,1"
hexmask.long.byte 0x4 0.--7. 1. "DIV,Clock divider value. 0: Divide by 1 up to 255: Divide by 256."
line.long 0x8 "FROHFCLKDIV,FROHF clock divider"
bitfld.long 0x8 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x8 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x8 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x8 0.--7. 1. "DIV,Clock divider value."
group.long 0x390++0x13
line.long 0x0 "SPIFICLKDIV,SPIFI clock divider"
bitfld.long 0x0 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x0 30. "HALT,Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output." "0,1"
newline
bitfld.long 0x0 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count." "0,1"
hexmask.long.byte 0x0 0.--7. 1. "DIV,Clock divider value."
line.long 0x4 "ADCCLKDIV,ADC clock divider"
bitfld.long 0x4 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x4 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x4 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x4 0.--7. 1. "DIV,Clock divider value."
line.long 0x8 "USB0CLKDIV,USB0 clock divider"
bitfld.long 0x8 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x8 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x8 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x8 0.--7. 1. "DIV,Clock divider value."
line.long 0xC "USB1CLKDIV,USB1 clock divider"
bitfld.long 0xC 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0xC 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0xC 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0xC 0.--7. 1. "DIV,Clock divider value."
line.long 0x10 "FRGCTRL,Fractional rate divider"
hexmask.long.byte 0x10 8.--15. 1. "MULT,Numerator of the fractional divider. MULT is equal to the programmed value."
hexmask.long.byte 0x10 0.--7. 1. "DIV,Denominator of the fractional divider. DIV is equal to the programmed value +1. Always set to 0xFF to use with the fractional baud rate generator."
group.long 0x3A8++0x17
line.long 0x0 "DMICCLKDIV,DMIC clock divider"
bitfld.long 0x0 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x0 30. "HALT,Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output." "0,1"
newline
bitfld.long 0x0 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count." "0,1"
hexmask.long.byte 0x0 0.--7. 1. "DIV,Clock divider value. 0: Divide by 1 up to 255: Divide by 256."
line.long 0x4 "MCLKDIV,I2S MCLK clock divider"
bitfld.long 0x4 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x4 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x4 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x4 0.--7. 1. "DIV,Clock divider value. 0: Divide by 1 up to 255: Divide by 256."
line.long 0x8 "LCDCLKDIV,LCD clock divider"
bitfld.long 0x8 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x8 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x8 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x8 0.--7. 1. "DIV,Clock divider value."
line.long 0xC "SCTCLKDIV,SCT/PWM clock divider"
bitfld.long 0xC 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0xC 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0xC 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0xC 0.--7. 1. "DIV,Clock divider value."
line.long 0x10 "EMCCLKDIV,EMC clock divider"
bitfld.long 0x10 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x10 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x10 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x10 0.--7. 1. "DIV,Clock divider value."
line.long 0x14 "SDIOCLKDIV,SDIO clock divider"
bitfld.long 0x14 31. "REQFLAG,Divider status flag." "0,1"
bitfld.long 0x14 30. "HALT,Halts the divider counter." "0,1"
newline
bitfld.long 0x14 29. "RESET,Resets the divider counter." "0,1"
hexmask.long.byte 0x14 0.--7. 1. "DIV,Clock divider value."
group.long 0x400++0x3
line.long 0x0 "FLASHCFG,Flash wait states configuration"
hexmask.long.byte 0x0 12.--15. 1. "FLASHTIM,Flash memory access time. The number of system clocks used for flash accesses is equal to FLASHTIM +1."
bitfld.long 0x0 6. "PREFOVR,Prefetch override. This bit only applies when PREFEN = 1 and a buffered instruction is completing for which the next flash line is not already buffered or being prefetched." "0: Any previously initiated prefetch will be..,1: Any previously initiated prefetch will be.."
newline
bitfld.long 0x0 5. "PREFEN,Prefetch enable." "0: No instruction prefetch is performed.,1: If the FETCHCFG field is not 0 the next flash.."
bitfld.long 0x0 4. "ACCEL,Acceleration enable." "0: Flash acceleration is disabled. Every flash read..,1: Flash acceleration is enabled. Performance is.."
newline
bitfld.long 0x0 2.--3. "DATACFG,Data read configuration. This field determines how flash accelerator buffers are used for data accesses." "0: Data accesses from flash are not buffered. Every..,1: One buffer is used for all data accesses.,2: All buffers may be used for data accesses.,?"
bitfld.long 0x0 0.--1. "FETCHCFG,Instruction fetch configuration. This field determines how flash accelerator buffers are used for instruction fetches." "0: Instruction fetches from flash are not buffered.,1: One buffer is used for all instruction fetches.,2: All buffers may be used for instruction fetches.,?"
group.long 0x40C++0x7
line.long 0x0 "USB0CLKCTRL,USB0 clock control"
bitfld.long 0x0 4. "PU_DISABLE,Internal pull-up disable control." "0,1"
bitfld.long 0x0 3. "POL_FS_HOST_CLK,USB0 Host USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt." "0,1"
newline
bitfld.long 0x0 2. "AP_FS_HOST_CLK,USB0 Host USB0_NEEDCLK signal control." "0,1"
bitfld.long 0x0 1. "POL_FS_DEV_CLK,USB0 Device USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt." "0,1"
newline
bitfld.long 0x0 0. "AP_FS_DEV_CLK,USB0 Device USB0_NEEDCLK signal control." "0,1"
line.long 0x4 "USB0CLKSTAT,USB0 clock status"
bitfld.long 0x4 1. "HOST_NEED_CLKST,USB0 Host USB0_NEEDCLK signal status." "0,1"
bitfld.long 0x4 0. "DEV_NEED_CLKST,USB0 Device USB0_NEEDCLK signal status." "0,1"
group.long 0x418++0x3
line.long 0x0 "FREQMECTRL,Frequency measure register"
bitfld.long 0x0 31. "PROG,Set this bit to one to initiate a frequency measurement cycle. Hardware clears this bit when the measurement cycle has completed and there is valid capture data in the CAPVAL field (bits 13:0)." "0,1"
hexmask.long.word 0x0 0.--13. 1. "CAPVAL,Stores the capture result which is used to calculate the frequency of the target clock. This field is read-only."
group.long 0x420++0xB
line.long 0x0 "MCLKIO,MCLK input/output control"
bitfld.long 0x0 0. "DIR,MCLK direction control." "0,1"
line.long 0x4 "USB1CLKCTRL,USB1 clock control"
bitfld.long 0x4 4. "HS_DEV_WAKEUP_N,External user wake-up signal for device mode; asserting this signal (active low) will result in exiting the low power mode; input to asynchronous control logic." "0,1"
bitfld.long 0x4 3. "POL_FS_HOST_CLK,USB1 Host need_clock polarity for triggering the USB1 wake-up interrupt." "0,1"
newline
bitfld.long 0x4 2. "AP_FS_HOST_CLK,USB1 Host need_clock signal control." "0,1"
bitfld.long 0x4 1. "POL_FS_DEV_CLK,USB1 Device need_clock polarity for triggering the USB1 wake-up interrupt." "0,1"
newline
bitfld.long 0x4 0. "AP_FS_DEV_CLK,USB1 Device need_clock signal control." "0,1"
line.long 0x8 "USB1CLKSTAT,USB1 clock status"
bitfld.long 0x8 1. "HOST_NEED_CLKST,USB1 Device host USB1_NEEDCLK signal status." "0,1"
bitfld.long 0x8 0. "DEV_NEED_CLKST,USB1 Device USB1_NEEDCLK signal status." "0,1"
group.long 0x444++0x13
line.long 0x0 "EMCSYSCTRL,EMC system control"
bitfld.long 0x0 3. "EMCFBCLKINSEL,External Memory Controller clock select." "0,1"
bitfld.long 0x0 2. "EMCBC,External Memory Controller burst control." "0,1"
newline
bitfld.long 0x0 1. "EMCRD,EMC Reset Disable." "0,1"
bitfld.long 0x0 0. "EMCSC,EMC Shift Control." "0,1"
line.long 0x4 "EMCDLYCTRL,EMC clock delay control"
hexmask.long.byte 0x4 8.--12. 1. "FBCLK_DELAY,Programmable delay value for the feedback clock that controls input data sampling."
hexmask.long.byte 0x4 0.--4. 1. "CMD_DELAY,Programmable delay value for EMC outputs in command delayed mode."
line.long 0x8 "EMCDLYCAL,EMC delay chain calibration control"
bitfld.long 0x8 15. "DONE,Measurement completion flag." "0,1"
bitfld.long 0x8 14. "START,Start control bit for the EMC calibration counter." "0,1"
newline
hexmask.long.byte 0x8 0.--7. 1. "CALVALUE,Returns the count of the approximately 50 MHz ring oscillator that occur during 32 clocks of the FRO 12 MHz."
line.long 0xC "ETHPHYSEL,Ethernet PHY Selection"
bitfld.long 0xC 2. "PHY_SEL,PHY interface select." "0,1"
line.long 0x10 "ETHSBDCTRL,Ethernet SBD flow control"
bitfld.long 0x10 0.--1. "SBD_CTRL,Sideband Flow Control." "0,1,2,3"
group.long 0x460++0x3
line.long 0x0 "SDIOCLKCTRL,SDIO CCLKIN phase and delay control"
bitfld.long 0x0 31. "CCLK_SAMPLE_DELAY_ACTIVE,Enables sample delay  as controlled by the CCLK_SAMPLE_DELAY field." "0,1"
hexmask.long.byte 0x0 24.--28. 1. "CCLK_SAMPLE_DELAY,Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in."
newline
bitfld.long 0x0 23. "CCLK_DRV_DELAY_ACTIVE,Enables drive delay  as controlled by the CCLK_DRV_DELAY field." "0,1"
hexmask.long.byte 0x0 16.--20. 1. "CCLK_DRV_DELAY,Programmable delay value by which cclk_in_drv is delayed with regard to cclk_in."
newline
bitfld.long 0x0 7. "PHASE_ACTIVE,sdio_clk by 2  before feeding into ccl_in  cclk_in_sample  and cclk_in_drv." "0,1"
bitfld.long 0x0 2.--3. "CCLK_SAMPLE_PHASE,Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in." "0,1,2,3"
newline
bitfld.long 0x0 0.--1. "CCLK_DRV_PHASE,Programmable delay value by which cclk_in_drv is phase-shifted with regard to cclk_in." "0,1,2,3"
group.long 0x500++0xF
line.long 0x0 "FROCTRL,FRO oscillator control"
bitfld.long 0x0 31. "WRTRIM,Write Trim value." "0,1"
bitfld.long 0x0 30. "HSPDCLK,High speed clock enable." "0,1"
newline
bitfld.long 0x0 25. "USBMODCHG,USB Mode value Change flag." "0,1"
bitfld.long 0x0 24. "USBCLKADJ,USB clock adjust mode." "0,1"
newline
hexmask.long.byte 0x0 16.--23. 1. "FREQTRIM,Frequency trim."
bitfld.long 0x0 14. "SEL,Select the FRO HF output frequency." "0,1"
newline
hexmask.long.word 0x0 0.--13. 1. "TRIM,This value is factory trimmed to account for bias and temperature compensation."
line.long 0x4 "SYSOSCCTRL,System oscillator control"
bitfld.long 0x4 1. "FREQRANGE,Determines frequency range for system oscillator." "0,1"
bitfld.long 0x4 0. "BYPASS,Bypass system oscillator." "0,1"
line.long 0x8 "WDTOSCCTRL,Watchdog oscillator control"
hexmask.long.byte 0x8 5.--9. 1. "FREQSEL,Frequency select."
hexmask.long.byte 0x8 0.--4. 1. "DIVSEL,Divider select."
line.long 0xC "RTCOSCCTRL,RTC oscillator 32 kHz output control"
bitfld.long 0xC 0. "EN,RTC 32 kHz clock enable." "0,1"
group.long 0x51C++0x7
line.long 0x0 "USBPLLCTRL,USB PLL control"
bitfld.long 0x0 14. "FBSEL,Feedback divider input clock control." "0,1"
bitfld.long 0x0 13. "BYPASS,Input clock bypass control." "0: CCO clock is sent to post dividers..,1: PLL input clock is sent to post dividers.."
newline
bitfld.long 0x0 12. "DIRECT,Direct CCO clock output control." "0: CCO Clock signal goes through post divider.,1: CCO Clock signal goes directly to output(s).."
bitfld.long 0x0 10.--11. "NSEL,PLL feedback Divider value." "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "PSEL,PLL Divider value." "0,1,2,3"
hexmask.long.byte 0x0 0.--7. 1. "MSEL,PLL feedback Divider value."
line.long 0x4 "USBPLLSTAT,USB PLL status"
bitfld.long 0x4 0. "LOCK,USBPLL lock indicator." "0,1"
group.long 0x580++0x13
line.long 0x0 "SYSPLLCTRL,System PLL control"
bitfld.long 0x0 20. "DIRECTO,PLL0 direct output enable." "0: Disabled. The PLL output divider (P divider) is..,1: Enabled. The PLL output divider (P divider) is.."
bitfld.long 0x0 19. "DIRECTI,PLL0 direct input enable." "0,1"
newline
bitfld.long 0x0 17. "UPLIMOFF,Disable upper frequency limiter." "0,1"
bitfld.long 0x0 15. "BYPASS,PLL bypass control." "0: Bypass disabled. PLL CCO is sent to the PLL..,1: Bypass enabled. PLL input clock is sent directly.."
newline
hexmask.long.byte 0x0 10.--14. 1. "SELP,Bandwidth select P value."
hexmask.long.byte 0x0 4.--9. 1. "SELI,Bandwidth select I value."
newline
hexmask.long.byte 0x0 0.--3. 1. "SELR,Bandwidth select R value."
line.long 0x4 "SYSPLLSTAT,PLL status"
bitfld.long 0x4 0. "LOCK,PLL lock indicator." "0,1"
line.long 0x8 "SYSPLLNDEC,PLL N divider"
bitfld.long 0x8 10. "NREQ,NDEC reload request." "0,1"
hexmask.long.word 0x8 0.--9. 1. "NDEC,Decoded N-divider coefficient value."
line.long 0xC "SYSPLLPDEC,PLL P divider"
bitfld.long 0xC 7. "PREQ,." "0,1"
hexmask.long.byte 0xC 0.--6. 1. "PDEC,Decoded P-divider coefficient value."
line.long 0x10 "SYSPLLMDEC,System PLL M divider"
bitfld.long 0x10 17. "MREQ,MDEC reload request." "0,1"
hexmask.long.tbyte 0x10 0.--16. 1. "MDEC,Decoded M-divider coefficient value."
group.long 0x5A0++0x17
line.long 0x0 "AUDPLLCTRL,Audio PLL control"
bitfld.long 0x0 20. "DIRECTO,PLL direct output enable" "0: Disabled. The PLL output divider (P divider) is..,1: Enabled. The PLL output divider (P divider) is.."
bitfld.long 0x0 19. "DIRECTI,PLL direct input enable." "0,1"
newline
bitfld.long 0x0 17. "UPLIMOFF,Disable upper frequency limiter." "0,1"
bitfld.long 0x0 15. "BYPASS,PLL bypass control." "0: Bypass disabled. PLL CCO is sent to the PLL..,1: Bypass enabled. PLL input clock is sent directly.."
newline
hexmask.long.byte 0x0 10.--14. 1. "SELP,."
hexmask.long.byte 0x0 4.--9. 1. "SELI,Bandwidth select I value."
newline
hexmask.long.byte 0x0 0.--3. 1. "SELR,Bandwidth select R value."
line.long 0x4 "AUDPLLSTAT,Audio PLL status"
bitfld.long 0x4 0. "LOCK,PLL lock indicator." "0,1"
line.long 0x8 "AUDPLLNDEC,Audio PLL N divider"
bitfld.long 0x8 10. "NREQ,NDEC reload request." "0,1"
hexmask.long.word 0x8 0.--9. 1. "NDEC,Decoded N-divider coefficient value."
line.long 0xC "AUDPLLPDEC,Audio PLL P divider"
bitfld.long 0xC 7. "PREQ,PDEC reload request." "0,1"
hexmask.long.byte 0xC 0.--6. 1. "PDEC,Decoded P-divider coefficient value."
line.long 0x10 "AUDPLLMDEC,Audio PLL M divider"
bitfld.long 0x10 17. "MREQ,MDEC reload request." "0,1"
hexmask.long.tbyte 0x10 0.--16. 1. "MDEC,Decoded M-divider coefficient value."
line.long 0x14 "AUDPLLFRAC,Audio PLL fractional divider control"
bitfld.long 0x14 23. "SEL_EXT,Select fractional divider." "0,1"
bitfld.long 0x14 22. "REQ,Writing 1 to REQ signal loads CTRL value into fractional wrapper modulator." "0,1"
newline
hexmask.long.tbyte 0x14 0.--21. 1. "CTRL,PLL fractional divider control word"
group.long 0x600++0x7
line.long 0x0 "PDSLEEPCFG0,Sleep configuration register"
bitfld.long 0x0 29. "PDEN_VD6,Power control for EEPROM." "0,1"
bitfld.long 0x0 28. "PDEN_VD5,Power control both USB0 PHY and USB1 PHY." "0,1"
newline
bitfld.long 0x0 27. "PDEN_VD4,Power control for all SRAMs and ROM." "0,1"
bitfld.long 0x0 26. "PDEN_VD3,Power control for all PLLs." "0,1"
newline
bitfld.long 0x0 23. "PDEN_VREFP,VREFP to the ADC must be enabled for the ADC to work (also enable/disable bit 9  10  and 19)." "0,1"
bitfld.long 0x0 22. "PDEN_SYS_PLL,System PLL (PLL0) power (also enable/disable bit 26)." "0,1"
newline
bitfld.long 0x0 21. "PDEN_USB0_PHY,USB0 PHY power (also enable/disable bit 28)." "0,1"
bitfld.long 0x0 20. "PDEN_WDT_OSC,Watchdog oscillator." "0,1"
newline
bitfld.long 0x0 19. "PDEN_VDDA,Vdda to the ADC  must be enabled for the ADC to work (also enable/disable bit 9  10  and 23)." "0,1"
bitfld.long 0x0 17. "PDEN_ROM,ROM (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 16. "PDEN_USB_RAM,PDEN_USB_SRAM controls USB_RAM (also enable/disable bit 27)." "0,1"
bitfld.long 0x0 15. "PDEN_SRAM1_2_3,PDEN_SRAM1_2_3 controls SRAM1  SRAM2  and SRAM3 (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 14. "PDEN_SRAM0,PDEN_SRAM0 controls SRAM0 (also enable/disable bit 27)." "0,1"
bitfld.long 0x0 13. "PDEN_SRAMX,PDEN_SRAMX controls SRAMX (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 10. "PDEN_ADC0,ADC power." "0,1"
bitfld.long 0x0 9. "PDEN_VD2_ANA,Analog supply for System Oscillator (also enable/disable bit 3 in PDRUNCFG1 register)  Temperature Sensor (also  enable/disable bit 6)  ADC (also  enable/disable bits 10  19  and 23)." "0,1"
newline
bitfld.long 0x0 8. "PDEN_BOD_INTR,Brown-out Detect interrupt." "0,1"
bitfld.long 0x0 7. "PDEN_BOD_RST,Brown-out Detect reset." "0,1"
newline
bitfld.long 0x0 6. "PDEN_TS,Temp sensor." "0,1"
bitfld.long 0x0 4. "PDEN_FRO,FRO oscillator." "0,1"
line.long 0x4 "PDSLEEPCFG1,Sleep configuration register"
bitfld.long 0x4 7. "PDEN_RNG,Random Number Generator Power." "0,1"
bitfld.long 0x4 5. "PDEN_EEPROM,EEPROM power (also  enable/disable bit 29 in PDRUNCFG0 register)." "0,1"
newline
bitfld.long 0x4 3. "PDEN_SYSOSC,System Oscillator Power (also  enable/disable bit 9 in PDRUNCFG0 register)." "0,1"
bitfld.long 0x4 2. "PDEN_AUD_PLL,Audio PLL (PLL2) power and fractional divider (also  enable/disable bit 26 in PDRUNCFG0 register)." "0,1"
newline
bitfld.long 0x4 1. "PDEN_USB1_PLL,USB PLL (PLL1) power (also  enable/disable bit 26 in PDRUNCFG0 register)." "0,1"
bitfld.long 0x4 0. "PDEN_USB1_PHY,USB1 high speed PHY (also  enable/disable bit 28 in PDRUNCFG0 register)." "0,1"
group.long 0x610++0x7
line.long 0x0 "PDRUNCFG0,Power configuration register"
bitfld.long 0x0 29. "PDEN_VD6,Power control for EEPROM." "0,1"
bitfld.long 0x0 28. "PDEN_VD5,Power control both USB0 PHY and USB1 PHY." "0,1"
newline
bitfld.long 0x0 27. "PDEN_VD4,Power control for all SRAMs and ROM." "0,1"
bitfld.long 0x0 26. "PDEN_VD3,Power control for all PLLs." "0,1"
newline
bitfld.long 0x0 23. "PDEN_VREFP,VREFP to the ADC must be enabled for the ADC to work (also enable/disable bit 9  10  and 19)." "0,1"
bitfld.long 0x0 22. "PDEN_SYS_PLL,System PLL (PLL0) power (also enable/disable bit 26)." "0,1"
newline
bitfld.long 0x0 21. "PDEN_USB0_PHY,USB0 PHY power (also enable/disable bit 28)." "0,1"
bitfld.long 0x0 20. "PDEN_WDT_OSC,Watchdog oscillator." "0,1"
newline
bitfld.long 0x0 19. "PDEN_VDDA,Vdda to the ADC  must be enabled for the ADC to work (also enable/disable bit 9  10  and 23)." "0,1"
bitfld.long 0x0 17. "PDEN_ROM,ROM (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 16. "PDEN_USB_RAM,PDEN_USB_SRAM controls USB_RAM (also enable/disable bit 27)." "0,1"
bitfld.long 0x0 15. "PDEN_SRAM1_2_3,PDEN_SRAM1_2_3 controls SRAM1  SRAM2  and SRAM3 (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 14. "PDEN_SRAM0,PDEN_SRAM0 controls SRAM0 (also enable/disable bit 27)." "0,1"
bitfld.long 0x0 13. "PDEN_SRAMX,PDEN_SRAMX controls SRAMX (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 10. "PDEN_ADC0,ADC power." "0,1"
bitfld.long 0x0 9. "PDEN_VD2_ANA,Analog supply for System Oscillator (also enable/disable bit 3 in PDRUNCFG1 register)  Temperature Sensor (also  enable/disable bit 6)  ADC (also  enable/disable bits 10  19  and 23)." "0,1"
newline
bitfld.long 0x0 8. "PDEN_BOD_INTR,Brown-out Detect interrupt." "0,1"
bitfld.long 0x0 7. "PDEN_BOD_RST,Brown-out Detect reset." "0,1"
newline
bitfld.long 0x0 6. "PDEN_TS,Temp sensor." "0,1"
bitfld.long 0x0 4. "PDEN_FRO,FRO oscillator." "0,1"
line.long 0x4 "PDRUNCFG1,Power configuration register"
bitfld.long 0x4 7. "PDEN_RNG,Random Number Generator Power." "0,1"
bitfld.long 0x4 5. "PDEN_EEPROM,EEPROM power (also  enable/disable bit 29 in PDRUNCFG0 register)." "0,1"
newline
bitfld.long 0x4 3. "PDEN_SYSOSC,System Oscillator Power (also  enable/disable bit 9 in PDRUNCFG0 register)." "0,1"
bitfld.long 0x4 2. "PDEN_AUD_PLL,Audio PLL (PLL2) power and fractional divider (also  enable/disable bit 26 in PDRUNCFG0 register)." "0,1"
newline
bitfld.long 0x4 1. "PDEN_USB1_PLL,USB PLL (PLL1) power (also  enable/disable bit 26 in PDRUNCFG0 register)." "0,1"
bitfld.long 0x4 0. "PDEN_USB1_PHY,USB1 high speed PHY (also  enable/disable bit 28 in PDRUNCFG0 register)." "0,1"
group.long 0x620++0x7
line.long 0x0 "PDRUNCFGSET0,Power configuration set register"
bitfld.long 0x0 29. "PDEN_VD6,Power control for EEPROM." "0,1"
bitfld.long 0x0 28. "PDEN_VD5,Power control both USB0 PHY and USB1 PHY." "0,1"
newline
bitfld.long 0x0 27. "PDEN_VD4,Power control for all SRAMs and ROM." "0,1"
bitfld.long 0x0 26. "PDEN_VD3,Power control for all PLLs." "0,1"
newline
bitfld.long 0x0 23. "PDEN_VREFP,VREFP to the ADC must be enabled for the ADC to work (also enable/disable bit 9  10  and 19)." "0,1"
bitfld.long 0x0 22. "PDEN_SYS_PLL,System PLL (PLL0) power (also enable/disable bit 26)." "0,1"
newline
bitfld.long 0x0 21. "PDEN_USB0_PHY,USB0 PHY power (also enable/disable bit 28)." "0,1"
bitfld.long 0x0 20. "PDEN_WDT_OSC,Watchdog oscillator." "0,1"
newline
bitfld.long 0x0 19. "PDEN_VDDA,Vdda to the ADC  must be enabled for the ADC to work (also enable/disable bit 9  10  and 23)." "0,1"
bitfld.long 0x0 17. "PDEN_ROM,ROM (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 16. "PDEN_USB_RAM,PDEN_USB_SRAM controls USB_RAM (also enable/disable bit 27)." "0,1"
bitfld.long 0x0 15. "PDEN_SRAM1_2_3,PDEN_SRAM1_2_3 controls SRAM1  SRAM2  and SRAM3 (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 14. "PDEN_SRAM0,PDEN_SRAM0 controls SRAM0 (also enable/disable bit 27)." "0,1"
bitfld.long 0x0 13. "PDEN_SRAMX,PDEN_SRAMX controls SRAMX (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 10. "PDEN_ADC0,ADC power." "0,1"
bitfld.long 0x0 9. "PDEN_VD2_ANA,Analog supply for System Oscillator (also enable/disable bit 3 in PDRUNCFG1 register)  Temperature Sensor (also  enable/disable bit 6)  ADC (also  enable/disable bits 10  19  and 23)." "0,1"
newline
bitfld.long 0x0 8. "PDEN_BOD_INTR,Brown-out Detect interrupt." "0,1"
bitfld.long 0x0 7. "PDEN_BOD_RST,Brown-out Detect reset." "0,1"
newline
bitfld.long 0x0 6. "PDEN_TS,Temp sensor." "0,1"
bitfld.long 0x0 4. "PDEN_FRO,FRO oscillator." "0,1"
line.long 0x4 "PDRUNCFGSET1,Power configuration set register"
bitfld.long 0x4 7. "PDEN_RNG,Random Number Generator Power." "0,1"
bitfld.long 0x4 5. "PDEN_EEPROM,EEPROM power (also  enable/disable bit 29 in PDRUNCFG0 register)." "0,1"
newline
bitfld.long 0x4 3. "PDEN_SYSOSC,System Oscillator Power (also  enable/disable bit 9 in PDRUNCFG0 register)." "0,1"
bitfld.long 0x4 2. "PDEN_AUD_PLL,Audio PLL (PLL2) power and fractional divider (also  enable/disable bit 26 in PDRUNCFG0 register)." "0,1"
newline
bitfld.long 0x4 1. "PDEN_USB1_PLL,USB PLL (PLL1) power (also  enable/disable bit 26 in PDRUNCFG0 register)." "0,1"
bitfld.long 0x4 0. "PDEN_USB1_PHY,USB1 high speed PHY (also  enable/disable bit 28 in PDRUNCFG0 register)." "0,1"
group.long 0x630++0x7
line.long 0x0 "PDRUNCFGCLR0,Power configuration clear register"
bitfld.long 0x0 29. "PDEN_VD6,Power control for EEPROM." "0,1"
bitfld.long 0x0 28. "PDEN_VD5,Power control both USB0 PHY and USB1 PHY." "0,1"
newline
bitfld.long 0x0 27. "PDEN_VD4,Power control for all SRAMs and ROM." "0,1"
bitfld.long 0x0 26. "PDEN_VD3,Power control for all PLLs." "0,1"
newline
bitfld.long 0x0 23. "PDEN_VREFP,VREFP to the ADC must be enabled for the ADC to work (also enable/disable bit 9  10  and 19)." "0,1"
bitfld.long 0x0 22. "PDEN_SYS_PLL,System PLL (PLL0) power (also enable/disable bit 26)." "0,1"
newline
bitfld.long 0x0 21. "PDEN_USB0_PHY,USB0 PHY power (also enable/disable bit 28)." "0,1"
bitfld.long 0x0 20. "PDEN_WDT_OSC,Watchdog oscillator." "0,1"
newline
bitfld.long 0x0 19. "PDEN_VDDA,Vdda to the ADC  must be enabled for the ADC to work (also enable/disable bit 9  10  and 23)." "0,1"
bitfld.long 0x0 17. "PDEN_ROM,ROM (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 16. "PDEN_USB_RAM,PDEN_USB_SRAM controls USB_RAM (also enable/disable bit 27)." "0,1"
bitfld.long 0x0 15. "PDEN_SRAM1_2_3,PDEN_SRAM1_2_3 controls SRAM1  SRAM2  and SRAM3 (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 14. "PDEN_SRAM0,PDEN_SRAM0 controls SRAM0 (also enable/disable bit 27)." "0,1"
bitfld.long 0x0 13. "PDEN_SRAMX,PDEN_SRAMX controls SRAMX (also enable/disable bit 27)." "0,1"
newline
bitfld.long 0x0 10. "PDEN_ADC0,ADC power." "0,1"
bitfld.long 0x0 9. "PDEN_VD2_ANA,Analog supply for System Oscillator (also enable/disable bit 3 in PDRUNCFG1 register)  Temperature Sensor (also  enable/disable bit 6)  ADC (also  enable/disable bits 10  19  and 23)." "0,1"
newline
bitfld.long 0x0 8. "PDEN_BOD_INTR,Brown-out Detect interrupt." "0,1"
bitfld.long 0x0 7. "PDEN_BOD_RST,Brown-out Detect reset." "0,1"
newline
bitfld.long 0x0 6. "PDEN_TS,Temp sensor." "0,1"
bitfld.long 0x0 4. "PDEN_FRO,FRO oscillator." "0,1"
line.long 0x4 "PDRUNCFGCLR1,Power configuration clear register"
bitfld.long 0x4 7. "PDEN_RNG,Random Number Generator Power." "0,1"
bitfld.long 0x4 5. "PDEN_EEPROM,EEPROM power (also  enable/disable bit 29 in PDRUNCFG0 register)." "0,1"
newline
bitfld.long 0x4 3. "PDEN_SYSOSC,System Oscillator Power (also  enable/disable bit 9 in PDRUNCFG0 register)." "0,1"
bitfld.long 0x4 2. "PDEN_AUD_PLL,Audio PLL (PLL2) power and fractional divider (also  enable/disable bit 26 in PDRUNCFG0 register)." "0,1"
newline
bitfld.long 0x4 1. "PDEN_USB1_PLL,USB PLL (PLL1) power (also  enable/disable bit 26 in PDRUNCFG0 register)." "0,1"
bitfld.long 0x4 0. "PDEN_USB1_PHY,USB1 high speed PHY (also  enable/disable bit 28 in PDRUNCFG0 register)." "0,1"
group.long 0x680++0x7
line.long 0x0 "STARTER0,Start logic 0 wake-up enable register"
bitfld.long 0x0 29. "RTC,RTC interrupt alarm and wake-up timer." "0,1"
bitfld.long 0x0 28. "USB0,USB function interrupt wake-up." "0,1"
newline
bitfld.long 0x0 27. "USB0_NEEDCLK,USB activity interrupt wake-up." "0,1"
bitfld.long 0x0 26. "HWVAD,Hardware voice activity detect interrupt wake-up." "0,1"
newline
bitfld.long 0x0 25. "DMIC,Digital microphone interrupt wake-up." "0,1"
bitfld.long 0x0 24. "ADC0_THCMP,ADC0 threshold and error interrupt wake-up." "0,1"
newline
bitfld.long 0x0 23. "ADC0_SEQB,ADC0 sequence B interrupt wake-up." "0,1"
bitfld.long 0x0 22. "ADC0_SEQA,ADC0 sequence A interrupt wake-up." "0,1"
newline
bitfld.long 0x0 21. "FLEXCOMM7,Flexcomm7 peripheral interrupt wake-up." "0,1"
bitfld.long 0x0 20. "FLEXCOMM6,Flexcomm6 peripheral interrupt wake-up." "0,1"
newline
bitfld.long 0x0 19. "FLEXCOMM5,Flexcomm5 peripheral interrupt wake-up." "0,1"
bitfld.long 0x0 18. "FLEXCOMM4,Flexcomm4 peripheral interrupt wake-up." "0,1"
newline
bitfld.long 0x0 17. "FLEXCOMM3,Flexcomm3 peripheral interrupt wake-up." "0,1"
bitfld.long 0x0 16. "FLEXCOMM2,Flexcomm2 peripheral interrupt wake-up." "0,1"
newline
bitfld.long 0x0 15. "FLEXCOMM1,Flexcomm1 peripheral interrupt wake-up." "0,1"
bitfld.long 0x0 14. "FLEXCOMM0,Flexcomm0 peripheral interrupt wake-up." "0,1"
newline
bitfld.long 0x0 13. "CTIMER3,Standard counter/timer CTIMER3 wake-up." "0,1"
bitfld.long 0x0 12. "SCT0,SCT0 wake-up." "0,1"
newline
bitfld.long 0x0 11. "CTIMER1,Standard counter/timer CTIMER1 wake-up." "0,1"
bitfld.long 0x0 10. "CTIMER0,Standard counter/timer CTIMER0 wake-up." "0,1"
newline
bitfld.long 0x0 9. "MRT,Multi-Rate Timer wake-up." "0,1"
bitfld.long 0x0 8. "UTICK,Micro-tick Timer wake-up." "0,1"
newline
bitfld.long 0x0 7. "PIN_INT3,GPIO pin interrupt 3 wake-up." "0,1"
bitfld.long 0x0 6. "PIN_INT2,GPIO pin interrupt 2 wake-up." "0,1"
newline
bitfld.long 0x0 5. "PIN_INT1,GPIO pin interrupt 1 wake-up." "0,1"
bitfld.long 0x0 4. "PIN_INT0,GPIO pin interrupt 0 wake-up." "0,1"
newline
bitfld.long 0x0 3. "GINT1,Group interrupt 1 wake-up." "0,1"
bitfld.long 0x0 2. "GINT0,Group interrupt 0 wake-up." "0,1"
newline
bitfld.long 0x0 1. "DMA,DMA wake-up." "0,1"
bitfld.long 0x0 0. "WDT_BOD,WWDT and BOD interrupt wake-up." "0,1"
line.long 0x4 "STARTER1,Start logic 0 wake-up enable register"
bitfld.long 0x4 24. "SMARTCARD1,Smart card 1 wake-up." "0,1"
bitfld.long 0x4 23. "SMARTCARD0,Smart card 0 wake-up." "0,1"
newline
bitfld.long 0x4 19. "ENET_INT0,Ethernet." "0,1"
bitfld.long 0x4 18. "ENET_INT2,Ethernet." "0,1"
newline
bitfld.long 0x4 17. "ENET_INT1,Ethernet." "0,1"
bitfld.long 0x4 16. "USB1_ACT,USB 1 activity wake-up." "0,1"
newline
bitfld.long 0x4 15. "USB1,USB 1 wake-up." "0,1"
bitfld.long 0x4 9. "FLEXCOMM9,Flexcomm Interface 9 wake-up." "0,1"
newline
bitfld.long 0x4 8. "FLEXCOMM8,Flexcomm Interface 8 wake-up." "0,1"
bitfld.long 0x4 7. "SPIFI,SPIFI interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled." "0: Wake-up disabled,1: Wake-up enabled"
newline
bitfld.long 0x4 5. "CTIMER4,Standard counter/timer CTIMER4 wake-up." "0,1"
bitfld.long 0x4 4. "CTIMER2,Standard counter/timer CTIMER2 wake-up." "0,1"
newline
bitfld.long 0x4 3. "PINT7,GPIO pin interrupt 7 wake-up." "0,1"
bitfld.long 0x4 2. "PINT6,GPIO pin interrupt 6 wake-up." "0,1"
newline
bitfld.long 0x4 1. "PINT5,GPIO pin interrupt 5 wake-up." "0,1"
bitfld.long 0x4 0. "PINT4,GPIO pin interrupt 4 wake-up." "0,1"
group.long 0x780++0x3
line.long 0x0 "HWWAKE,Configures special cases of hardware wake-up"
bitfld.long 0x0 3. "WAKEDMA,Wake for DMA. When 1  DMA being busy will cause peripheral clocking to remain running until DMA completes. This is generally used in conjunction with bit 1 and/or 2 in order to prevent peripheral clocking from being shut down as soon as the cause.." "0,1"
bitfld.long 0x0 2. "WAKEDMIC,Wake for Digital Microphone. When 1  the digital microphone input FIFO reaching the level specified by TRIGLVL of either channel will cause peripheral clocking to wake up temporarily while the related status is asserted." "0,1"
newline
bitfld.long 0x0 1. "FCWAKE,Wake for Flexcomms. When 1  any Flexcomm FIFO reaching the level specified by its own TXLVL will cause peripheral clocking to wake up temporarily while the related status is asserted." "0,1"
bitfld.long 0x0 0. "FORCEWAKE,Force peripheral clocking to stay on during Deep Sleep and Power-down modes. When 1  clocking to peripherals is prevented from being shut down when the CPU enters Deep Sleep and Power-down modes. This is intended to allow a coprocessor to.." "0,1"
group.long 0xE04++0x3
line.long 0x0 "AUTOCGOR,Auto Clock-Gate Override Register"
bitfld.long 0x0 4. "RAM3,When 1  automatic clock gating for RAM1 are turned off." "0,1"
bitfld.long 0x0 3. "RAM2,When 1  automatic clock gating for RAM1 are turned off." "0,1"
newline
bitfld.long 0x0 2. "RAM1,When 1  automatic clock gating for RAM1 are turned off." "0,1"
bitfld.long 0x0 1. "RAM0X,When 1  automatic clock gating for RAMX and RAM0 are turned off." "0,1"
rgroup.long 0xFF4++0xB
line.long 0x0 "JTAGIDCODE,JTAG ID code register"
hexmask.long 0x0 0.--31. 1. "JTAGID,JTAG ID code."
line.long 0x4 "DEVICE_ID0,Part ID register"
hexmask.long 0x4 0.--31. 1. "PARTID,Part ID"
line.long 0x8 "DEVICE_ID1,Boot ROM and die revision register"
hexmask.long 0x8 0.--31. 1. "REVID,Revision."
group.long 0x20044++0x3
line.long 0x0 "BODCTRL,Brown-Out Detect control"
bitfld.long 0x0 7. "BODINTSTAT,BOD interrupt status. When 1  a BOD interrupt has occurred. Cleared by writing 1 to this bit." "0,1"
bitfld.long 0x0 6. "BODRSTSTAT,BOD reset status. When 1  a BOD reset has occurred. Cleared by writing 1 to this bit." "0,1"
newline
bitfld.long 0x0 5. "BODINTENA,BOD interrupt enable" "0: Disable interrupt function.,1: Enable interrupt function."
bitfld.long 0x0 3.--4. "BODINTLEV,BOD interrupt level" "0: Level 0: 2.05 V,1: Level 1: 2.45 V,2: Level 2: 2.75 V,3: Level 3: 3.05 V"
newline
bitfld.long 0x0 2. "BODRSTENA,BOD reset enable" "0: Disable reset function.,1: Enable reset function."
bitfld.long 0x0 0.--1. "BODRSTLEV,BOD reset level" "0: Level 0: 1.5 V,1: Level 1: 1.85 V,2: Level 2: 2.0 V,3: Level 3: 2.3 V"
endif
tree.end
tree "SYSTICK (System Timer)"
base ad:0xE000E010
group.long 0x0++0xB
line.long 0x0 "CSR,SysTick Control and Status Register"
bitfld.long 0x0 16. "COUNTFLAG,no description available" "0,1"
bitfld.long 0x0 2. "CLKSOURCE,no description available" "0: external clock,1: processor clock"
newline
bitfld.long 0x0 1. "TICKINT,no description available" "0: counting down to 0 does not assert the SysTick..,1: counting down to 0 asserts the SysTick exception.."
bitfld.long 0x0 0. "ENABLE,no description available" "0: counter disabled,1: counter enabled"
line.long 0x4 "RVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x4 0.--23. 1. "RELOAD,Value to load into the SysTick Current Value Register when the counter reaches 0"
line.long 0x8 "CVR,SysTick Current Value Register"
hexmask.long.tbyte 0x8 0.--23. 1. "CURRENT,Current value at the time the register is accessed"
rgroup.long 0xC++0x3
line.long 0x0 "CALIB,SysTick Calibration Value Register"
bitfld.long 0x0 31. "NOREF,no description available" "0: The reference clock is provided,1: The reference clock is not provided"
bitfld.long 0x0 30. "SKEW,no description available" "0: 10ms calibration value is exact,1: 10ms calibration value is inexact because of the.."
newline
hexmask.long.tbyte 0x0 0.--23. 1. "TENMS,Reload value to use for 10ms timing"
tree.end
tree "USART"
base ad:0x0
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
base ad:0x40086000
elif (cpuis("LPC54101*"))
base ad:0x40084000
endif
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54101*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
tree "USART0"
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
newline
bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
newline
bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
newline
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
newline
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
newline
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
endif
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
newline
bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
newline
sif (cpuis("LPC54101*"))
bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
endif
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
newline
bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
sif (cpuis("LPC54101*"))
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
newline
endif
bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
sif (cpuis("LPC54101*"))
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
newline
endif
newline
bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
newline
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
newline
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
newline
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
endif
bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
newline
sif (cpuis("LPC54101*"))
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
endif
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
newline
bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
newline
bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
newline
rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
newline
bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
newline
rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
newline
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
newline
bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character.." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
newline
bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
newline
bitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x8 8. "OVERRUNINT,Overrun Error interrupt flag. This flag is set when a new character is received while the receiver buffer is still in use. If this occurs  the newly received character in the shift register is lost." "0,1"
newline
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
newline
bitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
bitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
newline
bitfld.long 0x8 2. "TXRDY,Transmitter Ready flag. When 1  this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT. Set when the data is moved from the transmit.." "0,1"
bitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
newline
bitfld.long 0x8 0. "RXRDY,Receiver Ready flag. When 1  indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT or RXDATSTAT registers." "0,1"
endif
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
newline
bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
newline
bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
newline
sif (cpuis("LPC54101*"))
bitfld.long 0xC 8. "OVERRUNEN,When 1  enables an interrupt when an overrun error occurred." "0,1"
endif
bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
newline
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
newline
sif (cpuis("LPC54101*"))
bitfld.long 0xC 2. "TXRDYEN,When 1  enables an interrupt when the TXDAT register is available to take another character to transmit." "0,1"
endif
sif (cpuis("LPC54101*"))
bitfld.long 0xC 0. "RXRDYEN,When 1  enables an interrupt when there is a received character available to be read from the RXDAT register." "0,1"
endif
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x0 8. "OVERRUNCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 2. "TXRDYCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x0 0. "RXRDYCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
endif
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
rbitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
rbitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
newline
rbitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
rbitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
newline
rbitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
rbitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
newline
rbitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
rbitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
newline
rbitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
newline
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
newline
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
newline
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x0 8. "OVERRUNINT,Overrun Error interrupt flag." "0,1"
newline
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
newline
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
bitfld.long 0x0 2. "TXRDY,Transmitter Ready flag." "0,1"
newline
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x0 0. "RXRDY,Receiver Ready flag." "0,1"
endif
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
newline
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
newline
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
newline
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
newline
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
newline
rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
newline
rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
newline
rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
newline
bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
newline
bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
newline
bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
newline
bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
newline
bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
newline
bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
wgroup.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
endif
sif (cpuis("LPC54101*"))
group.long 0x10++0xF
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
line.long 0x4 "RXDAT,Receiver Data register. Contains the last character received."
hexmask.long.word 0x4 0.--8. 1. "DATA,The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings."
line.long 0x8 "RXDATSTAT,Receiver Data with Status register. Combines the last character received with the current USART receive status. Allows DMA or software to recover incoming data and status together."
bitfld.long 0x8 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 311." "0,1"
bitfld.long 0x8 14. "PARITYERR,Parity Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x8 13. "FRAMERR,Framing Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will set when the character in RXDAT was received with a missing stop bit at the expected.." "0,1"
hexmask.long.word 0x8 0.--8. 1. "RXDATA,The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings."
line.long 0xC "TXDAT,Transmit Data register. Data to be transmitted is written here."
hexmask.long.word 0xC 0.--8. 1. "TXDATA,Writing to the USART Transmit Data Register causes the data to be transmitted as soon as the transmit shift register is available and any conditions for transmitting data are met: CTS low (if CTSEN bit = 1)  TXDIS bit = 0."
endif
sif (cpuis("LPC54101*"))
group.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
endif
tree.end
endif
tree "USART4"
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
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bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
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bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
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bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
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rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
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bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
newline
rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
newline
bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
wgroup.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
newline
bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "USART5"
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
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bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
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bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
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bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
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rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
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bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
wgroup.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "USART6"
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
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bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
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bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
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bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
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rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
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bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
wgroup.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "USART7"
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
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bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
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bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
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bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
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rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
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bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
wgroup.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "USART8"
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
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bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
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bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
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bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
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rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
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bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
wgroup.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "USART9"
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
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bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
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bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
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bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
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rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
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bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
newline
bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
newline
bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
newline
bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
wgroup.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
newline
bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
newline
bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
newline
hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
base ad:0x40087000
elif (cpuis("LPC54101*"))
base ad:0x40088000
endif
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54101*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
tree "USART1"
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
newline
bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
newline
bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
newline
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
newline
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
newline
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
endif
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
newline
bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
newline
sif (cpuis("LPC54101*"))
bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
endif
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
newline
bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
sif (cpuis("LPC54101*"))
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
newline
endif
bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
sif (cpuis("LPC54101*"))
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
newline
endif
newline
bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
newline
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
newline
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
newline
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
endif
bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
newline
sif (cpuis("LPC54101*"))
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
endif
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
newline
bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
newline
bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
newline
rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
newline
bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
newline
rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
newline
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
newline
bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character.." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
newline
bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
newline
bitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x8 8. "OVERRUNINT,Overrun Error interrupt flag. This flag is set when a new character is received while the receiver buffer is still in use. If this occurs  the newly received character in the shift register is lost." "0,1"
newline
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
newline
bitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
bitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
newline
bitfld.long 0x8 2. "TXRDY,Transmitter Ready flag. When 1  this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT. Set when the data is moved from the transmit.." "0,1"
bitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
newline
bitfld.long 0x8 0. "RXRDY,Receiver Ready flag. When 1  indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT or RXDATSTAT registers." "0,1"
endif
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
newline
bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
newline
bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
newline
sif (cpuis("LPC54101*"))
bitfld.long 0xC 8. "OVERRUNEN,When 1  enables an interrupt when an overrun error occurred." "0,1"
endif
bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
newline
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
newline
sif (cpuis("LPC54101*"))
bitfld.long 0xC 2. "TXRDYEN,When 1  enables an interrupt when the TXDAT register is available to take another character to transmit." "0,1"
endif
sif (cpuis("LPC54101*"))
bitfld.long 0xC 0. "RXRDYEN,When 1  enables an interrupt when there is a received character available to be read from the RXDAT register." "0,1"
endif
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x0 8. "OVERRUNCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 2. "TXRDYCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x0 0. "RXRDYCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
endif
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
rbitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
rbitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
newline
rbitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
rbitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
newline
rbitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
rbitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
newline
rbitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
rbitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
newline
rbitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
newline
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
newline
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
newline
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x0 8. "OVERRUNINT,Overrun Error interrupt flag." "0,1"
newline
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
newline
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
bitfld.long 0x0 2. "TXRDY,Transmitter Ready flag." "0,1"
newline
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x0 0. "RXRDY,Receiver Ready flag." "0,1"
endif
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
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bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
newline
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
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bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
newline
rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
newline
bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
newline
bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
wgroup.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
newline
bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
newline
bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
endif
sif (cpuis("LPC54101*"))
group.long 0x10++0xF
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
line.long 0x4 "RXDAT,Receiver Data register. Contains the last character received."
hexmask.long.word 0x4 0.--8. 1. "DATA,The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings."
line.long 0x8 "RXDATSTAT,Receiver Data with Status register. Combines the last character received with the current USART receive status. Allows DMA or software to recover incoming data and status together."
bitfld.long 0x8 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 311." "0,1"
bitfld.long 0x8 14. "PARITYERR,Parity Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will be set when a parity error is detected in a received character." "0,1"
newline
bitfld.long 0x8 13. "FRAMERR,Framing Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will set when the character in RXDAT was received with a missing stop bit at the expected.." "0,1"
hexmask.long.word 0x8 0.--8. 1. "RXDATA,The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings."
line.long 0xC "TXDAT,Transmit Data register. Data to be transmitted is written here."
hexmask.long.word 0xC 0.--8. 1. "TXDATA,Writing to the USART Transmit Data Register causes the data to be transmitted as soon as the transmit shift register is available and any conditions for transmitting data are met: CTS low (if CTSEN bit = 1)  TXDIS bit = 0."
endif
sif (cpuis("LPC54101*"))
group.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
endif
tree.end
endif
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
base ad:0x40088000
elif (cpuis("LPC54101*"))
base ad:0x4008C000
endif
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54101*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
tree "USART2"
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
newline
bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
newline
bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
newline
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
newline
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
newline
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
endif
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
newline
bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
newline
sif (cpuis("LPC54101*"))
bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
endif
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
newline
bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
sif (cpuis("LPC54101*"))
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
newline
endif
bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
sif (cpuis("LPC54101*"))
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
newline
endif
newline
bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
newline
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
newline
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
newline
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
endif
bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
newline
sif (cpuis("LPC54101*"))
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
endif
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
newline
bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
newline
bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
newline
rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
newline
bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
newline
rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
newline
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
newline
bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character.." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
newline
bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
newline
bitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x8 8. "OVERRUNINT,Overrun Error interrupt flag. This flag is set when a new character is received while the receiver buffer is still in use. If this occurs  the newly received character in the shift register is lost." "0,1"
newline
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
newline
bitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
bitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
newline
bitfld.long 0x8 2. "TXRDY,Transmitter Ready flag. When 1  this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT. Set when the data is moved from the transmit.." "0,1"
bitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
newline
bitfld.long 0x8 0. "RXRDY,Receiver Ready flag. When 1  indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT or RXDATSTAT registers." "0,1"
endif
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
newline
bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
newline
bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
newline
sif (cpuis("LPC54101*"))
bitfld.long 0xC 8. "OVERRUNEN,When 1  enables an interrupt when an overrun error occurred." "0,1"
endif
bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
newline
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
newline
sif (cpuis("LPC54101*"))
bitfld.long 0xC 2. "TXRDYEN,When 1  enables an interrupt when the TXDAT register is available to take another character to transmit." "0,1"
endif
sif (cpuis("LPC54101*"))
bitfld.long 0xC 0. "RXRDYEN,When 1  enables an interrupt when there is a received character available to be read from the RXDAT register." "0,1"
endif
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x0 8. "OVERRUNCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 2. "TXRDYCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x0 0. "RXRDYCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
endif
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
rbitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
rbitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
newline
rbitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
rbitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
newline
rbitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
rbitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
newline
rbitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
rbitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
newline
rbitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
newline
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
newline
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
newline
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x0 8. "OVERRUNINT,Overrun Error interrupt flag." "0,1"
newline
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
newline
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
bitfld.long 0x0 2. "TXRDY,Transmitter Ready flag." "0,1"
newline
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x0 0. "RXRDY,Receiver Ready flag." "0,1"
endif
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
newline
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
newline
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
newline
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
newline
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
newline
rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
newline
rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
newline
rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
newline
bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
newline
bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
newline
bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
newline
bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
newline
bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
newline
bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
wgroup.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
newline
bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
newline
bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
newline
hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
endif
sif (cpuis("LPC54101*"))
group.long 0x10++0xF
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
line.long 0x4 "RXDAT,Receiver Data register. Contains the last character received."
hexmask.long.word 0x4 0.--8. 1. "DATA,The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings."
line.long 0x8 "RXDATSTAT,Receiver Data with Status register. Combines the last character received with the current USART receive status. Allows DMA or software to recover incoming data and status together."
bitfld.long 0x8 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 311." "0,1"
bitfld.long 0x8 14. "PARITYERR,Parity Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will be set when a parity error is detected in a received character." "0,1"
newline
bitfld.long 0x8 13. "FRAMERR,Framing Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will set when the character in RXDAT was received with a missing stop bit at the expected.." "0,1"
hexmask.long.word 0x8 0.--8. 1. "RXDATA,The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings."
line.long 0xC "TXDAT,Transmit Data register. Data to be transmitted is written here."
hexmask.long.word 0xC 0.--8. 1. "TXDATA,Writing to the USART Transmit Data Register causes the data to be transmitted as soon as the transmit shift register is available and any conditions for transmitting data are met: CTS low (if CTSEN bit = 1)  TXDIS bit = 0."
endif
sif (cpuis("LPC54101*"))
group.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
endif
tree.end
endif
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
base ad:0x40089000
elif (cpuis("LPC54101*"))
base ad:0x40090000
endif
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54101*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
tree "USART3"
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
newline
bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
newline
bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
newline
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
newline
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
newline
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
endif
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
newline
bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
newline
sif (cpuis("LPC54101*"))
bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
endif
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
newline
bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
sif (cpuis("LPC54101*"))
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
newline
endif
bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
sif (cpuis("LPC54101*"))
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
newline
endif
newline
bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
newline
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
newline
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
newline
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
endif
bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
newline
sif (cpuis("LPC54101*"))
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
endif
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
newline
bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
newline
bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
newline
rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
newline
bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
newline
rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
newline
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
newline
bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character.." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
newline
bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
newline
bitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x8 8. "OVERRUNINT,Overrun Error interrupt flag. This flag is set when a new character is received while the receiver buffer is still in use. If this occurs  the newly received character in the shift register is lost." "0,1"
newline
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
newline
bitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
bitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
newline
bitfld.long 0x8 2. "TXRDY,Transmitter Ready flag. When 1  this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT. Set when the data is moved from the transmit.." "0,1"
bitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
newline
bitfld.long 0x8 0. "RXRDY,Receiver Ready flag. When 1  indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT or RXDATSTAT registers." "0,1"
endif
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
newline
bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
newline
bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
newline
sif (cpuis("LPC54101*"))
bitfld.long 0xC 8. "OVERRUNEN,When 1  enables an interrupt when an overrun error occurred." "0,1"
endif
bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
newline
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
newline
sif (cpuis("LPC54101*"))
bitfld.long 0xC 2. "TXRDYEN,When 1  enables an interrupt when the TXDAT register is available to take another character to transmit." "0,1"
endif
sif (cpuis("LPC54101*"))
bitfld.long 0xC 0. "RXRDYEN,When 1  enables an interrupt when there is a received character available to be read from the RXDAT register." "0,1"
endif
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x0 8. "OVERRUNCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 2. "TXRDYCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x0 0. "RXRDYCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
endif
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
rbitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
rbitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
newline
rbitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
rbitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
newline
rbitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
rbitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
newline
rbitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
rbitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
newline
rbitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
newline
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
newline
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
newline
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x0 8. "OVERRUNINT,Overrun Error interrupt flag." "0,1"
newline
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
newline
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
bitfld.long 0x0 2. "TXRDY,Transmitter Ready flag." "0,1"
newline
endif
sif (cpuis("LPC54101*"))
bitfld.long 0x0 0. "RXRDY,Receiver Ready flag." "0,1"
endif
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
newline
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
newline
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
newline
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
newline
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
newline
rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
newline
rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
newline
rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
newline
bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
newline
bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
newline
bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
newline
bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
newline
bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
newline
bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
wgroup.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
newline
bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
newline
bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
endif
sif (cpuis("LPC54101*"))
group.long 0x10++0xF
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
line.long 0x4 "RXDAT,Receiver Data register. Contains the last character received."
hexmask.long.word 0x4 0.--8. 1. "DATA,The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings."
line.long 0x8 "RXDATSTAT,Receiver Data with Status register. Combines the last character received with the current USART receive status. Allows DMA or software to recover incoming data and status together."
bitfld.long 0x8 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 311." "0,1"
bitfld.long 0x8 14. "PARITYERR,Parity Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will be set when a parity error is detected in a received character." "0,1"
newline
bitfld.long 0x8 13. "FRAMERR,Framing Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will set when the character in RXDAT was received with a missing stop bit at the expected.." "0,1"
hexmask.long.word 0x8 0.--8. 1. "RXDATA,The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings."
line.long 0xC "TXDAT,Transmit Data register. Data to be transmitted is written here."
hexmask.long.word 0xC 0.--8. 1. "TXDATA,Writing to the USART Transmit Data Register causes the data to be transmitted as soon as the transmit shift register is available and any conditions for transmitting data are met: CTS low (if CTSEN bit = 1)  TXDIS bit = 0."
endif
sif (cpuis("LPC54101*"))
group.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
endif
tree.end
endif
sif (cpuis("LPC54102*"))
tree "USART0"
base ad:0x40084000
group.long 0x0++0x2F
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
newline
bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
newline
bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
newline
bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
newline
bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
newline
bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
newline
bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
newline
bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
newline
bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
newline
bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
newline
bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
newline
bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character.." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
newline
bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
newline
bitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
bitfld.long 0x8 8. "OVERRUNINT,Overrun Error interrupt flag. This flag is set when a new character is received while the receiver buffer is still in use. If this occurs  the newly received character in the shift register is lost." "0,1"
newline
bitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
newline
bitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
bitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
newline
bitfld.long 0x8 2. "TXRDY,Transmitter Ready flag. When 1  this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT. Set when the data is moved from the transmit.." "0,1"
bitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
newline
bitfld.long 0x8 0. "RXRDY,Receiver Ready flag. When 1  indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT or RXDATSTAT registers." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register. Contains an individual interrupt enable bit for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 311." "0,1"
newline
bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
newline
bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
newline
bitfld.long 0xC 8. "OVERRUNEN,When 1  enables an interrupt when an overrun error occurred." "0,1"
bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
newline
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
newline
bitfld.long 0xC 2. "TXRDYEN,When 1  enables an interrupt when the TXDAT register is available to take another character to transmit." "0,1"
bitfld.long 0xC 0. "RXRDYEN,When 1  enables an interrupt when there is a received character available to be read from the RXDAT register." "0,1"
line.long 0x10 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x10 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x10 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x10 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x10 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x10 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x10 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x10 8. "OVERRUNCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x10 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x10 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x10 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x10 2. "TXRDYCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x10 0. "RXRDYCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
line.long 0x14 "RXDAT,Receiver Data register. Contains the last character received."
hexmask.long.word 0x14 0.--8. 1. "DATA,The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings."
line.long 0x18 "RXDATSTAT,Receiver Data with Status register. Combines the last character received with the current USART receive status. Allows DMA or software to recover incoming data and status together."
bitfld.long 0x18 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 311." "0,1"
bitfld.long 0x18 14. "PARITYERR,Parity Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will be set when a parity error is detected in a received character." "0,1"
newline
bitfld.long 0x18 13. "FRAMERR,Framing Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will set when the character in RXDAT was received with a missing stop bit at the expected.." "0,1"
hexmask.long.word 0x18 0.--8. 1. "RXDATA,The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings."
line.long 0x1C "TXDAT,Transmit Data register. Data to be transmitted is written here."
hexmask.long.word 0x1C 0.--8. 1. "TXDATA,Writing to the USART Transmit Data Register causes the data to be transmitted as soon as the transmit shift register is available and any conditions for transmitting data are met: CTS low (if CTSEN bit = 1)  TXDIS bit = 0."
line.long 0x20 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x20 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = The FRG clock is used directly by the USART function. 1 = The FRG clock is divided by 2 before use by the USART function. 2 =.."
line.long 0x24 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x24 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x24 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
newline
bitfld.long 0x24 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x24 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
newline
bitfld.long 0x24 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x24 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
newline
bitfld.long 0x24 8. "OVERRUNINT,Overrun Error interrupt flag." "0,1"
bitfld.long 0x24 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
newline
bitfld.long 0x24 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
bitfld.long 0x24 3. "TXIDLE,Transmitter Idle status." "0,1"
newline
bitfld.long 0x24 2. "TXRDY,Transmitter Ready flag." "0,1"
bitfld.long 0x24 0. "RXRDY,Receiver Ready flag." "0,1"
line.long 0x28 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x28 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 peripheral clocks are used to transmit and receive each data bit. 0x5 = 6 peripheral clocks are used to transmit and receive each data bit. ... 0xF= 16 peripheral clocks are used to.."
line.long 0x2C "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x2C 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
tree.end
tree "USART1"
base ad:0x40088000
group.long 0x0++0x2F
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
newline
bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
newline
bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
newline
bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
newline
bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
newline
bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
newline
bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
newline
bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
newline
bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
newline
bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
newline
bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
newline
bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character.." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
newline
bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
newline
bitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
bitfld.long 0x8 8. "OVERRUNINT,Overrun Error interrupt flag. This flag is set when a new character is received while the receiver buffer is still in use. If this occurs  the newly received character in the shift register is lost." "0,1"
newline
bitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
newline
bitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
bitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
newline
bitfld.long 0x8 2. "TXRDY,Transmitter Ready flag. When 1  this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT. Set when the data is moved from the transmit.." "0,1"
bitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
newline
bitfld.long 0x8 0. "RXRDY,Receiver Ready flag. When 1  indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT or RXDATSTAT registers." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register. Contains an individual interrupt enable bit for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 311." "0,1"
newline
bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
newline
bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
newline
bitfld.long 0xC 8. "OVERRUNEN,When 1  enables an interrupt when an overrun error occurred." "0,1"
bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
newline
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
newline
bitfld.long 0xC 2. "TXRDYEN,When 1  enables an interrupt when the TXDAT register is available to take another character to transmit." "0,1"
bitfld.long 0xC 0. "RXRDYEN,When 1  enables an interrupt when there is a received character available to be read from the RXDAT register." "0,1"
line.long 0x10 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x10 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x10 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x10 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x10 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x10 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x10 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x10 8. "OVERRUNCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x10 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x10 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x10 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x10 2. "TXRDYCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x10 0. "RXRDYCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
line.long 0x14 "RXDAT,Receiver Data register. Contains the last character received."
hexmask.long.word 0x14 0.--8. 1. "DATA,The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings."
line.long 0x18 "RXDATSTAT,Receiver Data with Status register. Combines the last character received with the current USART receive status. Allows DMA or software to recover incoming data and status together."
bitfld.long 0x18 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 311." "0,1"
bitfld.long 0x18 14. "PARITYERR,Parity Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will be set when a parity error is detected in a received character." "0,1"
newline
bitfld.long 0x18 13. "FRAMERR,Framing Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will set when the character in RXDAT was received with a missing stop bit at the expected.." "0,1"
hexmask.long.word 0x18 0.--8. 1. "RXDATA,The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings."
line.long 0x1C "TXDAT,Transmit Data register. Data to be transmitted is written here."
hexmask.long.word 0x1C 0.--8. 1. "TXDATA,Writing to the USART Transmit Data Register causes the data to be transmitted as soon as the transmit shift register is available and any conditions for transmitting data are met: CTS low (if CTSEN bit = 1)  TXDIS bit = 0."
line.long 0x20 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x20 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = The FRG clock is used directly by the USART function. 1 = The FRG clock is divided by 2 before use by the USART function. 2 =.."
line.long 0x24 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x24 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x24 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
newline
bitfld.long 0x24 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x24 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
newline
bitfld.long 0x24 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x24 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
newline
bitfld.long 0x24 8. "OVERRUNINT,Overrun Error interrupt flag." "0,1"
bitfld.long 0x24 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
newline
bitfld.long 0x24 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
bitfld.long 0x24 3. "TXIDLE,Transmitter Idle status." "0,1"
newline
bitfld.long 0x24 2. "TXRDY,Transmitter Ready flag." "0,1"
bitfld.long 0x24 0. "RXRDY,Receiver Ready flag." "0,1"
line.long 0x28 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x28 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 peripheral clocks are used to transmit and receive each data bit. 0x5 = 6 peripheral clocks are used to transmit and receive each data bit. ... 0xF= 16 peripheral clocks are used to.."
line.long 0x2C "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x2C 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
tree.end
tree "USART2"
base ad:0x4008C000
group.long 0x0++0x2F
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
newline
bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
newline
bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
newline
bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
newline
bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
newline
bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
newline
bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
newline
bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
newline
bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
newline
bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
newline
bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
newline
bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character.." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
newline
bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
newline
bitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
bitfld.long 0x8 8. "OVERRUNINT,Overrun Error interrupt flag. This flag is set when a new character is received while the receiver buffer is still in use. If this occurs  the newly received character in the shift register is lost." "0,1"
newline
bitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
newline
bitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
bitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
newline
bitfld.long 0x8 2. "TXRDY,Transmitter Ready flag. When 1  this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT. Set when the data is moved from the transmit.." "0,1"
bitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
newline
bitfld.long 0x8 0. "RXRDY,Receiver Ready flag. When 1  indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT or RXDATSTAT registers." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register. Contains an individual interrupt enable bit for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 311." "0,1"
newline
bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
newline
bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
newline
bitfld.long 0xC 8. "OVERRUNEN,When 1  enables an interrupt when an overrun error occurred." "0,1"
bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
newline
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
newline
bitfld.long 0xC 2. "TXRDYEN,When 1  enables an interrupt when the TXDAT register is available to take another character to transmit." "0,1"
bitfld.long 0xC 0. "RXRDYEN,When 1  enables an interrupt when there is a received character available to be read from the RXDAT register." "0,1"
line.long 0x10 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x10 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x10 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x10 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x10 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x10 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x10 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x10 8. "OVERRUNCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x10 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x10 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x10 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x10 2. "TXRDYCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x10 0. "RXRDYCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
line.long 0x14 "RXDAT,Receiver Data register. Contains the last character received."
hexmask.long.word 0x14 0.--8. 1. "DATA,The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings."
line.long 0x18 "RXDATSTAT,Receiver Data with Status register. Combines the last character received with the current USART receive status. Allows DMA or software to recover incoming data and status together."
bitfld.long 0x18 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 311." "0,1"
bitfld.long 0x18 14. "PARITYERR,Parity Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will be set when a parity error is detected in a received character." "0,1"
newline
bitfld.long 0x18 13. "FRAMERR,Framing Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will set when the character in RXDAT was received with a missing stop bit at the expected.." "0,1"
hexmask.long.word 0x18 0.--8. 1. "RXDATA,The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings."
line.long 0x1C "TXDAT,Transmit Data register. Data to be transmitted is written here."
hexmask.long.word 0x1C 0.--8. 1. "TXDATA,Writing to the USART Transmit Data Register causes the data to be transmitted as soon as the transmit shift register is available and any conditions for transmitting data are met: CTS low (if CTSEN bit = 1)  TXDIS bit = 0."
line.long 0x20 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x20 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = The FRG clock is used directly by the USART function. 1 = The FRG clock is divided by 2 before use by the USART function. 2 =.."
line.long 0x24 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x24 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x24 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
newline
bitfld.long 0x24 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x24 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
newline
bitfld.long 0x24 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x24 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
newline
bitfld.long 0x24 8. "OVERRUNINT,Overrun Error interrupt flag." "0,1"
bitfld.long 0x24 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
newline
bitfld.long 0x24 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
bitfld.long 0x24 3. "TXIDLE,Transmitter Idle status." "0,1"
newline
bitfld.long 0x24 2. "TXRDY,Transmitter Ready flag." "0,1"
bitfld.long 0x24 0. "RXRDY,Receiver Ready flag." "0,1"
line.long 0x28 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x28 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 peripheral clocks are used to transmit and receive each data bit. 0x5 = 6 peripheral clocks are used to transmit and receive each data bit. ... 0xF= 16 peripheral clocks are used to.."
line.long 0x2C "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x2C 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
tree.end
tree "USART3"
base ad:0x40090000
group.long 0x0++0x2F
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
newline
bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
newline
bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
newline
bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
newline
bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
newline
bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
newline
bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
newline
bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
newline
bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
newline
bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
newline
bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character.." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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bitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
bitfld.long 0x8 8. "OVERRUNINT,Overrun Error interrupt flag. This flag is set when a new character is received while the receiver buffer is still in use. If this occurs  the newly received character in the shift register is lost." "0,1"
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bitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
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bitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
bitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
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bitfld.long 0x8 2. "TXRDY,Transmitter Ready flag. When 1  this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT. Set when the data is moved from the transmit.." "0,1"
bitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
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bitfld.long 0x8 0. "RXRDY,Receiver Ready flag. When 1  indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT or RXDATSTAT registers." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register. Contains an individual interrupt enable bit for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 311." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
newline
bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 8. "OVERRUNEN,When 1  enables an interrupt when an overrun error occurred." "0,1"
bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
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bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
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bitfld.long 0xC 2. "TXRDYEN,When 1  enables an interrupt when the TXDAT register is available to take another character to transmit." "0,1"
bitfld.long 0xC 0. "RXRDYEN,When 1  enables an interrupt when there is a received character available to be read from the RXDAT register." "0,1"
line.long 0x10 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x10 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x10 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x10 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x10 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x10 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x10 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x10 8. "OVERRUNCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x10 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x10 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x10 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x10 2. "TXRDYCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x10 0. "RXRDYCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
line.long 0x14 "RXDAT,Receiver Data register. Contains the last character received."
hexmask.long.word 0x14 0.--8. 1. "DATA,The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings."
line.long 0x18 "RXDATSTAT,Receiver Data with Status register. Combines the last character received with the current USART receive status. Allows DMA or software to recover incoming data and status together."
bitfld.long 0x18 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 311." "0,1"
bitfld.long 0x18 14. "PARITYERR,Parity Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x18 13. "FRAMERR,Framing Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will set when the character in RXDAT was received with a missing stop bit at the expected.." "0,1"
hexmask.long.word 0x18 0.--8. 1. "RXDATA,The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings."
line.long 0x1C "TXDAT,Transmit Data register. Data to be transmitted is written here."
hexmask.long.word 0x1C 0.--8. 1. "TXDATA,Writing to the USART Transmit Data Register causes the data to be transmitted as soon as the transmit shift register is available and any conditions for transmitting data are met: CTS low (if CTSEN bit = 1)  TXDIS bit = 0."
line.long 0x20 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x20 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = The FRG clock is used directly by the USART function. 1 = The FRG clock is divided by 2 before use by the USART function. 2 =.."
line.long 0x24 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x24 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x24 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x24 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x24 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x24 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x24 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x24 8. "OVERRUNINT,Overrun Error interrupt flag." "0,1"
bitfld.long 0x24 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
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bitfld.long 0x24 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
bitfld.long 0x24 3. "TXIDLE,Transmitter Idle status." "0,1"
newline
bitfld.long 0x24 2. "TXRDY,Transmitter Ready flag." "0,1"
bitfld.long 0x24 0. "RXRDY,Receiver Ready flag." "0,1"
line.long 0x28 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x28 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 peripheral clocks are used to transmit and receive each data bit. 0x5 = 6 peripheral clocks are used to transmit and receive each data bit. ... 0xF= 16 peripheral clocks are used to.."
line.long 0x2C "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x2C 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
tree.end
endif
sif (cpuis("LPC54113*"))
tree "USART0"
base ad:0x40086000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
newline
bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 16. "IOMODE,I/O output mode." "0: Standard. USART output and input operate in..,1: IrDA. USART output and input operate in IrDA mode."
bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
newline
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
newline
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
newline
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
newline
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
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bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
newline
bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
newline
bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
newline
bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
newline
bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
newline
rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
newline
bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
newline
rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
newline
bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
newline
bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
newline
bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
newline
bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
newline
bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
newline
bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
newline
bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
newline
bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
newline
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
newline
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
newline
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
newline
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
newline
rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
newline
rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
tree.end
tree "USART1"
base ad:0x40087000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 16. "IOMODE,I/O output mode." "0: Standard. USART output and input operate in..,1: IrDA. USART output and input operate in IrDA mode."
bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
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bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
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bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
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bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
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bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
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bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
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bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
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rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
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bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
newline
bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
tree.end
tree "USART2"
base ad:0x40088000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
newline
bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 16. "IOMODE,I/O output mode." "0: Standard. USART output and input operate in..,1: IrDA. USART output and input operate in IrDA mode."
bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
newline
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
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bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
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bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
newline
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
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bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
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bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
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rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
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bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
newline
bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
newline
bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
newline
bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
newline
bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
tree.end
tree "USART3"
base ad:0x40089000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
newline
bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 16. "IOMODE,I/O output mode." "0: Standard. USART output and input operate in..,1: IrDA. USART output and input operate in IrDA mode."
bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
newline
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
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bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
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bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
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bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
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bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
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bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
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rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
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bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
tree.end
tree "USART4"
base ad:0x4008A000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 16. "IOMODE,I/O output mode." "0: Standard. USART output and input operate in..,1: IrDA. USART output and input operate in IrDA mode."
bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
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bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
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bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
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bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
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bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
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bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
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bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
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rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
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bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
newline
bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
newline
bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
tree.end
tree "USART5"
base ad:0x40096000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
newline
bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 16. "IOMODE,I/O output mode." "0: Standard. USART output and input operate in..,1: IrDA. USART output and input operate in IrDA mode."
bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
newline
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
newline
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
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bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
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bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
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bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
newline
bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
newline
bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
newline
bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
newline
rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
newline
bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
newline
bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
newline
bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
newline
bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
newline
bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
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bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
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rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
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bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
tree.end
tree "USART6"
base ad:0x40097000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 16. "IOMODE,I/O output mode." "0: Standard. USART output and input operate in..,1: IrDA. USART output and input operate in IrDA mode."
bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
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bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
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bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
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bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
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bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
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bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
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bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
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rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
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bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
newline
bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
newline
bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
tree.end
tree "USART7"
base ad:0x40098000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
newline
bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 16. "IOMODE,I/O output mode." "0: Standard. USART output and input operate in..,1: IrDA. USART output and input operate in IrDA mode."
bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
newline
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
newline
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
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bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
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bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
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bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
newline
bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
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bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
newline
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
newline
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
newline
rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
newline
rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
newline
rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
newline
bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
newline
bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
newline
bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
newline
bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
newline
bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
newline
bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
newline
bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
newline
bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
tree.end
endif
sif (cpuis("LPC54114*"))
tree "USART0"
base ad:0x40086000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 16. "IOMODE,I/O output mode." "0: Standard. USART output and input operate in..,1: IrDA. USART output and input operate in IrDA mode."
bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
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bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
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bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
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bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
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bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
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bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
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bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
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rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
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bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
tree.end
tree "USART1"
base ad:0x40087000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 16. "IOMODE,I/O output mode." "0: Standard. USART output and input operate in..,1: IrDA. USART output and input operate in IrDA mode."
bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
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bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
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bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
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bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
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bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
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bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
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bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
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rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
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bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
newline
bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
tree.end
tree "USART2"
base ad:0x40088000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 16. "IOMODE,I/O output mode." "0: Standard. USART output and input operate in..,1: IrDA. USART output and input operate in IrDA mode."
bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
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bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
newline
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
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bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
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bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
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bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
newline
bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
newline
bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
newline
rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
newline
bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
newline
bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
newline
bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
newline
bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
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bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
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rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
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bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
tree.end
tree "USART3"
base ad:0x40089000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 16. "IOMODE,I/O output mode." "0: Standard. USART output and input operate in..,1: IrDA. USART output and input operate in IrDA mode."
bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
newline
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
newline
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
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bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
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bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
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bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
newline
rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
newline
bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
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bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
newline
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
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bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
tree.end
tree "USART4"
base ad:0x4008A000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 16. "IOMODE,I/O output mode." "0: Standard. USART output and input operate in..,1: IrDA. USART output and input operate in IrDA mode."
bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
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bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
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bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
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bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
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bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
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bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
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bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
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rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
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bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
newline
bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
tree.end
tree "USART5"
base ad:0x40096000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 16. "IOMODE,I/O output mode." "0: Standard. USART output and input operate in..,1: IrDA. USART output and input operate in IrDA mode."
bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
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bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
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bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
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bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
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bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
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bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
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bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
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rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
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bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
tree.end
tree "USART6"
base ad:0x40097000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 16. "IOMODE,I/O output mode." "0: Standard. USART output and input operate in..,1: IrDA. USART output and input operate in IrDA mode."
bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
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bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
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bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
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bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
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bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
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bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
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bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
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rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
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bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
tree.end
tree "USART7"
base ad:0x40098000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 16. "IOMODE,I/O output mode." "0: Standard. USART output and input operate in..,1: IrDA. USART output and input operate in IrDA mode."
bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
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bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
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bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
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bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
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bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
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bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
newline
bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
newline
bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
newline
bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
newline
bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
newline
bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
newline
bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
newline
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
newline
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
newline
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
newline
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
newline
rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
newline
rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
newline
rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
newline
bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
newline
bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
newline
bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
newline
bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
newline
bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
newline
bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
newline
bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
newline
bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
tree.end
endif
sif (cpuis("LPC54605*"))
tree "USART0"
base ad:0x40086000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
newline
bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
newline
bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
newline
bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
newline
bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
newline
bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
newline
bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
newline
bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
newline
bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
newline
bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
newline
bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
newline
bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
newline
bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
newline
rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
newline
bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
newline
rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
newline
bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
newline
bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
newline
bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
newline
bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
newline
bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
newline
bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
newline
bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
newline
bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "USART1"
base ad:0x40087000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
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bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
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bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "USART2"
base ad:0x40088000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
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bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
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bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
newline
bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "USART3"
base ad:0x40089000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
newline
bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
newline
bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
newline
bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
newline
bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
newline
bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
newline
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
newline
rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
newline
bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
newline
bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
newline
bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
newline
bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "USART4"
base ad:0x4008A000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
newline
bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
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bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
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bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "USART5"
base ad:0x40096000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
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bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
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bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "USART6"
base ad:0x40097000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
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bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
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bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "USART7"
base ad:0x40098000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
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bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
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bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "USART8"
base ad:0x40099000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
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bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
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bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
newline
bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "USART9"
base ad:0x4009A000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
newline
bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
newline
bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
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bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
newline
bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
newline
bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
newline
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
newline
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
newline
rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
newline
rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
newline
bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
newline
bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
newline
bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
newline
bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
newline
bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
newline
bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
newline
bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
endif
sif (cpuis("LPC54606*"))
tree "USART0"
base ad:0x40086000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
newline
bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
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bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
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bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "USART1"
base ad:0x40087000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
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bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
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bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "USART2"
base ad:0x40088000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
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bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
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bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
newline
rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "USART3"
base ad:0x40089000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
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bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
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bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "USART4"
base ad:0x4008A000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
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bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
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bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "USART5"
base ad:0x40096000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
newline
bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
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bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
newline
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
newline
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
newline
rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
newline
bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
newline
bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
newline
bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
newline
bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
newline
hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "USART6"
base ad:0x40097000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
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bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
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bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "USART7"
base ad:0x40098000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
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bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
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bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "USART8"
base ad:0x40099000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
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bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
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bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "USART9"
base ad:0x4009A000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
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bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
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bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
endif
sif (cpuis("LPC54607*"))
tree "USART0"
base ad:0x40086000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
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bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
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bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "USART1"
base ad:0x40087000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
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bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
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bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
newline
bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "USART2"
base ad:0x40088000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
newline
bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
newline
bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
newline
bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
newline
bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
newline
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
newline
rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
newline
bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
newline
bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
newline
bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "USART3"
base ad:0x40089000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
newline
bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
newline
bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
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bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "USART4"
base ad:0x4008A000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
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bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
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bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "USART5"
base ad:0x40096000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
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bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
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bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "USART6"
base ad:0x40097000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
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bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
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bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "USART7"
base ad:0x40098000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
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bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
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bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "USART8"
base ad:0x40099000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
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bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
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bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "USART9"
base ad:0x4009A000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
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bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
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bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
endif
sif (cpuis("LPC54608*"))
tree "USART0"
base ad:0x40086000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
newline
bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
newline
bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
newline
bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
newline
bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "USART1"
base ad:0x40087000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
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bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
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bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
newline
bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
newline
rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "USART2"
base ad:0x40088000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
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bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
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bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "USART3"
base ad:0x40089000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
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bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
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bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
newline
bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "USART4"
base ad:0x4008A000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
newline
bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
newline
bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
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bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
newline
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
newline
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
newline
rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
newline
bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
newline
bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
newline
bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
newline
bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
newline
bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
newline
bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
newline
bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
newline
hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "USART5"
base ad:0x40096000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
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bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
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bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "USART6"
base ad:0x40097000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
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bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
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bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "USART7"
base ad:0x40098000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
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bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
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bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "USART8"
base ad:0x40099000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
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bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
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bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "USART9"
base ad:0x4009A000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
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bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
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bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
newline
bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
endif
sif (cpuis("LPC54616*"))
tree "USART0"
base ad:0x40086000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
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bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
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bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
newline
bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
newline
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
newline
rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
newline
rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
newline
bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
newline
bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "USART1"
base ad:0x40087000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
newline
bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
newline
bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
newline
bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
newline
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
newline
bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
newline
bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
newline
bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "USART2"
base ad:0x40088000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
newline
bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
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bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
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bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "USART3"
base ad:0x40089000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
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bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
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bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "USART4"
base ad:0x4008A000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
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bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
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bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "USART5"
base ad:0x40096000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
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bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
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bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "USART6"
base ad:0x40097000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
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bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
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bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "USART7"
base ad:0x40098000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
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bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
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bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "USART8"
base ad:0x40099000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
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bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
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bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "USART9"
base ad:0x4009A000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
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bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
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bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
newline
bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
newline
rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
newline
bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
newline
bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
newline
bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
newline
bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
newline
bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
newline
bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
newline
bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
newline
bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
newline
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
newline
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
newline
rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
newline
rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
newline
rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
newline
bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
newline
bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
newline
bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
newline
bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
newline
bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
newline
bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
newline
bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
newline
bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
newline
hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
endif
sif (cpuis("LPC54618*"))
tree "USART0"
base ad:0x40086000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
newline
bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
newline
bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
newline
bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
newline
bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
newline
bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
newline
bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
newline
bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
newline
bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
newline
bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
newline
bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
newline
bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
newline
bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
newline
rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
newline
bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
newline
rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
newline
bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
newline
bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
newline
bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
newline
bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "USART1"
base ad:0x40087000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
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bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
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bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "USART2"
base ad:0x40088000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
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bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
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bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "USART3"
base ad:0x40089000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
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bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
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bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "USART4"
base ad:0x4008A000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
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bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
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bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "USART5"
base ad:0x40096000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
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bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
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bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "USART6"
base ad:0x40097000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
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bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
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bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "USART7"
base ad:0x40098000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
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bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
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bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "USART8"
base ad:0x40099000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
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bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
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bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "USART9"
base ad:0x4009A000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
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bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
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bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
newline
bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
newline
hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
endif
sif (cpuis("LPC54628*"))
tree "USART0"
base ad:0x40086000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
newline
bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
newline
bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
newline
bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
newline
bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
newline
bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
newline
bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
newline
bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
newline
bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
newline
bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
newline
bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
newline
bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
newline
bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
newline
rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
newline
bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
newline
rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
newline
bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
newline
bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
newline
bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
newline
bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
newline
bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
newline
bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
newline
bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
newline
bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
newline
bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
newline
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
newline
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
newline
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
newline
bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
newline
rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
newline
rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
newline
rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
newline
bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
newline
bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
newline
bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
newline
bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
newline
bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
newline
bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
newline
bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
newline
bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
newline
hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "USART1"
base ad:0x40087000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
newline
bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
newline
bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
newline
bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
newline
bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
newline
bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
newline
bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
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bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "USART2"
base ad:0x40088000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
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bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
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bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "USART3"
base ad:0x40089000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
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bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
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bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "USART4"
base ad:0x4008A000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
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bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
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bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "USART5"
base ad:0x40096000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
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bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
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bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "USART6"
base ad:0x40097000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
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bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
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bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "USART7"
base ad:0x40098000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
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bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
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bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "USART8"
base ad:0x40099000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
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bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
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bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
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rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
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bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
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bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
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bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
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bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
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bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
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bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
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bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
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bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
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rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
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rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
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rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
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bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
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bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
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bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
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bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
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bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
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bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
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bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
tree "USART9"
base ad:0x4009A000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration register. Basic USART configuration settings that typically are not changed during operation."
bitfld.long 0x0 23. "TXPOL,Transmit data polarity." "0: Standard. The TX signal is sent out without..,1: Inverted. The TX signal is inverted by the USART.."
bitfld.long 0x0 22. "RXPOL,Receive data polarity." "0: Standard. The RX signal is used as it arrives..,1: Inverted. The RX signal is inverted before being.."
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bitfld.long 0x0 21. "OEPOL,Output Enable Polarity." "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
bitfld.long 0x0 20. "OESEL,Output Enable Select." "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal configured to provide an.."
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bitfld.long 0x0 19. "AUTOADDR,Automatic Address matching enable." "0: Disabled. When addressing is enabled by ADDRDET..,1: Enabled. When addressing is enabled by ADDRDET.."
bitfld.long 0x0 18. "OETA,Output Enable Turnaround time enable for RS-485 operation." "0: Disabled. If selected by OESEL the Output Enable..,1: Enabled. If selected by OESEL the Output Enable.."
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bitfld.long 0x0 15. "LOOP,Selects data loopback mode." "0: Normal operation.,1: Loopback mode. This provides a mechanism to.."
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master select." "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
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bitfld.long 0x0 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode." "0: Falling edge. Un_RXD is sampled on the falling..,1: Rising edge. Un_RXD is sampled on the rising.."
bitfld.long 0x0 11. "SYNCEN,Selects synchronous or asynchronous operation." "0: Asynchronous mode.,1: Synchronous mode."
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bitfld.long 0x0 9. "CTSEN,CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin  or from the USART's own RTS if loopback mode is enabled." "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
bitfld.long 0x0 8. "LINMODE,LIN break mode enable." "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
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bitfld.long 0x0 7. "MODE32K,Selects standard or 32 kHz clocking mode." "0: Disabled. USART uses standard clocking.,1: Enabled. USART uses the 32 kHz clock from the.."
bitfld.long 0x0 6. "STOPLEN,Number of stop bits appended to transmitted data. Only a single stop bit is required for received data." "0: 1 stop bit.,1: 2 stop bits. This setting should only be used.."
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bitfld.long 0x0 4.--5. "PARITYSEL,Selects what type of parity is used by the USART." "0: No parity.,?,2: Even parity. Adds a bit to each character such..,3: Odd parity. Adds a bit to each character such.."
bitfld.long 0x0 2.--3. "DATALEN,Selects the data size for the USART." "0: 7 bit Data length.,1: 8 bit Data length.,2: 9 bit data length. The 9th bit is commonly used..,?"
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bitfld.long 0x0 0. "ENABLE,USART Enable." "0: Disabled. The USART is disabled and the internal..,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control register. USART control settings that are more likely to change during operation."
bitfld.long 0x4 16. "AUTOBAUD,Autobaud enable." "0: Disabled. USART is in normal operating mode.,1: Enabled. USART is in autobaud mode. This bit.."
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock." "0: No effect. No effect on the CC bit.,1: Auto-clear. The CC bit is automatically cleared.."
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bitfld.long 0x4 8. "CC,Continuous Clock generation. By default  SCLK is only output while data is being transmitted in synchronous mode." "0: Clock on character. In synchronous mode SCLK..,1: Continuous clock. SCLK runs continuously in.."
bitfld.long 0x4 6. "TXDIS,Transmit Disable." "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
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bitfld.long 0x4 2. "ADDRDET,Enable address detect mode." "0: Disabled. The USART presents all incoming data.,1: Enabled. The USART receiver ignores incoming.."
bitfld.long 0x4 1. "TXBRKEN,Break Enable." "0: Normal operation.,1: Continuous break. Continuous break is sent.."
line.long 0x8 "STAT,USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them."
bitfld.long 0x8 16. "ABERR,Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured  essentially an auto baud time-out." "0,1"
bitfld.long 0x8 15. "RXNOISEINT,Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit  except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a.." "0,1"
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bitfld.long 0x8 14. "PARITYERRINT,Parity Error interrupt flag. This flag is set when a parity error is detected in a received character." "0,1"
bitfld.long 0x8 13. "FRAMERRINT,Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." "0,1"
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bitfld.long 0x8 12. "START,This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." "0,1"
bitfld.long 0x8 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs. Cleared by software." "0,1"
newline
rbitfld.long 0x8 10. "RXBRK,Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the.." "0,1"
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status flag. When 1  this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1)." "0,1"
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bitfld.long 0x8 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." "0,1"
rbitfld.long 0x8 4. "CTS,This bit reflects the current state of the CTS signal  regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." "0,1"
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rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle. When 0  indicates that the transmitter is currently in the process of sending data.When 1  indicate that the transmitter is not currently in the process of sending data." "0,1"
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle. When 0  indicates that the receiver is currently in the process of receiving data. When 1  indicates that the receiver is not currently in the process of receiving data." "0,1"
line.long 0xC "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes.."
bitfld.long 0xC 16. "ABERREN,When 1  enables an interrupt when an auto baud error occurs." "0,1"
bitfld.long 0xC 15. "RXNOISEEN,When 1  enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354." "0,1"
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bitfld.long 0xC 14. "PARITYERREN,When 1  enables an interrupt when a parity error has been detected." "0,1"
bitfld.long 0xC 13. "FRAMERREN,When 1  enables an interrupt when a framing error has been detected." "0,1"
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bitfld.long 0xC 12. "STARTEN,When 1  enables an interrupt when a received start bit has been detected." "0,1"
bitfld.long 0xC 11. "DELTARXBRKEN,When 1  enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." "0,1"
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bitfld.long 0xC 6. "TXDISEN,When 1  enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." "0,1"
bitfld.long 0xC 5. "DELTACTSEN,When 1  enables an interrupt when there is a change in the state of the CTS input." "0,1"
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bitfld.long 0xC 3. "TXIDLEEN,When 1  enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." "0,1"
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared."
bitfld.long 0x0 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
bitfld.long 0x0 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
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bitfld.long 0x0 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register." "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator register. 16-bit integer baud rate divisor value."
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate  based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided.."
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt status register. Reflects interrupts that are currently enabled."
bitfld.long 0x0 16. "ABERRINT,Auto baud Error Interrupt flag." "0,1"
bitfld.long 0x0 15. "RXNOISEINT,Received Noise interrupt flag." "0,1"
newline
bitfld.long 0x0 14. "PARITYERRINT,Parity Error interrupt flag." "0,1"
bitfld.long 0x0 13. "FRAMERRINT,Framing Error interrupt flag." "0,1"
newline
bitfld.long 0x0 12. "START,This bit is set when a start is detected on the receiver input." "0,1"
bitfld.long 0x0 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs." "0,1"
newline
bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt flag." "0,1"
bitfld.long 0x0 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected." "0,1"
newline
bitfld.long 0x0 3. "TXIDLE,Transmitter Idle status." "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample selection register for asynchronous communication."
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and.."
line.long 0x4 "ADDR,Address register for automatic address matching."
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO configuration and enable register."
bitfld.long 0x0 18. "POPDBG,Pop FIFO for debug reads." "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit  the RX FIFO is emptied." "0,1"
newline
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit  the TX FIFO is emptied." "0,1"
bitfld.long 0x0 15. "WAKERX,Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
newline
bitfld.long 0x0 14. "WAKETX,Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down  as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up  processes data .." "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x0 13. "DMARX,DMA configuration for receive." "0: DMA is not used for the receive function.,1: Trigger DMA for the receive function if the FIFO.."
newline
bitfld.long 0x0 12. "DMATX,DMA configuration for transmit." "0: DMA is not used for the transmit function.,1: Trigger DMA for the transmit function if the.."
rbitfld.long 0x0 4.--5. "SIZE,FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1  0x2  0x3 = not applicable to USART." "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
newline
bitfld.long 0x0 1. "ENABLERX,Enable the receive FIFO." "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
bitfld.long 0x0 0. "ENABLETX,Enable the transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO status register."
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO current level. A 0 means the RX FIFO is currently empty  and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full  the RXFULL.."
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO current level. A 0 means the TX FIFO is currently empty  and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full  the TXEMPTY.."
newline
rbitfld.long 0x4 7. "RXFULL,Receive FIFO full. When 1  the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow." "0,1"
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO not empty. When 1  the receive FIFO is not empty  so data can be read. When 0  the receive FIFO is empty." "0,1"
newline
rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO not full. When 1  the transmit FIFO is not full  so more data can be written. When 0  the transmit FIFO is full and another write would cause it to overflow." "0,1"
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO empty. When 1  the transmit FIFO is empty. The peripheral may still be processing the last piece of data." "0,1"
newline
rbitfld.long 0x4 3. "PERINT,Peripheral interrupt. When 1  this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register." "0,1"
bitfld.long 0x4 1. "RXERR,RX FIFO error. Will be set if a receive FIFO overflow occurs  caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit." "0,1"
newline
bitfld.long 0x4 0. "TXERR,TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO  or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit." "0,1"
line.long 0x8 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request."
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to.."
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so  the FIFO level can wake up the device just enough to perform DMA  then return to the reduced power mode. See Hardware Wake-up control register. 0 =.."
newline
bitfld.long 0x8 1. "RXLVLENA,Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMARX in FIFOCFG is set." "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET  or a DMA trigger if DMATX in FIFOCFG is set." "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register."
bitfld.long 0x0 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the RX..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x0 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register." "0: No interrupt will be generated based on the TX..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
newline
bitfld.long 0x0 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs  based on the RXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x0 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs  based on the TXERR flag in the FIFOSTAT register." "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register."
bitfld.long 0x4 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
newline
bitfld.long 0x4 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
bitfld.long 0x4 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register." "0,1"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO interrupt status register."
bitfld.long 0x0 4. "PERINT,Peripheral interrupt." "0,1"
bitfld.long 0x0 3. "RXLVL,Receive FIFO level interrupt." "0,1"
newline
bitfld.long 0x0 2. "TXLVL,Transmit FIFO level interrupt." "0,1"
bitfld.long 0x0 1. "RXERR,RX FIFO error." "0,1"
newline
bitfld.long 0x0 0. "TXERR,TX FIFO error." "0,1"
group.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO write data."
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO."
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO read data."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
newline
bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO data read with no FIFO pop."
bitfld.long 0x0 15. "RXNOISE,Received Noise flag. See description of the RxNoiseInt bit in Table 354." "0,1"
bitfld.long 0x0 14. "PARITYERR,Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character." "0,1"
newline
bitfld.long 0x0 13. "FRAMERR,Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO  and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate.." "0,1"
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings."
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral identification register."
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function."
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation."
newline
hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation."
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1  so 0x00 means a 4K aperture."
tree.end
endif
tree.end
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54113*")||cpuis("LPC54114*")||cpuis("LPC54605*")||cpuis("LPC54606*")||cpuis("LPC54607*")||cpuis("LPC54608*")||cpuis("LPC54616*")||cpuis("LPC54618*")||cpuis("LPC54628*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
tree "USB (Universal Serial Bus)"
base ad:0x40084000
group.long 0x0++0x2B
line.long 0x0 "DEVCMDSTAT,USB Device Command/Status register"
rbitfld.long 0x0 28. "VBUSDEBOUNCED,This bit indicates if Vbus is detected or not. The bit raises immediately when Vbus becomes high. It drops to zero if Vbus is low for at least 3 ms. If this bit is high and the DCon bit is set  the HW will enable the pull-up resistor to.." "0,1"
bitfld.long 0x0 26. "DRES_C,Device status - reset change. This bit is set when the device received a bus reset. On a bus reset the device will automatically go to the default state (unconfigured and responding to address 0). The bit is reset by writing a one to it." "0,1"
newline
bitfld.long 0x0 25. "DSUS_C,Device status - suspend change. The suspend change bit is set to 1 when the suspend bit toggles. The suspend bit can toggle because: - The device goes in the suspended state - The device is disconnected - The device receives resume signaling on.." "0,1"
bitfld.long 0x0 24. "DCON_C,Device status - connect change. The Connect Change bit is set when the device's pull-up resistor is disconnected because VBus disappeared. The bit is reset by writing a one to it." "0,1"
newline
rbitfld.long 0x0 20. "LPM_REWP,LPM Remote Wake-up Enabled by USB host. HW sets this bit to one when the bRemoteWake bit in the LPM extended token is set to 1. HW will reset this bit to 0 when it receives the host initiated LPM resume  when a remote wake-up is sent by the.." "0,1"
bitfld.long 0x0 19. "LPM_SUS,Device status - LPM Suspend. This bit represents the current LPM suspend state. It is set to 1 by HW when the device has acknowledged the LPM request from the USB host and the Token Retry Time of 10 ms has elapsed. When the device is in the LPM.." "0,1"
newline
bitfld.long 0x0 17. "DSUS,Device status - suspend. The suspend bit indicates the current suspend state. It is set to 1 when the device hasn't seen any activity on its upstream port for more than 3 milliseconds. It is reset to 0 on any activity. When the device is suspended.." "0,1"
bitfld.long 0x0 16. "DCON,Device status - connect. The connect bit must be set by SW to indicate that the device must signal a connect. The pull-up resistor on USB_DP will be enabled when this bit is set and the VBUSDEBOUNCED bit is one." "0,1"
newline
bitfld.long 0x0 15. "INTONNAK_CI,Interrupt on NAK for control IN EP" "0: Only acknowledged packets generate an interrupt,1: Both acknowledged and NAKed packets generate.."
bitfld.long 0x0 14. "INTONNAK_CO,Interrupt on NAK for control OUT EP" "0: Only acknowledged packets generate an interrupt,1: Both acknowledged and NAKed packets generate.."
newline
bitfld.long 0x0 13. "INTONNAK_AI,Interrupt on NAK for interrupt and bulk IN EP" "0: Only acknowledged packets generate an interrupt,1: Both acknowledged and NAKed packets generate.."
bitfld.long 0x0 12. "INTONNAK_AO,Interrupt on NAK for interrupt and bulk OUT EP" "0: Only acknowledged packets generate an interrupt,1: Both acknowledged and NAKed packets generate.."
newline
bitfld.long 0x0 11. "LPM_SUP,LPM Supported:" "0: LPM not supported.,1: LPM supported."
bitfld.long 0x0 9. "FORCE_NEEDCLK,Forces the NEEDCLK output to always be on:" "0: USB_NEEDCLK has normal function.,1: USB_NEEDCLK always 1. Clock will not be stopped.."
newline
bitfld.long 0x0 8. "SETUP,SETUP token received. If a SETUP token is received and acknowledged by the device  this bit is set. As long as this bit is set all received IN and OUT tokens will be NAKed by HW. SW must clear this bit by writing a one. If this bit is zero  HW will.." "0,1"
bitfld.long 0x0 7. "DEV_EN,USB device enable. If this bit is set  the HW will start responding on packets for function address DEV_ADDR." "0,1"
newline
hexmask.long.byte 0x0 0.--6. 1. "DEV_ADDR,USB device address. After bus reset  the address is reset to 0x00. If the enable bit is set  the device will respond on packets for function address DEV_ADDR. When receiving a SetAddress Control Request from the USB host  software must program.."
line.long 0x4 "INFO,USB Info register"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
hexmask.long.byte 0x4 24.--31. 1. "MAJREV,Major Revision."
hexmask.long.byte 0x4 16.--23. 1. "MINREV,Minor Revision."
newline
endif
sif (cpuis("LPC54605*"))
hexmask.long.byte 0x4 24.--31. 1. "MAJREV,Major Revision."
hexmask.long.byte 0x4 16.--23. 1. "MINREV,Minor Revision."
newline
endif
sif (cpuis("LPC54606*"))
hexmask.long.byte 0x4 24.--31. 1. "MAJREV,Major Revision."
hexmask.long.byte 0x4 16.--23. 1. "MINREV,Minor Revision."
newline
endif
sif (cpuis("LPC54607*"))
hexmask.long.byte 0x4 24.--31. 1. "MAJREV,Major Revision."
hexmask.long.byte 0x4 16.--23. 1. "MINREV,Minor Revision."
newline
endif
sif (cpuis("LPC54608*"))
hexmask.long.byte 0x4 24.--31. 1. "MAJREV,Major Revision."
hexmask.long.byte 0x4 16.--23. 1. "MINREV,Minor Revision."
newline
endif
sif (cpuis("LPC54616*"))
hexmask.long.byte 0x4 24.--31. 1. "MAJREV,Major Revision."
hexmask.long.byte 0x4 16.--23. 1. "MINREV,Minor Revision."
newline
endif
sif (cpuis("LPC54618*"))
hexmask.long.byte 0x4 24.--31. 1. "MAJREV,Major Revision."
hexmask.long.byte 0x4 16.--23. 1. "MINREV,Minor Revision."
newline
endif
sif (cpuis("LPC54628*"))
hexmask.long.byte 0x4 24.--31. 1. "MAJREV,Major Revision."
hexmask.long.byte 0x4 16.--23. 1. "MINREV,Minor Revision."
newline
endif
hexmask.long.byte 0x4 11.--14. 1. "ERR_CODE,The error code which last occurred:"
hexmask.long.word 0x4 0.--10. 1. "FRAME_NR,Frame number. This contains the frame number of the last successfully received SOF. In case no SOF was received by the device at the beginning of a frame  the frame number returned is that of the last successfully received SOF. In case the SOF.."
line.long 0x8 "EPLISTSTART,USB EP Command/Status List start address"
hexmask.long.tbyte 0x8 8.--31. 1. "EP_LIST,Start address of the USB EP Command/Status List."
line.long 0xC "DATABUFSTART,USB Data buffer start address"
hexmask.long.word 0xC 22.--31. 1. "DA_BUF,Start address of the buffer pointer page where all endpoint data buffers are located."
line.long 0x10 "LPM,USB Link Power Management register"
bitfld.long 0x10 8. "DATA_PENDING,As long as this bit is set to one and LPM supported bit is set to one  HW will return a NYET handshake on every LPM token it receives. If LPM supported bit is set to one and this bit is zero  HW will return an ACK handshake on every LPM.." "0,1"
hexmask.long.byte 0x10 4.--7. 1. "HIRD_SW,Host Initiated Resume Duration - SW. This is the time duration required by the USB device system to come out of LPM initiated suspend after receiving the host initiated LPM resume."
newline
hexmask.long.byte 0x10 0.--3. 1. "HIRD_HW,Host Initiated Resume Duration - HW. This is the HIRD value from the last received LPM token"
line.long 0x14 "EPSKIP,USB Endpoint skip"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
hexmask.long.word 0x14 0.--9. 1. "SKIP,Endpoint skip: Writing 1 to one of these bits  will indicate to HW that it must deactivate the buffer assigned to this endpoint and return control back to software. When HW has deactivated the endpoint  it will clear this bit  but it will not modify.."
endif
sif (cpuis("LPC54113*"))
hexmask.long 0x14 0.--29. 1. "SKIP,Endpoint skip: Writing 1 to one of these bits  will indicate to HW that it must deactivate the buffer assigned to this endpoint and return control back to software. When HW has deactivated the endpoint  it will clear this bit  but it will not modify.."
newline
endif
sif (cpuis("LPC54114*"))
hexmask.long 0x14 0.--29. 1. "SKIP,Endpoint skip: Writing 1 to one of these bits  will indicate to HW that it must deactivate the buffer assigned to this endpoint and return control back to software. When HW has deactivated the endpoint  it will clear this bit  but it will not modify.."
endif
sif (cpuis("LPC54605*"))
hexmask.long.word 0x14 0.--9. 1. "SKIP,Endpoint skip: Writing 1 to one of these bits  will indicate to HW that it must deactivate the buffer assigned to this endpoint and return control back to software. When HW has deactivated the endpoint  it will clear this bit  but it will not modify.."
newline
endif
sif (cpuis("LPC54606*"))
hexmask.long.word 0x14 0.--9. 1. "SKIP,Endpoint skip: Writing 1 to one of these bits  will indicate to HW that it must deactivate the buffer assigned to this endpoint and return control back to software. When HW has deactivated the endpoint  it will clear this bit  but it will not modify.."
endif
sif (cpuis("LPC54607*"))
hexmask.long.word 0x14 0.--9. 1. "SKIP,Endpoint skip: Writing 1 to one of these bits  will indicate to HW that it must deactivate the buffer assigned to this endpoint and return control back to software. When HW has deactivated the endpoint  it will clear this bit  but it will not modify.."
newline
endif
sif (cpuis("LPC54608*"))
hexmask.long.word 0x14 0.--9. 1. "SKIP,Endpoint skip: Writing 1 to one of these bits  will indicate to HW that it must deactivate the buffer assigned to this endpoint and return control back to software. When HW has deactivated the endpoint  it will clear this bit  but it will not modify.."
endif
sif (cpuis("LPC54616*"))
hexmask.long.word 0x14 0.--9. 1. "SKIP,Endpoint skip: Writing 1 to one of these bits  will indicate to HW that it must deactivate the buffer assigned to this endpoint and return control back to software. When HW has deactivated the endpoint  it will clear this bit  but it will not modify.."
newline
endif
sif (cpuis("LPC54618*"))
hexmask.long.word 0x14 0.--9. 1. "SKIP,Endpoint skip: Writing 1 to one of these bits  will indicate to HW that it must deactivate the buffer assigned to this endpoint and return control back to software. When HW has deactivated the endpoint  it will clear this bit  but it will not modify.."
endif
sif (cpuis("LPC54628*"))
hexmask.long.word 0x14 0.--9. 1. "SKIP,Endpoint skip: Writing 1 to one of these bits  will indicate to HW that it must deactivate the buffer assigned to this endpoint and return control back to software. When HW has deactivated the endpoint  it will clear this bit  but it will not modify.."
endif
line.long 0x18 "EPINUSE,USB Endpoint Buffer in use"
hexmask.long.byte 0x18 2.--9. 1. "BUF,Buffer in use: This register has one bit per physical endpoint. 0: HW is accessing buffer 0. 1: HW is accessing buffer 1."
line.long 0x1C "EPBUFCFG,USB Endpoint Buffer Configuration register"
hexmask.long.byte 0x1C 2.--9. 1. "BUF_SB,Buffer usage: This register has one bit per physical endpoint. 0: Single-buffer. 1: Double-buffer. If the bit is set to single-buffer (0)  it will not toggle the corresponding EPINUSE bit when it clears the active bit. If the bit is set to.."
line.long 0x20 "INTSTAT,USB interrupt status register"
bitfld.long 0x20 31. "DEV_INT,Device status interrupt. This bit is set by HW when one of the bits in the Device Status Change register are set. Software can clear this bit by writing a one to it." "0,1"
bitfld.long 0x20 30. "FRAME_INT,Frame interrupt. This bit is set to one every millisecond when the VbusDebounced bit and the DCON bit are set. This bit can be used by software when handling isochronous endpoints. Software can clear this bit by writing a one to it." "0,1"
newline
bitfld.long 0x20 9. "EP4IN,Interrupt status register bit for the EP4 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is.." "0,1"
bitfld.long 0x20 8. "EP4OUT,Interrupt status register bit for the EP4 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO.." "0,1"
newline
bitfld.long 0x20 7. "EP3IN,Interrupt status register bit for the EP3 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is.." "0,1"
bitfld.long 0x20 6. "EP3OUT,Interrupt status register bit for the EP3 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO.." "0,1"
newline
bitfld.long 0x20 5. "EP2IN,Interrupt status register bit for the EP2 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is.." "0,1"
bitfld.long 0x20 4. "EP2OUT,Interrupt status register bit for the EP2 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO.." "0,1"
newline
bitfld.long 0x20 3. "EP1IN,Interrupt status register bit for the EP1 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is.." "0,1"
bitfld.long 0x20 2. "EP1OUT,Interrupt status register bit for the EP1 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO.." "0,1"
newline
bitfld.long 0x20 1. "EP0IN,Interrupt status register bit for the Control EP0 IN direction. This bit will be set if NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_CI is set  this bit will also be set when a NAK is transmitted for the Control.." "0,1"
bitfld.long 0x20 0. "EP0OUT,Interrupt status register bit for the Control EP0 OUT direction. This bit will be set if NBytes transitions to zero or the skip bit is set by software or a SETUP packet is successfully received for the control EP0. If the IntOnNAK_CO is set  this.." "0,1"
line.long 0x24 "INTEN,USB interrupt enable register"
bitfld.long 0x24 31. "DEV_INT_EN,If this bit is set and the corresponding USB interrupt status bit is set  a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit." "0,1"
bitfld.long 0x24 30. "FRAME_INT_EN,If this bit is set and the corresponding USB interrupt status bit is set  a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit." "0,1"
newline
hexmask.long.word 0x24 0.--9. 1. "EP_INT_EN,If this bit is set and the corresponding USB interrupt status bit is set  a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit."
line.long 0x28 "INTSETSTAT,USB set interrupt status register"
bitfld.long 0x28 31. "DEV_SET_INT,If software writes a one to one of these bits  the corresponding USB interrupt status bit is set. When this register is read  the same value as the USB interrupt status register is returned." "0,1"
bitfld.long 0x28 30. "FRAME_SET_INT,If software writes a one to one of these bits  the corresponding USB interrupt status bit is set. When this register is read  the same value as the USB interrupt status register is returned." "0,1"
newline
hexmask.long.word 0x28 0.--9. 1. "EP_SET_INT,If software writes a one to one of these bits  the corresponding USB interrupt status bit is set. When this register is read  the same value as the USB interrupt status register is returned."
group.long 0x34++0x3
line.long 0x0 "EPTOGGLE,USB Endpoint toggle register"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
hexmask.long.word 0x0 0.--9. 1. "TOGGLE,Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint."
endif
sif (cpuis("LPC54113*"))
hexmask.long.word 0x0 0.--9. 1. "TOGGLE,Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint."
newline
endif
sif (cpuis("LPC54114*"))
hexmask.long.word 0x0 0.--9. 1. "TOGGLE,Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint."
endif
sif (cpuis("LPC54605*"))
hexmask.long.word 0x0 0.--9. 1. "TOGGLE,Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint."
newline
endif
sif (cpuis("LPC54606*"))
hexmask.long.word 0x0 0.--9. 1. "TOGGLE,Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint."
endif
sif (cpuis("LPC54607*"))
hexmask.long.word 0x0 0.--9. 1. "TOGGLE,Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint."
newline
endif
sif (cpuis("LPC54608*"))
hexmask.long.word 0x0 0.--9. 1. "TOGGLE,Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint."
endif
sif (cpuis("LPC54616*"))
hexmask.long.word 0x0 0.--9. 1. "TOGGLE,Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint."
newline
endif
sif (cpuis("LPC54618*"))
hexmask.long.word 0x0 0.--9. 1. "TOGGLE,Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint."
endif
sif (cpuis("LPC54628*"))
hexmask.long.word 0x0 0.--9. 1. "TOGGLE,Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint."
endif
sif (cpuis("LPC54113*"))
rgroup.long 0x34++0x3
line.long 0x0 "EPTOGGLE,USB Endpoint toggle register"
endif
sif (cpuis("LPC54114*"))
rgroup.long 0x34++0x3
line.long 0x0 "EPTOGGLE,USB Endpoint toggle register"
endif
tree.end
endif
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54605*")||cpuis("LPC54606*")||cpuis("LPC54607*")||cpuis("LPC54608*")||cpuis("LPC54616*")||cpuis("LPC54618*")||cpuis("LPC54628*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
tree "USBFSH (USB Full-speed Host Controller)"
base ad:0x400A2000
rgroup.long 0x0++0x3
line.long 0x0 "HCREVISION,BCD representation of the version of the HCI specification that is implemented by the Host Controller (HC)"
hexmask.long.byte 0x0 0.--7. 1. "REV,Revision."
group.long 0x4++0x53
line.long 0x0 "HCCONTROL,Defines the operating modes of the HC"
bitfld.long 0x0 10. "RWE,RemoteWakeupEnable This bit is used by HCD to enable or disable the remote wake-up feature upon the detection of upstream resume signaling." "0,1"
bitfld.long 0x0 9. "RWC,RemoteWakeupConnected This bit indicates whether HC supports remote wake-up signaling." "0,1"
bitfld.long 0x0 8. "IR,InterruptRouting This bit determines the routing of interrupts generated by events registered in HcInterruptStatus." "0,1"
bitfld.long 0x0 6.--7. "HCFS,HostControllerFunctionalState for USB 00b: USBRESET 01b: USBRESUME 10b: USBOPERATIONAL 11b: USBSUSPEND A transition to USBOPERATIONAL from another state causes SOFgeneration to begin 1 ms later." "0,1,2,3"
bitfld.long 0x0 5. "BLE,BulkListEnable This bit is set to enable the processing of the Bulk list in the next Frame." "0,1"
newline
bitfld.long 0x0 4. "CLE,ControlListEnable." "0,1"
bitfld.long 0x0 3. "IE,IsochronousEnable." "0,1"
bitfld.long 0x0 2. "PLE,PeriodicListEnable." "0,1"
bitfld.long 0x0 0.--1. "CBSR,ControlBulkServiceRatio." "0,1,2,3"
line.long 0x4 "HCCOMMANDSTATUS,This register is used to receive the commands from the Host Controller Driver (HCD)"
bitfld.long 0x4 6.--7. "SOC,SchedulingOverrunCount These bits are incremented on each scheduling overrun error." "0,1,2,3"
bitfld.long 0x4 3. "OCR,OwnershipChangeRequest This bit is set by an OS HCD to request a change of control of the HC." "0,1"
bitfld.long 0x4 2. "BLF,BulkListFilled This bit is used to indicate whether there are any TDs on the Bulk list." "0,1"
bitfld.long 0x4 1. "CLF,ControlListFilled This bit is used to indicate whether there are any TDs on the Control list." "0,1"
bitfld.long 0x4 0. "HCR,HostControllerReset This bit is set by HCD to initiate a software reset of HC." "0,1"
line.long 0x8 "HCINTERRUPTSTATUS,Indicates the status on various events that cause hardware interrupts by setting the appropriate bits"
hexmask.long.tbyte 0x8 10.--31. 1. "OC,OwnershipChange This bit is set by HC when HCD sets the OwnershipChangeRequest field in HcCommandStatus."
bitfld.long 0x8 6. "RHSC,RootHubStatusChange This bit is set when the content of HcRhStatus or the content of any of HcRhPortStatus[NumberofDownstreamPort] has changed." "0,1"
bitfld.long 0x8 5. "FNO,FrameNumberOverflow This bit is set when the MSb of HcFmNumber (bit 15) changes value  from 0 to 1 or from 1 to 0  and after HccaFrameNumber has been updated." "0,1"
bitfld.long 0x8 4. "UE,UnrecoverableError This bit is set when HC detects a system error not related to USB." "0,1"
bitfld.long 0x8 3. "RD,ResumeDetected This bit is set when HC detects that a device on the USB is asserting resume signaling." "0,1"
newline
bitfld.long 0x8 2. "SF,StartofFrame This bit is set by HC at each start of a frame and after the update of HccaFrameNumber." "0,1"
bitfld.long 0x8 1. "WDH,WritebackDoneHead This bit is set immediately after HC has written HcDoneHead to HccaDoneHead." "0,1"
bitfld.long 0x8 0. "SO,SchedulingOverrun This bit is set when the USB schedule for the current Frame overruns and after the update of HccaFrameNumber." "0,1"
line.long 0xC "HCINTERRUPTENABLE,Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt"
bitfld.long 0xC 31. "MIE,Master Interrupt Enable." "0,1"
bitfld.long 0xC 30. "OC,Ownership Change interrupt." "0,1"
bitfld.long 0xC 6. "RHSC,Root Hub Status Change interrupt." "0,1"
bitfld.long 0xC 5. "FNO,Frame Number Overflow interrupt." "0,1"
bitfld.long 0xC 4. "UE,Unrecoverable Error interrupt." "0,1"
newline
bitfld.long 0xC 3. "RD,Resume Detect interrupt." "0,1"
bitfld.long 0xC 2. "SF,Start of Frame interrupt." "0,1"
bitfld.long 0xC 1. "WDH,HcDoneHead Writeback interrupt." "0,1"
bitfld.long 0xC 0. "SO,Scheduling Overrun interrupt." "0,1"
line.long 0x10 "HCINTERRUPTDISABLE,The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt"
bitfld.long 0x10 31. "MIE,A 0 written to this field is ignored by HC." "0,1"
bitfld.long 0x10 30. "OC,Ownership Change interrupt." "0,1"
bitfld.long 0x10 6. "RHSC,Root Hub Status Change interrupt." "0,1"
bitfld.long 0x10 5. "FNO,Frame Number Overflow interrupt." "0,1"
bitfld.long 0x10 4. "UE,Unrecoverable Error interrupt." "0,1"
newline
bitfld.long 0x10 3. "RD,Resume Detect interrupt." "0,1"
bitfld.long 0x10 2. "SF,Start of Frame interrupt." "0,1"
bitfld.long 0x10 1. "WDH,HcDoneHead Writeback interrupt." "0,1"
bitfld.long 0x10 0. "SO,Scheduling Overrun interrupt." "0,1"
line.long 0x14 "HCHCCA,Contains the physical address of the host controller communication area"
hexmask.long.tbyte 0x14 8.--31. 1. "HCCA,Base address of the Host Controller Communication Area."
line.long 0x18 "HCPERIODCURRENTED,Contains the physical address of the current isochronous or interrupt endpoint descriptor"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
hexmask.long 0x18 4.--31. 1. "PCED,The content of this register is updated by HC after a periodic ED is processed."
endif
sif (cpuis("LPC54605*"))
hexmask.long 0x18 4.--31. 1. "PCED,The content of this register is updated by HC after a periodic ED is processed."
endif
sif (cpuis("LPC54606*"))
hexmask.long 0x18 4.--31. 1. "PCED,The content of this register is updated by HC after a periodic ED is processed."
endif
sif (cpuis("LPC54607*"))
hexmask.long 0x18 4.--31. 1. "PCED,The content of this register is updated by HC after a periodic ED is processed."
endif
sif (cpuis("LPC54608*"))
hexmask.long 0x18 4.--31. 1. "PCED,The content of this register is updated by HC after a periodic ED is processed."
newline
endif
sif (cpuis("LPC54616*"))
hexmask.long 0x18 4.--31. 1. "PCED,The content of this register is updated by HC after a periodic ED is processed."
endif
sif (cpuis("LPC54618*"))
hexmask.long 0x18 4.--31. 1. "PCED,The content of this register is updated by HC after a periodic ED is processed."
endif
sif (cpuis("LPC54628*"))
hexmask.long 0x18 4.--31. 1. "PCED,The content of this register is updated by HC after a periodic ED is processed."
endif
line.long 0x1C "HCCONTROLHEADED,Contains the physical address of the first endpoint descriptor of the control list"
hexmask.long 0x1C 4.--31. 1. "CHED,HC traverses the Control list starting with the HcControlHeadED pointer."
line.long 0x20 "HCCONTROLCURRENTED,Contains the physical address of the current endpoint descriptor of the control list"
hexmask.long 0x20 4.--31. 1. "CCED,ControlCurrentED."
line.long 0x24 "HCBULKHEADED,Contains the physical address of the first endpoint descriptor of the bulk list"
hexmask.long 0x24 4.--31. 1. "BHED,BulkHeadED HC traverses the bulk list starting with the HcBulkHeadED pointer."
line.long 0x28 "HCBULKCURRENTED,Contains the physical address of the current endpoint descriptor of the bulk list"
hexmask.long 0x28 4.--31. 1. "BCED,BulkCurrentED This is advanced to the next ED after the HC has served the current one."
line.long 0x2C "HCDONEHEAD,Contains the physical address of the last transfer descriptor added to the 'Done' queue"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
hexmask.long 0x2C 4.--31. 1. "DH,DoneHead When a TD is completed  HC writes the content of HcDoneHead to the NextTD field of the TD."
endif
sif (cpuis("LPC54605*"))
hexmask.long 0x2C 4.--31. 1. "DH,DoneHead When a TD is completed  HC writes the content of HcDoneHead to the NextTD field of the TD."
endif
sif (cpuis("LPC54606*"))
hexmask.long 0x2C 4.--31. 1. "DH,DoneHead When a TD is completed  HC writes the content of HcDoneHead to the NextTD field of the TD."
endif
sif (cpuis("LPC54607*"))
hexmask.long 0x2C 4.--31. 1. "DH,DoneHead When a TD is completed  HC writes the content of HcDoneHead to the NextTD field of the TD."
endif
sif (cpuis("LPC54608*"))
hexmask.long 0x2C 4.--31. 1. "DH,DoneHead When a TD is completed  HC writes the content of HcDoneHead to the NextTD field of the TD."
newline
endif
sif (cpuis("LPC54616*"))
hexmask.long 0x2C 4.--31. 1. "DH,DoneHead When a TD is completed  HC writes the content of HcDoneHead to the NextTD field of the TD."
endif
sif (cpuis("LPC54618*"))
hexmask.long 0x2C 4.--31. 1. "DH,DoneHead When a TD is completed  HC writes the content of HcDoneHead to the NextTD field of the TD."
endif
sif (cpuis("LPC54628*"))
hexmask.long 0x2C 4.--31. 1. "DH,DoneHead When a TD is completed  HC writes the content of HcDoneHead to the NextTD field of the TD."
endif
line.long 0x30 "HCFMINTERVAL,Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun"
bitfld.long 0x30 31. "FIT,FrameIntervalToggle HCD toggles this bit whenever it loads a new value to FrameInterval." "0,1"
hexmask.long.word 0x30 16.--30. 1. "FSMPS,FSLargestDataPacket This field specifies a value which is loaded into the Largest Data Packet Counter at the beginning of each frame."
hexmask.long.word 0x30 0.--13. 1. "FI,FrameInterval This specifies the interval between two consecutive SOFs in bit times."
line.long 0x34 "HCFMREMAINING,A 14-bit counter showing the bit time remaining in the current frame"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
rbitfld.long 0x34 31. "FRT,FrameRemainingToggle This bit is loaded from the FrameIntervalToggle field of HcFmInterval whenever FrameRemaining reaches 0." "0,1"
hexmask.long.word 0x34 0.--13. 1. "FR,FrameRemaining This counter is decremented at each bit time."
endif
sif (cpuis("LPC54605*"))
bitfld.long 0x34 31. "FRT,FrameRemainingToggle This bit is loaded from the FrameIntervalToggle field of HcFmInterval whenever FrameRemaining reaches 0." "0,1"
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x34 31. "FRT,FrameRemainingToggle This bit is loaded from the FrameIntervalToggle field of HcFmInterval whenever FrameRemaining reaches 0." "0,1"
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x34 31. "FRT,FrameRemainingToggle This bit is loaded from the FrameIntervalToggle field of HcFmInterval whenever FrameRemaining reaches 0." "0,1"
newline
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x34 31. "FRT,FrameRemainingToggle This bit is loaded from the FrameIntervalToggle field of HcFmInterval whenever FrameRemaining reaches 0." "0,1"
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x34 31. "FRT,FrameRemainingToggle This bit is loaded from the FrameIntervalToggle field of HcFmInterval whenever FrameRemaining reaches 0." "0,1"
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x34 31. "FRT,FrameRemainingToggle This bit is loaded from the FrameIntervalToggle field of HcFmInterval whenever FrameRemaining reaches 0." "0,1"
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x34 31. "FRT,FrameRemainingToggle This bit is loaded from the FrameIntervalToggle field of HcFmInterval whenever FrameRemaining reaches 0." "0,1"
endif
sif (cpuis("LPC54605*"))
hexmask.long.word 0x34 0.--13. 1. "FR,FrameRemaining This counter is decremented at each bit time."
newline
endif
sif (cpuis("LPC54606*"))
hexmask.long.word 0x34 0.--13. 1. "FR,FrameRemaining This counter is decremented at each bit time."
endif
sif (cpuis("LPC54607*"))
hexmask.long.word 0x34 0.--13. 1. "FR,FrameRemaining This counter is decremented at each bit time."
endif
sif (cpuis("LPC54608*"))
hexmask.long.word 0x34 0.--13. 1. "FR,FrameRemaining This counter is decremented at each bit time."
endif
sif (cpuis("LPC54616*"))
hexmask.long.word 0x34 0.--13. 1. "FR,FrameRemaining This counter is decremented at each bit time."
endif
sif (cpuis("LPC54618*"))
hexmask.long.word 0x34 0.--13. 1. "FR,FrameRemaining This counter is decremented at each bit time."
newline
endif
sif (cpuis("LPC54628*"))
hexmask.long.word 0x34 0.--13. 1. "FR,FrameRemaining This counter is decremented at each bit time."
endif
line.long 0x38 "HCFMNUMBER,Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
hexmask.long.word 0x38 0.--15. 1. "FN,FrameNumber This is incremented when HcFmRemaining is re-loaded."
endif
sif (cpuis("LPC54605*"))
hexmask.long.word 0x38 0.--15. 1. "FN,FrameNumber This is incremented when HcFmRemaining is re-loaded."
endif
sif (cpuis("LPC54606*"))
hexmask.long.word 0x38 0.--15. 1. "FN,FrameNumber This is incremented when HcFmRemaining is re-loaded."
endif
sif (cpuis("LPC54607*"))
hexmask.long.word 0x38 0.--15. 1. "FN,FrameNumber This is incremented when HcFmRemaining is re-loaded."
endif
sif (cpuis("LPC54608*"))
hexmask.long.word 0x38 0.--15. 1. "FN,FrameNumber This is incremented when HcFmRemaining is re-loaded."
newline
endif
sif (cpuis("LPC54616*"))
hexmask.long.word 0x38 0.--15. 1. "FN,FrameNumber This is incremented when HcFmRemaining is re-loaded."
endif
sif (cpuis("LPC54618*"))
hexmask.long.word 0x38 0.--15. 1. "FN,FrameNumber This is incremented when HcFmRemaining is re-loaded."
endif
sif (cpuis("LPC54628*"))
hexmask.long.word 0x38 0.--15. 1. "FN,FrameNumber This is incremented when HcFmRemaining is re-loaded."
endif
line.long 0x3C "HCPERIODICSTART,Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list"
hexmask.long.word 0x3C 0.--13. 1. "PS,PeriodicStart After a hardware reset  this field is cleared and then set by HCD during the HC initialization."
line.long 0x40 "HCLSTHRESHOLD,Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF"
hexmask.long.word 0x40 0.--11. 1. "LST,LSThreshold This field contains a value which is compared to the FrameRemaining field prior to initiating a Low Speed transaction."
line.long 0x44 "HCRHDESCRIPTORA,First of the two registers which describes the characteristics of the root hub"
hexmask.long.byte 0x44 24.--31. 1. "POTPGT,PowerOnToPowerGoodTime This byte specifies the duration the HCD has to wait before accessing a powered-on port of the root hub."
bitfld.long 0x44 12. "NOCP,NoOverCurrentProtection This bit describes how the overcurrent status for the root hub ports are reported." "0,1"
bitfld.long 0x44 11. "OCPM,OverCurrentProtectionMode This bit describes how the overcurrent status for the root hub ports are reported." "0,1"
bitfld.long 0x44 10. "DT,DeviceType This bit specifies that the root hub is not a compound device." "0,1"
bitfld.long 0x44 9. "NPS,NoPowerSwitching These bits are used to specify whether power switching is supported or port are always powered." "0,1"
newline
bitfld.long 0x44 8. "PSM,PowerSwitchingMode This bit is used to specify how the power switching of the root hub ports is controlled." "0,1"
hexmask.long.byte 0x44 0.--7. 1. "NDP,NumberDownstreamPorts These bits specify the number of downstream ports supported by the root hub."
line.long 0x48 "HCRHDESCRIPTORB,Second of the two registers which describes the characteristics of the Root Hub"
hexmask.long.word 0x48 16.--31. 1. "PPCM,PortPowerControlMask Each bit indicates if a port is affected by a global power control command when PowerSwitchingMode is set."
hexmask.long.word 0x48 0.--15. 1. "DR,DeviceRemovable Each bit is dedicated to a port of the Root Hub."
line.long 0x4C "HCRHSTATUS,This register is divided into two parts"
bitfld.long 0x4C 31. "CRWE,(write) ClearRemoteWakeupEnable Writing a 1 clears DeviceRemoveWakeupEnable." "0,1"
bitfld.long 0x4C 17. "OCIC,OverCurrentIndicatorChange This bit is set by hardware when a change has occurred to the OCI field of this register." "0,1"
bitfld.long 0x4C 16. "LPSC,(read) LocalPowerStatusChange The root hub does not support the local power status feature." "0,1"
bitfld.long 0x4C 15. "DRWE,(read) DeviceRemoteWakeupEnable This bit enables a ConnectStatusChange bit as a resume event  causing a USBSUSPEND to USBRESUME state transition and setting the ResumeDetected interrupt." "0,1"
bitfld.long 0x4C 1. "OCI,OverCurrentIndicator This bit reports overcurrent conditions when the global reporting is implemented." "0,1"
newline
bitfld.long 0x4C 0. "LPS,(read) LocalPowerStatus The Root Hub does not support the local power status feature; thus  this bit is always read as 0." "0,1"
line.long 0x50 "HCRHPORTSTATUS,Controls and reports the port events on a per-port basis"
bitfld.long 0x50 20. "PRSC,PortResetStatusChange This bit is set at the end of the 10 ms port reset signal." "0,1"
bitfld.long 0x50 19. "OCIC,PortOverCurrentIndicatorChange This bit is valid only if overcurrent conditions are reported on a per-port basis." "0,1"
bitfld.long 0x50 18. "PSSC,PortSuspendStatusChange This bit is set when the full resume sequence is completed." "0,1"
bitfld.long 0x50 17. "PESC,PortEnableStatusChange This bit is set when hardware events cause the PortEnableStatus bit to be cleared." "0,1"
bitfld.long 0x50 16. "CSC,ConnectStatusChange This bit is set whenever a connect or disconnect event occurs." "0,1"
newline
bitfld.long 0x50 9. "LSDA,(read) LowSpeedDeviceAttached This bit indicates the speed of the device attached to this port." "0,1"
bitfld.long 0x50 8. "PPS,(read) PortPowerStatus This bit reflects the porta's power status  regardless of the type of power switching implemented." "0,1"
bitfld.long 0x50 4. "PRS,(read) PortResetStatus When this bit is set by a write to SetPortReset  port reset signaling is asserted." "0,1"
bitfld.long 0x50 3. "POCI,(read) PortOverCurrentIndicator This bit is only valid when the Root Hub is configured in such a way that overcurrent conditions are reported on a per-port basis." "0,1"
bitfld.long 0x50 2. "PSS,(read) PortSuspendStatus This bit indicates the port is suspended or in the resume sequence." "0,1"
newline
bitfld.long 0x50 1. "PES,(read) PortEnableStatus This bit indicates whether the port is enabled or disabled." "0,1"
bitfld.long 0x50 0. "CCS,(read) CurrentConnectStatus This bit reflects the current state of the downstream port." "0,1"
group.long 0x5C++0x3
line.long 0x0 "PORTMODE,Controls the port if it is attached to the host block or the device block"
bitfld.long 0x0 16. "DEV_ENABLE,1: device 0: host." "0: host,1: device"
bitfld.long 0x0 8. "ID_EN,Port ID pin pull-up enable." "0,1"
bitfld.long 0x0 0. "ID,Port ID pin value." "0,1"
tree.end
tree "USBHSD (USB High-speed Device Controller)"
base ad:0x40094000
group.long 0x0++0x3
line.long 0x0 "DEVCMDSTAT,USB Device Command/Status register"
bitfld.long 0x0 29.--31. "PHY_TEST_MODE,This field is written by firmware to put the PHY into a test mode as defined by the USB2." "0,1,2,3,4,5,6,7"
rbitfld.long 0x0 28. "VBUS_DEBOUNCED,This bit indicates if VBUS is detected or not." "0,1"
bitfld.long 0x0 26. "DRES_C,Device status - reset change." "0,1"
bitfld.long 0x0 25. "DSUS_C,Device status - suspend change." "0,1"
newline
bitfld.long 0x0 24. "DCON_C,Device status - connect change." "0,1"
rbitfld.long 0x0 22.--23. "Speed,This field indicates the speed at which the device operates: 00b: reserved 01b: full-speed 10b: high-speed 11b: super-speed (reserved for future use)." "0,1,2,3"
rbitfld.long 0x0 20. "LPM_REWP,LPM Remote Wake-up Enabled by USB host." "0,1"
bitfld.long 0x0 19. "LPM_SUS,Device status - LPM Suspend." "0,1"
newline
bitfld.long 0x0 17. "DSUS,Device status - suspend." "0,1"
bitfld.long 0x0 16. "DCON,Device status - connect." "0,1"
bitfld.long 0x0 15. "INTONNAK_CI,Interrupt on NAK for control IN EP:." "0,1"
bitfld.long 0x0 14. "INTONNAK_CO,Interrupt on NAK for control OUT EP:." "0,1"
newline
bitfld.long 0x0 13. "INTONNAK_AI,Interrupt on NAK for interrupt and bulk IN EP:." "0,1"
bitfld.long 0x0 12. "INTONNAK_AO,Interrupt on NAK for interrupt and bulk OUT EP:." "0,1"
bitfld.long 0x0 11. "LPM_SUP,LPM Supported:." "0,1"
bitfld.long 0x0 10. "FORCE_VBUS,If this bit is set to 1  the VBUS voltage indicators from the PHY are overruled." "0,1"
newline
bitfld.long 0x0 9. "FORCE_NEEDCLK,Forces the NEEDCLK output to always be on:." "0,1"
bitfld.long 0x0 8. "SETUP,SETUP token received." "0,1"
bitfld.long 0x0 7. "DEV_EN,USB device enable." "0,1"
hexmask.long.byte 0x0 0.--6. 1. "DEV_ADDR,USB device address."
rgroup.long 0x4++0x3
line.long 0x0 "INFO,USB Info register"
hexmask.long.byte 0x0 24.--31. 1. "Majrev,Major revision."
hexmask.long.byte 0x0 16.--23. 1. "Minrev,Minor revision."
hexmask.long.byte 0x0 11.--14. 1. "ERR_CODE,The error code which last occurred:."
hexmask.long.word 0x0 0.--10. 1. "FRAME_NR,Frame number."
group.long 0x8++0x23
line.long 0x0 "EPLISTSTART,USB EP Command/Status List start address"
hexmask.long.word 0x0 20.--31. 1. "EP_LIST_FIXED,Fixed portion of USB EP Command/Status List address."
hexmask.long.word 0x0 8.--19. 1. "EP_LIST_PRG,Programmable portion of the USB EP Command/Status List address."
line.long 0x4 "DATABUFSTART,USB Data buffer start address"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
hexmask.long.word 0x4 18.--31. 1. "DA_BUF,Start address of the memory page where all endpoint data buffers are located."
endif
sif (cpuis("LPC54605*"))
hexmask.long 0x4 0.--31. 1. "DA_BUF,Start address of the memory page where all endpoint data buffers are located."
endif
sif (cpuis("LPC54606*"))
hexmask.long 0x4 0.--31. 1. "DA_BUF,Start address of the memory page where all endpoint data buffers are located."
endif
sif (cpuis("LPC54607*"))
hexmask.long 0x4 0.--31. 1. "DA_BUF,Start address of the memory page where all endpoint data buffers are located."
newline
endif
sif (cpuis("LPC54608*"))
hexmask.long 0x4 0.--31. 1. "DA_BUF,Start address of the memory page where all endpoint data buffers are located."
endif
sif (cpuis("LPC54616*"))
hexmask.long 0x4 0.--31. 1. "DA_BUF,Start address of the memory page where all endpoint data buffers are located."
endif
sif (cpuis("LPC54618*"))
hexmask.long 0x4 0.--31. 1. "DA_BUF,Start address of the memory page where all endpoint data buffers are located."
endif
sif (cpuis("LPC54628*"))
hexmask.long 0x4 0.--31. 1. "DA_BUF,Start address of the memory page where all endpoint data buffers are located."
endif
line.long 0x8 "LPM,USB Link Power Management register"
bitfld.long 0x8 8. "DATA_PENDING,As long as this bit is set to one and LPM supported bit is set to one  HW will return a NYET handshake on every LPM token it receives." "0,1"
hexmask.long.byte 0x8 4.--7. 1. "HIRD_SW,Host Initiated Resume Duration - SW."
hexmask.long.byte 0x8 0.--3. 1. "HIRD_HW,Host Initiated Resume Duration - HW."
line.long 0xC "EPSKIP,USB Endpoint skip"
hexmask.long.word 0xC 0.--11. 1. "SKIP,Endpoint skip: Writing 1 to one of these bits  will indicate to HW that it must deactivate the buffer assigned to this endpoint and return control back to software."
line.long 0x10 "EPINUSE,USB Endpoint Buffer in use"
hexmask.long.word 0x10 2.--11. 1. "BUF,Buffer in use: This register has one bit per physical endpoint."
line.long 0x14 "EPBUFCFG,USB Endpoint Buffer Configuration register"
hexmask.long.word 0x14 2.--11. 1. "BUF_SB,Buffer usage: This register has one bit per physical endpoint."
line.long 0x18 "INTSTAT,USB interrupt status register"
bitfld.long 0x18 31. "DEV_INT,Device status interrupt." "0,1"
bitfld.long 0x18 30. "FRAME_INT,Frame interrupt." "0,1"
bitfld.long 0x18 11. "EP5IN,Interrupt status register bit for the EP5 IN direction." "0,1"
bitfld.long 0x18 10. "EP5OUT,Interrupt status register bit for the EP5 OUT direction." "0,1"
newline
bitfld.long 0x18 9. "EP4IN,Interrupt status register bit for the EP4 IN direction." "0,1"
bitfld.long 0x18 8. "EP4OUT,Interrupt status register bit for the EP4 OUT direction." "0,1"
bitfld.long 0x18 7. "EP3IN,Interrupt status register bit for the EP3 IN direction." "0,1"
bitfld.long 0x18 6. "EP3OUT,Interrupt status register bit for the EP3 OUT direction." "0,1"
newline
bitfld.long 0x18 5. "EP2IN,Interrupt status register bit for the EP2 IN direction." "0,1"
bitfld.long 0x18 4. "EP2OUT,Interrupt status register bit for the EP2 OUT direction." "0,1"
bitfld.long 0x18 3. "EP1IN,Interrupt status register bit for the EP1 IN direction." "0,1"
bitfld.long 0x18 2. "EP1OUT,Interrupt status register bit for the EP1 OUT direction." "0,1"
newline
bitfld.long 0x18 1. "EP0IN,Interrupt status register bit for the Control EP0 IN direction." "0,1"
bitfld.long 0x18 0. "EP0OUT,Interrupt status register bit for the Control EP0 OUT direction." "0,1"
line.long 0x1C "INTEN,USB interrupt enable register"
bitfld.long 0x1C 31. "DEV_INT_EN,If this bit is set and the corresponding USB interrupt status bit is set  a HW interrupt is generated on the interrupt line." "0,1"
bitfld.long 0x1C 30. "FRAME_INT_EN,If this bit is set and the corresponding USB interrupt status bit is set  a HW interrupt is generated on the interrupt line." "0,1"
hexmask.long.word 0x1C 0.--11. 1. "EP_INT_EN,If this bit is set and the corresponding USB interrupt status bit is set  a HW interrupt is generated on the interrupt line."
line.long 0x20 "INTSETSTAT,USB set interrupt status register"
bitfld.long 0x20 31. "DEV_SET_INT,If software writes a one to one of these bits  the corresponding USB interrupt status bit is set." "0,1"
bitfld.long 0x20 30. "FRAME_SET_INT,If software writes a one to one of these bits  the corresponding USB interrupt status bit is set." "0,1"
hexmask.long.word 0x20 0.--11. 1. "EP_SET_INT,If software writes a one to one of these bits  the corresponding USB interrupt status bit is set."
rgroup.long 0x34++0x3
line.long 0x0 "EPTOGGLE,USB Endpoint toggle register"
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
hexmask.long 0x0 0.--29. 1. "TOGGLE,Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint."
endif
sif (cpuis("LPC54605*"))
hexmask.long 0x0 0.--29. 1. "TOGGLE,Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint."
endif
sif (cpuis("LPC54606*"))
hexmask.long 0x0 0.--29. 1. "TOGGLE,Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint."
endif
sif (cpuis("LPC54607*"))
hexmask.long 0x0 0.--29. 1. "TOGGLE,Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint."
newline
endif
sif (cpuis("LPC54608*"))
hexmask.long 0x0 0.--29. 1. "TOGGLE,Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint."
endif
sif (cpuis("LPC54616*"))
hexmask.long 0x0 0.--29. 1. "TOGGLE,Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint."
endif
sif (cpuis("LPC54618*"))
hexmask.long 0x0 0.--29. 1. "TOGGLE,Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint."
endif
sif (cpuis("LPC54628*"))
hexmask.long 0x0 0.--29. 1. "TOGGLE,Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint."
endif
sif (cpuis("LPC54605*"))
group.long 0x34++0x3
line.long 0x0 "EPTOGGLE,USB Endpoint toggle register"
group.long 0x3C++0x3
line.long 0x0 "ULPIDEBUG,UTMI/ULPI debug register"
bitfld.long 0x0 31. "PHY_MODE,This bit indicates if the interface between the controller is UTMI+ or ULPI." "0,1"
bitfld.long 0x0 25. "PHY_ACCESS,Software writes this bit to one to start a read or write operation." "0,1"
newline
bitfld.long 0x0 24. "PHY_RW,UTMI+ mode: Reserved." "0,1"
hexmask.long.byte 0x0 16.--23. 1. "PHY_RDATA,UTMI+ mode: Bits 7:0 contains the value returned by the VStatus signal on Vendor Interface of UTMI+."
newline
hexmask.long.byte 0x0 8.--15. 1. "PHY_WDATA,UTMI+ mode: Reserved."
hexmask.long.byte 0x0 0.--7. 1. "PHY_ADDR,ULPI mode: Bits 7:0 are used as the address when doing a register access over the ULPI interface."
endif
sif (cpuis("LPC54606*"))
group.long 0x34++0x3
line.long 0x0 "EPTOGGLE,USB Endpoint toggle register"
group.long 0x3C++0x3
line.long 0x0 "ULPIDEBUG,UTMI/ULPI debug register"
bitfld.long 0x0 31. "PHY_MODE,This bit indicates if the interface between the controller is UTMI+ or ULPI." "0,1"
bitfld.long 0x0 25. "PHY_ACCESS,Software writes this bit to one to start a read or write operation." "0,1"
newline
bitfld.long 0x0 24. "PHY_RW,UTMI+ mode: Reserved." "0,1"
hexmask.long.byte 0x0 16.--23. 1. "PHY_RDATA,UTMI+ mode: Bits 7:0 contains the value returned by the VStatus signal on Vendor Interface of UTMI+."
newline
hexmask.long.byte 0x0 8.--15. 1. "PHY_WDATA,UTMI+ mode: Reserved."
hexmask.long.byte 0x0 0.--7. 1. "PHY_ADDR,ULPI mode: Bits 7:0 are used as the address when doing a register access over the ULPI interface."
endif
sif (cpuis("LPC54607*"))
group.long 0x34++0x3
line.long 0x0 "EPTOGGLE,USB Endpoint toggle register"
group.long 0x3C++0x3
line.long 0x0 "ULPIDEBUG,UTMI/ULPI debug register"
bitfld.long 0x0 31. "PHY_MODE,This bit indicates if the interface between the controller is UTMI+ or ULPI." "0,1"
bitfld.long 0x0 25. "PHY_ACCESS,Software writes this bit to one to start a read or write operation." "0,1"
newline
bitfld.long 0x0 24. "PHY_RW,UTMI+ mode: Reserved." "0,1"
hexmask.long.byte 0x0 16.--23. 1. "PHY_RDATA,UTMI+ mode: Bits 7:0 contains the value returned by the VStatus signal on Vendor Interface of UTMI+."
newline
hexmask.long.byte 0x0 8.--15. 1. "PHY_WDATA,UTMI+ mode: Reserved."
hexmask.long.byte 0x0 0.--7. 1. "PHY_ADDR,ULPI mode: Bits 7:0 are used as the address when doing a register access over the ULPI interface."
endif
sif (cpuis("LPC54608*"))
group.long 0x34++0x3
line.long 0x0 "EPTOGGLE,USB Endpoint toggle register"
group.long 0x3C++0x3
line.long 0x0 "ULPIDEBUG,UTMI/ULPI debug register"
bitfld.long 0x0 31. "PHY_MODE,This bit indicates if the interface between the controller is UTMI+ or ULPI." "0,1"
bitfld.long 0x0 25. "PHY_ACCESS,Software writes this bit to one to start a read or write operation." "0,1"
newline
bitfld.long 0x0 24. "PHY_RW,UTMI+ mode: Reserved." "0,1"
hexmask.long.byte 0x0 16.--23. 1. "PHY_RDATA,UTMI+ mode: Bits 7:0 contains the value returned by the VStatus signal on Vendor Interface of UTMI+."
newline
hexmask.long.byte 0x0 8.--15. 1. "PHY_WDATA,UTMI+ mode: Reserved."
hexmask.long.byte 0x0 0.--7. 1. "PHY_ADDR,ULPI mode: Bits 7:0 are used as the address when doing a register access over the ULPI interface."
endif
sif (cpuis("LPC54616*"))
group.long 0x34++0x3
line.long 0x0 "EPTOGGLE,USB Endpoint toggle register"
group.long 0x3C++0x3
line.long 0x0 "ULPIDEBUG,UTMI/ULPI debug register"
bitfld.long 0x0 31. "PHY_MODE,This bit indicates if the interface between the controller is UTMI+ or ULPI." "0,1"
bitfld.long 0x0 25. "PHY_ACCESS,Software writes this bit to one to start a read or write operation." "0,1"
newline
bitfld.long 0x0 24. "PHY_RW,UTMI+ mode: Reserved." "0,1"
hexmask.long.byte 0x0 16.--23. 1. "PHY_RDATA,UTMI+ mode: Bits 7:0 contains the value returned by the VStatus signal on Vendor Interface of UTMI+."
newline
hexmask.long.byte 0x0 8.--15. 1. "PHY_WDATA,UTMI+ mode: Reserved."
hexmask.long.byte 0x0 0.--7. 1. "PHY_ADDR,ULPI mode: Bits 7:0 are used as the address when doing a register access over the ULPI interface."
endif
sif (cpuis("LPC54618*"))
group.long 0x34++0x3
line.long 0x0 "EPTOGGLE,USB Endpoint toggle register"
group.long 0x3C++0x3
line.long 0x0 "ULPIDEBUG,UTMI/ULPI debug register"
bitfld.long 0x0 31. "PHY_MODE,This bit indicates if the interface between the controller is UTMI+ or ULPI." "0,1"
bitfld.long 0x0 25. "PHY_ACCESS,Software writes this bit to one to start a read or write operation." "0,1"
newline
bitfld.long 0x0 24. "PHY_RW,UTMI+ mode: Reserved." "0,1"
hexmask.long.byte 0x0 16.--23. 1. "PHY_RDATA,UTMI+ mode: Bits 7:0 contains the value returned by the VStatus signal on Vendor Interface of UTMI+."
newline
hexmask.long.byte 0x0 8.--15. 1. "PHY_WDATA,UTMI+ mode: Reserved."
hexmask.long.byte 0x0 0.--7. 1. "PHY_ADDR,ULPI mode: Bits 7:0 are used as the address when doing a register access over the ULPI interface."
endif
sif (cpuis("LPC54628*"))
group.long 0x34++0x3
line.long 0x0 "EPTOGGLE,USB Endpoint toggle register"
group.long 0x3C++0x3
line.long 0x0 "ULPIDEBUG,UTMI/ULPI debug register"
bitfld.long 0x0 31. "PHY_MODE,This bit indicates if the interface between the controller is UTMI+ or ULPI." "0,1"
bitfld.long 0x0 25. "PHY_ACCESS,Software writes this bit to one to start a read or write operation." "0,1"
newline
bitfld.long 0x0 24. "PHY_RW,UTMI+ mode: Reserved." "0,1"
hexmask.long.byte 0x0 16.--23. 1. "PHY_RDATA,UTMI+ mode: Bits 7:0 contains the value returned by the VStatus signal on Vendor Interface of UTMI+."
newline
hexmask.long.byte 0x0 8.--15. 1. "PHY_WDATA,UTMI+ mode: Reserved."
hexmask.long.byte 0x0 0.--7. 1. "PHY_ADDR,ULPI mode: Bits 7:0 are used as the address when doing a register access over the ULPI interface."
endif
tree.end
tree "USBHSH (USB High-speed Host Controller)"
base ad:0x400A3000
rgroup.long 0x0++0xB
line.long 0x0 "CAPLENGTH_CHIPID,This register contains the offset value towards the start of the operational register space and the version number of the IP block"
hexmask.long.word 0x0 16.--31. 1. "CHIPID,Chip identification: indicates major and minor revision of the IP: [31:24] = Major revision [23:16] = Minor revision Major revisions used: 0x01: USB2."
hexmask.long.byte 0x0 0.--7. 1. "CAPLENGTH,Capability Length: This is used as an offset."
line.long 0x4 "HCSPARAMS,Host Controller Structural Parameters"
bitfld.long 0x4 16. "P_INDICATOR,This bit indicates whether the ports support port indicator control." "0,1"
bitfld.long 0x4 4. "PPC,This field indicates whether the host controller implementation includes port power control." "0,1"
hexmask.long.byte 0x4 0.--3. 1. "N_PORTS,This register specifies the number of physical downstream ports implemented on this host controller."
line.long 0x8 "HCCPARAMS,Host Controller Capability Parameters"
bitfld.long 0x8 17. "LPMC,Link Power Management Capability." "0,1"
group.long 0xC++0x3B
line.long 0x0 "FLADJ_FRINDEX,Frame Length Adjustment"
hexmask.long.word 0x0 16.--29. 1. "FRINDEX,Frame Index: Bits 29 to16 in this register are used for the frame number field in the SOF packet."
hexmask.long.byte 0x0 0.--5. 1. "FLADJ,Frame Length Timing Value."
line.long 0x4 "ATL_PTD_BASE_ADDR,Memory base address where ATL PTD0 is stored"
hexmask.long.tbyte 0x4 9.--31. 1. "ATL_BASE,Base address to be used by the hardware to find the start of the ATL list."
hexmask.long.byte 0x4 4.--8. 1. "ATL_CUR,This indicates the current PTD that is used by the hardware when it is processing the ATL list."
line.long 0x8 "ISO_PTD_BASE_ADDR,Memory base address where ISO PTD0 is stored"
hexmask.long.tbyte 0x8 10.--31. 1. "ISO_BASE,Base address to be used by the hardware to find the start of the ISO list."
hexmask.long.byte 0x8 5.--9. 1. "ISO_FIRST,This indicates the first PTD that is used by the hardware when it is processing the ISO list."
line.long 0xC "INT_PTD_BASE_ADDR,Memory base address where INT PTD0 is stored"
hexmask.long.tbyte 0xC 10.--31. 1. "INT_BASE,Base address to be used by the hardware to find the start of the INT list."
hexmask.long.byte 0xC 5.--9. 1. "INT_FIRST,This indicates the first PTD that is used by the hardware when it is processing the INT list."
line.long 0x10 "DATA_PAYLOAD_BASE_ADDR,Memory base address that indicates the start of the data payload buffers"
hexmask.long.word 0x10 16.--31. 1. "DAT_BASE,Base address to be used by the hardware to find the start of the data payload section."
line.long 0x14 "USBCMD,USB Command register"
sif (cpuis("LPC54605*"))
bitfld.long 0x14 28. "LPM_RWU,bRemoteWake field." "0,1"
endif
sif (cpuis("LPC54606*"))
bitfld.long 0x14 28. "LPM_RWU,bRemoteWake field." "0,1"
endif
sif (cpuis("LPC54607*"))
bitfld.long 0x14 28. "LPM_RWU,bRemoteWake field." "0,1"
endif
sif (cpuis("LPC54608*"))
bitfld.long 0x14 28. "LPM_RWU,bRemoteWake field." "0,1"
newline
endif
sif (cpuis("LPC54616*"))
bitfld.long 0x14 28. "LPM_RWU,bRemoteWake field." "0,1"
endif
sif (cpuis("LPC54618*"))
bitfld.long 0x14 28. "LPM_RWU,bRemoteWake field." "0,1"
endif
sif (cpuis("LPC54628*"))
bitfld.long 0x14 28. "LPM_RWU,bRemoteWake field." "0,1"
endif
hexmask.long.byte 0x14 24.--27. 1. "HIRD,Host-Initiated Resume Duration."
newline
bitfld.long 0x14 10. "INT_EN,INT List enabled." "0,1"
bitfld.long 0x14 9. "ISO_EN,ISO List enabled." "0,1"
bitfld.long 0x14 8. "ATL_EN,ATL List enabled." "0,1"
bitfld.long 0x14 7. "LHCR,Light Host Controller Reset: This bit allows the driver software to reset the host controller without affecting the state of the ports." "0,1"
newline
bitfld.long 0x14 2.--3. "FLS,Frame List Size: This field specifies the size of the frame list." "0,1,2,3"
bitfld.long 0x14 1. "HCRESET,Host Controller Reset: This control bit is used by the software to reset the host controller." "0,1"
bitfld.long 0x14 0. "RS,Run/Stop: 1b = Run." "0,1"
line.long 0x18 "USBSTS,USB Interrupt Status register"
bitfld.long 0x18 19. "SOF_IRQ,SOF interrupt: Every time when the host sends a Start of Frame token on the USB bus  this bit is set." "0,1"
bitfld.long 0x18 18. "INT_IRQ,INT IRQ: Indicates that an INT PTD (with I-bit set) was completed." "0,1"
bitfld.long 0x18 17. "ISO_IRQ,ISO IRQ: Indicates that an ISO PTD (with I-bit set) was completed." "0,1"
bitfld.long 0x18 16. "ATL_IRQ,ATL IRQ: Indicates that an ATL PTD (with I-bit set) was completed." "0,1"
newline
bitfld.long 0x18 3. "FLR,Frame List Rollover: The host controller sets this bit to logic 1 when the frame list index rolls over its maximum value to 0." "0,1"
bitfld.long 0x18 2. "PCD,Port Change Detect: The host controller sets this bit to logic 1 when any port has a change bit transition from a 0 to a one or a Force Port Resume bit transition from a 0 to a 1 as a result of a J-K transition detected on a suspended port." "0,1"
line.long 0x1C "USBINTR,USB Interrupt Enable register"
bitfld.long 0x1C 19. "SOF_E,SOF Interrupt Enable bit: 1: enable 0: disable." "0: disable,1: enable"
bitfld.long 0x1C 18. "INT_IRQ_E,INT IRQ Enable bit: 1: enable 0: disable." "0: disable,1: enable"
bitfld.long 0x1C 17. "ISO_IRQ_E,ISO IRQ Enable bit: 1: enable 0: disable." "0: disable,1: enable"
bitfld.long 0x1C 16. "ATL_IRQ_E,ATL IRQ Enable bit: 1: enable 0: disable." "0: disable,1: enable"
newline
bitfld.long 0x1C 3. "FLRE,Frame List Rollover Interrupt Enable: 1: enable 0: disable." "0: disable,1: enable"
bitfld.long 0x1C 2. "PCDE,Port Change Detect Interrupt Enable: 1: enable 0: disable." "0: disable,1: enable"
line.long 0x20 "PORTSC1,Port Status and Control register"
hexmask.long.byte 0x20 25.--31. 1. "DEV_ADD,Device Address for LPM tokens."
bitfld.long 0x20 23.--24. "SUS_STAT,These two bits are used by software to determine whether the most recent L1 suspend request was successful: 00b: Success-state transition was successful (ACK) 01b: Not Yet - Device was unable to enter the L1 state at this time (NYET) 10b: Not.." "0,1,2,3"
bitfld.long 0x20 22. "WOO,Wake on overcurrent enable: Writing this bit to a one enables the port to be sensitive to overcurrent conditions as wake-up events." "0,1"
bitfld.long 0x20 20.--21. "PSPD,Port Speed: 00b: Low-speed 01b: Full-speed 10b: High-speed 11b: Reserved." "0,1,2,3"
newline
hexmask.long.byte 0x20 16.--19. 1. "PTC,Port Test Control: A non-zero value indicates that the port is operating in the test mode as indicated by the value."
bitfld.long 0x20 14.--15. "PIC,Port Indicator Control : Writing to this field has no effect if the P_INDICATOR bit in the HCSPARAMS register is logic 0." "0,1,2,3"
bitfld.long 0x20 12. "PP,Port Power: The function of this bit depends on the value of the Port Power Control (PPC) bit in the HCSPARAMS register." "0,1"
rbitfld.long 0x20 10.--11. "LS,Line Status: This field reflects the current logical levels of the DP (bit 11) and DM (bit 10) signal lines." "0,1,2,3"
newline
bitfld.long 0x20 9. "SUS_L1,Suspend using L1 0b = Suspend using L2 1b = Suspend using L1 When this bit is set to a 1 and a non-zero value is specified in the Device Address field  the host controller will generate an LPM Token to enter the L1 state whenever software writes a.." "0,1"
bitfld.long 0x20 8. "PR,Port Reset: Logic 1 means the port is in the reset state." "0,1"
bitfld.long 0x20 7. "SUSP,Suspend: Logic 1 means port is in the suspend state." "0,1"
bitfld.long 0x20 6. "FPR,Force Port Resume: Logic 1 means resume (K-state) detected or driven on the port." "0,1"
newline
bitfld.long 0x20 5. "OCC,Over-current change: Logic 1 means that the value of OCA has changed." "0,1"
bitfld.long 0x20 4. "OCA,Over-current active: Logic 1 means that this port has an over-current condition." "0,1"
bitfld.long 0x20 3. "PEDC,Port Enabled/Disabled Change: Logic 1 means that the value of PED has changed." "0,1"
bitfld.long 0x20 2. "PED,Port Enabled/Disabled." "0,1"
newline
bitfld.long 0x20 1. "CSC,Connect Status Change: Logic 1 means that the value of CCS has changed." "0,1"
bitfld.long 0x20 0. "CCS,Current Connect Status: Logic 1 indicates a device is present on the port." "0,1"
line.long 0x24 "ATL_PTD_DONE_MAP,Done map for each ATL PTD"
hexmask.long 0x24 0.--31. 1. "ATL_DONE,The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed."
line.long 0x28 "ATL_PTD_SKIP_MAP,Skip map for each ATL PTD"
hexmask.long 0x28 0.--31. 1. "ATL_SKIP,When a bit in the PTD Skip Map is set to logic 1  the corresponding PTD will be skipped  independent of the V bit setting."
line.long 0x2C "ISO_PTD_DONE_MAP,Done map for each ISO PTD"
hexmask.long 0x2C 0.--31. 1. "ISO_DONE,The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed."
line.long 0x30 "ISO_PTD_SKIP_MAP,Skip map for each ISO PTD"
hexmask.long 0x30 0.--31. 1. "ISO_SKIP,The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed."
line.long 0x34 "INT_PTD_DONE_MAP,Done map for each INT PTD"
hexmask.long 0x34 0.--31. 1. "INT_DONE,The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed."
line.long 0x38 "INT_PTD_SKIP_MAP,Skip map for each INT PTD"
hexmask.long 0x38 0.--31. 1. "INT_SKIP,When a bit in the PTD Skip Map is set to logic 1  the corresponding PTD will be skipped  independent of the V bit setting."
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
group.long 0x48++0x3
line.long 0x0 "LASTPTD,Marks the last PTD in the list for ISO. INT and ATL"
hexmask.long.byte 0x0 16.--20. 1. "INT_LAST,This indicates the last PTD in the INT list."
hexmask.long.byte 0x0 8.--12. 1. "ISO_LAST,This indicates the last PTD in the ISO list."
newline
hexmask.long.byte 0x0 0.--4. 1. "ATL_LAST,If hardware has reached this PTD and the J bit is not set  it will go to PTD0 as the next PTD to be processed."
endif
sif (cpuis("LPC54605*"))
group.long 0x48++0x7
line.long 0x0 "LAST_PTD_INUSE,Marks the last PTD in the list for ISO. INT and ATL"
hexmask.long.byte 0x0 16.--20. 1. "INT_LAST,This indicates the last PTD in the INT list."
hexmask.long.byte 0x0 8.--12. 1. "ISO_LAST,This indicates the last PTD in the ISO list."
newline
hexmask.long.byte 0x0 0.--4. 1. "ATL_LAST,If hardware has reached this PTD and the J bit is not set  it will go to PTD0 as the next PTD to be processed."
line.long 0x4 "UTMIPLUS_ULPI_DEBUG,Register to read/write registers in the attached USB PHY"
bitfld.long 0x4 31. "PHY_MODE,This bit indicates if the interface between the controller is UTMI+ or ULPI 0b: UTMI+ 1b: ULPI If the hardware supports both modes  this bit is RW by SW." "0,1"
bitfld.long 0x4 25. "PHY_ACCESS,Software writes this bit to one to start a read or write operation." "0,1"
newline
bitfld.long 0x4 24. "PHY_RW,UTMI+ mode: Reserved." "0,1"
hexmask.long.byte 0x4 16.--23. 1. "PHY_RDATA,UTMI+ mode: Bits 7:0 contains the value returned by the VStatus signal on Vendor Interface of UTMI+ ULPI mode: Bits 7:0 are used for the read data when reading a value to a ULPI PHY register."
newline
hexmask.long.byte 0x4 8.--15. 1. "PHY_WDATA,UTMI+ mode: Reserved."
hexmask.long.byte 0x4 0.--7. 1. "PHY_ADDR,UTMI+ mode: Bits 3:0 are used to control VControl signal on Vendor Interface of UTMI+ ULPI mode: Bits 7:0 are used as the address when doing a register access over the ULPI interface."
endif
sif (cpuis("LPC54606*"))
group.long 0x48++0x7
line.long 0x0 "LAST_PTD_INUSE,Marks the last PTD in the list for ISO. INT and ATL"
hexmask.long.byte 0x0 16.--20. 1. "INT_LAST,This indicates the last PTD in the INT list."
hexmask.long.byte 0x0 8.--12. 1. "ISO_LAST,This indicates the last PTD in the ISO list."
newline
hexmask.long.byte 0x0 0.--4. 1. "ATL_LAST,If hardware has reached this PTD and the J bit is not set  it will go to PTD0 as the next PTD to be processed."
line.long 0x4 "UTMIPLUS_ULPI_DEBUG,Register to read/write registers in the attached USB PHY"
bitfld.long 0x4 31. "PHY_MODE,This bit indicates if the interface between the controller is UTMI+ or ULPI 0b: UTMI+ 1b: ULPI If the hardware supports both modes  this bit is RW by SW." "0,1"
bitfld.long 0x4 25. "PHY_ACCESS,Software writes this bit to one to start a read or write operation." "0,1"
newline
bitfld.long 0x4 24. "PHY_RW,UTMI+ mode: Reserved." "0,1"
hexmask.long.byte 0x4 16.--23. 1. "PHY_RDATA,UTMI+ mode: Bits 7:0 contains the value returned by the VStatus signal on Vendor Interface of UTMI+ ULPI mode: Bits 7:0 are used for the read data when reading a value to a ULPI PHY register."
newline
hexmask.long.byte 0x4 8.--15. 1. "PHY_WDATA,UTMI+ mode: Reserved."
hexmask.long.byte 0x4 0.--7. 1. "PHY_ADDR,UTMI+ mode: Bits 3:0 are used to control VControl signal on Vendor Interface of UTMI+ ULPI mode: Bits 7:0 are used as the address when doing a register access over the ULPI interface."
endif
sif (cpuis("LPC54607*"))
group.long 0x48++0x7
line.long 0x0 "LAST_PTD_INUSE,Marks the last PTD in the list for ISO. INT and ATL"
hexmask.long.byte 0x0 16.--20. 1. "INT_LAST,This indicates the last PTD in the INT list."
hexmask.long.byte 0x0 8.--12. 1. "ISO_LAST,This indicates the last PTD in the ISO list."
newline
hexmask.long.byte 0x0 0.--4. 1. "ATL_LAST,If hardware has reached this PTD and the J bit is not set  it will go to PTD0 as the next PTD to be processed."
line.long 0x4 "UTMIPLUS_ULPI_DEBUG,Register to read/write registers in the attached USB PHY"
bitfld.long 0x4 31. "PHY_MODE,This bit indicates if the interface between the controller is UTMI+ or ULPI 0b: UTMI+ 1b: ULPI If the hardware supports both modes  this bit is RW by SW." "0,1"
bitfld.long 0x4 25. "PHY_ACCESS,Software writes this bit to one to start a read or write operation." "0,1"
newline
bitfld.long 0x4 24. "PHY_RW,UTMI+ mode: Reserved." "0,1"
hexmask.long.byte 0x4 16.--23. 1. "PHY_RDATA,UTMI+ mode: Bits 7:0 contains the value returned by the VStatus signal on Vendor Interface of UTMI+ ULPI mode: Bits 7:0 are used for the read data when reading a value to a ULPI PHY register."
newline
hexmask.long.byte 0x4 8.--15. 1. "PHY_WDATA,UTMI+ mode: Reserved."
hexmask.long.byte 0x4 0.--7. 1. "PHY_ADDR,UTMI+ mode: Bits 3:0 are used to control VControl signal on Vendor Interface of UTMI+ ULPI mode: Bits 7:0 are used as the address when doing a register access over the ULPI interface."
endif
sif (cpuis("LPC54608*"))
group.long 0x48++0x7
line.long 0x0 "LAST_PTD_INUSE,Marks the last PTD in the list for ISO. INT and ATL"
hexmask.long.byte 0x0 16.--20. 1. "INT_LAST,This indicates the last PTD in the INT list."
hexmask.long.byte 0x0 8.--12. 1. "ISO_LAST,This indicates the last PTD in the ISO list."
newline
hexmask.long.byte 0x0 0.--4. 1. "ATL_LAST,If hardware has reached this PTD and the J bit is not set  it will go to PTD0 as the next PTD to be processed."
line.long 0x4 "UTMIPLUS_ULPI_DEBUG,Register to read/write registers in the attached USB PHY"
bitfld.long 0x4 31. "PHY_MODE,This bit indicates if the interface between the controller is UTMI+ or ULPI 0b: UTMI+ 1b: ULPI If the hardware supports both modes  this bit is RW by SW." "0,1"
bitfld.long 0x4 25. "PHY_ACCESS,Software writes this bit to one to start a read or write operation." "0,1"
newline
bitfld.long 0x4 24. "PHY_RW,UTMI+ mode: Reserved." "0,1"
hexmask.long.byte 0x4 16.--23. 1. "PHY_RDATA,UTMI+ mode: Bits 7:0 contains the value returned by the VStatus signal on Vendor Interface of UTMI+ ULPI mode: Bits 7:0 are used for the read data when reading a value to a ULPI PHY register."
newline
hexmask.long.byte 0x4 8.--15. 1. "PHY_WDATA,UTMI+ mode: Reserved."
hexmask.long.byte 0x4 0.--7. 1. "PHY_ADDR,UTMI+ mode: Bits 3:0 are used to control VControl signal on Vendor Interface of UTMI+ ULPI mode: Bits 7:0 are used as the address when doing a register access over the ULPI interface."
endif
sif (cpuis("LPC54616*"))
group.long 0x48++0x7
line.long 0x0 "LAST_PTD_INUSE,Marks the last PTD in the list for ISO. INT and ATL"
hexmask.long.byte 0x0 16.--20. 1. "INT_LAST,This indicates the last PTD in the INT list."
hexmask.long.byte 0x0 8.--12. 1. "ISO_LAST,This indicates the last PTD in the ISO list."
newline
hexmask.long.byte 0x0 0.--4. 1. "ATL_LAST,If hardware has reached this PTD and the J bit is not set  it will go to PTD0 as the next PTD to be processed."
line.long 0x4 "UTMIPLUS_ULPI_DEBUG,Register to read/write registers in the attached USB PHY"
bitfld.long 0x4 31. "PHY_MODE,This bit indicates if the interface between the controller is UTMI+ or ULPI 0b: UTMI+ 1b: ULPI If the hardware supports both modes  this bit is RW by SW." "0,1"
bitfld.long 0x4 25. "PHY_ACCESS,Software writes this bit to one to start a read or write operation." "0,1"
newline
bitfld.long 0x4 24. "PHY_RW,UTMI+ mode: Reserved." "0,1"
hexmask.long.byte 0x4 16.--23. 1. "PHY_RDATA,UTMI+ mode: Bits 7:0 contains the value returned by the VStatus signal on Vendor Interface of UTMI+ ULPI mode: Bits 7:0 are used for the read data when reading a value to a ULPI PHY register."
newline
hexmask.long.byte 0x4 8.--15. 1. "PHY_WDATA,UTMI+ mode: Reserved."
hexmask.long.byte 0x4 0.--7. 1. "PHY_ADDR,UTMI+ mode: Bits 3:0 are used to control VControl signal on Vendor Interface of UTMI+ ULPI mode: Bits 7:0 are used as the address when doing a register access over the ULPI interface."
endif
sif (cpuis("LPC54618*"))
group.long 0x48++0x7
line.long 0x0 "LAST_PTD_INUSE,Marks the last PTD in the list for ISO. INT and ATL"
hexmask.long.byte 0x0 16.--20. 1. "INT_LAST,This indicates the last PTD in the INT list."
hexmask.long.byte 0x0 8.--12. 1. "ISO_LAST,This indicates the last PTD in the ISO list."
newline
hexmask.long.byte 0x0 0.--4. 1. "ATL_LAST,If hardware has reached this PTD and the J bit is not set  it will go to PTD0 as the next PTD to be processed."
line.long 0x4 "UTMIPLUS_ULPI_DEBUG,Register to read/write registers in the attached USB PHY"
bitfld.long 0x4 31. "PHY_MODE,This bit indicates if the interface between the controller is UTMI+ or ULPI 0b: UTMI+ 1b: ULPI If the hardware supports both modes  this bit is RW by SW." "0,1"
bitfld.long 0x4 25. "PHY_ACCESS,Software writes this bit to one to start a read or write operation." "0,1"
newline
bitfld.long 0x4 24. "PHY_RW,UTMI+ mode: Reserved." "0,1"
hexmask.long.byte 0x4 16.--23. 1. "PHY_RDATA,UTMI+ mode: Bits 7:0 contains the value returned by the VStatus signal on Vendor Interface of UTMI+ ULPI mode: Bits 7:0 are used for the read data when reading a value to a ULPI PHY register."
newline
hexmask.long.byte 0x4 8.--15. 1. "PHY_WDATA,UTMI+ mode: Reserved."
hexmask.long.byte 0x4 0.--7. 1. "PHY_ADDR,UTMI+ mode: Bits 3:0 are used to control VControl signal on Vendor Interface of UTMI+ ULPI mode: Bits 7:0 are used as the address when doing a register access over the ULPI interface."
endif
sif (cpuis("LPC54628*"))
group.long 0x48++0x7
line.long 0x0 "LAST_PTD_INUSE,Marks the last PTD in the list for ISO. INT and ATL"
hexmask.long.byte 0x0 16.--20. 1. "INT_LAST,This indicates the last PTD in the INT list."
hexmask.long.byte 0x0 8.--12. 1. "ISO_LAST,This indicates the last PTD in the ISO list."
newline
hexmask.long.byte 0x0 0.--4. 1. "ATL_LAST,If hardware has reached this PTD and the J bit is not set  it will go to PTD0 as the next PTD to be processed."
line.long 0x4 "UTMIPLUS_ULPI_DEBUG,Register to read/write registers in the attached USB PHY"
bitfld.long 0x4 31. "PHY_MODE,This bit indicates if the interface between the controller is UTMI+ or ULPI 0b: UTMI+ 1b: ULPI If the hardware supports both modes  this bit is RW by SW." "0,1"
bitfld.long 0x4 25. "PHY_ACCESS,Software writes this bit to one to start a read or write operation." "0,1"
newline
bitfld.long 0x4 24. "PHY_RW,UTMI+ mode: Reserved." "0,1"
hexmask.long.byte 0x4 16.--23. 1. "PHY_RDATA,UTMI+ mode: Bits 7:0 contains the value returned by the VStatus signal on Vendor Interface of UTMI+ ULPI mode: Bits 7:0 are used for the read data when reading a value to a ULPI PHY register."
newline
hexmask.long.byte 0x4 8.--15. 1. "PHY_WDATA,UTMI+ mode: Reserved."
hexmask.long.byte 0x4 0.--7. 1. "PHY_ADDR,UTMI+ mode: Bits 3:0 are used to control VControl signal on Vendor Interface of UTMI+ ULPI mode: Bits 7:0 are used as the address when doing a register access over the ULPI interface."
endif
group.long 0x50++0x3
line.long 0x0 "PORTMODE,Controls the port if it is attached to the host block or the device block"
bitfld.long 0x0 19. "SW_PDCOM,This bit is only used when SW_CTRL_PDCOM is set to 1b." "0,1"
bitfld.long 0x0 18. "SW_CTRL_PDCOM,This bit indicates if the PHY power-down input is controlled by software or by hardware." "0,1"
bitfld.long 0x0 16. "DEV_ENABLE,If this bit is set to one  one of the ports will behave as a USB device." "0,1"
bitfld.long 0x0 8. "ID0_EN,Port 0 ID pin pull-up enable." "0,1"
newline
bitfld.long 0x0 0. "ID0,Port 0 ID pin value." "0,1"
tree.end
endif
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54113*")||cpuis("LPC54114*")||cpuis("LPC54605*")||cpuis("LPC54606*")||cpuis("LPC54607*")||cpuis("LPC54608*")||cpuis("LPC54616*")||cpuis("LPC54618*")||cpuis("LPC54628*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
base ad:0x4000E000
elif (cpuis("LPC54101*")||cpuis("LPC54102*"))
base ad:0x40020000
endif
tree "UTICK (Micro-tick Timer)"
group.long 0x0++0xB
line.long 0x0 "CTRL,Control register."
bitfld.long 0x0 31. "REPEAT,Repeat delay. 0 = One-time delay. 1 = Delay repeats continuously." "0: One-time delay,1: Delay repeats continuously"
hexmask.long 0x0 0.--30. 1. "DELAYVAL,Tick interval value. The delay will be equal to DELAYVAL + 1 periods of the timer clock. The minimum usable value is 1  for a delay of 2 timer clocks. A value of 0 stops the timer."
line.long 0x4 "STAT,Status register."
bitfld.long 0x4 1. "ACTIVE,Active flag. 0 = The Micro-Tick Timer is stopped. 1 = The Micro-Tick Timer is currently active." "0: The Micro-Tick Timer is stopped,1: The Micro-Tick Timer is currently active"
bitfld.long 0x4 0. "INTR,Interrupt flag. 0 = No interrupt is pending. 1 = An interrupt is pending. A write of any value to this register clears this flag." "0: No interrupt is pending,1: An interrupt is pending"
line.long 0x8 "CFG,Capture configuration register."
bitfld.long 0x8 11. "CAPPOL3,Capture Polarity 3. 0 = Positive edge capture  1 = Negative edge capture." "0: Positive edge capture,1: Negative edge capture"
bitfld.long 0x8 10. "CAPPOL2,Capture Polarity 2. 0 = Positive edge capture  1 = Negative edge capture." "0: Positive edge capture,1: Negative edge capture"
bitfld.long 0x8 9. "CAPPOL1,Capture Polarity 1. 0 = Positive edge capture  1 = Negative edge capture." "0: Positive edge capture,1: Negative edge capture"
newline
bitfld.long 0x8 8. "CAPPOL0,Capture Polarity 0. 0 = Positive edge capture  1 = Negative edge capture." "0: Positive edge capture,1: Negative edge capture"
bitfld.long 0x8 3. "CAPEN3,Enable Capture 3. 1 = Enabled  0 = Disabled." "0: Disabled,1: Enabled"
bitfld.long 0x8 2. "CAPEN2,Enable Capture 2. 1 = Enabled  0 = Disabled." "0: Disabled,1: Enabled"
newline
bitfld.long 0x8 1. "CAPEN1,Enable Capture 1. 1 = Enabled  0 = Disabled." "0: Disabled,1: Enabled"
bitfld.long 0x8 0. "CAPEN0,Enable Capture 0. 1 = Enabled  0 = Disabled." "0: Disabled,1: Enabled"
wgroup.long 0xC++0x3
line.long 0x0 "CAPCLR,Capture clear register."
bitfld.long 0x0 3. "CAPCLR3,Clear capture 3. Writing 1 to this bit clears the CAP3 register value." "0,1"
bitfld.long 0x0 2. "CAPCLR2,Clear capture 2. Writing 1 to this bit clears the CAP2 register value." "0,1"
bitfld.long 0x0 1. "CAPCLR1,Clear capture 1. Writing 1 to this bit clears the CAP1 register value." "0,1"
newline
bitfld.long 0x0 0. "CAPCLR0,Clear capture 0. Writing 1 to this bit clears the CAP0 register value." "0,1"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x10)++0x3
line.long 0x0 "CAP[$1],Capture register ."
bitfld.long 0x0 31. "VALID,Capture Valid. When 1  a value has been captured based on a transition of the related UTICK_CAPn pin. Cleared by writing to the related bit in the CAPCLR register." "0,1"
hexmask.long 0x0 0.--30. 1. "CAP_VALUE,Capture value for the related capture event (UTICK_CAPn. Note: the value is 1 lower than the actual value of the Micro-tick Timer at the moment of the capture event."
repeat.end
tree.end
sif (cpuis("LPC54101*")||cpuis("LPC54102*"))
tree "VFIFO (System FIFO for Serial Peripherals)"
base ad:0x1C038000
group.long 0x100++0x7
line.long 0x0 "FIFOCTLUSART,USART FIFO global control register. These registers are byte. halfword. and word addressable.The upper 16 bits of these registers provide information about the System FIFO configuration. and are specific to each device type."
hexmask.long.byte 0x0 24.--31. 1. "TXFIFOTOTAL,Reports the transmit FIFO space available for USARTs on this FIFO. The reset value is device specific."
hexmask.long.byte 0x0 16.--23. 1. "RXFIFOTOTAL,Reports the receive FIFO space available for USARTs on this FIFO. The reset value is device specific."
bitfld.long 0x0 10. "TXEMPTY,All USART transmit FIFOs are empty." "0,1"
bitfld.long 0x0 9. "TXPAUSED,All USART transmit FIFOs are paused." "0,1"
bitfld.long 0x0 8. "TXPAUSE,Pause all USARTs transmit FIFO operations. This can be used to prepare the System FIFO to reconfigure FIFO allocations among the USART transmitters." "0,1"
newline
bitfld.long 0x0 2. "RXEMPTY,All USART receive FIFOs are empty." "0,1"
bitfld.long 0x0 1. "RXPAUSED,All USART receive FIFOs are paused." "0,1"
bitfld.long 0x0 0. "RXPAUSE,Pause all USARTs receive FIFO operations. This can be used to prepare the System FIFO to reconfigure FIFO allocations among the USART receivers." "0,1"
line.long 0x4 "FIFOUPDATEUSART,USART FIFO global update register"
bitfld.long 0x4 19. "USART3TXUPDATESIZE,Writing 1 updates USART3 Tx FIFO size to match the USART3 TXSIZE. Must be done for all USARTs when any USART TXSIZE is changed." "0,1"
bitfld.long 0x4 18. "USART2TXUPDATESIZE,Writing 1 updates USART2 Tx FIFO size to match the USART2 TXSIZE. Must be done for all USARTs when any USART TXSIZE is changed." "0,1"
bitfld.long 0x4 17. "USART1TXUPDATESIZE,Writing 1 updates USART1 Tx FIFO size to match the USART1 TXSIZE. Must be done for all USARTs when any USART TXSIZE is changed." "0,1"
bitfld.long 0x4 16. "USART0TXUPDATESIZE,Writing 1 updates USART0 Tx FIFO size to match the USART0 TXSIZE. Must be done for all USARTs when any USART TXSIZE is changed." "0,1"
bitfld.long 0x4 3. "USART3RXUPDATESIZE,Writing 1 updates USART3 Rx FIFO size to match the USART3 RXSIZE. Must be done for all USARTs when any USART RXSIZE is changed." "0,1"
newline
bitfld.long 0x4 2. "USART2RXUPDATESIZE,Writing 1 updates USART2 Rx FIFO size to match the USART2 RXSIZE. Must be done for all USARTs when any USART RXSIZE is changed." "0,1"
bitfld.long 0x4 1. "USART1RXUPDATESIZE,Writing 1 updates USART1 Rx FIFO size to match the USART1 RXSIZE. Must be done for all USARTs when any USART RXSIZE is changed." "0,1"
bitfld.long 0x4 0. "USART0RXUPDATESIZE,Writing 1 updates USART0 Rx FIFO size to match the USART0 RXSIZE. Must be done for all USARTs when any USART RXSIZE is changed." "0,1"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x110)++0x3
line.long 0x0 "FIFOCFGUSART[$1],FIFO configuration register for USART0"
hexmask.long.byte 0x0 8.--15. 1. "TXSIZE,Configures the USART transmit FIFO size. A zero values provides no System FIFO service for the related USART transmitter."
hexmask.long.byte 0x0 0.--7. 1. "RXSIZE,Configures the USART receive FIFO size. A zero values provides no System FIFO service for the related USART receiver."
repeat.end
group.long 0x200++0x7
line.long 0x0 "FIFOCTLSPI,SPI FIFO global control register. These registers are byte. halfword. and word addressable. The upper 16 bits of these registers provide information about the System FIFO configuration. and are specific to each device type."
hexmask.long.byte 0x0 24.--31. 1. "TXFIFOTOTAL,Reports the transmit FIFO space available for SPIs on the System FIFO. The reset value is device specific."
hexmask.long.byte 0x0 16.--23. 1. "RXFIFOTOTAL,Reports the receive FIFO space available for SPIs on the System FIFO. The reset value is device specific."
bitfld.long 0x0 10. "TXEMPTY,All SPI transmit FIFOs are empty." "0,1"
bitfld.long 0x0 9. "TXPAUSED,All SPI transmit FIFOs are paused." "0,1"
bitfld.long 0x0 8. "TXPAUSE,Pause all SPIs transmit FIFO operations. This can be used to prepare the System FIFO to reconfigure FIFO allocations among the SPI transmitters." "0,1"
newline
bitfld.long 0x0 2. "RXEMPTY,All SPI receive FIFOs are empty." "0,1"
bitfld.long 0x0 1. "RXPAUSED,All SPI receive FIFOs are paused." "0,1"
bitfld.long 0x0 0. "RXPAUSE,Pause all SPIs receive FIFO operations. This can be used to prepare the System FIFO to reconfigure FIFO allocations among the SPI receivers." "0,1"
line.long 0x4 "FIFOUPDATESPI,SPI FIFO global update register"
bitfld.long 0x4 17. "SPI1TXUPDATESIZE,Writing 1 updates SPI1 Tx FIFO size to match the SPI1 TXSIZE. Must be done for all SPIs when any SPI TXSIZE is changed." "0,1"
bitfld.long 0x4 16. "SPI0TXUPDATESIZE,Writing 1 updates SPI0 Tx FIFO size to match the SPI0 TXSIZE. Must be done for all SPIs when any SPI TXSIZE is changed." "0,1"
bitfld.long 0x4 1. "SPI1RXUPDATESIZE,Writing 1 updates SPI1 Rx FIFO size to match the SPI1 RXSIZE. Must be done for all SPIs when any SPI RXSIZE is changed." "0,1"
bitfld.long 0x4 0. "SPI0RXUPDATESIZE,Writing 1 updates SPI0 Rx FIFO size to match the SPI0 RXSIZE. Must be done for all SPIs when any SPI RXSIZE is changed." "0,1"
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x210)++0x3
line.long 0x0 "FIFOCFGSPI[$1],FIFO configuration register for SPI0"
hexmask.long.byte 0x0 8.--15. 1. "TXSIZE,Configures the SPI transmit FIFO size. A zero values provides no System FIFO service for the related SPI transmitter."
hexmask.long.byte 0x0 0.--7. 1. "RXSIZE,Configures the SPI receive FIFO size. A zero values provides no System FIFO service for the related SPI receiver."
repeat.end
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x1C039000 ad:0x1C039100 ad:0x1C039200 ad:0x1C039300)
tree "USART[$1]"
base $2
group.long ($2)++0x1F
line.long 0x0 "CFGUSART,USART0 configuration"
hexmask.long.byte 0x0 24.--31. 1. "TXTHRESHOLD,Transmit FIFO Threshold. The System FIFO indicates that the threshold has been reached when the number of free entries in the transmit FIFO is less than or equal to this value. For example  when TxThreshold = 0  the threshold is exceeded when.."
hexmask.long.byte 0x0 16.--23. 1. "RXTHRESHOLD,Receive FIFO Threshold. The System FIFO indicates that the threshold has been reached when the number of entries in the receive FIFO is greater than this value. For example  when RxThreshold = 0  the threshold is exceeded when there is at.."
hexmask.long.byte 0x0 12.--15. 1. "TIMEOUTVALUE,Specifies the maximum time value for timeout at the timer position identified by TimeoutBase. Minimum time TimeoutValue - 1. is See Section 24.5.7.1 below. TimeoutValue should not be 0 or 1 when timeout is enabled."
hexmask.long.byte 0x0 8.--11. 1. "TIMEOUTBASE,Specifies the least significant timer bit to compare to TimeoutValue. See Section 24.5.7.1 below. Value can be 0 through 15."
bitfld.long 0x0 5. "TIMEOUTCONTONEMPTY,Timeout Continue On Empty. When 0  the timeout for the related peripheral is reset when the receive FIFO becomes empty. When 1  the timeout for the related peripheral is not reset when the receive FIFO becomes empty. This allows the.." "0,1"
bitfld.long 0x0 4. "TIMEOUTCONTONWRITE,Timeout Continue On Write. When 0  the timeout for the related peripheral is reset every time data is transferred from the peripheral into the receive FIFO. When 1  the timeout for the related peripheral is not reset every time data is.." "0,1"
line.long 0x4 "STATUSART,USART0 status"
hexmask.long.byte 0x4 24.--31. 1. "TXCOUNT,Transmit FIFO Count. Indicates how many entries may be written to the transmit FIFO. 0 = FIFO full. This is a read-only field that is valid only when the TxFIFO is fully configured and enabled."
hexmask.long.byte 0x4 16.--23. 1. "RXCOUNT,Receive FIFO Count. Indicates how many entries may be read from the receive FIFO. 0 = FIFO empty. This is a read-only field."
bitfld.long 0x4 9. "TXEMPTY,Transmit FIFO Empty. When 1  the transmit FIFO is currently empty. This is a read-only bit." "0,1"
bitfld.long 0x4 8. "RXEMPTY,Receive FIFO Empty. When 1  the receive FIFO is currently empty. This is a read-only bit." "0,1"
bitfld.long 0x4 7. "BUSERR,Bus Error. When 1  a bus error has occurred while processing data for USARTn. The bus error flag can be cleared by writing a 1 to this bit." "0,1"
bitfld.long 0x4 4. "RXTIMEOUT,Receive FIFO Timeout. When 1  the receive FIFO has timed out  based on the timeout configuration in the CFGUSART register. The timeout condition can be cleared by writing a 1 to this bit  by enabling or disabling the timeout interrupt  or by.." "0,1"
newline
bitfld.long 0x4 1. "TXTH,Transmit FIFO Threshold. When 1  the transmit FIFO threshold has been reached. This is a read-only bit." "0,1"
bitfld.long 0x4 0. "RXTH,Receive FIFO Threshold. When 1  the receive FIFO threshold has been reached. This is a read-only bit." "0,1"
line.long 0x8 "INTSTATUSART,USART0 interrupt status"
hexmask.long.byte 0x8 24.--31. 1. "TXCOUNT,Transmit FIFO Available. This is simply a copy of the same field in the STATUSART register  included here so an ISR can read all needed status information in one read."
hexmask.long.byte 0x8 16.--23. 1. "RXCOUNT,Receive FIFO Count. This is simply a copy of the same field in the STATUSART register  included here so an ISR can read all needed status information in one read."
bitfld.long 0x8 9. "TXEMPTY,Transmit FIFO Empty. This is simply a copy of the same bit in the STATUSART register." "0,1"
bitfld.long 0x8 8. "RXEMPTY,Receive FIFO Empty. This is simply a copy of the same bit in the STATUSART register." "0,1"
bitfld.long 0x8 7. "BUSERR,Bus Error. This is simply a copy of the same bit in the STATUSART register. The bus error interrupt is always enabled." "0,1"
bitfld.long 0x8 4. "RXTIMEOUT,Receive Timeout. When 1  the receive FIFO has timed out  based on the timeout configuration in the CFGUSART register  and the related interrupt is enabled." "0,1"
newline
bitfld.long 0x8 1. "TXTH,Transmit FIFO Threshold. When 1  the transmit FIFO threshold has been reached  and the related interrupt is enabled." "0,1"
bitfld.long 0x8 0. "RXTH,Receive FIFO Threshold. When 1  the receive FIFO threshold has been reached  and the related interrupt is enabled." "0,1"
line.long 0xC "CTLSETUSART,USART0 control read and set register. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 9. "TXFLUSH,Transmit FIFO flush. Writing a 1 to this bit forces the transmit FIFO to be empty." "0,1"
bitfld.long 0xC 8. "RXFLUSH,Receive FIFO flush. Writing a 1 to this bit forces the receive FIFO to be empty." "0,1"
bitfld.long 0xC 4. "RXTIMEOUTINTEN,Receive FIFO Timeout Interrupt Enable. When enabled  this also enables the timeout for this USART. Writing a 1 to this bit resets the USART timeout logic." "0,1"
bitfld.long 0xC 1. "TXTHINTEN,Transmit FIFO Threshold Interrupt Enable." "0,1"
bitfld.long 0xC 0. "RXTHINTEN,Receive FIFO Threshold Interrupt Enable." "0,1"
line.long 0x10 "CTLCLRUSART,USART0 control clear register. Writing a 1 to any implemented bit position causes the corresponding bit in the related CTLSET register to be cleared."
bitfld.long 0x10 9. "TXFLUSHCLR,Transmit FIFO flush clear." "0,1"
bitfld.long 0x10 8. "RXFLUSHCLR,Receive FIFO flush clear." "0,1"
bitfld.long 0x10 4. "RXTIMEOUTINTCLR,Receive FIFO Time-out Interrupt clear." "0,1"
bitfld.long 0x10 1. "TXTHINTCLR,Transmit FIFO Threshold Interrupt clear." "0,1"
bitfld.long 0x10 0. "RXTHINTCLR,Receive FIFO Threshold Interrupt clear." "0,1"
line.long 0x14 "RXDATUSART,USART0 received data"
hexmask.long.word 0x14 0.--8. 1. "RXDAT,The UART Receiver Data register contains the next received character. The number of bits that are relevant depends on the UART configuration settings."
line.long 0x18 "RXDATSTATUSART,USART0 received data with status"
bitfld.long 0x18 15. "RXNOISE,Received Noise flag." "0,1"
bitfld.long 0x18 14. "PARITYERR,Parity Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will be set when a parity error is detected in a received character." "0,1"
bitfld.long 0x18 13. "FRAMERR,Framing Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will set when the character in RXDAT was received with a missing stop bit at the expected.." "0,1"
hexmask.long.word 0x18 0.--8. 1. "RXDAT,The UART Receiver Data register contains the next received character. The number of bits that are relevant depends on the UART configuration settings."
line.long 0x1C "TXDATUSART,USART0 transmit data"
hexmask.long.word 0x1C 0.--8. 1. "TXDAT,Writing to the UART Transmit Data Register causes the data to be transmitted as soon as the transmit shift register is available and the condition for transmitting data is met: TXDIS bit = 0."
tree.end
repeat.end
repeat 2. (list 0x0 0x1)(list ad:0x1C03A000 ad:0x1C03A100)
tree "SPI[$1]"
base $2
group.long ($2)++0x1B
line.long 0x0 "CFGSPI,SPI0 configuration"
hexmask.long.byte 0x0 24.--31. 1. "TXTHRESHOLD,Transmit FIFO Threshold. The System FIFO indicates that the threshold has been reached when the number of free entries in the transmit FIFO is less than or equal to this value. For example  when TxThreshold = 0  the threshold is exceeded when.."
hexmask.long.byte 0x0 16.--23. 1. "RXTHRESHOLD,Receive FIFO Threshold. The System FIFO indicates that the threshold has been reached when the number of entries in the receive FIFO is greater than this value. For example  when RxThreshold = 0  the threshold is exceeded when there is at.."
newline
hexmask.long.byte 0x0 12.--15. 1. "TIMEOUTVALUE,Specifies the maximum time value for timeout at the timer position identified by TimeoutBase. Minimum time TimeoutValue - 1. TimeoutValue should not be 0 or 1 when timeout is enabled."
hexmask.long.byte 0x0 8.--11. 1. "TIMEOUTBASE,Specifies the least significant timer bit to compare to TimeoutValue. Value can be 0 through 15."
newline
bitfld.long 0x0 5. "TIMEOUTCONTONEMPTY,Timeout Continue On Empty. When 0  the timeout for the related peripheral is reset when the receive FIFO becomes empty. When 1  the timeout for the related peripheral is not reset when the receive FIFO becomes empty. This allows the.." "0,1"
bitfld.long 0x0 4. "TIMEOUTCONTONWRITE,Timeout Continue On Write. When 0  the timeout for the related peripheral is reset every time data is transferred from the peripheral into the receive FIFO. When 1  the timeout for the related peripheral is not reset every time data is.." "0,1"
line.long 0x4 "STATSPI,SPI0 status"
hexmask.long.byte 0x4 24.--31. 1. "TXCOUNT,Transmit FIFO Count. Indicates how many entries may be written to the transmit FIFO. 0 = FIFO full. This is a read-only field that is valid only when the TxFIFO is fully configured and enabled."
hexmask.long.byte 0x4 16.--23. 1. "RXCOUNT,Receive FIFO Count. Indicates how many entries may be read from the receive FIFO. 0 = FIFO empty. This is a read-only field."
newline
bitfld.long 0x4 9. "TXEMPTY,Transmit FIFO Empty. When 1  the transmit FIFO is currently empty. This is a read-only bit." "0,1"
bitfld.long 0x4 8. "RXEMPTY,Receive FIFO Empty. When 1  the receive FIFO is currently empty. This is a read-only bit." "0,1"
newline
bitfld.long 0x4 7. "BUSERR,Bus Error. When 1  a bus error has occurred while processing data for SPI. The bus error flag can be cleared by writing a 1 to this bit." "0,1"
bitfld.long 0x4 4. "RXTIMEOUT,Receive FIFO Timeout. When 1  the receive FIFO has timed out  based on the timeout configuration in the CFGSPI register. The timeout condition can be cleared by writing a 1 to this bit  by enabling or disabling the timeout interrupt  or by.." "0,1"
newline
bitfld.long 0x4 1. "TXTH,Transmit FIFO Threshold. When 1  the transmit FIFO threshold has been reached. This is a read-only bit." "0,1"
bitfld.long 0x4 0. "RXTH,Receive FIFO Threshold. When 1  the receive FIFO threshold has been reached. This is a read-only bit." "0,1"
line.long 0x8 "INTSTATSPI,SPI0 interrupt status"
hexmask.long.byte 0x8 24.--31. 1. "TXCOUNT,Transmit FIFO Available. This is simply a copy of the same field in the STATSPI register  included here so an ISR can read all needed status information in one read."
hexmask.long.byte 0x8 16.--23. 1. "RXCOUNT,Receive FIFO Count. This is simply a copy of the same field in the STATSPI register  included here so an ISR can read all needed status information in one read."
newline
bitfld.long 0x8 9. "TXEMPTY,Transmit FIFO Empty. This is simply a copy of the same bit in the STATSPI register." "0,1"
bitfld.long 0x8 8. "RXEMPTY,Receive FIFO Empty. This is simply a copy of the same bit in the STATSPI register." "0,1"
newline
bitfld.long 0x8 7. "BUSERR,Bus Error. This is simply a copy of the same bit in the STATSPI register. The bus error interrupt is always enabled." "0,1"
bitfld.long 0x8 4. "RXTIMEOUT,Receive Timeout. When 1  the receive FIFO has timed out  based on the timeout configuration in the CFGSPI register  and the related interrupt is enabled." "0,1"
newline
bitfld.long 0x8 1. "TXTH,Transmit FIFO Threshold. When 1  the transmit FIFO threshold has been reached  and the related interrupt is enabled." "0,1"
bitfld.long 0x8 0. "RXTH,Receive FIFO Threshold. When 1  the receive FIFO threshold has been reached  and the related interrupt is enabled." "0,1"
line.long 0xC "CTLSETSPI,SPI0 control read and set register. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."
bitfld.long 0xC 9. "TXFLUSH,Transmit FIFO flush. Writing a 1 to this bit forces the transmit FIFO to be empty." "0,1"
bitfld.long 0xC 8. "RXFLUSH,Receive FIFO flush. Writing a 1 to this bit forces the receive FIFO to be empty." "0,1"
newline
bitfld.long 0xC 4. "RXTIMEOUTINTEN,Receive FIFO Timeout Interrupt Enable. When enabled  this also enables the timeout for this SPI. Writing a 1 to this bit resets the SPI timeout logic." "0,1"
bitfld.long 0xC 1. "TXTHINTEN,Transmit FIFO Threshold Interrupt Enable." "0,1"
newline
bitfld.long 0xC 0. "RXTHINTEN,Receive FIFO Threshold Interrupt Enable." "0,1"
line.long 0x10 "CTLCLRSPI,SPI0 control clear register. Writing a 1 to any implemented bit position causes the corresponding bit in the related CTLSET register to be cleared."
bitfld.long 0x10 9. "TXFLUSHCLR,Transmit FIFO flush clear." "0,1"
bitfld.long 0x10 8. "RXFLUSHCLR,Receive FIFO flush clear. do the clear bits 8 and 9 do anything?" "0,1"
newline
bitfld.long 0x10 4. "RXTIMEOUTINTCLR,Receive FIFO Timeout Interrupt clear." "0,1"
bitfld.long 0x10 1. "TXTHINTCLR,Transmit FIFO Threshold Interrupt clear." "0,1"
newline
bitfld.long 0x10 0. "RXTHINTCLR,Receive FIFO Threshold Interrupt clear." "0,1"
line.long 0x14 "RXDATSPI,SPI0 received data. These registers are half word addressable."
bitfld.long 0x14 20. "SOT,Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e.  any previous transfer has ended). This information can be used to identify the first piece of data in cases where the.." "0,1"
bitfld.long 0x14 19. "RXSSEL3_N,Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
newline
bitfld.long 0x14 18. "RXSSEL2_N,Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
bitfld.long 0x14 17. "RXSSEL1_N,Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
newline
bitfld.long 0x14 16. "RXSSEL0_N,Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual.." "0,1"
hexmask.long.word 0x14 0.--15. 1. "RXDAT,Receiver Data. This contains the next piece of received data. The number of bits that are used depends on the LEN setting in TXCTL / TXDATCTL."
line.long 0x18 "TXDATSPI,SPI0 transmit data. These registers are half word addressable."
hexmask.long.byte 0x18 24.--27. 1. "LEN,Data Length. Specifies the data length from 1 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential data transmits. 0x0 = Data transfer is 1 bit in length. 0x1 = Data transfer is 2 bits in.."
bitfld.long 0x18 22. "RXIGNORE,Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver to simplify the transmit process and can be used with the DMA." "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
newline
bitfld.long 0x18 21. "EOF,End of Frame. Between frames  a delay may be inserted  as defined by the FRAME_DELAY value in the DLY register. The end of a frame may not be particularly meaningful if the FRAME_DELAY value = 0. This control can be used as part of the support for.." "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
bitfld.long 0x18 20. "EOT,End of Transfer. The asserted SSEL will be deasserted at the end of a transfer  and remain so for at least the time specified by the Transfer_delay value in the DLY register." "0: Not deasserted. SSEL not deasserted. This piece..,1: Deasserted. SSEL deasserted. This piece of data.."
newline
bitfld.long 0x18 19. "TXSSEL3_N,Transmit Slave Select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default. The active state of the SSEL3 pin is configured by bits in the CFG register." "0: Asserted. SSEL3 asserted.,1: Not asserted. SSEL3 not asserted."
bitfld.long 0x18 18. "TXSSEL2_N,Transmit Slave Select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default. The active state of the SSEL2 pin is configured by bits in the CFG register." "0: Asserted. SSEL2 asserted.,1: Not asserted. SSEL2 not asserted."
newline
bitfld.long 0x18 17. "TXSSEL1_N,Transmit Slave Select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default. The active state of the SSEL1 pin is configured by bits in the CFG register." "0: Asserted. SSEL1 asserted.,1: Not asserted. SSEL1 not asserted."
bitfld.long 0x18 16. "TXSSEL0_N,Transmit Slave Select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default. The active state of the SSEL0 pin is configured by bits in the CFG register." "0: Asserted. SSEL0 asserted.,1: Not asserted. SSEL0 not asserted."
newline
hexmask.long.word 0x18 0.--15. 1. "TXDAT,Transmit Data. This field provides from 1 to 16 bits of data to be transmitted."
tree.end
repeat.end
tree.end
endif
sif (cpuis("LPC54005*")||cpuis("LPC54016*")||cpuis("LPC54018*")||cpuis("LPC54113*")||cpuis("LPC54114*")||cpuis("LPC54605*")||cpuis("LPC54606*")||cpuis("LPC54607*")||cpuis("LPC54608*")||cpuis("LPC54616*")||cpuis("LPC54618*")||cpuis("LPC54628*")||cpuis("LPC54S005*")||cpuis("LPC54S016*")||cpuis("LPC54S018*"))
base ad:0x4000C000
elif (cpuis("LPC54101*")||cpuis("LPC54102*"))
base ad:0x40038000
endif
tree "WWDT (Windowed Watchdog Timer)"
group.long 0x0++0x7
line.long 0x0 "MOD,Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer."
bitfld.long 0x0 5. "LOCK,Once this bit is set to one and a watchdog feed is performed  disabling or powering down the watchdog oscillator is prevented by hardware. This bit can be set once by software and is only cleared by any reset." "0,1"
bitfld.long 0x0 4. "WDPROTECT,Watchdog update mode. This bit can be set once by software and is only cleared by a reset." "0: Flexible. The watchdog time-out value (TC) can..,1: Threshold. The watchdog time-out value (TC) can.."
newline
bitfld.long 0x0 3. "WDINT,Warning interrupt flag. Set when the timer is at or below the value in WDWARNINT. Cleared by software writing a 1 to this bit position. Note that this bit cannot be cleared while the WARNINT value is equal to the value of the TV register. This can.." "0,1"
bitfld.long 0x0 2. "WDTOF,Watchdog time-out flag. Set when the watchdog timer times out  by a feed error  or by events associated with WDPROTECT. Cleared by software writing a 0 to this bit position. Causes a chip reset if WDRESET = 1." "0,1"
newline
bitfld.long 0x0 1. "WDRESET,Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be re-written with a 0." "0: Interrupt. A watchdog time-out will not cause a..,1: Reset. A watchdog time-out will cause a chip.."
bitfld.long 0x0 0. "WDEN,Watchdog enable bit. Once this bit is set to one and a watchdog feed is performed  the watchdog timer will run permanently." "0: Stop. The watchdog timer is stopped.,1: Run. The watchdog timer is running."
line.long 0x4 "TC,Watchdog timer constant register. This 24-bit register determines the time-out value."
hexmask.long.tbyte 0x4 0.--23. 1. "COUNT,Watchdog time-out value."
wgroup.long 0x8++0x3
line.long 0x0 "FEED,Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC."
hexmask.long.byte 0x0 0.--7. 1. "FEED,Feed value should be 0xAA followed by 0x55."
rgroup.long 0xC++0x3
line.long 0x0 "TV,Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer."
hexmask.long.tbyte 0x0 0.--23. 1. "COUNT,Counter timer value."
group.long 0x14++0x7
line.long 0x0 "WARNINT,Watchdog Warning Interrupt compare value."
hexmask.long.word 0x0 0.--9. 1. "WARNINT,Watchdog warning interrupt compare value."
line.long 0x4 "WINDOW,Watchdog Window compare value."
hexmask.long.tbyte 0x4 0.--23. 1. "WINDOW,Watchdog window value."
tree.end
AUTOINDENT.OFF